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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-06 20:38:32 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-06 20:38:32 +0200 |
| commit | ec96ff4b982030c779f8a4cb3d2642734605eb8d (patch) | |
| tree | 1228105367871cb0f2ce3f39919dfe70e74a1947 /src/synth | |
| parent | a0540030ea458ed15847de7641aaa4175bb631ac (diff) | |
| download | ghdl-ec96ff4b982030c779f8a4cb3d2642734605eb8d.tar.gz ghdl-ec96ff4b982030c779f8a4cb3d2642734605eb8d.tar.bz2 ghdl-ec96ff4b982030c779f8a4cb3d2642734605eb8d.zip | |
simul: signal attributes in actuals
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index d7a5abbe3..b64b6ec5a 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -147,7 +147,8 @@ package body Synth.Vhdl_Stmts is | Iir_Kind_Attribute_Value | Iir_Kind_Free_Quantity_Declaration | Iir_Kinds_Branch_Quantity_Declaration - | Iir_Kind_Dot_Attribute => + | Iir_Kind_Dot_Attribute + | Iir_Kinds_Signal_Attribute => Assign_Base (Syn_Inst); when Iir_Kind_Function_Call => Dest_Base := Synth_Expression (Syn_Inst, Pfx); @@ -408,7 +409,8 @@ package body Synth.Vhdl_Stmts is | Iir_Kind_Indexed_Name | Iir_Kind_Slice_Name | Iir_Kind_Dereference - | Iir_Kind_Dot_Attribute => + | Iir_Kind_Dot_Attribute + | Iir_Kinds_Signal_Attribute => declare Base : Valtyp; Typ : Type_Acc; |