synth: avoid crash on invalid hdl in psl. Fix #2204

3 files changed, 46 insertions, 17 deletions

diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb
index 0be74aeb6..d8c074cd4 100644
--- a/src/synth/synth-vhdl_decls.adb
+++ b/src/synth/synth-vhdl_decls.adb
@@ -931,6 +931,9 @@ package body Synth.Vhdl_Decls is
             Synth_Concurrent_Attribute_Specification (Syn_Inst, Decl);
          when Iir_Kind_Package_Instantiation_Declaration =>
             Synth_Package_Instantiation (Syn_Inst, Decl);
+         when Iir_Kind_Attribute_Implicit_Declaration =>
+            --  Error will be printed when the attribute is used.
+            null;
          when others =>
             Vhdl.Errors.Error_Kind ("synth_concurrent_declaration", Decl);
       end case;
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index a227e7511..c2d8f9eb8 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -1606,19 +1606,31 @@ package body Synth.Vhdl_Expr is
          when N_HDL_Bool =>
             declare
                E : constant Vhdl.Types.Vhdl_Node := Get_HDL_Node (Expr);
+               Val : Valtyp;
             begin
-               return Get_Net (Ctxt, Synth_Expression (Syn_Inst, E));
+               Val := Synth_Expression (Syn_Inst, E);
+               if Val = No_Valtyp then
+                  return No_Net;
+               end if;
+               return Get_Net (Ctxt, Val);
             end;
          when N_Not_Bool =>
-            pragma Assert (Loc /= No_Location);
-            Res := Build_Monadic
-              (Ctxt, Id_Not,
-               Synth_PSL_Expression (Syn_Inst, Get_Boolean (Expr)));
+            declare
+               V : Net;
+            begin
+               pragma Assert (Loc /= No_Location);
+               V := Synth_PSL_Expression (Syn_Inst, Get_Boolean (Expr));
+               if V = No_Net then
+                  return No_Net;
+               end if;
+               Res := Build_Monadic (Ctxt, Id_Not, V);
+            end;
          when N_And_Bool =>
             pragma Assert (Loc /= No_Location);
             declare
                L : constant PSL_Node := Get_Left (Expr);
                R : constant PSL_Node := Get_Right (Expr);
+               Lv, Rv : Net;
                Edge : Net;
             begin
                --  Handle edge (as it can be in default clock).
@@ -1633,17 +1645,26 @@ package body Synth.Vhdl_Expr is
                   --  It is never EOS!
                   Res := Build_Const_UB32 (Ctxt, 0, 1);
                else
-                  Res := Build_Dyadic (Ctxt, Id_And,
-                                       Synth_PSL_Expression (Syn_Inst, L),
-                                       Synth_PSL_Expression (Syn_Inst, R));
+                  Lv := Synth_PSL_Expression (Syn_Inst, L);
+                  Rv := Synth_PSL_Expression (Syn_Inst, R);
+                  if Lv = No_Net or Rv = No_Net then
+                     return No_Net;
+                  end if;
+                  Res := Build_Dyadic (Ctxt, Id_And, Lv, Rv);
                end if;
             end;
          when N_Or_Bool =>
-            pragma Assert (Loc /= No_Location);
-            Res := Build_Dyadic
-              (Ctxt, Id_Or,
-               Synth_PSL_Expression (Syn_Inst, Get_Left (Expr)),
-               Synth_PSL_Expression (Syn_Inst, Get_Right (Expr)));
+            declare
+               Lv, Rv : Net;
+            begin
+               pragma Assert (Loc /= No_Location);
+               Lv := Synth_PSL_Expression (Syn_Inst, Get_Left (Expr));
+               Rv := Synth_PSL_Expression (Syn_Inst, Get_Right (Expr));
+               if Lv = No_Net or Rv = No_Net then
+                  return No_Net;
+               end if;
+               Res := Build_Dyadic (Ctxt, Id_Or, Lv, Rv);
+            end;
          when N_True =>
             Res := Build_Const_UB32 (Ctxt, 1, 1);
          when N_False
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index 40a694940..b122c11ff 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -4217,6 +4217,7 @@ package body Synth.Vhdl_Stmts is
       Cond : Net;
       E : NFA_Edge;
       D_Arr : Net_Array_Acc;
+      N : Net;
       Res : Net;
    begin
       D_Arr := new Net_Array'(0 .. Nbr_States - 1 => No_Net);
@@ -4232,10 +4233,14 @@ package body Synth.Vhdl_Stmts is
          E := Get_First_Src_Edge (S);
          while E /= No_Edge loop
             --  Edge condition.
-            Cond := Build_Dyadic
-              (Ctxt, Id_And,
-               I, Synth_PSL_Expression (Syn_Inst, Get_Edge_Expr (E)));
-            Set_Location (Cond, Loc);
+            N := Synth_PSL_Expression (Syn_Inst, Get_Edge_Expr (E));
+            if N = No_Net then
+               --  Anything ?
+               Cond := I;
+            else
+               Cond := Build_Dyadic (Ctxt, Id_And, I, N);
+               Set_Location (Cond, Loc);
+            end if;
 
             --  TODO: if EOS is present, then this is a live state.