| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth-vhdl_oper.adb: fix mul uns uns. Fix #2169 | Tristan Gingold | 2022-08-10 | 1 | -1/+1 |
| * | synth-vhdl_oper: remove check for positive rotation amount. Fix #2159 | Tristan Gingold | 2022-08-04 | 1 | -3/+1 |
| * | netlists-memories: allow X in memories. Fix #2146 | Tristan Gingold | 2022-07-29 | 1 | -2/+4 |
| * | netlists-disp_verilog(disp_const_log): fix output. Fix #2149 | Tristan Gingold | 2022-07-28 | 1 | -2/+2 |
| * | synth-disp_vhdl: fix out conversion. Fix #2145 | Tristan Gingold | 2022-07-28 | 1 | -21/+29 |
| * | synth-vhdl_expr: add support for branch quantities | Tristan Gingold | 2022-07-28 | 2 | -0/+2 |
| * | elab-vhdl_expr: fix handling of multi-dim arrays. Fix #2144 | Tristan Gingold | 2022-07-27 | 1 | -9/+17 |
| * | synth-disp_vhdl: improve output for unsigned. Fix #2139 | Tristan Gingold | 2022-07-27 | 1 | -2/+17 |
| * | elab-vhdl_expr: fix incorrect type of multi-dim array indexing during elab | Tristan Gingold | 2022-07-27 | 1 | -0/+9 |
| * | synthesis.adb: cleanup after expand. For #2142 | Tristan Gingold | 2022-07-27 | 1 | -0/+2 |
| * | netlists-disp_vhdl: adjust output for #2140 | Tristan Gingold | 2022-07-27 | 1 | -2/+8 |
| * | netlists-expands: do not try to clean input of dyn_extract. Fix #2142 | Tristan Gingold | 2022-07-27 | 1 | -5/+1 |
| * | netlist-disp_vhdl: add a separator between instances and signals. | Tristan Gingold | 2022-07-26 | 1 | -1/+1 |
| * | simul: gather terminals | Tristan Gingold | 2022-07-25 | 1 | -0/+28 |
| * | synth/elab-vhdl_values: add Value_Terminal | Tristan Gingold | 2022-07-25 | 6 | -4/+38 |
| * | synth-environment: fix memory crash. Fix #2139 | Tristan Gingold | 2022-07-25 | 1 | -2/+8 |
| * | synth: add hook for dot attribute | Tristan Gingold | 2022-07-24 | 3 | -7/+17 |
| * | elab-vhdl_decls: elaborate dot attribute | Tristan Gingold | 2022-07-21 | 1 | -0/+13 |
| * | vhdl-nodes: renaming. | Tristan Gingold | 2022-07-21 | 2 | -5/+5 |
| * | elab-vhdl_decls: elaborate implicit signals | Tristan Gingold | 2022-07-21 | 1 | -2/+23 |
| * | synth-vhdl_expr: add hook for quantities | Tristan Gingold | 2022-07-20 | 2 | -11/+23 |
| * | elab-vhdl_debug: handle signals in packages | Tristan Gingold | 2022-07-20 | 1 | -2/+8 |
| * | grt: add real now variable. | Tristan Gingold | 2022-07-20 | 1 | -0/+3 |
| * | elab-vhdl_context: add iterator for top-level packages | Tristan Gingold | 2022-07-20 | 2 | -0/+36 |
| * | elab-vhdl_debug: disp fp64 values | Tristan Gingold | 2022-07-20 | 2 | -2/+3 |
| * | vhdl: preliminary work to elaborat quantities | Tristan Gingold | 2022-07-16 | 3 | -0/+17 |
| * | elab-vhdl_values: add Create_Value_Quantity | Tristan Gingold | 2022-07-16 | 6 | -2/+41 |
| * | netlists-inference: add (disabled) code to add a latch | Tristan Gingold | 2022-07-16 | 1 | -26/+103 |
| * | synth: Display dlatch | Tristan Gingold | 2022-07-14 | 3 | -2/+9 |
| * | netlists: add d-latch | Tristan Gingold | 2022-07-12 | 3 | -2/+38 |
| * | Fix access check failed from iir_kind_selected_element (#2132) | Michael Nolan | 2022-07-12 | 1 | -0/+1 |
| * | synth-environment: do inference during wire finalization | Tristan Gingold | 2022-07-11 | 1 | -13/+31 |
| * | synth-environment: add Loc parameter to Add_Conc_Assign | Tristan Gingold | 2022-07-11 | 3 | -4/+13 |
| * | netlists-inference: detect false loops only for variables. Fix #2125 | Tristan Gingold | 2022-07-11 | 1 | -2/+3 |
| * | netlists-disp_verilog: do not connect to null-range output. For #2113 | Tristan Gingold | 2022-07-08 | 1 | -41/+47 |
| * | netlists-disp_verilog: fix output for id_abs. For #2123 | Tristan Gingold | 2022-07-06 | 1 | -1/+2 |
| * | synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129 | Tristan Gingold | 2022-07-06 | 1 | -1/+3 |
| * | Fix issue #2126, add handling of to_ux01 to synthesis | Michael Nolan | 2022-07-05 | 1 | -1/+3 |
| * | synth-vhdl_insts: do not crash on unconnected input. Fix #2124 | Tristan Gingold | 2022-07-05 | 1 | -0/+4 |
| * | netlists-disp_verilog: handle Id_Abs. Fix #2113 | Tristan Gingold | 2022-07-04 | 1 | -1/+1 |
| * | synth-vhdl_insts: also handled unbounded records in hash names. | Tristan Gingold | 2022-07-02 | 1 | -0/+7 |
| * | netlists-disp_verilog: adjust, discard null signals. For #2113 | Tristan Gingold | 2022-06-28 | 1 | -1/+6 |
| * | netlists-disp_verilog: fix warning | Tristan Gingold | 2022-06-27 | 1 | -1/+2 |
| * | synth/netlists-disp_verilog: skip null input port. Fix #2113 | Tristan Gingold | 2022-06-27 | 1 | -15/+20 |
| * | synth: rework #2109 - remove null wires | Tristan Gingold | 2022-06-27 | 7 | -26/+85 |
| * | synth/netlists-disp_verilog: adjust previous patch. For #2109 | Tristan Gingold | 2022-06-27 | 1 | -1/+2 |
| * | netlists-disp_verilog: do not display ports of width 0. Fix #2109 | Tristan Gingold | 2022-06-27 | 1 | -5/+19 |
| * | synth-vhdl_insts(synth_single_input_assoc): handle type conversion. | Tristan Gingold | 2022-06-16 | 2 | -4/+13 |
| * | Add comments | Tristan Gingold | 2022-06-15 | 1 | -1/+1 |
| * | netlists-rename: handle handle signal instances. Fix #2093 | Tristan Gingold | 2022-06-15 | 3 | -2/+28 |
