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* testsuite/synth/dff02: do not run dff06 (creates a latch)Tristan Gingold2022-07-111-1/+2
* synth-environment: do inference during wire finalizationTristan Gingold2022-07-111-13/+31
* synth-environment: add Loc parameter to Add_Conc_AssignTristan Gingold2022-07-113-4/+13
* netlists-inference: detect false loops only for variables. Fix #2125Tristan Gingold2022-07-111-2/+3
* testsuite/synth: add a test for #2113Tristan Gingold2022-07-082-0/+66
* netlists-disp_verilog: do not connect to null-range output. For #2113Tristan Gingold2022-07-081-41/+47
* vhdl-evaluation: explicitly compute integer_exp to handle overflow.Tristan Gingold2022-07-071-2/+31
* vhdl-evaluation: make overflow_literal non locally static.Tristan Gingold2022-07-072-1/+6
* netlists-disp_verilog: fix output for id_abs. For #2123Tristan Gingold2022-07-061-1/+2
* testsuite/synth: add a test for #2129Tristan Gingold2022-07-062-0/+32
* synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129Tristan Gingold2022-07-061-1/+3
* testsuite/gna: adjust previous commitTristan Gingold2022-07-061-2/+10
* testsuite/gna: add more tests for #2116Tristan Gingold2022-07-063-0/+18
* Fix CI failure on macosx (llvm) (#2128)tgingold2022-07-061-4/+2
* Merge pull request #2127 from C-Elegans/to_ux01_unhandled_functiontgingold2022-07-053-1/+31
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| * Fix issue #2126, add handling of to_ux01 to synthesisMichael Nolan2022-07-053-1/+31
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* ci/Test: typoumarcor2022-07-051-1/+1
* Test.yml: list brew package on macosTristan Gingold2022-07-051-4/+2
* testsuite/synth: add a test for #2124Tristan Gingold2022-07-054-0/+81
* synth-vhdl_insts: do not crash on unconnected input. Fix #2124Tristan Gingold2022-07-051-0/+4
* Test.yml: add more debug commands for macosTristan Gingold2022-07-041-1/+1
* Test.yml: fix syntaxTristan Gingold2022-07-041-4/+5
* Test.yml: untabifyTristan Gingold2022-07-041-3/+3
* github/workflows: add log for llvm on macosTristan Gingold2022-07-041-0/+3
* doc: --gen-depends is not available with mcode. Fix #2121Tristan Gingold2022-07-041-3/+6
* testsuite/synth: add a test for #2123Tristan Gingold2022-07-042-0/+27
* netlists-disp_verilog: handle Id_Abs. Fix #2113Tristan Gingold2022-07-041-1/+1
* Merge pull request #2059 from Xiretza/testsuite-show-diffstgingold2022-07-035-7/+7
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| * fix(testsuite): show diffs on comparison failureXiretza2022-05-165-7/+7
* | Fix docstring and a small bug in PoSh precompile scriptPatrick Lehmann2022-07-038-11/+14
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| * | Update docstring for GHDL parameter of PoSh scriptsHauke Günther2022-06-247-7/+7
| * | Fix error when ghdl.exe is searched with Get-Command but not foundHauke Günther2022-06-241-4/+7
* | | testsuite/synth: add a test for #2119Tristan Gingold2022-07-022-0/+67
* | | synth-vhdl_insts: also handled unbounded records in hash names.Tristan Gingold2022-07-021-0/+7
* | | testsuite/gna: add tests, close #2116Tristan Gingold2022-07-0270-0/+622
* | | vhdl-sem_psl: analyze strong propertiesTristan Gingold2022-07-021-1/+2
* | | vhdl-sem_names: avoid crash on incorrect selected name.Tristan Gingold2022-07-021-6/+6
* | | vhdl-sem_decls: avoid crash on self use of a generic package.Tristan Gingold2022-07-021-0/+10
* | | vhdl: avoid crash on incorrect use of attributes.Tristan Gingold2022-07-025-14/+40
* | | vhdl: avoid crash on incorrect use of signaturesTristan Gingold2022-07-023-281/+292
* | | vhdl-evaluation: handle more operations (thought synth).Tristan Gingold2022-07-021-2/+1
* | | testsuite/gna: add a test from #2117Tristan Gingold2022-07-012-0/+20
* | | testsuite/gna: improve test #2115Tristan Gingold2022-06-293-7/+53
* | | testsuite/gna: add a test for #2115Tristan Gingold2022-06-282-0/+38
* | | libraries/textio-body.vhdl: use false/true for boolean write.Tristan Gingold2022-06-282-4/+7
* | | testsuite/gna: add a test for #2100Tristan Gingold2022-06-282-0/+30
* | | vhdl-sem_names: avoid duplicate error message. For #2100Tristan Gingold2022-06-281-1/+19
* | | testsuite/synth: strenghten test #2113Tristan Gingold2022-06-281-0/+3
* | | netlists-disp_verilog: adjust, discard null signals. For #2113Tristan Gingold2022-06-281-1/+6
* | | netlists-disp_verilog: fix warningTristan Gingold2022-06-271-1/+2
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