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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-28 02:42:05 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-28 02:42:05 +0200 |
| commit | 7e89ed2b5108163d52788927fe49b0c5686adbd6 (patch) | |
| tree | dd403c9e20e010a4cba2a8f4258e588d50dc0c31 | |
| parent | dabf31c2b12633033cea5a177f0deefe28c05c9b (diff) | |
| download | ghdl-7e89ed2b5108163d52788927fe49b0c5686adbd6.tar.gz ghdl-7e89ed2b5108163d52788927fe49b0c5686adbd6.tar.bz2 ghdl-7e89ed2b5108163d52788927fe49b0c5686adbd6.zip | |
netlists-disp_verilog: adjust, discard null signals. For #2113
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 47fa0047a..cd13a6d77 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -444,9 +444,14 @@ package body Netlists.Disp_Verilog is -- a name. In that case, a signal will be created and driven. function Need_Signal (Inst : Instance) return Boolean is + O : constant Net := Get_Output (Inst, 0); I : Input; begin - I := Get_First_Sink (Get_Output (Inst, 0)); + if not Flag_Null_Wires and then Get_Width (O) = 0 then + return False; + end if; + + I := Get_First_Sink (O); while I /= No_Input loop if Need_Name (Get_Input_Parent (I)) then return True; |