diff options
| author | Tristan Gingold <tgingold@free.fr> | 2022-07-06 22:38:50 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-06 22:38:50 +0200 |
| commit | 774dcd646151328991440b7b7c2cbaf750dcc2b6 (patch) | |
| tree | 47744f598b17094f4e5dbca9c1102faa0a533687 | |
| parent | 7783d1a1d87a8d8ae9c251d3a0091ff7fc728dd7 (diff) | |
| download | ghdl-774dcd646151328991440b7b7c2cbaf750dcc2b6.tar.gz ghdl-774dcd646151328991440b7b7c2cbaf750dcc2b6.tar.bz2 ghdl-774dcd646151328991440b7b7c2cbaf750dcc2b6.zip | |
netlists-disp_verilog: fix output for id_abs. For #2123
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 7d1354403..950f6fd36 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -854,7 +854,8 @@ package body Netlists.Disp_Verilog is when Id_Neg => Disp_Template (" assign \o0 = -\i0;" & NL, Inst); when Id_Abs=> - Disp_Template (" \o0 <= \si0 >= 0 ? \i0 : -\i0;" & NL, Inst); + Disp_Template (" assign \o0 = \si0 >= 0 ? \i0 : -\i0;" & NL, + Inst); when Id_Extract => Disp_Template (" assign \o0 = ", Inst); Disp_Extract (Inst); |