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authorTristan Gingold <tgingold@free.fr>2022-07-02 07:54:08 +0200
committerTristan Gingold <tgingold@free.fr>2022-07-02 07:54:08 +0200
commita33efb91d1573ce15c199cd1f89842f7170b69e4 (patch)
treeb8e073e4d8cbf0650291bf8094ab86e59ed5cba8
parent66e6648126a3bc6d78c073ea4badc107f2a46cf0 (diff)
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testsuite/synth: add a test for #2119
-rw-r--r--testsuite/synth/issue2119/test.vhdl58
-rwxr-xr-xtestsuite/synth/issue2119/testsuite.sh9
2 files changed, 67 insertions, 0 deletions
diff --git a/testsuite/synth/issue2119/test.vhdl b/testsuite/synth/issue2119/test.vhdl
new file mode 100644
index 000000000..755ea5ed8
--- /dev/null
+++ b/testsuite/synth/issue2119/test.vhdl
@@ -0,0 +1,58 @@
+-- Title : Testcase for unbounded records
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package test_pkg is
+ type test_rec is record
+ vec_bound : std_logic_vector(7 downto 0);
+ vec_unbound : std_logic_vector;
+ single_bit : std_logic;
+ end record test_rec;
+end test_pkg;
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+-- Inner module
+------------------------------------------------------------------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.test_pkg.all;
+
+entity test_impl is
+
+ port (
+ clk : in std_logic;
+ rec_out : out test_rec
+ );
+
+end entity test_impl;
+architecture str of test_impl is
+begin -- architecture str
+end architecture str;
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+-- Outer Wrapper
+------------------------------------------------------------------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use work.test_pkg.all;
+entity test is
+
+ generic (
+ unbound_len : natural := 10
+ );
+ port (
+ clk : in std_logic;
+ rec_out : out test_rec(vec_unbound(unbound_len-1 downto 0)));
+end entity test;
+
+architecture str of test is
+
+begin -- architecture str
+ test_impl_1: entity work.test_impl
+ port map (
+ clk => clk, -- [in std_logic]
+ rec_out => rec_out); -- [out test_rec]
+end architecture str;
diff --git a/testsuite/synth/issue2119/testsuite.sh b/testsuite/synth/issue2119/testsuite.sh
new file mode 100755
index 000000000..75ca5f68d
--- /dev/null
+++ b/testsuite/synth/issue2119/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+synth_only test
+
+echo "Test successful"