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authorTristan Gingold <tgingold@free.fr>2019-09-17 02:18:41 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-17 02:18:41 +0200
commitde899bb8cb6e2f43a3e80a6a273d6a459b08e401 (patch)
treee44c55c459c9a1fe5814103927d7ac8be4f8a40e /testsuite/synth
parentb7a36d7d7838d05b449aa7e23935cd0e3e4213d4 (diff)
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testsuite/synth: add var01
Diffstat (limited to 'testsuite/synth')
-rw-r--r--testsuite/synth/var01/tb_var01.vhdl51
-rw-r--r--testsuite/synth/var01/tb_var02.vhdl51
-rw-r--r--testsuite/synth/var01/tb_var03.vhdl42
-rw-r--r--testsuite/synth/var01/tb_var04.vhdl38
-rw-r--r--testsuite/synth/var01/tb_var05.vhdl48
-rwxr-xr-xtestsuite/synth/var01/testsuite.sh18
-rw-r--r--testsuite/synth/var01/var01.vhdl26
-rw-r--r--testsuite/synth/var01/var02.vhdl37
-rw-r--r--testsuite/synth/var01/var03.vhdl26
-rw-r--r--testsuite/synth/var01/var04.vhdl26
-rw-r--r--testsuite/synth/var01/var05.vhdl21
11 files changed, 384 insertions, 0 deletions
diff --git a/testsuite/synth/var01/tb_var01.vhdl b/testsuite/synth/var01/tb_var01.vhdl
new file mode 100644
index 000000000..48dca33a3
--- /dev/null
+++ b/testsuite/synth/var01/tb_var01.vhdl
@@ -0,0 +1,51 @@
+entity tb_var01 is
+end tb_var01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var01 is
+ signal clk : std_logic;
+ signal mask : std_logic_vector (3 downto 0);
+ signal val : std_logic_vector (31 downto 0);
+ signal res : std_logic_vector (31 downto 0);
+begin
+ dut: entity work.var01
+ port map (
+ clk => clk,
+ mask => mask,
+ val => val,
+ res => res);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ mask <= x"f";
+ val <= x"12_34_56_78";
+ pulse;
+ assert res = x"12_34_56_78" severity failure;
+
+ mask <= x"8";
+ val <= x"9a_00_00_00";
+ pulse;
+ assert res = x"9a_34_56_78" severity failure;
+
+ mask <= x"0";
+ val <= x"00_00_00_00";
+ pulse;
+ assert res = x"9a_34_56_78" severity failure;
+
+ mask <= x"5";
+ val <= x"00_bc_00_de";
+ pulse;
+ assert res = x"9a_bc_56_de" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/var01/tb_var02.vhdl b/testsuite/synth/var01/tb_var02.vhdl
new file mode 100644
index 000000000..e370cf1a1
--- /dev/null
+++ b/testsuite/synth/var01/tb_var02.vhdl
@@ -0,0 +1,51 @@
+entity tb_var02 is
+end tb_var02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var02 is
+ signal clk : std_logic;
+ signal mask : std_logic_vector (3 downto 0);
+ signal val : std_logic_vector (31 downto 0);
+ signal res : std_logic_vector (31 downto 0);
+begin
+ dut: entity work.var02
+ port map (
+ clk => clk,
+ mask => mask,
+ val => val,
+ res => res);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ mask <= x"f";
+ val <= x"12_34_56_78";
+ pulse;
+ assert res = x"12_34_56_78" severity failure;
+
+ mask <= x"8";
+ val <= x"9a_00_00_00";
+ pulse;
+ assert res = x"9a_34_56_78" severity failure;
+
+ mask <= x"0";
+ val <= x"00_00_00_00";
+ pulse;
+ assert res = x"9a_34_56_78" severity failure;
+
+ mask <= x"5";
+ val <= x"00_bc_00_de";
+ pulse;
+ assert res = x"9a_bc_56_de" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/var01/tb_var03.vhdl b/testsuite/synth/var01/tb_var03.vhdl
new file mode 100644
index 000000000..f5715abe7
--- /dev/null
+++ b/testsuite/synth/var01/tb_var03.vhdl
@@ -0,0 +1,42 @@
+entity tb_var03 is
+end tb_var03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var03 is
+ signal clk : std_logic;
+ signal mask : std_logic_vector (1 downto 0);
+ signal a, b : std_logic_vector (15 downto 0);
+ signal res : std_logic_vector (15 downto 0);
+begin
+ dut: entity work.var03
+ port map (
+ mask => mask,
+ a => a,
+ b => b,
+ res => res);
+
+ process
+ begin
+ mask <= "11";
+ a <= x"12_34";
+ b <= x"aa_bb";
+ wait for 1 ns;
+ assert res = x"aa_bb" severity failure;
+
+ mask <= "00";
+ a <= x"aa_bb";
+ b <= x"12_34";
+ wait for 1 ns;
+ assert res = x"aa_bb" severity failure;
+
+ mask <= "10";
+ a <= x"aa_bb";
+ b <= x"12_34";
+ wait for 1 ns;
+ assert res = x"12_bb" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/var01/tb_var04.vhdl b/testsuite/synth/var01/tb_var04.vhdl
new file mode 100644
index 000000000..2de5ffcc2
--- /dev/null
+++ b/testsuite/synth/var01/tb_var04.vhdl
@@ -0,0 +1,38 @@
+entity tb_var04 is
+end tb_var04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var04 is
+ signal clk : std_logic;
+ signal mask : std_logic_vector (1 downto 0);
+ signal val : std_logic_vector (15 downto 0);
+ signal res : std_logic_vector (15 downto 0);
+begin
+ dut: entity work.var04
+ port map (
+ mask => mask,
+ val => val,
+ res => res);
+
+ process
+ begin
+ mask <= "11";
+ val <= x"aa_bb";
+ wait for 1 ns;
+ assert res = x"aa_bb" severity failure;
+
+ mask <= "00";
+ val <= x"12_34";
+ wait for 1 ns;
+ assert res = x"00_00" severity failure;
+
+ mask <= "10";
+ val <= x"12_34";
+ wait for 1 ns;
+ assert res = x"12_00" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/var01/tb_var05.vhdl b/testsuite/synth/var01/tb_var05.vhdl
new file mode 100644
index 000000000..63d42bc12
--- /dev/null
+++ b/testsuite/synth/var01/tb_var05.vhdl
@@ -0,0 +1,48 @@
+entity tb_var05 is
+end tb_var05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var05 is
+ signal clk : std_logic;
+ signal sel : std_logic;
+ signal a, b : std_logic_vector (1 downto 0);
+ signal res : std_logic_vector (1 downto 0);
+begin
+ dut: entity work.var05
+ port map (
+ sel => sel,
+ a => a,
+ b => b,
+ res => res);
+
+ process
+ begin
+ sel <= '1';
+ a <= "00";
+ b <= "11";
+ wait for 1 ns;
+ assert res = "11" severity failure;
+
+ sel <= '0';
+ a <= "00";
+ b <= "11";
+ wait for 1 ns;
+ assert res = "00" severity failure;
+
+ sel <= '0';
+ a <= "10";
+ b <= "01";
+ wait for 1 ns;
+ assert res = "10" severity failure;
+
+ sel <= '1';
+ a <= "10";
+ b <= "01";
+ wait for 1 ns;
+ assert res = "01" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/var01/testsuite.sh b/testsuite/synth/var01/testsuite.sh
new file mode 100755
index 000000000..e72b66751
--- /dev/null
+++ b/testsuite/synth/var01/testsuite.sh
@@ -0,0 +1,18 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+for t in var01 var02 var03 var05; do
+ analyze $t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t --ieee-asserts=disable-at-0
+ clean
+done
+
+echo "Test successful"
diff --git a/testsuite/synth/var01/var01.vhdl b/testsuite/synth/var01/var01.vhdl
new file mode 100644
index 000000000..f81c10647
--- /dev/null
+++ b/testsuite/synth/var01/var01.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity var01 is
+ port (clk : std_logic;
+ mask : std_logic_vector (3 downto 0);
+ val : std_logic_vector (31 downto 0);
+ res : out std_logic_vector (31 downto 0));
+end var01;
+
+architecture behav of var01 is
+begin
+ process (clk)
+ variable hi, lo : natural;
+ begin
+ if rising_edge (clk) then
+ for i in 0 to 3 loop
+ if mask (i) = '1' then
+ lo := i * 8;
+ hi := lo + 7;
+ res (hi downto lo) <= val (hi downto lo);
+ end if;
+ end loop;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/var01/var02.vhdl b/testsuite/synth/var01/var02.vhdl
new file mode 100644
index 000000000..3825018b9
--- /dev/null
+++ b/testsuite/synth/var01/var02.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity var02 is
+ port (clk : std_logic;
+ mask : std_logic_vector (3 downto 0);
+ val : std_logic_vector (31 downto 0);
+ res : out std_logic_vector (31 downto 0));
+end var02;
+
+architecture behav of var02 is
+ signal r : std_logic_vector (31 downto 0) := (others => '0');
+ signal r_up : std_logic_vector (31 downto 0) := (others => '0');
+begin
+ process (all)
+ variable t : std_logic_vector (31 downto 0) := (others => '0');
+ variable hi, lo : natural;
+ begin
+ t := r;
+ for i in 0 to 3 loop
+ if mask (i) = '1' then
+ lo := i * 8;
+ hi := lo + 7;
+ t (hi downto lo) := val (hi downto lo);
+ end if;
+ end loop;
+ r_up <= t;
+ end process;
+
+ process (clk)
+ begin
+ if rising_edge (clk) then
+ r <= r_up;
+ end if;
+ end process;
+ res <= r;
+end behav;
diff --git a/testsuite/synth/var01/var03.vhdl b/testsuite/synth/var01/var03.vhdl
new file mode 100644
index 000000000..17998bba1
--- /dev/null
+++ b/testsuite/synth/var01/var03.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity var03 is
+ port (mask : std_logic_vector (1 downto 0);
+ a, b : std_logic_vector (15 downto 0);
+ res : out std_logic_vector (15 downto 0));
+end var03;
+
+architecture behav of var03 is
+begin
+ process (all)
+ variable t : std_logic_vector (15 downto 0) := (others => '0');
+ variable hi, lo : integer;
+ begin
+ t := a;
+ for i in 0 to 1 loop
+ if mask (i) = '1' then
+ lo := i * 8;
+ hi := lo + 7;
+ t (hi downto lo) := b (hi downto lo);
+ end if;
+ end loop;
+ res <= t;
+ end process;
+end behav;
diff --git a/testsuite/synth/var01/var04.vhdl b/testsuite/synth/var01/var04.vhdl
new file mode 100644
index 000000000..754e89428
--- /dev/null
+++ b/testsuite/synth/var01/var04.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity var04 is
+ port (mask : std_logic_vector (1 downto 0);
+ val : std_logic_vector (15 downto 0);
+ res : out std_logic_vector (15 downto 0));
+end var04;
+
+architecture behav of var04 is
+begin
+ process (all)
+ variable t : std_logic_vector (15 downto 0);
+ variable hi, lo : integer;
+ begin
+ t := (others => '0');
+ for i in 0 to 1 loop
+ if mask (i) = '1' then
+ lo := i * 8;
+ hi := lo + 7;
+ t (hi downto lo) := val (hi downto lo);
+ end if;
+ end loop;
+ res <= t;
+ end process;
+end behav;
diff --git a/testsuite/synth/var01/var05.vhdl b/testsuite/synth/var01/var05.vhdl
new file mode 100644
index 000000000..2965e3c1a
--- /dev/null
+++ b/testsuite/synth/var01/var05.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity var05 is
+ port (sel : std_logic;
+ a, b : std_logic_vector (1 downto 0);
+ res : out std_logic_vector (1 downto 0));
+end var05;
+
+architecture behav of var05 is
+begin
+ process (all)
+ variable idx : integer;
+ begin
+ res <= a;
+ if sel = '1' then
+ idx := 1;
+ res <= b;
+ end if;
+ end process;
+end behav;