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-rw-r--r--testsuite/synth/var01/tb_var02.vhdl51
1 files changed, 51 insertions, 0 deletions
diff --git a/testsuite/synth/var01/tb_var02.vhdl b/testsuite/synth/var01/tb_var02.vhdl
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--- /dev/null
+++ b/testsuite/synth/var01/tb_var02.vhdl
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+entity tb_var02 is
+end tb_var02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var02 is
+ signal clk : std_logic;
+ signal mask : std_logic_vector (3 downto 0);
+ signal val : std_logic_vector (31 downto 0);
+ signal res : std_logic_vector (31 downto 0);
+begin
+ dut: entity work.var02
+ port map (
+ clk => clk,
+ mask => mask,
+ val => val,
+ res => res);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ mask <= x"f";
+ val <= x"12_34_56_78";
+ pulse;
+ assert res = x"12_34_56_78" severity failure;
+
+ mask <= x"8";
+ val <= x"9a_00_00_00";
+ pulse;
+ assert res = x"9a_34_56_78" severity failure;
+
+ mask <= x"0";
+ val <= x"00_00_00_00";
+ pulse;
+ assert res = x"9a_34_56_78" severity failure;
+
+ mask <= x"5";
+ val <= x"00_bc_00_de";
+ pulse;
+ assert res = x"9a_bc_56_de" severity failure;
+
+ wait;
+ end process;
+end behav;