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author | Tristan Gingold <tgingold@free.fr> | 2019-10-08 06:28:45 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-08 06:28:45 +0200 |
commit | 14ba70a30d5ce4395eea8c668bcafc85790b5247 (patch) | |
tree | 573ed287f0e71e10c11de0758517a39d4a9c55b5 /testsuite/synth/issue964/ent.vhdl | |
parent | 5c029fecafa67b4d47ce904a9ce8c52a07e479f7 (diff) | |
download | ghdl-14ba70a30d5ce4395eea8c668bcafc85790b5247.tar.gz ghdl-14ba70a30d5ce4395eea8c668bcafc85790b5247.tar.bz2 ghdl-14ba70a30d5ce4395eea8c668bcafc85790b5247.zip |
testsuite/synth: add testcase for #964
Diffstat (limited to 'testsuite/synth/issue964/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue964/ent.vhdl | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/issue964/ent.vhdl b/testsuite/synth/issue964/ent.vhdl new file mode 100644 index 000000000..abed11a80 --- /dev/null +++ b/testsuite/synth/issue964/ent.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + clk : in std_logic; + reset : in std_logic; + enable : in std_logic; + q : out std_logic + ); +end; + +architecture a of ent is + signal s : std_logic; +begin + process(clk, reset) + begin + if reset = '1' then + s <= '0'; + elsif enable /= '1' then + -- [nothing] + elsif rising_edge(clk) then + s <= not s; + end if; + end process; + + q <= s; +end; |