From 14ba70a30d5ce4395eea8c668bcafc85790b5247 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 8 Oct 2019 06:28:45 +0200
Subject: testsuite/synth: add testcase for #964

---
 testsuite/synth/issue964/ent.vhdl | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 testsuite/synth/issue964/ent.vhdl

(limited to 'testsuite/synth/issue964/ent.vhdl')

diff --git a/testsuite/synth/issue964/ent.vhdl b/testsuite/synth/issue964/ent.vhdl
new file mode 100644
index 000000000..abed11a80
--- /dev/null
+++ b/testsuite/synth/issue964/ent.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+        enable : in std_logic;
+        q : out std_logic
+    );
+end;
+
+architecture a of ent is
+    signal s : std_logic;
+begin
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            s <= '0';
+        elsif enable /= '1' then
+            -- [nothing]
+        elsif rising_edge(clk) then
+            s <= not s;
+        end if;
+    end process;
+
+    q <= s;
+end;
-- 
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