testsuite/synth: add tests for previous commit.

25 files changed, 427 insertions, 0 deletions

diff --git a/testsuite/synth/dispout01/pkg_rec01.vhdl b/testsuite/synth/dispout01/pkg_rec01.vhdl
new file mode 100644
index 000000000..c2048c3ea
--- /dev/null
+++ b/testsuite/synth/dispout01/pkg_rec01.vhdl
@@ -0,0 +1,9 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package rec01_pkg is
+  type myrec is record
+     a : std_logic;
+     b : std_logic;
+  end record;
+end rec01_pkg;
diff --git a/testsuite/synth/dispout01/pkg_rec02.vhdl b/testsuite/synth/dispout01/pkg_rec02.vhdl
new file mode 100644
index 000000000..5b5b78850
--- /dev/null
+++ b/testsuite/synth/dispout01/pkg_rec02.vhdl
@@ -0,0 +1,9 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package rec02_pkg is
+  type myrec is record
+     a : natural range 0 to 5;
+     b : std_logic;
+  end record;
+end rec02_pkg;
diff --git a/testsuite/synth/dispout01/pkg_rec03.vhdl b/testsuite/synth/dispout01/pkg_rec03.vhdl
new file mode 100644
index 000000000..2c6204201
--- /dev/null
+++ b/testsuite/synth/dispout01/pkg_rec03.vhdl
@@ -0,0 +1,11 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package rec03_pkg is
+  type myenum is (s0, s1, s2, s3);
+
+  type myrec is record
+     a : myenum;
+     b : std_logic;
+  end record;
+end rec03_pkg;
diff --git a/testsuite/synth/dispout01/pkg_rec04.vhdl b/testsuite/synth/dispout01/pkg_rec04.vhdl
new file mode 100644
index 000000000..01cb4da3f
--- /dev/null
+++ b/testsuite/synth/dispout01/pkg_rec04.vhdl
@@ -0,0 +1,9 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package rec04_pkg is
+  type myrec is record
+     a : std_logic_vector (3 downto 0);
+     b : std_logic;
+  end record;
+end rec04_pkg;
diff --git a/testsuite/synth/dispout01/pkg_rec05.vhdl b/testsuite/synth/dispout01/pkg_rec05.vhdl
new file mode 100644
index 000000000..c73c67f05
--- /dev/null
+++ b/testsuite/synth/dispout01/pkg_rec05.vhdl
@@ -0,0 +1,10 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package rec05_pkg is
+  type myrec is record
+     a : unsigned (3 downto 0);
+     b : std_logic;
+  end record;
+end rec05_pkg;
diff --git a/testsuite/synth/dispout01/pkg_rec06.vhdl b/testsuite/synth/dispout01/pkg_rec06.vhdl
new file mode 100644
index 000000000..5e9a16186
--- /dev/null
+++ b/testsuite/synth/dispout01/pkg_rec06.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package rec06_pkg is
+  type myrec2 is record
+    c : natural range 0 to 3;
+    d : unsigned (3 downto 0);
+  end record;
+
+  type myrec is record
+    a : myrec2;
+    b : std_logic;
+  end record;
+end rec06_pkg;
diff --git a/testsuite/synth/dispout01/pkg_rec07.vhdl b/testsuite/synth/dispout01/pkg_rec07.vhdl
new file mode 100644
index 000000000..7c5775b5c
--- /dev/null
+++ b/testsuite/synth/dispout01/pkg_rec07.vhdl
@@ -0,0 +1,9 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package rec07_pkg is
+  type myrec is record
+     a : bit_vector (3 downto 0);
+     b : std_logic;
+  end record;
+end rec07_pkg;
diff --git a/testsuite/synth/dispout01/pkg_rec08.vhdl b/testsuite/synth/dispout01/pkg_rec08.vhdl
new file mode 100644
index 000000000..cebafe904
--- /dev/null
+++ b/testsuite/synth/dispout01/pkg_rec08.vhdl
@@ -0,0 +1,9 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package rec08_pkg is
+  type myrec is record
+     a : bit_vector (0 downto 0);
+     b : std_logic;
+  end record;
+end rec08_pkg;
diff --git a/testsuite/synth/dispout01/rec01.vhdl b/testsuite/synth/dispout01/rec01.vhdl
new file mode 100644
index 000000000..eee090ec2
--- /dev/null
+++ b/testsuite/synth/dispout01/rec01.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec01_pkg.all;
+
+entity rec01 is
+  port (inp : std_logic;
+        o : out myrec);
+end rec01;
+
+architecture behav of rec01 is
+begin
+  o.a <= inp;
+  o.b <= not inp;
+end behav;
diff --git a/testsuite/synth/dispout01/rec02.vhdl b/testsuite/synth/dispout01/rec02.vhdl
new file mode 100644
index 000000000..a93bc9f30
--- /dev/null
+++ b/testsuite/synth/dispout01/rec02.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec02_pkg.all;
+
+entity rec02 is
+  port (inp : std_logic;
+        o : out myrec);
+end rec02;
+
+architecture behav of rec02 is
+begin
+  o.b <= not inp;
+  o.a <= 3 when inp = '1' else 5;
+end behav;
diff --git a/testsuite/synth/dispout01/rec03.vhdl b/testsuite/synth/dispout01/rec03.vhdl
new file mode 100644
index 000000000..763f83a72
--- /dev/null
+++ b/testsuite/synth/dispout01/rec03.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec03_pkg.all;
+
+entity rec03 is
+  port (inp : std_logic;
+        o : out myrec);
+end rec03;
+
+architecture behav of rec03 is
+begin
+  o.b <= not inp;
+  o.a <= s3 when inp = '0' else s0;
+end behav;
diff --git a/testsuite/synth/dispout01/rec04.vhdl b/testsuite/synth/dispout01/rec04.vhdl
new file mode 100644
index 000000000..15fab1f6e
--- /dev/null
+++ b/testsuite/synth/dispout01/rec04.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec04_pkg.all;
+
+entity rec04 is
+  port (inp : std_logic;
+        o : out myrec);
+end rec04;
+
+architecture behav of rec04 is
+begin
+  o.b <= not inp;
+  o.a <= "0001" when inp = '1' else "1000";
+end behav;
diff --git a/testsuite/synth/dispout01/rec05.vhdl b/testsuite/synth/dispout01/rec05.vhdl
new file mode 100644
index 000000000..1d5623dce
--- /dev/null
+++ b/testsuite/synth/dispout01/rec05.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec05_pkg.all;
+
+entity rec05 is
+  port (inp : std_logic;
+        o : out myrec);
+end rec05;
+
+architecture behav of rec05 is
+begin
+  o.b <= not inp;
+  o.a <= "0101" when inp = '0' else "1010";
+end behav;
diff --git a/testsuite/synth/dispout01/rec06.vhdl b/testsuite/synth/dispout01/rec06.vhdl
new file mode 100644
index 000000000..8cebf82b8
--- /dev/null
+++ b/testsuite/synth/dispout01/rec06.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.rec06_pkg.all;
+
+entity rec06 is
+  port (inp : std_logic;
+        o : out myrec);
+end rec06;
+
+architecture behav of rec06 is
+begin
+  o.b <= not inp;
+  o.a.c <= 2 when inp = '1' else 3;
+  o.a.d <= "0000" when inp = '0' else "1000";
+end behav;
diff --git a/testsuite/synth/dispout01/rec07.vhdl b/testsuite/synth/dispout01/rec07.vhdl
new file mode 100644
index 000000000..f34c00483
--- /dev/null
+++ b/testsuite/synth/dispout01/rec07.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec07_pkg.all;
+
+entity rec07 is
+  port (inp : std_logic;
+        o : out myrec);
+end rec07;
+
+architecture behav of rec07 is
+begin
+  o.b <= not inp;
+  o.a <= "0001" when inp = '1' else "1000";
+end behav;
diff --git a/testsuite/synth/dispout01/rec08.vhdl b/testsuite/synth/dispout01/rec08.vhdl
new file mode 100644
index 000000000..cb56af4a1
--- /dev/null
+++ b/testsuite/synth/dispout01/rec08.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec08_pkg.all;
+
+entity rec08 is
+  port (inp : std_logic;
+        o : out myrec);
+end rec08;
+
+architecture behav of rec08 is
+begin
+  o.b <= not inp;
+  o.a <= "1" when inp = '1' else "0";
+end behav;
diff --git a/testsuite/synth/dispout01/tb_rec01.vhdl b/testsuite/synth/dispout01/tb_rec01.vhdl
new file mode 100644
index 000000000..7ec57d949
--- /dev/null
+++ b/testsuite/synth/dispout01/tb_rec01.vhdl
@@ -0,0 +1,27 @@
+entity tb_rec01 is
+end tb_rec01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec01_pkg.all;
+
+architecture behav of tb_rec01 is
+  signal inp : std_logic;
+  signal r : myrec;
+begin
+  dut: entity work.rec01
+    port map (inp => inp, o => r);
+
+  process
+  begin
+    inp <= '0';
+    wait for 1 ns;
+    assert r = (a => '0', b => '1') severity failure;
+
+    inp <= '1';
+    wait for 1 ns;
+    assert r = (a => '1', b => '0') severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dispout01/tb_rec02.vhdl b/testsuite/synth/dispout01/tb_rec02.vhdl
new file mode 100644
index 000000000..6bfb1ea80
--- /dev/null
+++ b/testsuite/synth/dispout01/tb_rec02.vhdl
@@ -0,0 +1,27 @@
+entity tb_rec02 is
+end tb_rec02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec02_pkg.all;
+
+architecture behav of tb_rec02 is
+  signal inp : std_logic;
+  signal r : myrec;
+begin
+  dut: entity work.rec02
+    port map (inp => inp, o => r);
+
+  process
+  begin
+    inp <= '0';
+    wait for 1 ns;
+    assert r = (b => '1', a => 5)  severity failure;
+
+    inp <= '1';
+    wait for 1 ns;
+    assert r = (b => '0', a => 3)  severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dispout01/tb_rec03.vhdl b/testsuite/synth/dispout01/tb_rec03.vhdl
new file mode 100644
index 000000000..982c8d7e6
--- /dev/null
+++ b/testsuite/synth/dispout01/tb_rec03.vhdl
@@ -0,0 +1,27 @@
+entity tb_rec03 is
+end tb_rec03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec03_pkg.all;
+
+architecture behav of tb_rec03 is
+  signal inp : std_logic;
+  signal r : myrec;
+begin
+  dut: entity work.rec03
+    port map (inp => inp, o => r);
+
+  process
+  begin
+    inp <= '1';
+    wait for 1 ns;
+    assert r = (a => s0, b => '0') severity failure;
+
+    inp <= '0';
+    wait for 1 ns;
+    assert r = (a => s3, b => '1') severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dispout01/tb_rec04.vhdl b/testsuite/synth/dispout01/tb_rec04.vhdl
new file mode 100644
index 000000000..fd91b32c8
--- /dev/null
+++ b/testsuite/synth/dispout01/tb_rec04.vhdl
@@ -0,0 +1,27 @@
+entity tb_rec04 is
+end tb_rec04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec04_pkg.all;
+
+architecture behav of tb_rec04 is
+  signal inp : std_logic;
+  signal r : myrec;
+begin
+  dut: entity work.rec04
+    port map (inp => inp, o => r);
+
+  process
+  begin
+    inp <= '1';
+    wait for 1 ns;
+    assert r = (a => "0001", b => '0') severity failure;
+
+    inp <= '0';
+    wait for 1 ns;
+    assert r = (a => "1000", b => '1') severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dispout01/tb_rec05.vhdl b/testsuite/synth/dispout01/tb_rec05.vhdl
new file mode 100644
index 000000000..40139d156
--- /dev/null
+++ b/testsuite/synth/dispout01/tb_rec05.vhdl
@@ -0,0 +1,27 @@
+entity tb_rec05 is
+end tb_rec05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec05_pkg.all;
+
+architecture behav of tb_rec05 is
+  signal inp : std_logic;
+  signal r : myrec;
+begin
+  dut: entity work.rec05
+    port map (inp => inp, o => r);
+
+  process
+  begin
+    inp <= '1';
+    wait for 1 ns;
+    assert r = (a => "1010", b => '0') severity failure;
+
+    inp <= '0';
+    wait for 1 ns;
+    assert r = (a => "0101", b => '1') severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dispout01/tb_rec06.vhdl b/testsuite/synth/dispout01/tb_rec06.vhdl
new file mode 100644
index 000000000..9da1579bc
--- /dev/null
+++ b/testsuite/synth/dispout01/tb_rec06.vhdl
@@ -0,0 +1,27 @@
+entity tb_rec06 is
+end tb_rec06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec06_pkg.all;
+
+architecture behav of tb_rec06 is
+  signal inp : std_logic;
+  signal r : myrec;
+begin
+  dut: entity work.rec06
+    port map (inp => inp, o => r);
+
+  process
+  begin
+    inp <= '1';
+    wait for 1 ns;
+    assert r = (a => (c => 2, d => "1000"), b => '0') severity failure;
+
+    inp <= '0';
+    wait for 1 ns;
+    assert r = (a => (c => 3, d => "0000"), b => '1') severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dispout01/tb_rec07.vhdl b/testsuite/synth/dispout01/tb_rec07.vhdl
new file mode 100644
index 000000000..75cb59de2
--- /dev/null
+++ b/testsuite/synth/dispout01/tb_rec07.vhdl
@@ -0,0 +1,27 @@
+entity tb_rec07 is
+end tb_rec07;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec07_pkg.all;
+
+architecture behav of tb_rec07 is
+  signal inp : std_logic;
+  signal r : myrec;
+begin
+  dut: entity work.rec07
+    port map (inp => inp, o => r);
+
+  process
+  begin
+    inp <= '1';
+    wait for 1 ns;
+    assert r = (a => "0001", b => '0') severity failure;
+
+    inp <= '0';
+    wait for 1 ns;
+    assert r = (a => "1000", b => '1') severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dispout01/tb_rec08.vhdl b/testsuite/synth/dispout01/tb_rec08.vhdl
new file mode 100644
index 000000000..8224c4b14
--- /dev/null
+++ b/testsuite/synth/dispout01/tb_rec08.vhdl
@@ -0,0 +1,27 @@
+entity tb_rec08 is
+end tb_rec08;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec08_pkg.all;
+
+architecture behav of tb_rec08 is
+  signal inp : std_logic;
+  signal r : myrec;
+begin
+  dut: entity work.rec08
+    port map (inp => inp, o => r);
+
+  process
+  begin
+    inp <= '1';
+    wait for 1 ns;
+    assert r = (a => "1", b => '0') severity failure;
+
+    inp <= '0';
+    wait for 1 ns;
+    assert r = (a => "0", b => '1') severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dispout01/testsuite.sh b/testsuite/synth/dispout01/testsuite.sh
new file mode 100755
index 000000000..94d07f0e2
--- /dev/null
+++ b/testsuite/synth/dispout01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in rec01 rec02 rec03 rec04 rec05 rec06 rec07 rec08; do
+    analyze pkg_$t.vhdl $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth pkg_$t.vhdl $t.vhdl -e $t > syn_$t.vhdl
+    analyze pkg_$t.vhdl syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"