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authorTristan Gingold <tgingold@free.fr>2019-11-08 19:30:16 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-11 20:25:42 +0100
commitcca6f6179bdf5e85e4b63d822c61a5a04def53a4 (patch)
tree32fbcebeda5c3d4c78dbb3786fafa85ff7480cbf /testsuite/synth/dff02
parentf3c6b53fd39049e8bda611dc98a50e93ceb7be39 (diff)
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testsuite/synth: add an incorrectly handled dff.
Diffstat (limited to 'testsuite/synth/dff02')
-rw-r--r--testsuite/synth/dff02/dff09.vhdl24
-rw-r--r--testsuite/synth/dff02/tb_dff09.vhdl49
-rwxr-xr-xtestsuite/synth/dff02/testsuite.sh2
3 files changed, 74 insertions, 1 deletions
diff --git a/testsuite/synth/dff02/dff09.vhdl b/testsuite/synth/dff02/dff09.vhdl
new file mode 100644
index 000000000..9ce4d14c4
--- /dev/null
+++ b/testsuite/synth/dff02/dff09.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff09 is
+ port (q : out std_logic_vector(3 downto 0);
+ d : std_logic_vector(3 downto 0);
+ clk : std_logic;
+ rst : std_logic);
+end dff09;
+
+architecture behav of dff09 is
+begin
+ process (clk, rst) is
+ begin
+ if rst = '1' then
+ for i in q'range loop
+ q(i) <= '0';
+ end loop;
+ -- q <= x"0";
+ elsif rising_edge (clk) then
+ q <= d;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff02/tb_dff09.vhdl b/testsuite/synth/dff02/tb_dff09.vhdl
new file mode 100644
index 000000000..49b017690
--- /dev/null
+++ b/testsuite/synth/dff02/tb_dff09.vhdl
@@ -0,0 +1,49 @@
+entity tb_dff09 is
+end tb_dff09;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff09 is
+ signal clk : std_logic;
+ signal rst : std_logic;
+ signal din : std_logic_vector (3 downto 0);
+ signal dout : std_logic_vector (3 downto 0);
+begin
+ dut: entity work.dff09
+ port map (
+ q => dout,
+ d => din,
+ clk => clk,
+ rst => rst);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ rst <= '1';
+ pulse;
+ assert dout = x"0" severity failure;
+
+ rst <= '0';
+ din <= x"3";
+ pulse;
+ assert dout = x"3" severity failure;
+
+ din <= x"a";
+ pulse;
+ assert dout = x"a" severity failure;
+
+ rst <= '1';
+ din <= x"5";
+ pulse;
+ assert dout = x"0" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff02/testsuite.sh b/testsuite/synth/dff02/testsuite.sh
index a479311ea..aa13c2c90 100755
--- a/testsuite/synth/dff02/testsuite.sh
+++ b/testsuite/synth/dff02/testsuite.sh
@@ -2,7 +2,7 @@
. ../../testenv.sh
-for t in dff05 dff06 dff08; do
+for t in dff05 dff06 dff08 dff09; do
analyze $t.vhdl tb_$t.vhdl
elab_simulate tb_$t
clean