testsuite/synth/dff02/dff09.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

library ieee;
use ieee.std_logic_1164.all;

entity dff09 is
  port (q : out std_logic_vector(3 downto 0);
        d : std_logic_vector(3 downto 0);
        clk : std_logic;
        rst : std_logic);
end dff09;

architecture behav of dff09 is
begin
  process (clk, rst) is
  begin
    if rst = '1' then
      for i in q'range loop
        q(i) <= '0';
      end loop;
      --  q <= x"0";
    elsif rising_edge (clk) then
      q <= d;
    end if;
  end process;
end behav;