testsuite/synth: add cases for assign.

4 files changed, 62 insertions, 4 deletions

diff --git a/testsuite/synth/asgn01/asgn02.vhdl b/testsuite/synth/asgn01/asgn02.vhdl
index f83690d8b..bb024de55 100644
--- a/testsuite/synth/asgn01/asgn02.vhdl
+++ b/testsuite/synth/asgn01/asgn02.vhdl
@@ -2,14 +2,13 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 entity asgn02 is
-  port (a : std_logic_vector (2 downto 0);
-        s0 : std_logic;
+  port (s0 : std_logic;
         r : out std_logic_vector (2 downto 0));
 end asgn02;
 
 architecture behav of asgn02 is
 begin
-  process (a, s0) is
+  process (s0) is
   begin
     r <= "000";
     if s0 = '1' then
diff --git a/testsuite/synth/asgn01/tb_asgn01.vhdl b/testsuite/synth/asgn01/tb_asgn01.vhdl
new file mode 100644
index 000000000..3c2ec076c
--- /dev/null
+++ b/testsuite/synth/asgn01/tb_asgn01.vhdl
@@ -0,0 +1,33 @@
+entity tb_asgn01 is
+end tb_asgn01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_asgn01 is
+  signal a  : std_logic_vector (2 downto 0);
+  signal s0 : std_logic;
+  signal r  : std_logic_vector (2 downto 0);
+begin
+  dut: entity work.asgn01
+    port map (a => a, s0 => s0, r => r);
+
+  process
+  begin
+    s0 <= '1';
+    wait for 1 ns;
+    assert r = "000" severity failure;
+
+    a <= "101";
+    s0 <= '0';
+    wait for 1 ns;
+    assert r = "101" severity failure;
+
+    a <= "110";
+    s0 <= '0';
+    wait for 1 ns;
+    assert r = "110" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/tb_asgn02.vhdl b/testsuite/synth/asgn01/tb_asgn02.vhdl
new file mode 100644
index 000000000..76382a71b
--- /dev/null
+++ b/testsuite/synth/asgn01/tb_asgn02.vhdl
@@ -0,0 +1,26 @@
+entity tb_asgn02 is
+end tb_asgn02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_asgn02 is
+  signal s0 : std_logic;
+  signal r  : std_logic_vector (2 downto 0);
+begin
+  dut: entity work.asgn02
+    port map (s0 => s0, r => r);
+
+  process
+  begin
+    s0 <= '1';
+    wait for 1 ns;
+    assert r = "010" severity failure;
+
+    s0 <= '0';
+    wait for 1 ns;
+    assert r = "000" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/testsuite.sh b/testsuite/synth/asgn01/testsuite.sh
index 8595e02ab..cb5ed0fb6 100755
--- a/testsuite/synth/asgn01/testsuite.sh
+++ b/testsuite/synth/asgn01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in arr04; do
+for t in asgn01 asgn02 arr04; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean