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| author | Tristan Gingold <tgingold@free.fr> | 2022-03-18 07:57:01 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-03-18 07:57:28 +0100 |
| commit | f1b1d83f51b3fc3415d870d35ed0eba2a98c7cd9 (patch) | |
| tree | babda7bfdc89101117a9c901fba7ff0f97b76165 /src | |
| parent | 2b6ce11b696a9e138f477c6325804e085dfbe771 (diff) | |
| download | ghdl-f1b1d83f51b3fc3415d870d35ed0eba2a98c7cd9.tar.gz ghdl-f1b1d83f51b3fc3415d870d35ed0eba2a98c7cd9.tar.bz2 ghdl-f1b1d83f51b3fc3415d870d35ed0eba2a98c7cd9.zip | |
synth-vhdl_context: adjust mask. Fix #2011
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_context.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index a01ad9db0..472d5ea4f 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -221,7 +221,7 @@ package body Synth.Vhdl_Context is end loop; pragma Assert (Vec'Last = Digit_Index ((W - 1) / 32)); - Mask := Shift_Right (not 0, 32 - Natural (W mod 32)); + Mask := Shift_Right (not 0, (32 - Natural (W mod 32)) mod 32); if (Vec (Vec'Last).Val and Mask) /= (Val and Mask) or else (Vec (Vec'Last).Zx and Mask) /= (Zx and Mask) then |