From f1b1d83f51b3fc3415d870d35ed0eba2a98c7cd9 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 18 Mar 2022 07:57:01 +0100 Subject: synth-vhdl_context: adjust mask. Fix #2011 --- src/synth/synth-vhdl_context.adb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index a01ad9db0..472d5ea4f 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -221,7 +221,7 @@ package body Synth.Vhdl_Context is end loop; pragma Assert (Vec'Last = Digit_Index ((W - 1) / 32)); - Mask := Shift_Right (not 0, 32 - Natural (W mod 32)); + Mask := Shift_Right (not 0, (32 - Natural (W mod 32)) mod 32); if (Vec (Vec'Last).Val and Mask) /= (Val and Mask) or else (Vec (Vec'Last).Zx and Mask) /= (Zx and Mask) then -- cgit v1.2.3