first cut at spartan 6 fpga

8 files changed, 595 insertions, 0 deletions

diff --git a/spartan6/hp_lcd_driver/.gitignore b/spartan6/hp_lcd_driver/.gitignore
new file mode 100644
index 0000000..567609b
--- /dev/null
+++ b/spartan6/hp_lcd_driver/.gitignore
@@ -0,0 +1 @@
+build/
diff --git a/spartan6/hp_lcd_driver/Makefile b/spartan6/hp_lcd_driver/Makefile
new file mode 100644
index 0000000..d526ede
--- /dev/null
+++ b/spartan6/hp_lcd_driver/Makefile
@@ -0,0 +1,288 @@
+include relpath.mk
+
+PART=xc6slx9-2-tqg144
+TOP=hp_lcd_driver
+BUILD=build
+VSRCS=hp_lcd_driver.vhd
+UCF=hp_lcd_driver.ucf
+UT=hp_lcd_driver.ut
+IPSRCS=vram.xco
+
+DESIGN_NAME=${TOP}
+ISE_BINDIR=/software/apps/xilinx/ISE/14.7/ISE_DS/ISE/bin/lin64
+INTSTYLE=
+
+XST_FLAGS=${INTSTYLE}
+NGDBUILD_FLAGS=${INTSTYLE} -p ${PART} -dd _ngo -nt timestamp
+MAP_FLAGS=${INTSTYLE} -p ${PART} -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off 
+PAR_FLAGS=${INTSTYLE} -w -ol high -mt off 
+TRCE_FLAGS=${INTSTYLE} -v 3 -s 2 -n 3 -fastpaths
+BITGEN_FLAGS=${INTSTYLE} 
+
+
+
+GEN_VSRCS=${IPSRCS:%.xco=${BUILD}/%.vhd}
+BASE=${BUILD}/${DESIGN_NAME}
+XST=${BASE}.xst
+PRJ=${BASE}.prj
+SYR=${BASE}.syr
+NGC=${BASE}.ngc
+NGD=${BASE}.ngd
+MAP_NCD=${BASE}_map.ncd
+NCD=${BASE}.ncd
+PCF=${BASE}.pcf
+TWR=${BASE}.twr
+TWX=${BASE}.twx
+BIT=${BASE}.bit
+SVF=${BASE}.svf
+
+XST_TMPDIR=xst/projnav.tmp
+XST_DIR=xst
+
+
+
+default: ${NCD} ${TWR} ${TWX} ${BIT} ${SVF}
+
+clean: 
+	/bin/rm -rf ${BUILD}
+
+${PRJ}: ${VSRCS} ${GEN_VSRCS}
+	mkdir -p ${BUILD}
+	rm -f  $@
+	for file in $(GEN_VSRCS) ${VSRCS}; do \
+	echo "vhdl work $$(realpath -m --relative-to=${BUILD} $${file})" >> $@ ; \
+	done ;
+
+${NGC}:${XST}
+	(cd ${BUILD} && mkdir -p ${XST_DIR} ${XST_TMPDIR} && ${ISE_BINDIR}/xst ${XST_FLAGS} -ifn $(call relpath,$<,${BUILD}) -ofn $(call relpath,${SYR},${BUILD}))
+
+${XST}: ${PRJ} ${DESIGN_NAME}.xst_template
+	rm -f  $@
+	echo 'set -tmpdir "${XST_TMPDIR}"' >> $@
+	echo 'set -xsthdpdir "${XST_DIR}"' >> $@
+	cat  ${DESIGN_NAME}.xst_template >> $@
+	echo "-ifn $(call relpath,${PRJ},${BUILD})" >> $@ 
+	echo "-ofn $(call relpath,${BASE},${BUILD})" >> $@ 
+	echo "-p ${PART}" >> $@
+	echo "-top ${TOP}" >> $@
+
+${NGD}:${NGC} ${UCF}
+	(cd ${BUILD} && ${ISE_BINDIR}/ngdbuild $(NGDBUILD_FLAGS) -uc $(call relpath,${UCF},${BUILD}) $(call relpath,${NGC},${BUILD}) $(call relpath,$@,${BUILD}))
+
+${MAP_NCD} ${PCF}:${NGD}
+	(cd ${BUILD} && ${ISE_BINDIR}/map $(MAP_FLAGS) -o $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NGD},${BUILD})  $(call relpath,${PCF},${BUILD}))
+
+${NCD}: ${MAP_NCD} ${PCF}
+	(cd ${BUILD} && ${ISE_BINDIR}/par $(PAR_FLAGS) $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NCD},${BUILD}) $(call relpath,${PCF},${BUILD}))
+
+${TWR} ${TWX}: ${NCD} ${PCF}
+	(cd ${BUILD} && ${ISE_BINDIR}/trce ${TRCE_FLAGS} -xml $(call relpath,${TWX},${BUILD}) $(call relpath,${NCD},${BUILD}) -o $(call relpath,${TWR},${BUILD}) $(call relpath,${PCF},${BUILD}))
+
+${BIT}:${NCD} ${UT}
+	(cd ${BUILD} && ${ISE_BINDIR}/bitgen ${BITGEN_FLAGS} -f  $(call relpath,${UT},${BUILD}) $(call relpath,${NCD},${BUILD}))
+
+${SVF}:${BIT}
+	( cd ${BUILD} && \
+	echo -e "setMode -bs \n\
+	setCable -p svf -file \"$(call relpath,${SVF},${BUILD})\"  \n\
+	addDevice -p 1 -file \"$(call relpath,${BIT},${BUILD})\" \n\
+	program -p 1 \n\
+	quit \n" > impact.run &&\
+	${ISE_BINDIR}/impact -batch impact.run)
+
+
+${BUILD}/%.vhd:%.xco
+	mkdir -p ${BUILD}
+	(cd ${BUILD} && touch empty.prj  && ${ISE_BINDIR}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj)
+
+
+#
+#
+##
+## Flags and option values that control the behavior of the Xilinx tools.
+## You can override these values in the makefile that includes this one.
+## Otherwise, the default values will be set as shown below.
+##
+#
+## Unless otherwise specified, the name of the design and the top-level
+## entity are derived from the name of the directory that contains the design.
+#DIR_SPACES  := $(subst /, ,$(CURDIR))
+#DIR_NAME    := $(word $(words $(DIR_SPACES)), $(DIR_SPACES))
+#DESIGN_NAME ?= $(DIR_NAME)
+#TOP_NAME    ?= $(DESIGN_NAME)
+#SYNTH_DIR   ?= .
+#SIM_DIR   ?= .
+#
+## Extract the part identifier from the project .npl file.
+#PART_TYPE        ?=            $(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVICE)
+#PART_SPEED_GRADE ?= $(subst -,,$(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVSPEED))
+#PART_PACKAGE     ?=            $(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVPKG)
+#PART             ?= $(PART_TYPE)-$(PART_SPEED_GRADE)-$(PART_PACKAGE)
+#
+## Flags common to both FPGA design flow.
+#INTSTYLE         ?= -intstyle silent      # call Xilinx tools in silent mode
+#XST_FLAGS        ?= $(INTSTYLE)           # most synthesis flags are specified in the .xst file
+#UCF_FILE         ?= $(DESIGN_NAME).ucf    # constraint/pin-assignment file
+#NGDBUILD_FLAGS   ?= $(INTSTYLE) -dd _ngo  # ngdbuild flags
+#NGDBUILD_FLAGS += $(if $(UCF_FILE),-uc,) $(UCF_FILE)         # append the UCF file option if it is specified 
+#
+## Flags for FPGA-specific tools.  These were extracted by looking in the
+## .cmd_log file after compiling the design with the WebPACK/ISE GUI.
+#MAP_FLAGS        ?= $(INTSTYLE) -cm area -pr b -c 100 -tx off
+#PAR_FLAGS        ?= $(INTSTYLE) -w -ol std -t 1
+#TRCE_FLAGS       ?= $(INTSTYLE) -e 3 -l 3
+#BITGEN_FLAGS     ?= $(INTSTYLE) -w        # most bitgen flags are specified in the .ut file
+#PROMGEN_FLAGS    ?= -u 0                  # flags that control the MCS/EXO file generation
+#
+## Determine the version of Xilinx ISE that is being used by reading it from the
+## readme.txt file in the top-level directory of the Xilinx software.
+#PROJNAV_DIR ?= .
+#
+#XST_FPGA_OPTIONS_FILE ?= $(PROJNAV_DIR)/$(DESIGN_NAME).xst
+#BITGEN_OPTIONS_FILE   ?= $(DESIGN_NAME).ut
+#XST_OPTIONS_FILE       = $(XST_FPGA_OPTIONS_FILE)
+#
+#
+#
+##
+## The following rules describe how to compile the design to an FPGA
+##
+#
+#HDL_FILES := $(foreach file,$(SRCS_SYNTH),$(SYNTH_DIR)/$(file))
+#SIM_FILES := $(foreach file,$(SRCS_SIM),$(SIM_DIR)/$(file))
+#
+## default target
+#all: bit
+#
+#
+## cleanup the source code to make it look nice
+#%.nice: %.vhd
+#	$(EMACS) -batch $< -f vhdl-beautify-buffer -f save-buffer
+#	$(RM) $<~
+#
+##PRJ FIle generation
+#%.prj:
+#	rm -f  $(DESIGN_NAME).prj;
+#	for file in $(HDL_FILES); do \
+#	echo "vhdl work $${file}" >> $(DESIGN_NAME).prj ; \
+#	done ;
+#
+#%.ut:
+#	cp -n $(UTILITY_DIR)/default.ut $(DESIGN_NAME).ut
+#
+#%.xst:
+#	cp -n $(UTILITY_DIR)/default.xst $(DESIGN_NAME).xst
+#
+#%.ucf:
+#	cp -n $(UTILITY_DIR)/default.ucf $(UCF_FILE)
+#
+#
+#
+#
+#
+## Synthesize the HDL files into an NGC file.  This rule is triggered if
+## any of the HDL files are changed or the synthesis options are changed.
+#%.ngc: $(HDL_FILES) $(XST_OPTIONS_FILE) $(DESIGN_NAME).prj $(DESIGN_NAME).ut
+#	$(SET_OPTION_VALUES) $(XST_OPTIONS_FILE) \
+#		"set -tmpdir $(PROJNAV_DIR)" \
+#		"-lso $(DESIGN_NAME).lso" \
+#		"-ifn $(DESIGN_NAME).prj" \
+#		"-ofn $(DESIGN_NAME)" \
+#		"-p $(PART)" \
+#		"-top $(TOP_NAME)" \
+#			> $(PROJNAV_DIR)/tmp.xst
+#	${ISE_BINDIR}/xst $(XST_FLAGS) -ifn $(PROJNAV_DIR)/tmp.xst -ofn $*.syr
+#
+## Take the output of the synthesizer and create the NGD file.  This rule
+## will also be triggered if constraints file is changed.
+#%.ngd: %.ngc %.ucf
+#	${ISE_BINDIR}/ngdbuild $(NGDBUILD_FLAGS) -p $(PART) $*.ngc $*.ngd
+#
+## Map the NGD file and physical-constraints to the FPGA to create the mapped NCD file.
+#%_map.ncd %.pcf: %.ngd
+#	${ISE_BINDIR}/map $(MAP_FLAGS) -p $(PART) -o $*_map.ncd $*.ngd $*.pcf
+#
+## Place & route the mapped NCD file to create the final NCD file.
+#%.ncd: %_map.ncd %.pcf
+#	${ISE_BINDIR}/par $(PAR_FLAGS) $*_map.ncd $*.ncd $*.pcf
+#
+## Take the final NCD file and create an FPGA bitstream file.  This rule will also be
+## triggered if the bit generation options file is changed.
+#%.bit: %.ncd $(BITGEN_OPTIONS_FILE)
+#	${ISE_BINDIR}/bitgen $(BITGEN_FLAGS) -f $(BITGEN_OPTIONS_FILE) $*.ncd
+#
+## Convert a bitstream file into an MCS hex file that can be stored into Flash memory.
+#%.mcs: %.bit
+#	${ISE_BINDIR}/promgen $(PROMGEN_FLAGS) $*.bit -p mcs
+#
+## Convert a bitstream file into an EXO hex file that can be stored into Flash memory.
+#%.exo: %.bit
+#	${ISE_BINDIR}/promgen $(PROMGEN_FLAGS) $*.bit -p exo
+#
+## Use .config suffix to trigger creation of a bit/svf file
+## depending upon whether an FPGA is the target device.
+#%.config: %.bit ;
+#
+## Create the FPGA timing report after place & route.
+#%.twr: %.ncd %.pcf
+#	${ISE_BINDIR}/trce $(TRCE_FLAGS) $*.ncd -o $*.twr $*.pcf
+#
+## Use .timing suffix to trigger timing report creation.
+#%.timing: %.twr ;
+#
+## Preserve intermediate files.
+#.PRECIOUS: %.ngc %.ngd %_map.ncd %.ncd %.twr %.vm6 %.jed %.prj %.ut %.xst %.ucf
+#
+## Clean up after creating the configuration file.
+#%.clean:
+#	-$(RM) *.stx *.ucf.untf *.mrp *.nc1 *.ngm *.prm *.lfp
+#	-$(RM) *.placed_ncd_tracker *.routed_ncd_tracker
+#	-$(RM) *.pad_txt *.twx *.log *.vhd~ *.dhp *.jhd *.cel
+#	-$(RM) *.ngr *.ngc *.ngd *.syr *.bld *.pcf
+#	-$(RM) *_map.mrp *_map.ncd *_map.ngm *.ncd *.pad *.bit
+#	-$(RM) *.par *.xpi *_pad.csv *_pad.txt *.drc *.bgn *.lso *.npl
+#	-$(RM) *.xml *_build.xml *.rpt *.gyd *.mfd *.pnx *.xrpt *.ptwx *.twr *.srp
+#	-$(RM) *.vm6 *.jed *.err *.ER result.txt tmperr.err *.bak *.vhd~
+#	-$(RM) *.zip *_backup *.*log *.map *.unroutes *.html
+#	-$(RM) impactcmd.txt tmp.xst impact.run *.wlf transcript
+#	-$(RMDIR) xst _ngo *_html __projnav xlnx_auto_* work
+#
+## Clean everything.
+#%.distclean: %.clean
+#	-$(RM) *.prj
+#
+#%.impact : $(DESIGN_NAME).bit
+#	echo -e "setMode -bs \n\
+#	setCable -p auto \n\
+#	identify  \n\
+#	assignFile -p 1 -file $(DESIGN_NAME).bit \n\
+#	program -p 1 \n\
+#	quit \n" > impact.run
+#	${ISE_BINDIR}/impact -batch impact.run
+#
+##Simulation using ModelSIM
+#setlib:
+#	${ISE_BINDIR}/vlib work
+#
+#vsim-compile: setlib $(SIM_FILES) $(HDL_FILES)
+#	${ISE_BINDIR}/vcom $(HDL_FILES)  $(SIM_FILES)
+#
+#vsim: vsim-compile
+#	${ISE_BINDIR}/vsim  $(TESTBENCH_NAME)
+#
+#vsim-run: vsim-compile
+#	${ISE_BINDIR}/vsim -c -do "run -all; quit" $(TESTBENCH_NAME)
+#
+##
+## Default targets for FPGA compilations.
+##
+#
+#config          : $(DESIGN_NAME).config
+#bit             : $(DESIGN_NAME).bit
+#mcs             : $(DESIGN_NAME).mcs
+#exo             : $(DESIGN_NAME).exo
+#timing          : $(DESIGN_NAME).timing
+#clean           : $(DESIGN_NAME).clean
+#distclean       : $(DESIGN_NAME).distclean
+#nice            : $(subst .vhd,.nice,$(HDL_FILES))
+#impact          : $(DESIGN_NAME).impact
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.ucf b/spartan6/hp_lcd_driver/hp_lcd_driver.ucf
new file mode 100644
index 0000000..8e67eae
--- /dev/null
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.ucf
@@ -0,0 +1,3 @@
+NET "hdmi_r" IOSTANDARD = LVCMOS33;
+NET "hdmi_b" LOC = P67;
+
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.ut b/spartan6/hp_lcd_driver/hp_lcd_driver.ut
new file mode 100644
index 0000000..ea9319f
--- /dev/null
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.ut
@@ -0,0 +1,30 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhd b/spartan6/hp_lcd_driver/hp_lcd_driver.vhd
new file mode 100644
index 0000000..9b7aac9
--- /dev/null
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhd
@@ -0,0 +1,84 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    13:20:32 04/26/2025 
+-- Design Name: 
+-- Module Name:    hp_lcd_driver - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity hp_lcd_driver is
+    Port ( clk_50m : in  STD_LOGIC;
+	   sys_rst_n : in STD_LOGIC;
+           hdmi_clk : out  STD_LOGIC;
+           hdmi_r : out  STD_LOGIC;
+           hdmi_g : out  STD_LOGIC;
+           hdmi_b : out  STD_LOGIC;
+           video : in  STD_LOGIC;
+           bright : in  STD_LOGIC;
+           hsync : in  STD_LOGIC;
+           vsync : in  STD_LOGIC);
+end hp_lcd_driver;
+
+architecture Behavioral of hp_lcd_driver is
+
+signal addr : std_logic_vector(17 downto 0);
+signal dout : std_logic_vector(1 downto 0);
+signal din : std_logic_vector(1 downto 0);
+
+begin
+
+hdmi_clk <= clk_50m;
+hdmi_b<='0';
+
+din <=(video,bright);
+
+vram0: entity work.vram
+	port map (
+	clka => clk_50m,
+	wea => "1",
+	addra => addr,
+	dina => din,
+	clkb => clk_50m,
+	addrb => addr,
+	doutb => dout
+);
+
+hdmi_g <= dout(0);
+hdmi_r <= dout(1);
+
+   process (sys_rst_n,clk_50m)  begin
+                if sys_rst_n = '0' then
+                        addr <=(others =>'0');
+                elsif rising_edge(clk_50m) then
+                   addr <= std_logic_vector(unsigned(addr)+1);
+                end if;
+        end process;
+
+
+
+end Behavioral;
+
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.xst_template b/spartan6/hp_lcd_driver/hp_lcd_driver.xst_template
new file mode 100644
index 0000000..b5f39c1
--- /dev/null
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.xst_template
@@ -0,0 +1,46 @@
+run
+-ofmt NGC
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/spartan6/hp_lcd_driver/relpath.mk b/spartan6/hp_lcd_driver/relpath.mk
new file mode 100644
index 0000000..ee42901
--- /dev/null
+++ b/spartan6/hp_lcd_driver/relpath.mk
@@ -0,0 +1,35 @@
+override define \s :=
+$() $()
+endef
+
+ifndef $(\s)
+override $(\s) :=
+else
+$(error Defined special variable '$(\s)': reserved for internal use)
+endif
+
+override define dirname
+$(patsubst %/,%,$(dir $(patsubst %/,%,$1)))
+endef
+
+override define prefix_1
+$(if $(or $\
+$(patsubst $(abspath $3)%,,$(abspath $1)),$\
+$(patsubst $(abspath $3)%,,$(abspath $2))),$\
+$(strip $(call prefix_1,$1,$2,$(call dirname,$3))),$\
+$(strip $(abspath $3)))
+endef
+
+override define prefix
+$(call prefix_1,$1,$2,$1)
+endef
+
+override define relpath_1
+$(patsubst /%,%,$(subst $(\s),/,$(patsubst %,..,$(subst /,$(\s),$\
+$(patsubst $3%,%,$(abspath $2)))))$\
+$(patsubst $3%,%,$(abspath $1)))
+endef
+
+override define relpath
+$(call relpath_1,$1,$2,$(call prefix,$1,$2))
+endef
diff --git a/spartan6/hp_lcd_driver/vram.xco b/spartan6/hp_lcd_driver/vram.xco
new file mode 100644
index 0000000..f4624c4
--- /dev/null
+++ b/spartan6/hp_lcd_driver/vram.xco
@@ -0,0 +1,108 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Sat Apr 26 13:15:00 2025
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:blk_mem_gen:7.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=vram
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Always_Enabled
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET mem_file=no_Mem_file_loaded
+CSET memory_type=Simple_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=2
+CSET read_width_b=2
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_bram_block=Stand_Alone
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=228096
+CSET write_width_a=2
+CSET write_width_b=2
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T16:22:25Z
+# END Extra information
+GENERATE
+# CRC: 74d82cad