add noddy cyclone IV fpga design

1 files changed, 26 insertions, 0 deletions

diff --git a/smh-ac415-fpga/lcd_driver/synchronizer.vhdl b/smh-ac415-fpga/lcd_driver/synchronizer.vhdl
new file mode 100644
index 0000000..99618b9
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/synchronizer.vhdl
@@ -0,0 +1,26 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity synchronizer is
+    generic (stages : natural := 2);
+    port (clk : in  std_logic;
+          i   : in  std_logic;
+          o   : out std_logic);
+end synchronizer;
+
+architecture Behavioral of synchronizer is
+    signal flipflops                 : std_logic_vector(stages-1 downto 0) := (others => '0');
+    attribute ASYNC_REG              : string;
+    attribute ASYNC_REG of flipflops : signal is "true";
+begin
+
+    o <= flipflops(flipflops'high);
+
+    clk_proc : process(clk,flipflops,i)
+    begin
+        if rising_edge(clk) then
+            flipflops <= flipflops(flipflops'high-1 downto 0) & i;
+        end if;
+    end process;
+
+end Behavioral;