From 6138bd2f72841f5af4bd7d8c089223be3fd23324 Mon Sep 17 00:00:00 2001 From: James McKenzie Date: Sun, 20 Apr 2025 18:17:56 +0100 Subject: add noddy cyclone IV fpga design --- smh-ac415-fpga/lcd_driver/synchronizer.vhdl | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 smh-ac415-fpga/lcd_driver/synchronizer.vhdl (limited to 'smh-ac415-fpga/lcd_driver/synchronizer.vhdl') diff --git a/smh-ac415-fpga/lcd_driver/synchronizer.vhdl b/smh-ac415-fpga/lcd_driver/synchronizer.vhdl new file mode 100644 index 0000000..99618b9 --- /dev/null +++ b/smh-ac415-fpga/lcd_driver/synchronizer.vhdl @@ -0,0 +1,26 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity synchronizer is + generic (stages : natural := 2); + port (clk : in std_logic; + i : in std_logic; + o : out std_logic); +end synchronizer; + +architecture Behavioral of synchronizer is + signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0'); + attribute ASYNC_REG : string; + attribute ASYNC_REG of flipflops : signal is "true"; +begin + + o <= flipflops(flipflops'high); + + clk_proc : process(clk,flipflops,i) + begin + if rising_edge(clk) then + flipflops <= flipflops(flipflops'high-1 downto 0) & i; + end if; + end process; + +end Behavioral; -- cgit v1.2.3