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author | root <root@new-fish.medaka.james.internal> | 2025-04-30 23:31:35 +0100 |
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committer | root <root@new-fish.medaka.james.internal> | 2025-04-30 23:31:35 +0100 |
commit | cff444eb1bd7bc498bc50dca506b745317bc3494 (patch) | |
tree | bc48b69e520f66f73eddefed6d430c03dc118b21 /fpga/hp_lcd_driver/synchronizer.vhdl | |
parent | 655dfad152b35b26f97db45b6723bfe7c91961f2 (diff) | |
download | hp_instrument_lcds-cff444eb1bd7bc498bc50dca506b745317bc3494.tar.gz hp_instrument_lcds-cff444eb1bd7bc498bc50dca506b745317bc3494.tar.bz2 hp_instrument_lcds-cff444eb1bd7bc498bc50dca506b745317bc3494.zip |
move fpga to fpga directory
Diffstat (limited to 'fpga/hp_lcd_driver/synchronizer.vhdl')
-rw-r--r-- | fpga/hp_lcd_driver/synchronizer.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/fpga/hp_lcd_driver/synchronizer.vhdl b/fpga/hp_lcd_driver/synchronizer.vhdl new file mode 100644 index 0000000..302cef9 --- /dev/null +++ b/fpga/hp_lcd_driver/synchronizer.vhdl @@ -0,0 +1,26 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity synchronizer is + generic (stages : natural := 2); + port (clk : in std_logic; + i : in std_logic; + o : out std_logic); +end synchronizer; + +architecture Behavioral of synchronizer is + signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0'); + attribute ASYNC_REG : string; + attribute ASYNC_REG of flipflops : signal is "true"; +begin + + o <= flipflops(flipflops'high); + + clk_proc : process(clk, flipflops, i) + begin + if rising_edge(clk) then + flipflops <= flipflops(flipflops'high-1 downto 0) & i; + end if; + end process; + +end Behavioral; |