From cff444eb1bd7bc498bc50dca506b745317bc3494 Mon Sep 17 00:00:00 2001 From: root Date: Wed, 30 Apr 2025 23:31:35 +0100 Subject: move fpga to fpga directory --- fpga/hp_lcd_driver/synchronizer.vhdl | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 fpga/hp_lcd_driver/synchronizer.vhdl (limited to 'fpga/hp_lcd_driver/synchronizer.vhdl') diff --git a/fpga/hp_lcd_driver/synchronizer.vhdl b/fpga/hp_lcd_driver/synchronizer.vhdl new file mode 100644 index 0000000..302cef9 --- /dev/null +++ b/fpga/hp_lcd_driver/synchronizer.vhdl @@ -0,0 +1,26 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity synchronizer is + generic (stages : natural := 2); + port (clk : in std_logic; + i : in std_logic; + o : out std_logic); +end synchronizer; + +architecture Behavioral of synchronizer is + signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0'); + attribute ASYNC_REG : string; + attribute ASYNC_REG of flipflops : signal is "true"; +begin + + o <= flipflops(flipflops'high); + + clk_proc : process(clk, flipflops, i) + begin + if rising_edge(clk) then + flipflops <= flipflops(flipflops'high-1 downto 0) & i; + end if; + end process; + +end Behavioral; -- cgit v1.2.3