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authorroot <root@new-fish.medaka.james.internal>2025-04-30 23:31:35 +0100
committerroot <root@new-fish.medaka.james.internal>2025-04-30 23:31:35 +0100
commitcff444eb1bd7bc498bc50dca506b745317bc3494 (patch)
treebc48b69e520f66f73eddefed6d430c03dc118b21 /fpga/hp_lcd_driver
parent655dfad152b35b26f97db45b6723bfe7c91961f2 (diff)
downloadhp_instrument_lcds-cff444eb1bd7bc498bc50dca506b745317bc3494.tar.gz
hp_instrument_lcds-cff444eb1bd7bc498bc50dca506b745317bc3494.tar.bz2
hp_instrument_lcds-cff444eb1bd7bc498bc50dca506b745317bc3494.zip
move fpga to fpga directory
Diffstat (limited to 'fpga/hp_lcd_driver')
-rw-r--r--fpga/hp_lcd_driver/.gitignore3
-rw-r--r--fpga/hp_lcd_driver/Makefile17
-rw-r--r--fpga/hp_lcd_driver/clkgen_cyclone4.vhdl63
-rw-r--r--fpga/hp_lcd_driver/clkgen_cyclone4_impl.vhdl461
-rw-r--r--fpga/hp_lcd_driver/clkgen_spartan6.vhdl73
-rw-r--r--fpga/hp_lcd_driver/debounce.vhdl32
-rw-r--r--fpga/hp_lcd_driver/edge_det.vhdl28
-rw-r--r--fpga/hp_lcd_driver/ep4ce15.cfg10
-rw-r--r--fpga/hp_lcd_driver/ep4ce15.mk126
-rw-r--r--fpga/hp_lcd_driver/ep4ce6.mk126
-rw-r--r--fpga/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft87
-rw-r--r--fpga/hp_lcd_driver/hp_lcd_driver.ep4ce6_qsft144
-rw-r--r--fpga/hp_lcd_driver/hp_lcd_driver.ucf34
-rw-r--r--fpga/hp_lcd_driver/hp_lcd_driver.ut30
-rw-r--r--fpga/hp_lcd_driver/hp_lcd_driver.vhdl221
-rw-r--r--fpga/hp_lcd_driver/hp_lcd_driver.xst_template46
-rw-r--r--fpga/hp_lcd_driver/input_formatter.vhdl142
-rw-r--r--fpga/hp_lcd_driver/input_stage.vhdl142
-rw-r--r--fpga/hp_lcd_driver/output_analog.vhdl82
-rw-r--r--fpga/hp_lcd_driver/output_formatter.vhdl137
-rw-r--r--fpga/hp_lcd_driver/output_stage.vhdl213
-rwxr-xr-xfpga/hp_lcd_driver/prog6
-rw-r--r--fpga/hp_lcd_driver/relpath.mk35
-rwxr-xr-xfpga/hp_lcd_driver/scripts/vhdl-pretty60
-rw-r--r--fpga/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl118
-rw-r--r--fpga/hp_lcd_driver/spartan6.mk129
-rw-r--r--fpga/hp_lcd_driver/synchronizer.vhdl26
-rw-r--r--fpga/hp_lcd_driver/tmds_encode.vhdl73
-rw-r--r--fpga/hp_lcd_driver/tmds_encoder.vhdl117
-rw-r--r--fpga/hp_lcd_driver/tmds_output_cyclone4.vhdl95
-rw-r--r--fpga/hp_lcd_driver/tmds_output_spartan6.vhdl121
-rw-r--r--fpga/hp_lcd_driver/tmds_phy_cyclone4.vhdl91
-rw-r--r--fpga/hp_lcd_driver/tmds_phy_spartan6.vhdl67
-rw-r--r--fpga/hp_lcd_driver/vram_cyclone4.vhdl35
-rw-r--r--fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl231
-rw-r--r--fpga/hp_lcd_driver/vram_spartan6.vhdl36
-rw-r--r--fpga/hp_lcd_driver/vram_spartan6_impl.xco108
-rw-r--r--fpga/hp_lcd_driver/xilinx_ise_vivado_license.lic868
38 files changed, 4433 insertions, 0 deletions
diff --git a/fpga/hp_lcd_driver/.gitignore b/fpga/hp_lcd_driver/.gitignore
new file mode 100644
index 0000000..8cdd988
--- /dev/null
+++ b/fpga/hp_lcd_driver/.gitignore
@@ -0,0 +1,3 @@
+build_spartan6/
+build_ep4ce15/
+build_ep4ce6/
diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
new file mode 100644
index 0000000..693085b
--- /dev/null
+++ b/fpga/hp_lcd_driver/Makefile
@@ -0,0 +1,17 @@
+TARGETS= ep4ce15 spartan6 #ep4ce6
+fish:ep4ce15
+default: ${TARGETS:%=build_%/hp_lcd_driver.svf}
+
+ep4ce15: build_ep4ce15/hp_lcd_driver.svf
+ep4ce6hp: build_ep4ce6/hp_lcd_driver.svf
+spartan6: build_spartan6/hp_lcd_driver.svf
+
+build_%/hp_lcd_driver.svf: dummy
+ ${MAKE} -f ${@:build_%/hp_lcd_driver.svf=%}.mk
+
+clean:
+ for i in ${TARGETS}; do ${MAKE} -f $$i.mk $@; done
+
+
+
+dummy:
diff --git a/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl b/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl
new file mode 100644
index 0000000..0c5b28f
--- /dev/null
+++ b/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl
@@ -0,0 +1,63 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+use work.all;
+
+entity clkgen is
+ port (
+ sys_rst_n : in std_logic;
+ clk_in : in std_logic;
+ i_clk : out std_logic;
+ o_clk : out std_logic;
+ o_clk_x2 : out std_logic;
+ o_clk_phy : out std_logic;
+ locked : out std_logic
+ );
+end clkgen;
+architecture Behavioural of clkgen is
+
+ signal clkfbout : std_logic;
+ signal clk_100m : std_logic;
+ signal clk_80m : std_logic;
+ signal clk_40m : std_logic;
+ signal clk_20m : std_logic;
+ signal pll_locked : std_logic;
+
+ signal reset : std_logic;
+begin
+
+ clkgen_impl0 : entity work.clkgen_cyclone4_impl
+ port map (
+ areset => not sys_rst_n,
+ inclk0 => clk_in,
+ c0 => clk_100m,
+ c1 => clk_80m,
+ c2 => clk_40m,
+ c3 => clk_20m,
+ locked => pll_locked);
+
+ o_clk <= clk_20m;
+-- o_clk_buf : BUFG port map (
+-- I => clk_20m,
+-- O => o_clk);
+--
+
+ o_clk_x2 <= clk_40m;
+
+-- o_clk_x2_buf : BUFG port map (
+-- I => clk_40m,
+-- O => o_clk_x2);
+--
+
+ i_clk <= clk_80m;
+-- i_clk_buf : BUFG port map (
+-- I => clk_80m,
+-- O => i_clk);
+--
+
+ o_clk_phy <= clk_100m;
+
+ locked <= pll_locked;
+
+
+end Behavioural;
diff --git a/fpga/hp_lcd_driver/clkgen_cyclone4_impl.vhdl b/fpga/hp_lcd_driver/clkgen_cyclone4_impl.vhdl
new file mode 100644
index 0000000..5a60e85
--- /dev/null
+++ b/fpga/hp_lcd_driver/clkgen_cyclone4_impl.vhdl
@@ -0,0 +1,461 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll
+
+-- ============================================================
+-- File Name: clkgen_cyclone4_impl.vhd
+-- Megafunction Name(s):
+-- altpll
+--
+-- Simulation Library Files(s):
+-- altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY clkgen_cyclone4_impl IS
+ PORT
+ (
+ areset : IN STD_LOGIC := '0';
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC ;
+ c1 : OUT STD_LOGIC ;
+ c2 : OUT STD_LOGIC ;
+ c3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+END clkgen_cyclone4_impl;
+
+
+ARCHITECTURE SYN OF clkgen_cyclone4_impl IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC ;
+ SIGNAL sub_wire4 : STD_LOGIC ;
+ SIGNAL sub_wire5 : STD_LOGIC ;
+ SIGNAL sub_wire6 : STD_LOGIC ;
+ SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+ COMPONENT altpll
+ GENERIC (
+ bandwidth_type : STRING;
+ clk0_divide_by : NATURAL;
+ clk0_duty_cycle : NATURAL;
+ clk0_multiply_by : NATURAL;
+ clk0_phase_shift : STRING;
+ clk1_divide_by : NATURAL;
+ clk1_duty_cycle : NATURAL;
+ clk1_multiply_by : NATURAL;
+ clk1_phase_shift : STRING;
+ clk2_divide_by : NATURAL;
+ clk2_duty_cycle : NATURAL;
+ clk2_multiply_by : NATURAL;
+ clk2_phase_shift : STRING;
+ clk3_divide_by : NATURAL;
+ clk3_duty_cycle : NATURAL;
+ clk3_multiply_by : NATURAL;
+ clk3_phase_shift : STRING;
+ compensate_clock : STRING;
+ inclk0_input_frequency : NATURAL;
+ intended_device_family : STRING;
+ lpm_hint : STRING;
+ lpm_type : STRING;
+ operation_mode : STRING;
+ pll_type : STRING;
+ port_activeclock : STRING;
+ port_areset : STRING;
+ port_clkbad0 : STRING;
+ port_clkbad1 : STRING;
+ port_clkloss : STRING;
+ port_clkswitch : STRING;
+ port_configupdate : STRING;
+ port_fbin : STRING;
+ port_inclk0 : STRING;
+ port_inclk1 : STRING;
+ port_locked : STRING;
+ port_pfdena : STRING;
+ port_phasecounterselect : STRING;
+ port_phasedone : STRING;
+ port_phasestep : STRING;
+ port_phaseupdown : STRING;
+ port_pllena : STRING;
+ port_scanaclr : STRING;
+ port_scanclk : STRING;
+ port_scanclkena : STRING;
+ port_scandata : STRING;
+ port_scandataout : STRING;
+ port_scandone : STRING;
+ port_scanread : STRING;
+ port_scanwrite : STRING;
+ port_clk0 : STRING;
+ port_clk1 : STRING;
+ port_clk2 : STRING;
+ port_clk3 : STRING;
+ port_clk4 : STRING;
+ port_clk5 : STRING;
+ port_clkena0 : STRING;
+ port_clkena1 : STRING;
+ port_clkena2 : STRING;
+ port_clkena3 : STRING;
+ port_clkena4 : STRING;
+ port_clkena5 : STRING;
+ port_extclk0 : STRING;
+ port_extclk1 : STRING;
+ port_extclk2 : STRING;
+ port_extclk3 : STRING;
+ self_reset_on_loss_lock : STRING;
+ width_clock : NATURAL
+ );
+ PORT (
+ areset : IN STD_LOGIC ;
+ clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+ inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+BEGIN
+ sub_wire8_bv(0 DOWNTO 0) <= "0";
+ sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
+ sub_wire5 <= sub_wire0(2);
+ sub_wire4 <= sub_wire0(0);
+ sub_wire2 <= sub_wire0(3);
+ sub_wire1 <= sub_wire0(1);
+ c1 <= sub_wire1;
+ c3 <= sub_wire2;
+ locked <= sub_wire3;
+ c0 <= sub_wire4;
+ c2 <= sub_wire5;
+ sub_wire6 <= inclk0;
+ sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+ altpll_component : altpll
+ GENERIC MAP (
+ bandwidth_type => "AUTO",
+ clk0_divide_by => 5,
+ clk0_duty_cycle => 50,
+ clk0_multiply_by => 12,
+ clk0_phase_shift => "0",
+ clk1_divide_by => 5,
+ clk1_duty_cycle => 50,
+ clk1_multiply_by => 8,
+ clk1_phase_shift => "0",
+ clk2_divide_by => 25,
+ clk2_duty_cycle => 50,
+ clk2_multiply_by => 24,
+ clk2_phase_shift => "0",
+ clk3_divide_by => 25,
+ clk3_duty_cycle => 50,
+ clk3_multiply_by => 12,
+ clk3_phase_shift => "0",
+ compensate_clock => "CLK0",
+ inclk0_input_frequency => 20000,
+ intended_device_family => "Cyclone IV E",
+ lpm_hint => "CBX_MODULE_PREFIX=clkgen_cyclone4_impl",
+ lpm_type => "altpll",
+ operation_mode => "NORMAL",
+ pll_type => "AUTO",
+ port_activeclock => "PORT_UNUSED",
+ port_areset => "PORT_USED",
+ port_clkbad0 => "PORT_UNUSED",
+ port_clkbad1 => "PORT_UNUSED",
+ port_clkloss => "PORT_UNUSED",
+ port_clkswitch => "PORT_UNUSED",
+ port_configupdate => "PORT_UNUSED",
+ port_fbin => "PORT_UNUSED",
+ port_inclk0 => "PORT_USED",
+ port_inclk1 => "PORT_UNUSED",
+ port_locked => "PORT_USED",
+ port_pfdena => "PORT_UNUSED",
+ port_phasecounterselect => "PORT_UNUSED",
+ port_phasedone => "PORT_UNUSED",
+ port_phasestep => "PORT_UNUSED",
+ port_phaseupdown => "PORT_UNUSED",
+ port_pllena => "PORT_UNUSED",
+ port_scanaclr => "PORT_UNUSED",
+ port_scanclk => "PORT_UNUSED",
+ port_scanclkena => "PORT_UNUSED",
+ port_scandata => "PORT_UNUSED",
+ port_scandataout => "PORT_UNUSED",
+ port_scandone => "PORT_UNUSED",
+ port_scanread => "PORT_UNUSED",
+ port_scanwrite => "PORT_UNUSED",
+ port_clk0 => "PORT_USED",
+ port_clk1 => "PORT_USED",
+ port_clk2 => "PORT_USED",
+ port_clk3 => "PORT_USED",
+ port_clk4 => "PORT_UNUSED",
+ port_clk5 => "PORT_UNUSED",
+ port_clkena0 => "PORT_UNUSED",
+ port_clkena1 => "PORT_UNUSED",
+ port_clkena2 => "PORT_UNUSED",
+ port_clkena3 => "PORT_UNUSED",
+ port_clkena4 => "PORT_UNUSED",
+ port_clkena5 => "PORT_UNUSED",
+ port_extclk0 => "PORT_UNUSED",
+ port_extclk1 => "PORT_UNUSED",
+ port_extclk2 => "PORT_UNUSED",
+ port_extclk3 => "PORT_UNUSED",
+ self_reset_on_loss_lock => "ON",
+ width_clock => 5
+ )
+ PORT MAP (
+ areset => areset,
+ inclk => sub_wire7,
+ clk => sub_wire0,
+ locked => sub_wire3
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "120.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "80.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "48.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "24.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "80.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "48.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen_cyclone4_impl.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "12"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "24"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "12"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/fpga/hp_lcd_driver/clkgen_spartan6.vhdl b/fpga/hp_lcd_driver/clkgen_spartan6.vhdl
new file mode 100644
index 0000000..7240abc
--- /dev/null
+++ b/fpga/hp_lcd_driver/clkgen_spartan6.vhdl
@@ -0,0 +1,73 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+use work.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clkgen is
+ port (
+ sys_rst_n : in std_logic;
+ clk_in : in std_logic;
+ i_clk : out std_logic;
+ o_clk : out std_logic;
+ o_clk_x2 : out std_logic;
+ o_clk_phy : out std_logic;
+ locked : out std_logic
+ );
+end clkgen;
+architecture Behavioural of clkgen is
+
+ signal clkfbout : std_logic;
+ signal clk_200m : std_logic;
+ signal clk_80m : std_logic;
+ signal clk_40m : std_logic;
+ signal clk_20m : std_logic;
+ signal pll_locked : std_logic;
+
+ signal reset : std_logic;
+begin
+
+ pll : PLL_BASE generic map (
+ CLKIN_PERIOD => 20.0,
+ CLKFBOUT_MULT => 8,
+ CLKOUT0_DIVIDE => 2,
+ CLKOUT1_DIVIDE => 5,
+ CLKOUT2_DIVIDE => 10,
+ CLKOUT3_DIVIDE => 20,
+ COMPENSATION => "INTERNAL")
+ port map (
+ CLKFBOUT => clkfbout,
+ CLKOUT0 => clk_200m,
+ CLKOUT1 => clk_80m,
+ CLKOUT2 => clk_40m,
+ CLKOUT3 => clk_20m,
+ LOCKED => pll_locked,
+ CLKFBIN => clkfbout,
+ CLKIN => clk_in,
+ RST => reset);
+
+ reset <= (not pll_locked) or (not sys_rst_n);
+
+
+
+ o_clk_buf : BUFG port map (
+ I => clk_20m,
+ O => o_clk);
+
+
+ o_clk_x2_buf : BUFG port map (
+ I => clk_40m,
+ O => o_clk_x2);
+
+
+ i_clk_buf : BUFG port map (
+ I => clk_80m,
+ O => i_clk);
+
+ o_clk_phy <= clk_200m;
+
+ locked <= pll_locked;
+
+end Behavioural;
diff --git a/fpga/hp_lcd_driver/debounce.vhdl b/fpga/hp_lcd_driver/debounce.vhdl
new file mode 100644
index 0000000..286367d
--- /dev/null
+++ b/fpga/hp_lcd_driver/debounce.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity debounce is
+ generic (stages : natural := 1);
+ port (clk : in std_logic;
+ i : in std_logic;
+ o : out std_logic);
+end debounce;
+
+architecture Behavioral of debounce is
+ signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0');
+ constant zero : std_logic_vector(stages-1 downto 0) := (others => '0');
+ constant one : std_logic_vector(stages-1 downto 0) := (others => '1');
+ signal output : std_logic := '0';
+begin
+
+ o <= output;
+
+ process (clk, flipflops, i)
+ begin
+ if rising_edge(clk) then
+ flipflops <= flipflops(flipflops'high-1 downto 0) & i;
+ if flipflops = one and i = '1' then
+ output <= '1';
+ elsif flipflops = zero and i = '0' then
+ output <= '0';
+ end if;
+ end if;
+ end process;
+
+end architecture;
diff --git a/fpga/hp_lcd_driver/edge_det.vhdl b/fpga/hp_lcd_driver/edge_det.vhdl
new file mode 100644
index 0000000..2a592a5
--- /dev/null
+++ b/fpga/hp_lcd_driver/edge_det.vhdl
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity edge_det is
+ port (clk : in std_logic;
+ sig : in std_logic;
+ pe : out std_logic;
+ ne : out std_logic;
+ e : out std_logic
+ );
+end edge_det;
+
+architecture Behavioral of edge_det is
+ signal last : std_logic := '0';
+begin
+
+ process(clk, last, sig)
+ begin
+ if rising_edge(clk) then
+ last <= sig;
+ end if;
+ end process;
+
+ pe <= '1' when sig = '1' and last = '0' else '0';
+ ne <= '1' when sig = '0' and last = '1' else '0';
+
+ e <= sig xor last;
+end Behavioral;
diff --git a/fpga/hp_lcd_driver/ep4ce15.cfg b/fpga/hp_lcd_driver/ep4ce15.cfg
new file mode 100644
index 0000000..39925e2
--- /dev/null
+++ b/fpga/hp_lcd_driver/ep4ce15.cfg
@@ -0,0 +1,10 @@
+
+set CHIPNAME ep4ce15
+set FPGA_TAPID 0x020f20dd
+
+jtag newtap $CHIPNAME tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $FPGA_TAPID
+
+init
+scan_chain
+svf -tap $CHIPNAME.tap ./build_ep4ce15/hp_lcd_driver.svf
+exit
diff --git a/fpga/hp_lcd_driver/ep4ce15.mk b/fpga/hp_lcd_driver/ep4ce15.mk
new file mode 100644
index 0000000..982934b
--- /dev/null
+++ b/fpga/hp_lcd_driver/ep4ce15.mk
@@ -0,0 +1,126 @@
+include relpath.mk
+
+FAMILY=Cyclone IV E
+PART=EP4CE15F23C8
+TOP=hp_lcd_driver
+BUILD=build_ep4ce15
+OF=output_files
+
+PROJECT = hp_lcd_driver
+VSRCS =synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl
+IPS= vram_cyclone4_impl.vhdl clkgen_cyclone4_impl.vhdl input_pll.vhdl
+
+DESIGN_NAME=${TOP}
+
+MAP_ARGS = --smart
+FIT_ARGS =
+ASM_ARGS =
+STA_ARGS =
+CPF_ARGS = -c -q 1MHZ -g 3.3 -n p
+
+GEN_VSRCS=${IPS:%.vhdl=${BUILD}/%.vhd}
+QIP=${GEN_VSRCS:%.vhd=%.qip}
+
+BASE=${BUILD}/${DESIGN_NAME}
+QSF=${BASE}.qsf
+QPF=${BASE}.qpf
+MAP=${BUILD}/${OF}/$(PROJECT).map.rpt
+FIT=${BUILD}/${OF}/$(PROJECT).fit.rpt
+ASM=${BUILD}/${OF}/$(PROJECT).asm.rpt
+ASM=${BUILD}/${OF}/$(PROJECT).sta.rpt
+SOF=${BUILD}/${OF}/${PROJECT}.sof
+SVF=${BUILD}/${PROJECT}.svf
+
+default:${SVF}
+
+
+${BUILD}/%.vhd ${BUILD}/%.qip:%.vhdl
+ cat $< > ${BUILD}/${<:%.vhdl=%.vhd}
+ (cd ${BUILD} && run_quartus qmegawiz -silent $(call relpath,${BUILD}/${<:%.vhdl=%.vhd},${BUILD}))
+
+
+${QSF}: ${PRJ} ${DESIGN_NAME}.ep4ce15_qsft
+ mkdir -p ${BUILD}
+ rm -f $@
+ echo 'set_global_assignment -name TOP_LEVEL_ENTITY ${TOP}' >> $@
+ echo 'set_global_assignment -name FAMILY "${FAMILY}"' >> $@
+ echo 'set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ${OF}' >> $@
+ echo 'set_global_assignment -name DEVICE ${PART}' >> $@
+ cat ${DESIGN_NAME}.ep4ce15_qsft >> $@
+ for file in ${GEN_VSRCS} ${VSRCS}; do \
+ echo "set_global_assignment -name VHDL_FILE $$(realpath -m --relative-to=${BUILD} $${file})" >> $@; \
+ done
+
+
+
+${QPF}:
+ mkdir -p ${BUILD}
+ rm -f $@
+ echo 'PROJECT_REVISION = "${TOP}"' > $@
+
+
+map: ${MAP}
+${MAP}: ${VSRCS} ${QPF} ${QSF} ${GEN_VSRCS} ${QIP}
+ (cd ${BUILD} && run_quartus quartus_map $(MAP_ARGS) ${PROJECT})
+
+fit: ${FIT}
+${FIT}:${MAP}
+ (cd ${BUILD} && run_quartus quartus_fit $(FIT_ARGS) $(PROJECT))
+
+asm: ${ASM}
+sof: ${ASM}
+${SOF} ${ASM}:${FIT}
+ (cd ${BUILD} && run_quartus quartus_asm $(ASM_ARGS) $(PROJECT))
+
+sta: ${STA}
+${STA}:${FIT}
+ (cd ${BUILD} && run_quartus quartus_sta $(STA_ARGS) $(PROJECT))
+
+
+svf:${SVF}
+${SVF}:${SOF}
+ (cd ${BUILD} && run_quartus quartus_cpf ${CPF_ARGS} $(call relpath,$<,${BUILD}) $(call relpath,$@,${BUILD}) )
+
+
+
+tidy:
+ git diff --exit-code -s ${VSRCS}
+ for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done
+
+
+
+#
+#
+##OPENOCD=openocd -f interface/altera-usb-blaster.cfg -f cpld/altera-epm240.cfg
+#
+#FIT_ARGS =
+#ASM_ARGS =
+#
+#SVF=${PROJECT}.svf
+#
+#
+#
+#default: ${SVF}
+#
+#${SVF}: ${BUILD}/${PROJECT}.svf
+# cat $< > $@ || /bin/rm -f $@
+#
+#program: ${SVF}
+# ${OPENOCD} -c "init; svf $<; exit"
+#
+#all: ${BUILD}/$(PROJECT).asm.rpt ${BUILD}/$(PROJECT).sta.rpt ${BUILD}/${PROJECT}.svf
+#
+clean:
+ rm -rf db ${BUILD} *.orig *.bak incremental_db db
+
+#
+#
+#
+#
+#
+#
+
+#tidy:
+# for i in ${SOURCE_FILES}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done
+#
+#
diff --git a/fpga/hp_lcd_driver/ep4ce6.mk b/fpga/hp_lcd_driver/ep4ce6.mk
new file mode 100644
index 0000000..f758f9c
--- /dev/null
+++ b/fpga/hp_lcd_driver/ep4ce6.mk
@@ -0,0 +1,126 @@
+include relpath.mk
+
+FAMILY=Cyclone IV E
+PART=EP4CE6E22C8
+TOP=hp_lcd_driver
+BUILD=build_ep4ce6
+OF=output_files
+
+PROJECT = hp_lcd_driver
+VSRCS =synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl
+IPS= vram_cyclone4_impl.vhdl clkgen_cyclone4_impl.vhdl
+
+DESIGN_NAME=${TOP}
+
+MAP_ARGS = --smart
+FIT_ARGS =
+ASM_ARGS =
+STA_ARGS =
+CPF_ARGS = -c -q 1MHZ -g 3.3 -n p
+
+GEN_VSRCS=${IPS:%.vhdl=${BUILD}/%.vhd}
+QIP=${GEN_VSRCS:%.vhd=%.qip}
+
+BASE=${BUILD}/${DESIGN_NAME}
+QSF=${BASE}.qsf
+QPF=${BASE}.qpf
+MAP=${BUILD}/${OF}/$(PROJECT).map.rpt
+FIT=${BUILD}/${OF}/$(PROJECT).fit.rpt
+ASM=${BUILD}/${OF}/$(PROJECT).asm.rpt
+ASM=${BUILD}/${OF}/$(PROJECT).sta.rpt
+SOF=${BUILD}/${OF}/${PROJECT}.sof
+SVF=${BUILD}/${PROJECT}.svf
+
+default:${SVF}
+
+
+${BUILD}/%.vhd ${BUILD}/%.qip:%.vhdl
+ cat $< > ${BUILD}/${<:%.vhdl=%.vhd}
+ (cd ${BUILD} && run_quartus qmegawiz -silent $(call relpath,${BUILD}/${<:%.vhdl=%.vhd},${BUILD}))
+
+
+${QSF}: ${PRJ} ${DESIGN_NAME}.ep4ce6_qsft
+ mkdir -p ${BUILD}
+ rm -f $@
+ echo 'set_global_assignment -name TOP_LEVEL_ENTITY ${TOP}' >> $@
+ echo 'set_global_assignment -name FAMILY "${FAMILY}"' >> $@
+ echo 'set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ${OF}' >> $@
+ echo 'set_global_assignment -name DEVICE ${PART}' >> $@
+ cat ${DESIGN_NAME}.ep4ce6_qsft >> $@
+ for file in ${GEN_VSRCS} ${VSRCS}; do \
+ echo "set_global_assignment -name VHDL_FILE $$(realpath -m --relative-to=${BUILD} $${file})" >> $@; \
+ done
+
+
+
+${QPF}:
+ mkdir -p ${BUILD}
+ rm -f $@
+ echo 'PROJECT_REVISION = "${TOP}"' > $@
+
+
+map: ${MAP}
+${MAP}: ${VSRCS} ${QPF} ${QSF} ${GEN_VSRCS} ${QIP}
+ (cd ${BUILD} && run_quartus quartus_map $(MAP_ARGS) ${PROJECT})
+
+fit: ${FIT}
+${FIT}:${MAP}
+ (cd ${BUILD} && run_quartus quartus_fit $(FIT_ARGS) $(PROJECT))
+
+asm: ${ASM}
+sof: ${ASM}
+${SOF} ${ASM}:${FIT}
+ (cd ${BUILD} && run_quartus quartus_asm $(ASM_ARGS) $(PROJECT))
+
+sta: ${STA}
+${STA}:${FIT}
+ (cd ${BUILD} && run_quartus quartus_sta $(STA_ARGS) $(PROJECT))
+
+
+svf:${SVF}
+${SVF}:${SOF}
+ (cd ${BUILD} && run_quartus quartus_cpf ${CPF_ARGS} $(call relpath,$<,${BUILD}) $(call relpath,$@,${BUILD}) )
+
+
+
+tidy:
+ git diff --exit-code -s ${VSRCS}
+ for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done
+
+
+
+#
+#
+##OPENOCD=openocd -f interface/altera-usb-blaster.cfg -f cpld/altera-epm240.cfg
+#
+#FIT_ARGS =
+#ASM_ARGS =
+#
+#SVF=${PROJECT}.svf
+#
+#
+#
+#default: ${SVF}
+#
+#${SVF}: ${BUILD}/${PROJECT}.svf
+# cat $< > $@ || /bin/rm -f $@
+#
+#program: ${SVF}
+# ${OPENOCD} -c "init; svf $<; exit"
+#
+#all: ${BUILD}/$(PROJECT).asm.rpt ${BUILD}/$(PROJECT).sta.rpt ${BUILD}/${PROJECT}.svf
+#
+clean:
+ rm -rf db ${BUILD} *.orig *.bak incremental_db db
+
+#
+#
+#
+#
+#
+#
+
+#tidy:
+# for i in ${SOURCE_FILES}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done
+#
+#
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft b/fpga/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft
new file mode 100644
index 0000000..e22c246
--- /dev/null
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft
@@ -0,0 +1,87 @@
+#set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+#set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:47:00 APRIL 20, 2025"
+#set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+
+set_parameter -name target "cyclone4"
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+set_location_assignment PIN_T22 -to clk_50m
+set_location_assignment PIN_U20 -to sys_rst_n
+
+set_location_assignment PIN_AB17 -to vsync_out
+set_location_assignment PIN_AA18 -to hsync_out
+
+set_location_assignment PIN_J21 -to r_out
+set_instance_assignment -name IO_STANDARD "2.5 V" -to r_out
+#set_location_assignment PIN_K21 -to rgb[14]
+#set_location_assignment PIN_L22 -to rgb[13]
+#set_location_assignment PIN_L21 -to rgb[12]
+#set_location_assignment PIN_M22 -to rgb[11]
+set_location_assignment PIN_M21 -to g_out
+#set_location_assignment PIN_N21 -to rgb[9]
+#set_location_assignment PIN_N20 -to rgb[8]
+#set_location_assignment PIN_U22 -to rgb[7]
+#set_location_assignment PIN_U21 -to rgb[6]
+#set_location_assignment PIN_W20 -to rgb[5]
+set_location_assignment PIN_W19 -to b_out
+#set_location_assignment PIN_Y21 -to rgb[3]
+#set_location_assignment PIN_AB19 -to rgb[2]
+#set_location_assignment PIN_AA19 -to rgb[1]
+#set_location_assignment PIN_AB18 -to rgb[0]
+
+
+
+set_location_assignment PIN_H21 -to hdmi_c_p
+set_location_assignment PIN_H22 -to hdmi_c_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_c_p
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_c_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_c_p
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_c_n
+
+set_location_assignment PIN_F21 -to hdmi_b_p
+set_location_assignment PIN_F22 -to hdmi_b_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_b_p
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_b_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_b_p
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_b_n
+
+set_location_assignment PIN_E21 -to hdmi_g_p
+set_location_assignment PIN_E22 -to hdmi_g_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_g_p
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_g_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_g_p
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_g_n
+
+set_location_assignment PIN_D21 -to hdmi_r_p
+set_location_assignment PIN_D22 -to hdmi_r_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_r_p
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_r_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_r_p
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_r_n
+
+
+set_location_assignment PIN_AA14 -to hsync_in
+set_location_assignment PIN_W14 -to vsync_in
+set_location_assignment PIN_AA15 -to video[0]
+set_location_assignment PIN_V15 -to video[1]
+set_location_assignment PIN_W7 -to i_clk_out
+
+
+
+
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.ep4ce6_qsft b/fpga/hp_lcd_driver/hp_lcd_driver.ep4ce6_qsft
new file mode 100644
index 0000000..e3bc6c5
--- /dev/null
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.ep4ce6_qsft
@@ -0,0 +1,144 @@
+#set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+#set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:47:00 APRIL 20, 2025"
+#set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+
+set_parameter -name target "cyclone4"
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+
+# use the beeper for this!
+set_location_assignment PIN_85 -to sys_rst_n
+
+#key 3
+set_location_assignment PIN_89 -to video(0)
+#key 4
+set_location_assignment PIN_90 -to video(1)
+
+set_location_assignment PIN_98 -to hsync_in
+set_location_assignment PIN_99 -to vsync_in
+
+#lies - it's 48
+set_location_assignment PIN_24 -to clk_50m
+
+set_location_assignment PIN_100 -to hsync_out
+#set_location_assignment PIN_101 -to vsync_out
+
+set_location_assignment PIN_126 -to r_out
+set_location_assignment PIN_110 -to b_out
+set_location_assignment PIN_119 -to g_out
+
+set_location_assignment PIN_133 -to hdmi_c_p
+set_location_assignment PIN_135 -to hdmi_c_n
+set_location_assignment PIN_136 -to hdmi_r_p
+set_location_assignment PIN_137 -to hdmi_r_n
+set_location_assignment PIN_138 -to hdmi_g_p
+set_location_assignment PIN_142 -to hdmi_g_n
+set_location_assignment PIN_143 -to hdmi_b_p
+set_location_assignment PIN_144 -to hdmi_b_n
+
+
+
+# bank 1
+#
+#set_location_assignment PIN_141 -to led_5
+#set_location_assignment PIN_1 -to led_4
+#set_location_assignment PIN_2 -to led_3
+#set_location_assignment PIN_3 -to led_2
+#
+#set_location_assignment PIN_7 -to flash_di
+#set_location_assignment PIN_10 -to flash_clk
+#set_location_assignment PIN_11 -to flash_ncs
+#set_location_assignment PIN_23 -to flash_do
+#set_location_assignment PIN_25 -to tmp1
+##
+##bank 2
+#set_location_assignment PIN_28 -to dram_dq[1]
+#set_location_assignment PIN_30 -to dram_dq[0]
+#set_location_assignment PIN_31 -to dram_dq[3]
+#set_location_assignment PIN_32 -to dram_dq[2]
+#set_location_assignment PIN_33 -to dram_dq[4]
+#set_location_assignment PIN_34 -to dram_dq[5]
+#
+##bank 3
+#set_location_assignment PIN_38 -to dram_dq[6]
+#set_location_assignment PIN_39 -to dram_dq[7]
+#set_location_assignment PIN_42 -to dram_ldqm
+#set_location_assignment PIN_43 -to dram_we_n
+#set_location_assignment PIN_44 -to dram_cas_n
+#set_location_assignment PIN_46 -to dram_ras_n
+#set_location_assignment PIN_49 -to dram_dq[15]
+#set_location_assignment PIN_50 -to dram_dq[14]
+#set_location_assignment PIN_51 -to dram_dq[13]
+#set_location_assignment PIN_52 -to dram_dq[12]
+#set_location_assignment PIN_53 -to dram_dq[11]
+#
+##bank 4
+#set_location_assignment PIN_54 -to dram_dq[10]
+#set_location_assignment PIN_55 -to dram_dq[9]
+#set_location_assignment PIN_58 -to dram_dq[8]
+#set_location_assignment PIN_59 -to dram_udqm
+#set_location_assignment PIN_60 -to dram_clk
+#set_location_assignment PIN_64 -to dram_cke
+#set_location_assignment PIN_65 -to dram_addr[12]
+#set_location_assignment PIN_66 -to dram_addr[11]
+#set_location_assignment PIN_67 -to dram_addr[9]
+#set_location_assignment PIN_68 -to dram_addr[8]
+#set_location_assignment PIN_69 -to dram_addr[7]
+#set_location_assignment PIN_70 -to dram_addr[6]
+#set_location_assignment PIN_71 -to dram_addr[5]
+#set_location_assignment PIN_72 -to dram_addr[4]
+#
+## bank 5
+#set_location_assignment PIN_73 -to dram_ba_0
+#set_location_assignment PIN_74 -to dram_cs_n
+#set_location_assignment PIN_75 -to dram_ba_1
+#set_location_assignment PIN_76 -to dram_addr[10]
+#set_location_assignment PIN_77 -to dram_addr[0]
+#set_location_assignment PIN_80 -to dram_addr[1]
+#set_location_assignment PIN_83 -to dram_addr[2]
+#set_location_assignment PIN_84 -to dram_addr[3]
+#set_location_assignment PIN_86 -to uart_txd
+#set_location_assignment PIN_87 -to uart_rxd
+##
+## clocks 2
+#set_location_assignment PIN_88 -to key_2
+#set_location_assignment PIN_89 -to key_3
+#set_location_assignment PIN_90 -to key_4
+#set_location_assignment PIN_91 -to key_1
+#
+## bank 6
+#set_location_assignment PIN_103 -to vga_b[0]
+#set_location_assignment PIN_104 -to vga_b[1]
+#set_location_assignment PIN_105 -to vga_b[2]
+#set_location_assignment PIN_106 -to vga_b[3]
+##
+##bank 7
+#set_location_assignment PIN_111 -to vga_g[0]
+#set_location_assignment PIN_112 -to vga_g[1]
+#set_location_assignment PIN_113 -to vga_g[2]
+#set_location_assignment PIN_114 -to vga_g[3]
+#set_location_assignment PIN_115 -to vga_g[4]
+#set_location_assignment PIN_120 -to vga_r[0]
+#set_location_assignment PIN_121 -to vga_r[1]
+#set_location_assignment PIN_121 -to vga_r[2]
+#set_location_assignment PIN_125 -to vga_r[3]
+#set_location_assignment PIN_127 -to adc_clk
+#
+##bank 8
+#set_location_assignment PIN_128 -to adc_dat
+#set_location_assignment PIN_129 -to adc_ncs
+#set_location_assignment PIN_132 -to ir
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.ucf b/fpga/hp_lcd_driver/hp_lcd_driver.ucf
new file mode 100644
index 0000000..ae00a1b
--- /dev/null
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.ucf
@@ -0,0 +1,34 @@
+#NET "hdmi_r" IOSTANDARD = LVCMOS33;
+#NET "hdmi_b" LOC = P67;
+
+NET "clk_50m" IOSTANDARD = LVCMOS33;
+NET "sys_rst_n" IOSTANDARD = LVCMOS33;
+NET "video[0]" IOSTANDARD = LVCMOS33;
+NET "video[1]" IOSTANDARD = LVCMOS33;
+NET "hsync_in" IOSTANDARD = LVCMOS33;
+NET "vsync_in" IOSTANDARD = LVCMOS33;
+NET "r_out" IOSTANDARD = LVCMOS33;
+NET "b_out" IOSTANDARD = LVCMOS33;
+NET "g_out" IOSTANDARD = LVCMOS33;
+NET "hsync_out" IOSTANDARD = LVCMOS33;
+NET "vsync_out" IOSTANDARD = LVCMOS33;
+
+
+INST "clkgen/pll" LOC = PLL_ADV_X0Y1;
+INST "output0/tmds_o/ioclk_buf" LOC = BUFPLL_X1Y5;
+
+NET "hdmi_c_p" LOC = P144;
+NET "hdmi_c_n" LOC = P143;
+NET "hdmi_r_p" LOC = P142;
+NET "hdmi_r_n" LOC = P141;
+NET "hdmi_g_p" LOC = P140;
+NET "hdmi_g_n" LOC = P139;
+
+
+
+
+
+
+NET "clk_50m" PERIOD = 20 ns;
+NET "hdmi_b_p" LOC = P138;
+NET "hdmi_b_n" LOC = P137;
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.ut b/fpga/hp_lcd_driver/hp_lcd_driver.ut
new file mode 100644
index 0000000..ea9319f
--- /dev/null
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.ut
@@ -0,0 +1,30 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
new file mode 100644
index 0000000..a8cf948
--- /dev/null
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -0,0 +1,221 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+use work.all;
+
+entity hp_lcd_driver is
+ generic (video_width : natural := 2;
+ addr_width : natural := 18;
+ phase_slip : natural := 320;
+ target : string := "spartan6");
+ port (clk_50m : in std_logic;
+ sys_rst_n : in std_logic;
+ video : in std_logic_vector(video_width-1 downto 0);
+ hsync_in : in std_logic;
+ vsync_in : in std_logic;
+ r_out : out std_logic;
+ b_out : out std_logic;
+ g_out : out std_logic;
+ hsync_out : out std_logic;
+ vsync_out : out std_logic;
+ hdmi_c_p : out std_logic;
+ hdmi_c_n : out std_logic;
+ hdmi_r_p : out std_logic;
+ hdmi_r_n : out std_logic;
+ hdmi_g_p : out std_logic;
+ hdmi_g_n : out std_logic;
+ hdmi_b_p : out std_logic;
+ hdmi_b_n : out std_logic;
+ i_clk_out : out std_logic);
+
+end hp_lcd_driver;
+
+architecture Behavioral of hp_lcd_driver is
+
+ signal wr_addr : std_logic_vector(addr_width-1 downto 0);
+ signal wr_data : std_logic_vector(video_width-1 downto 0);
+ signal wr_en : std_logic;
+
+ signal rd_addr : std_logic_vector(addr_width-1 downto 0);
+ signal rd_data : std_logic_vector(video_width-1 downto 0);
+
+ signal r : std_logic_vector(7 downto 0);
+ signal g : std_logic_vector(7 downto 0);
+ signal b : std_logic_vector(7 downto 0);
+
+
+ signal clk_locked : std_logic;
+
+ signal i_clk : std_logic;
+
+ signal o_clk : std_logic;
+ signal o_clk_x2 : std_logic;
+ signal o_clk_phy : std_logic;
+ signal sys_rst : std_logic;
+
+ signal pa : natural;
+ signal epk : std_logic;
+ signal ic : natural;
+
+
+
+begin
+
+
+-- clocking:
+-- i_clk is 4*20MHz to give us 4 choices of sampling position
+-- o_clk is the output pixel clock
+-- o_clk_x2 is used by the spartan serdes
+-- o_clk_phy is used the the hdmi phy (cylone4 it's o_clk x5, spartan 6 it's o_clk x 10)
+
+ i_clkgen : entity work.input_pll
+ port map (
+ areset => open,
+ inclk0 => clk_50m,
+ c0 => i_clk,
+ locked => open);
+
+
+ process (i_clk, sys_rst_n)
+ begin
+ if sys_rst_n = '0' then
+ ic <= 0;
+ pa <= phase_slip;
+ epk <= '0';
+ elsif rising_edge(i_clk) then
+
+ if ic = 0 then
+ epk <= '1';
+ if pa = 0 then
+ pa <= phase_slip;
+ ic <= 4;
+ else
+ ic <= 3;
+ pa <= pa -1;
+ end if;
+ else
+ if epk = '1' then
+ epk <= '0';
+ end if;
+ ic <= ic-1;
+ end if;
+ end if;
+ end process;
+
+
+ i_clk_out <= epk;
+
+ clkgen : entity work.clkgen
+ port map (
+ sys_rst_n => sys_rst_n,
+ clk_in => clk_50m,
+ i_clk => open,
+ o_clk => o_clk,
+ o_clk_x2 => o_clk_x2,
+ o_clk_phy => o_clk_phy,
+ locked => clk_locked
+ );
+
+ --i_clk_out <= i_clk;
+
+ input0 : entity work.input_stage
+ generic map(
+ video_width => video_width,
+ addr_width => addr_width,
+ clk_multiple => 4,
+ phase => 3,
+ h_front_porch => 208,
+ h_active => 592,
+ v_front_porch => 2,
+ v_active => 384,
+ frame_start => 380,
+ h_stride => 384,
+ v_stride => 262143,
+ phase_slip => phase_slip
+ )
+ port map (
+ sys_rst_n => sys_rst_n,
+ clk => i_clk,
+ video_in => video,
+ hsync_in => hsync_in,
+ vsync_in => vsync_in,
+
+ video_out => wr_data,
+ addr_out => wr_addr,
+ wren_out => wr_en);
+
+
+ vram0 : entity work.vram
+ generic map (
+ video_width => video_width,
+ addr_width => addr_width
+ )
+ port map (
+ wr_clk => i_clk,
+ wr_en => wr_en,
+ wr_addr => wr_addr,
+ wr_data => wr_data,
+ rd_clk => o_clk,
+ rd_addr => rd_addr,
+ rd_data => rd_data
+ );
+
+
+ r <= x"ff" when rd_data(1) = '1' else
+ x"00";
+ g <= x"ff" when rd_data(0) = '1' else
+ x"ff" when rd_data(1) = '1' else
+ x"00";
+ b <= x"ff" when rd_data(1) = '1' else
+ x"00";
+
+
+
+ output0 : entity work.output_stage
+
+-- didn't work for me from this thing, only from mac, works at 60Hz xrandr --newmode "$M" 18.24 384 400 440 600 592 593 596 613 -HSync +Vsync
+-- Modeline "384x592_80.00" 25.40 384 408 448 512 592 593 596 620 -HSync +Vsync
+
+ generic map (
+ target => target,
+ addr_width => addr_width,
+ h_active => 384,
+ h_sync_start => 400,
+ h_sync_end => 440,
+ h_total => 620,
+ v_active => 592,
+ v_sync_start => 593,
+ v_sync_end => 596,
+ v_total => 613,
+ h_stride => 1,
+ v_stride => 384
+ )
+ port map(
+ clk_locked => clk_locked,
+ clk => o_clk,
+ clk_x2 => o_clk_x2,
+ clk_phy => o_clk_phy,
+ sys_rst_n => sys_rst_n,
+ vsync_in => vsync_in,
+ r_in => r,
+ g_in => g,
+ b_in => b,
+ addr_out => rd_addr,
+ r_out => r_out,
+ g_out => g_out,
+ b_out => b_out,
+ hsync_out => hsync_out,
+ vsync_out => vsync_out,
+ hdmi_c_p => hdmi_c_p,
+ hdmi_c_n => hdmi_c_n,
+ hdmi_r_p => hdmi_r_p,
+ hdmi_r_n => hdmi_r_n,
+ hdmi_g_p => hdmi_g_p,
+ hdmi_g_n => hdmi_g_n,
+ hdmi_b_p => hdmi_b_p,
+ hdmi_b_n => hdmi_b_n
+ );
+
+
+end Behavioral;
+
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.xst_template b/fpga/hp_lcd_driver/hp_lcd_driver.xst_template
new file mode 100644
index 0000000..b5f39c1
--- /dev/null
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.xst_template
@@ -0,0 +1,46 @@
+run
+-ofmt NGC
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl
new file mode 100644
index 0000000..9c04493
--- /dev/null
+++ b/fpga/hp_lcd_driver/input_formatter.vhdl
@@ -0,0 +1,142 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+-- i_clk is 78.704625
+-- the scope's pixel clock is 19.660819
+-- ratio is 4.003120
+-- 1/0.003120 is 320
+
+
+
+entity input_formatter is
+ generic (
+ addr_width : natural := 17;
+ clk_multiple : natural := 4;
+ phase : natural := 2;
+ h_front_porch : natural := 208;
+ h_active : natural := 592;
+ v_front_porch : natural := 2;
+ v_active : natural := 384;
+ frame_start : natural := 0;
+ h_stride : natural := 384;
+ v_stride : natural := 1;
+ phase_slip : natural := 320);
+ port
+ (
+ sys_rst_n : in std_logic;
+ clk : in std_logic;
+ hsync : in std_logic;
+ vsync : in std_logic;
+ addr_out : out std_logic_vector(addr_width-1 downto 0);
+ wren_out : out std_logic;
+ h_grid : out std_logic;
+ v_grid : out std_logic
+ );
+
+end input_formatter;
+
+
+architecture beh of input_formatter is
+
+ signal row_addr : std_logic_vector(addr_width-1 downto 0);
+ signal addr : std_logic_vector(addr_width-1 downto 0);
+ signal wren : std_logic;
+
+ signal hsync_ne : std_logic;
+ signal hsync_pe : std_logic;
+
+ signal v_fp_counter : natural;
+ signal v_active_counter : natural;
+ signal h_fp_counter : natural;
+ signal h_active_counter : natural;
+ signal h_div : natural;
+
+ signal phase_accum : natural;
+
+
+begin
+
+
+ hsync_ed : entity work.edge_det
+ port map(
+ clk => clk,
+ sig => hsync,
+ e => open,
+ ne => hsync_ne,
+ pe => hsync_pe);
+
+
+
+
+ addr_out <= addr;
+
+
+ process (sys_rst_n, clk, hsync_pe, vsync)
+ begin
+ if sys_rst_n = '0' then
+ row_addr <= (others => '0');
+ addr <= (others => '0');
+ h_div <= 0;
+ h_active_counter <= 0;
+ h_fp_counter <= 0;
+ v_active_counter <= 0;
+ v_fp_counter <= 0;
+ phase_accum <= 0;
+ elsif rising_edge(clk) then
+ if hsync_pe = '1' then
+ --if v_active_counter = 0 and v_fp_counter=0 then
+ if vsync = '1' then
+ row_addr <= std_logic_vector(to_unsigned(frame_start, addr_width));
+ v_fp_counter <= v_front_porch;
+ v_active_counter <= v_active;
+ elsif v_fp_counter /= 0 then
+ v_fp_counter <= v_fp_counter -1;
+ elsif v_active_counter /= 0 then
+ v_active_counter <= v_active_counter -1;
+
+ h_fp_counter <= h_front_porch * clk_multiple + phase;
+ h_active_counter <= h_active;
+ phase_accum <= phase_slip;
+ h_div <= 0;
+
+ addr <= row_addr;
+ row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
+ end if;
+ elsif h_fp_counter /= 0 then
+ h_fp_counter <= h_fp_counter -1;
+ elsif h_active_counter /= 0 then
+
+ if h_div = 0 then
+ wren <= '1';
+ if phase_accum = 0 then
+ phase_accum <= phase_slip;
+ h_div <= clk_multiple;
+ else
+ phase_accum <= phase_accum-1;
+ h_div <= clk_multiple -1;
+ end if;
+ else
+ if wren = '1' then
+ wren <= '0';
+ h_active_counter <= h_active_counter -1;
+ addr <= std_logic_vector(unsigned(addr)+h_stride);
+ end if;
+ h_div <= h_div -1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ addr_out <= addr;
+ wren_out <= wren;
+
+
+ h_grid <= '1' when (h_active_counter mod 8) = 0
+ else '0';
+
+ v_grid <= '1' when (v_active_counter mod 8) = 0
+ else '0';
+
+
+end beh;
diff --git a/fpga/hp_lcd_driver/input_stage.vhdl b/fpga/hp_lcd_driver/input_stage.vhdl
new file mode 100644
index 0000000..e9a7549
--- /dev/null
+++ b/fpga/hp_lcd_driver/input_stage.vhdl
@@ -0,0 +1,142 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity input_stage is
+ generic (debounce_stages : natural := 2;
+ sync_stages : natural := 2;
+ video_width : natural := 2;
+ addr_width : natural := 17;
+ clk_multiple : natural := 4;
+ phase : natural := 2;
+ h_front_porch : natural := 208;
+ h_active : natural := 592;
+ v_front_porch : natural := 2;
+ v_active : natural := 384;
+ frame_start : natural := 0;
+ h_stride : natural := 384;
+ v_stride : natural := 1;
+ phase_slip : natural := 320);
+ port
+ (
+ clk : in std_logic;
+ sys_rst_n : in std_logic;
+
+ video_in : in std_logic_vector(video_width -1 downto 0);
+
+ hsync_in : in std_logic;
+ vsync_in : in std_logic;
+
+ video_out : out std_logic_vector(video_width-1 downto 0);
+ addr_out : out std_logic_vector(addr_width - 1 downto 0);
+ wren_out : out std_logic
+ );
+end input_stage;
+
+
+architecture beh of input_stage is
+
+ signal s_hsync : std_logic;
+ signal d_hsync : std_logic;
+
+ signal s_vsync : std_logic;
+ signal d_vsync : std_logic;
+
+ signal s_video : std_logic_vector(video_width-1 downto 0);
+
+ signal addr : std_logic_vector(addr_width - 1 downto 0);
+ signal wren : std_logic;
+
+ signal h_grid : std_logic;
+ signal v_grid : std_logic;
+
+ signal addr_test : std_logic_vector(addr_width - 1 downto 0);
+
+begin
+
+ video_sync_for : for b in 0 to video_width -1 generate
+ sync : entity work.synchronizer
+ generic map(stages => sync_stages + debounce_stages)
+ port map (
+ clk => clk,
+ i => video_in(b),
+ o => s_video(b)
+ );
+ end generate;
+
+
+
+ hsync_sync : entity work.synchronizer
+ generic map(stages => sync_stages)
+ port map (
+ clk => clk,
+ i => hsync_in,
+ o => s_hsync
+ );
+
+ vsync_sync : entity work.synchronizer
+ generic map(stages => sync_stages)
+ port map (
+ clk => clk,
+ i => vsync_in,
+ o => s_vsync
+ );
+
+ hsync_debounce : entity work.debounce
+ generic map(stages => debounce_stages)
+ port map(
+ clk => clk,
+ i => s_hsync,
+ o => d_hsync);
+
+
+
+ vsync_debounce : entity work.debounce
+ generic map(stages => debounce_stages)
+ port map(
+ clk => clk,
+ i => s_vsync,
+ o => d_vsync);
+
+
+ input_formatter : entity work.input_formatter
+ generic map(
+ -- 20.000 592 608 680 816 384 385 400 402
+ addr_width => addr_width,
+ clk_multiple => clk_multiple,
+ phase => phase,
+ h_front_porch => h_front_porch,
+ h_active => h_active,
+ v_front_porch => v_front_porch,
+ v_active => v_active,
+ frame_start => frame_start,
+ h_stride => h_stride,
+ v_stride => v_stride,
+ phase_slip => phase_slip)
+ port map (
+ sys_rst_n => sys_rst_n,
+ clk => clk,
+ hsync => d_hsync,
+ vsync => d_vsync,
+ addr_out => addr,
+ wren_out => wren,
+ h_grid => h_grid,
+ v_grid => v_grid
+ );
+
+
+--wren_out <='1';
+
+--video_out(0) <='1';
+--video_out(1) <='1';
+
+ addr_out <= addr;
+ wren_out <= wren;
+
+ video_out <= s_video;
+
+ --video_out(0) <= h_grid;
+ --video_out(1) <= v_grid;
+
+
+end beh;
diff --git a/fpga/hp_lcd_driver/output_analog.vhdl b/fpga/hp_lcd_driver/output_analog.vhdl
new file mode 100644
index 0000000..af9eb71
--- /dev/null
+++ b/fpga/hp_lcd_driver/output_analog.vhdl
@@ -0,0 +1,82 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+entity output_analog is
+ port
+ (
+ clk : in std_logic;
+ sys_rst_n : in std_logic;
+
+ r_in : in std_logic;
+ g_in : in std_logic;
+ b_in : in std_logic;
+ hsync_in : in std_logic;
+ vsync_in : in std_logic;
+ blank_in : in std_logic;
+
+ r_out : out std_logic;
+ g_out : out std_logic;
+ b_out : out std_logic;
+ hsync_out : out std_logic;
+ vsync_out : out std_logic
+ );
+end output_analog;
+
+
+architecture beh of output_analog is
+
+
+ signal r_r : std_logic;
+ signal g_r : std_logic;
+ signal b_r : std_logic;
+
+ signal hsync_r : std_logic;
+ signal vsync_r : std_logic;
+ signal blank_r : std_logic;
+
+
+
+begin
+
+ process (sys_rst_n, clk)
+ begin
+ if sys_rst_n = '0' then
+ r_r <= '0';
+ g_r <= '0';
+ b_r <= '0';
+ hsync_r <= '0';
+ vsync_r <= '0';
+ blank_r <= '0';
+ elsif rising_edge(clk) then
+ r_r <= r_in;
+ g_r <= g_in;
+ b_r <= b_in;
+ hsync_r <= hsync_in;
+ vsync_r <= vsync_in;
+ blank_r <= blank_in;
+
+ end if;
+ end process;
+
+
+ process (sys_rst_n, clk)
+ begin
+ if sys_rst_n = '0' then
+ r_out <= '0';
+ g_out <= '0';
+ b_out <= '0';
+ hsync_out <= '0';
+ vsync_out <= '0';
+ elsif rising_edge(clk) then
+ r_out <= r_r and not blank_r;
+ g_out <= g_r and not blank_r;
+ b_out <= b_r and not blank_r;
+ hsync_out <= hsync_r;
+ vsync_out <= vsync_r;
+ end if;
+ end process;
+
+
+end beh;
diff --git a/fpga/hp_lcd_driver/output_formatter.vhdl b/fpga/hp_lcd_driver/output_formatter.vhdl
new file mode 100644
index 0000000..96964ed
--- /dev/null
+++ b/fpga/hp_lcd_driver/output_formatter.vhdl
@@ -0,0 +1,137 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+
+entity output_formatter is
+ generic (addr_width : natural := 17;
+ h_front_porch : natural := 208;
+ h_active : natural := 384;
+ h_sync_start : natural := 400;
+ h_sync_end : natural := 440;
+ h_total : natural := 600;
+ v_active : natural := 592;
+ v_sync_start : natural := 593;
+ v_sync_end : natural := 596;
+ v_total : natural := 614;
+ h_stride : natural := 1;
+ v_stride : natural := 384
+ );
+ port (
+ sys_rst_n : in std_logic;
+ clk : in std_logic;
+ vsync_in : in std_logic;
+ addr_out : out std_logic_vector(addr_width -1 downto 0);
+ blank_out : out std_logic;
+ vsync_out : out std_logic;
+ hsync_out : out std_logic;
+ h_grid : out std_logic;
+ v_grid : out std_logic
+ );
+end output_formatter;
+
+
+architecture beh of output_formatter is
+
+ signal row_addr : std_logic_vector(addr_width-1 downto 0);
+ signal addr : std_logic_vector(addr_width-1 downto 0);
+
+ signal vsync_in_ne : std_logic;
+
+ signal h : natural;
+ signal v : natural;
+
+
+ signal blank : std_logic;
+ signal vblank : std_logic;
+ signal vsync : std_logic;
+ signal hsync : std_logic;
+
+
+begin
+
+ vsync_ed : entity work.edge_det
+ port map(
+ clk => clk,
+ sig => vsync_in,
+ e => open,
+ pe => open,
+ ne => vsync_in_ne);
+
+ process (clk, vsync_in_ne, sys_rst_n)
+ begin
+ if sys_rst_n = '0' then
+ h <= 0;
+ v <= 0;
+ elsif rising_edge(clk) then
+ if h /= (h_total-1) then
+ h <= h+1;
+ else
+ if v /= (v_total-1) then
+ v <= v+1;
+ h <= 0;
+ else --if vsync_in_ne = '1' then
+ h <= 0;
+ v <= 0;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ process (clk, h, h, sys_rst_n)
+ begin
+ if sys_rst_n = '0' then
+ row_addr <= (others => '0');
+ addr <= (others => '0');
+ blank <= '1';
+ vsync <= '0';
+ hsync <= '0';
+ elsif rising_edge(clk) then
+
+ if h = 0 then
+ if v = 0 then
+ row_addr <= (others => '0');
+ addr <= (others => '0');
+ blank <= '0';
+ vblank <= '0';
+ elsif v = v_active then
+ vblank <= '1';
+ elsif v = v_sync_start then
+ vsync <= '1';
+ elsif v = v_sync_end then
+ vsync <= '0';
+ else
+ blank <= vblank;
+ row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
+ addr <= row_addr;
+ end if;
+ elsif h = h_active then
+ blank <= '1';
+ elsif h = h_sync_start then
+ hsync <= '1';
+ elsif h = h_sync_end then
+ hsync <= '0';
+ else
+ addr <= std_logic_vector(unsigned(addr)+h_stride);
+ end if;
+ end if;
+ end process;
+
+ h_grid <= '1' when (h mod 8) = 0
+ else '0';
+
+ v_grid <= '1' when (v mod 8) = 0
+ else '0';
+
+
+ addr_out <= addr;
+ blank_out <= blank;
+ hsync_out <= hsync;
+ vsync_out <= vsync;
+
+end beh;
+
+
+
diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl
new file mode 100644
index 0000000..831e9f8
--- /dev/null
+++ b/fpga/hp_lcd_driver/output_stage.vhdl
@@ -0,0 +1,213 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity output_stage is
+ generic (target : string := "spartan6";
+ debounce_stages : natural := 2;
+ sync_stages : natural := 2;
+ addr_width : natural := 17;
+ h_front_porch : natural := 208;
+ h_active : natural := 384;
+ h_sync_start : natural := 400;
+ h_sync_end : natural := 440;
+ h_total : natural := 600;
+ v_active : natural := 592;
+ v_sync_start : natural := 593;
+ v_sync_end : natural := 596;
+ v_total : natural := 614;
+ h_stride : natural := 1;
+ v_stride : natural := 384
+ );
+ port
+ (
+ clk_locked : in std_logic;
+ clk : in std_logic;
+ clk_x2 : in std_logic;
+ clk_phy : in std_logic;
+ sys_rst_n : in std_logic;
+
+ vsync_in : in std_logic;
+
+ addr_out : out std_logic_vector(addr_width - 1 downto 0);
+
+ r_in : in std_logic_vector(7 downto 0);
+ g_in : in std_logic_vector(7 downto 0);
+ b_in : in std_logic_vector(7 downto 0);
+
+
+ r_out : out std_logic;
+ g_out : out std_logic;
+ b_out : out std_logic;
+ hsync_out : out std_logic;
+ vsync_out : out std_logic;
+
+ hdmi_c_p : out std_logic;
+ hdmi_c_n : out std_logic;
+ hdmi_r_p : out std_logic;
+ hdmi_r_n : out std_logic;
+ hdmi_g_p : out std_logic;
+ hdmi_g_n : out std_logic;
+ hdmi_b_p : out std_logic;
+ hdmi_b_n : out std_logic
+ );
+end output_stage;
+
+
+architecture beh of output_stage is
+
+
+ signal s_vsync_in : std_logic;
+ signal d_vsync_in : std_logic;
+
+ signal blank : std_logic;
+
+ signal hsync : std_logic;
+ signal vsync : std_logic;
+
+ signal addr : std_logic_vector(addr_width - 1 downto 0);
+
+ signal r : std_logic_vector(7 downto 0);
+ signal g : std_logic_vector(7 downto 0);
+ signal b : std_logic_vector(7 downto 0);
+
+ signal h_grid : std_logic;
+ signal v_grid : std_logic;
+
+ signal r_p10 : std_logic_vector(9 downto 0);
+ signal g_p10 : std_logic_vector(9 downto 0);
+ signal b_p10 : std_logic_vector(9 downto 0);
+ signal c_p10 : std_logic_vector(9 downto 0);
+
+
+begin
+
+
+ vsync_sync : entity work.synchronizer
+ generic map(stages => sync_stages)
+ port map (
+ clk => clk,
+ i => vsync_in,
+ o => s_vsync_in
+ );
+
+ vsync_debounce : entity work.debounce
+ generic map(stages => debounce_stages)
+ port map(
+ clk => clk,
+ i => s_vsync_in,
+ o => d_vsync_in);
+
+
+ output_formatter : entity work.output_formatter
+ generic map(
+ addr_width => addr_width,
+ h_active => h_active,
+ h_sync_start => h_sync_start,
+ h_sync_end => h_sync_end,
+ h_total => h_total,
+ v_active => v_active,
+ v_sync_start => v_sync_start,
+ v_sync_end => v_sync_end,
+ v_total => v_total,
+ h_stride => h_stride,
+ v_stride => v_stride
+ )
+ port map (
+ sys_rst_n => sys_rst_n,
+ clk => clk,
+ vsync_in => d_vsync_in,
+ addr_out => addr,
+ blank_out => blank,
+ vsync_out => vsync,
+ hsync_out => hsync,
+ h_grid => h_grid,
+ v_grid => v_grid
+ );
+
+
+ addr_out <= addr;
+
+
+ r <=r_in;
+ g <=g_in;
+ b <=b_in;
+
+
+-- r<=x"00" when h_grid='0'
+-- else x"ff";
+
+-- g<=x"00" when v_grid='0'
+-- else x"ff";
+
+
+
+
+
+ analog : entity work.output_analog
+ port map(
+ sys_rst_n => sys_rst_n,
+
+ clk => clk,
+
+ hsync_in => hsync,
+ vsync_in => vsync,
+ blank_in => blank,
+ r_in => g(7),
+ g_in => r(7),
+ b_in => b(7),
+
+ r_out => r_out,
+ g_out => g_out,
+ b_out => b_out,
+ hsync_out => hsync_out,
+ vsync_out => vsync_out
+ );
+
+
+ tmds_e : entity work.tmds_encode port map (
+ sys_rst_n => sys_rst_n,
+ pclk => clk,
+
+ r_in => r,
+ g_in => g,
+ b_in => b,
+ hsync => hsync,
+ vsync => vsync,
+ blank => blank,
+
+ r_p10 => r_p10,
+ g_p10 => g_p10,
+ b_p10 => b_p10,
+ c_p10 => c_p10
+
+ );
+
+
+ tmds_o : entity work.tmds_output
+ port map (
+ sys_rst_n => sys_rst_n,
+ pclk_locked => clk_locked,
+ pclk => clk,
+ pclk_x2 => clk_x2,
+ pclk_phy => clk_phy,
+
+ r_p10 => r_p10,
+ g_p10 => g_p10,
+ b_p10 => b_p10,
+ c_p10 => c_p10,
+
+ tmds_c_out_p => hdmi_c_p,
+ tmds_c_out_n => hdmi_c_n,
+ tmds_r_out_p => hdmi_r_p,
+ tmds_r_out_n => hdmi_r_n,
+ tmds_g_out_p => hdmi_g_p,
+ tmds_g_out_n => hdmi_g_n,
+ tmds_b_out_p => hdmi_b_p,
+ tmds_b_out_n => hdmi_b_n
+ );
+
+
+
+
+end beh;
diff --git a/fpga/hp_lcd_driver/prog b/fpga/hp_lcd_driver/prog
new file mode 100755
index 0000000..c0e433c
--- /dev/null
+++ b/fpga/hp_lcd_driver/prog
@@ -0,0 +1,6 @@
+#!/bin/bash
+
+
+OPENOCD="/root/projects/hp_instrument_lcds/fpga/prefix/bin/openocd -f interface/altera-usb-blaster.cfg -f ep4ce15.cfg"
+${OPENOCD} -c quit
+
diff --git a/fpga/hp_lcd_driver/relpath.mk b/fpga/hp_lcd_driver/relpath.mk
new file mode 100644
index 0000000..ee42901
--- /dev/null
+++ b/fpga/hp_lcd_driver/relpath.mk
@@ -0,0 +1,35 @@
+override define \s :=
+$() $()
+endef
+
+ifndef $(\s)
+override $(\s) :=
+else
+$(error Defined special variable '$(\s)': reserved for internal use)
+endif
+
+override define dirname
+$(patsubst %/,%,$(dir $(patsubst %/,%,$1)))
+endef
+
+override define prefix_1
+$(if $(or $\
+$(patsubst $(abspath $3)%,,$(abspath $1)),$\
+$(patsubst $(abspath $3)%,,$(abspath $2))),$\
+$(strip $(call prefix_1,$1,$2,$(call dirname,$3))),$\
+$(strip $(abspath $3)))
+endef
+
+override define prefix
+$(call prefix_1,$1,$2,$1)
+endef
+
+override define relpath_1
+$(patsubst /%,%,$(subst $(\s),/,$(patsubst %,..,$(subst /,$(\s),$\
+$(patsubst $3%,%,$(abspath $2)))))$\
+$(patsubst $3%,%,$(abspath $1)))
+endef
+
+override define relpath
+$(call relpath_1,$1,$2,$(call prefix,$1,$2))
+endef
diff --git a/fpga/hp_lcd_driver/scripts/vhdl-pretty b/fpga/hp_lcd_driver/scripts/vhdl-pretty
new file mode 100755
index 0000000..c514b85
--- /dev/null
+++ b/fpga/hp_lcd_driver/scripts/vhdl-pretty
@@ -0,0 +1,60 @@
+#! /bin/sh
+":"; exec emacs --no-site-file --script "$0" -- "$0" "$@" # -*-emacs-lisp-*-
+; vim: noai:ts=4:sw=4:syntax=lisp
+
+(setq arg0 (file-truename (car (cdr argv))))
+(setq args (cdr (cdr argv)))
+(setq argv nil)
+
+; Parse the command line arguments,
+; --xxx -> ("xxx" t)
+; --no-xxx -> ("xxx" nil)
+; --xxx=123 -> ("xxx" 123)
+; --xxx=abc -> ("xxx" "abc")
+; --xxx='abc 123' -> ("xxx" "abc 123")
+; --xxx=abc=123 -> ("xxx" "abc=123")
+(setq args
+ (mapcar
+ (lambda (arg)
+ (cond
+ ((string-match "^--no-\\([^=]*\\)$" arg)
+ (list (intern (match-string 1 arg)) nil))
+ ((string-match "^--\\([^=]*\\)$" arg)
+ (list (intern (match-string 1 arg)) t))
+ ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\([0-9]+\\)\\2$" arg)
+ (list (intern (match-string 1 arg)) (string-to-number (match-string 3 arg))))
+ ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\(.+?\\)\\2$" arg)
+ (list (intern (match-string 1 arg)) (match-string 3 arg)))
+ (t nil)
+ ))
+ args))
+
+; Read stdin into buffer
+(defun insert-standard-input ()
+ "insert contents from standard input"
+ (condition-case nil
+ (let (line)
+ (while (setq line (read-from-minibuffer ""))
+ (insert line "\n")))
+ (error nil)))
+
+(insert-standard-input)
+(goto-char (point-min))
+
+; Load library
+(setq basedir (concat (file-name-directory arg0) "vhdl-mode"))
+(setq load-path (cons basedir load-path))
+(load-library "vhdl-mode")
+
+; Default customisation
+(vhdl-set-style "IEEE")
+
+; Customisation from cmdline
+(mapc (lambda (arg) (customize-set-variable (car arg) (car (cdr arg)))) args)
+
+; Turn on mode and beautify
+(vhdl-mode)
+(vhdl-beautify-region (point-min) (point-max))
+
+; Output buffer to stdout
+(princ (buffer-string))
diff --git a/fpga/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl b/fpga/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl
new file mode 100644
index 0000000..01fc578
--- /dev/null
+++ b/fpga/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl
@@ -0,0 +1,118 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+entity serdes_n_to_1_spartan6 is
+ generic (
+ SF : natural := 8
+ );
+ port (
+
+ ioclk : in std_logic;
+ serdesstrobe : in std_logic;
+ reset : in std_logic;
+ gclk : in std_logic;
+ datain : in std_logic_vector(SF-1 downto 0);
+ iob_data_out : out std_logic
+ );
+end serdes_n_to_1_spartan6;
+
+
+architecture beh of serdes_n_to_1_spartan6 is
+
+ signal cascade_di : std_logic;
+ signal cascade_do : std_logic;
+ signal cascade_ti : std_logic;
+ signal cascade_to : std_logic;
+ signal mdatain : std_logic_vector(8 downto 0);
+
+begin
+
+ datain_for_1 : for b in 0 to SF -1 generate
+ mdatain(b) <= datain(b);
+ end generate;
+
+ datain_for_2 : for b in SF to 8 generate
+ mdatain(b) <= '0';
+ end generate;
+
+-- mdatain <= ( SF-1 downto 0 => datain, others =>'0');
+
+ oserdes_m : OSERDES2
+ generic map (
+ DATA_WIDTH => SF,
+ DATA_RATE_OQ => "SDR",
+ DATA_RATE_OT => "SDR",
+ SERDES_MODE => "MASTER",
+ OUTPUT_MODE => "DIFFERENTIAL"
+ )
+ port map (
+ OQ => iob_data_out,
+ OCE => '1',
+ CLK0 => ioclk,
+ CLK1 => '0',
+ IOCE => serdesstrobe,
+ RST => reset,
+ CLKDIV => gclk,
+ D4 => mdatain(7),
+ D3 => mdatain(6),
+ D2 => mdatain(5),
+ D1 => mdatain(4),
+-- TQ => ,
+ T1 => '0',
+ T2 => '0',
+ T3 => '0',
+ T4 => '0',
+ TRAIN => '0',
+ TCE => '1',
+ SHIFTIN1 => '1', -- Dummy input in Master
+ SHIFTIN2 => '1', -- Dummy input in Master
+ SHIFTIN3 => cascade_do, -- Cascade output D data from slave
+ SHIFTIN4 => cascade_to, -- Cascade output T data from slave
+ SHIFTOUT1 => cascade_di, -- Cascade input D data to slave
+ SHIFTOUT2 => cascade_ti -- Cascade input T data to slave
+-- SHIFTOUT3 => , -- Dummy output in Master
+-- SHIFTOUT4 => -- Dummy output in Master
+ );
+
+ oserdes_s : OSERDES2
+ generic map (
+ DATA_WIDTH => SF, -- SERDES word width. This should match the setting is BUFPLL
+ DATA_RATE_OQ => "SDR", -- <SDR>, DDR
+ DATA_RATE_OT => "SDR", -- <SDR>, DDR
+ SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
+ OUTPUT_MODE => "DIFFERENTIAL"
+ )
+ port map (
+-- OQ => ,
+ OCE => '1',
+ CLK0 => ioclk,
+ CLK1 => '0',
+ IOCE => serdesstrobe,
+ RST => reset,
+ CLKDIV => gclk,
+ D4 => mdatain(3),
+ D3 => mdatain(2),
+ D2 => mdatain(1),
+ D1 => mdatain(0),
+-- TQ => ,
+ T1 => '0',
+ T2 => '0',
+ T3 => '0',
+ T4 => '0',
+ TRAIN => '0',
+ TCE => '1',
+ SHIFTIN1 => cascade_di, -- Cascade input D from Master
+ SHIFTIN2 => cascade_ti, -- Cascade input T from Master
+ SHIFTIN3 => '1', -- Dummy input in Slave
+ SHIFTIN4 => '1', -- Dummy input in Slave
+-- SHIFTOUT1 => , -- Dummy output in Slave
+-- SHIFTOUT2 => , -- Dummy output in Slave
+ SHIFTOUT3 => cascade_do, -- Cascade output D data to Master
+ SHIFTOUT4 => cascade_to); -- Cascade output T data to Master
+
+end beh;
diff --git a/fpga/hp_lcd_driver/spartan6.mk b/fpga/hp_lcd_driver/spartan6.mk
new file mode 100644
index 0000000..0d0f90e
--- /dev/null
+++ b/fpga/hp_lcd_driver/spartan6.mk
@@ -0,0 +1,129 @@
+include relpath.mk
+
+XILNXD_LICENSE_FILE:=${PWD}/xilinx_ise_vivado_license.lic
+export XILINXD_LICENSE_FILE
+PART=xc6slx9-2-tqg144
+TOP=hp_lcd_driver
+BUILD=build_spartan6
+VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1_spartan6.vhdl tmds_encoder.vhdl tmds_phy_spartan6.vhdl tmds_encode.vhdl tmds_output_spartan6.vhdl vram_spartan6.vhdl output_stage.vhdl clkgen_spartan6.vhdl hp_lcd_driver.vhdl
+UCF=hp_lcd_driver.ucf
+UT=hp_lcd_driver.ut
+IPSRCS=vram_spartan6_impl.xco
+DESIGN_NAME=${TOP}
+DS_HOME=/software/apps/xilinx/ISE/14.7/ISE_DS
+ISE_HOME=${DS_HOME}/ISE
+ISE_BINDIR_32=${ISE_HOME}/bin/lin
+ISE_BINDIR_64=${ISE_HOME}/bin/lin64
+INTSTYLE=
+
+XST_FLAGS=${INTSTYLE}
+NGDBUILD_FLAGS=${INTSTYLE} -p ${PART} -dd _ngo -nt timestamp
+MAP_FLAGS=${INTSTYLE} -p ${PART} -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off
+PAR_FLAGS=${INTSTYLE} -w -ol high -mt off
+TRCE_FLAGS=${INTSTYLE} -v 3 -s 2 -n 3 -fastpaths
+BITGEN_FLAGS=${INTSTYLE}
+
+
+
+GEN_VSRCS=${IPSRCS:%.xco=${BUILD}/%.vhd}
+BASE=${BUILD}/${DESIGN_NAME}
+XST=${BASE}.xst
+PRJ=${BASE}.prj
+SYR=${BASE}.syr
+NGC=${BASE}.ngc
+NGD=${BASE}.ngd
+MAP_NCD=${BASE}_map.ncd
+NCD=${BASE}.ncd
+PCF=${BASE}.pcf
+TWR=${BASE}.twr
+TWX=${BASE}.twx
+BIT=${BASE}.bit
+SVF=${BASE}.svf
+PA=${BUILD}/pa
+PAT=${PA}/script.tcl
+
+XST_TMPDIR=xst/projnav.tmp
+XST_DIR=xst
+
+
+
+default: ${NCD} ${TWR} ${TWX} ${BIT} ${SVF}
+
+clean:
+ /bin/rm -rf ${BUILD} *.orig *~
+
+${PRJ}: ${VSRCS} ${GEN_VSRCS}
+ mkdir -p ${BUILD}
+ rm -f $@
+ for file in $(GEN_VSRCS) ${VSRCS}; do \
+ echo "vhdl work $$(realpath -m --relative-to=${BUILD} $${file})" >> $@ ; \
+ done ;
+
+${NGC}:${XST}
+ (cd ${BUILD} && mkdir -p ${XST_DIR} ${XST_TMPDIR} && ${ISE_BINDIR_64}/xst ${XST_FLAGS} -ifn $(call relpath,$<,${BUILD}) -ofn $(call relpath,${SYR},${BUILD}))
+
+${XST}: ${PRJ} ${DESIGN_NAME}.xst_template
+ rm -f $@
+ echo 'set -tmpdir "${XST_TMPDIR}"' >> $@
+ echo 'set -xsthdpdir "${XST_DIR}"' >> $@
+ cat ${DESIGN_NAME}.xst_template >> $@
+ echo "-ifn $(call relpath,${PRJ},${BUILD})" >> $@
+ echo "-ofn $(call relpath,${BASE},${BUILD})" >> $@
+ echo "-p ${PART}" >> $@
+ echo "-top ${TOP}" >> $@
+
+${NGD}:${NGC} ${UCF}
+ (cd ${BUILD} && ${ISE_BINDIR_64}/ngdbuild $(NGDBUILD_FLAGS) -uc $(call relpath,${UCF},${BUILD}) $(call relpath,${NGC},${BUILD}) $(call relpath,$@,${BUILD}))
+
+${MAP_NCD} ${PCF}:${NGD}
+ (cd ${BUILD} && ${ISE_BINDIR_64}/map $(MAP_FLAGS) -o $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NGD},${BUILD}) $(call relpath,${PCF},${BUILD}))
+
+${NCD}: ${MAP_NCD} ${PCF}
+ (cd ${BUILD} && ${ISE_BINDIR_64}/par $(PAR_FLAGS) $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NCD},${BUILD}) $(call relpath,${PCF},${BUILD}))
+
+${TWR} ${TWX}: ${NCD} ${PCF}
+ (cd ${BUILD} && ${ISE_BINDIR_64}/trce ${TRCE_FLAGS} -xml $(call relpath,${TWX},${BUILD}) $(call relpath,${NCD},${BUILD}) -o $(call relpath,${TWR},${BUILD}) $(call relpath,${PCF},${BUILD}))
+
+${BIT}:${NCD} ${UT}
+ (cd ${BUILD} && ${ISE_BINDIR_64}/bitgen ${BITGEN_FLAGS} -f $(call relpath,${UT},${BUILD}) $(call relpath,${NCD},${BUILD}))
+
+${SVF}:${BIT}
+ ( cd ${BUILD} && \
+ echo -e "setMode -bs \n\
+ setCable -p svf -file \"$(call relpath,${SVF},${BUILD})\" \n\
+ addDevice -p 1 -file \"$(call relpath,${BIT},${BUILD})\" \n\
+ program -p 1 \n\
+ quit \n" > impact.run &&\
+ ${ISE_BINDIR_64}/impact -batch impact.run)
+
+
+${BUILD}/%.vhd:%.xco
+ mkdir -p ${BUILD}
+ (cd ${BUILD} && touch empty.prj && ${ISE_BINDIR_32}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj)
+
+
+planahead: ${NGC} ${TWX}
+ rm -rf ${PA}
+ mkdir -p ${PA}
+ echo 'create_project -name ${TOP} -dir "$(abspath ${PA})" -part ${PART}' >> ${PAT}
+ echo 'set srcset [get_property srcset [current_run -impl]]' >> ${PAT}
+ echo 'set_property design_mode GateLvl $$srcset' >> ${PAT}
+ echo 'set_property top ${TOP} [current_fileset]' >> ${PAT}
+ echo 'set_property edif_top_file "$(abspasth ${NGC})" [ get_property srcset [ current_run ] ]' >> ${PAT}
+ echo 'add_files -norecurse { {$(abspath ${BUILD})} }' >> ${PAT}
+ echo 'set_property target_constrs_file "$(abspath ${UCF})" [current_fileset -constrset]' >> ${PAT}
+ echo 'add_files [list {$(abspath ${UCF})}] -fileset [get_property constrset [current_run]]' >> ${PAT}
+ echo 'link_design' >> ${PAT}
+ echo 'read_xdl -file "$(abspath ${NCD})"' >> ${PAT}
+ echo 'if {[catch {read_twx -name results_1 -file "$(abspath ${TWX})"} eInfo]} {' >> ${PAT}
+ echo 'puts "WARNING: there was a problem importing \"$(abspath ${TWX})\": $$eInfo"' >> ${PAT}
+ echo '}' >> ${PAT}
+ (cd ${PA} && ${DS_HOME}/PlanAhead/bin/planAhead -log $(abspath ${PA}/pa.log) -journal $(abspath ${PA}/pa.jou) -source $(abspath ${PAT}))
+
+
+
+tidy:
+ git diff --exit-code -s ${VSRCS}
+ for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done
+
+
diff --git a/fpga/hp_lcd_driver/synchronizer.vhdl b/fpga/hp_lcd_driver/synchronizer.vhdl
new file mode 100644
index 0000000..302cef9
--- /dev/null
+++ b/fpga/hp_lcd_driver/synchronizer.vhdl
@@ -0,0 +1,26 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity synchronizer is
+ generic (stages : natural := 2);
+ port (clk : in std_logic;
+ i : in std_logic;
+ o : out std_logic);
+end synchronizer;
+
+architecture Behavioral of synchronizer is
+ signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0');
+ attribute ASYNC_REG : string;
+ attribute ASYNC_REG of flipflops : signal is "true";
+begin
+
+ o <= flipflops(flipflops'high);
+
+ clk_proc : process(clk, flipflops, i)
+ begin
+ if rising_edge(clk) then
+ flipflops <= flipflops(flipflops'high-1 downto 0) & i;
+ end if;
+ end process;
+
+end Behavioral;
diff --git a/fpga/hp_lcd_driver/tmds_encode.vhdl b/fpga/hp_lcd_driver/tmds_encode.vhdl
new file mode 100644
index 0000000..fe69a56
--- /dev/null
+++ b/fpga/hp_lcd_driver/tmds_encode.vhdl
@@ -0,0 +1,73 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+entity tmds_encode is
+ port (
+ sys_rst_n : in std_logic;
+ pclk : in std_logic;
+
+ r_in : in std_logic_vector(7 downto 0);
+ g_in : in std_logic_vector(7 downto 0);
+ b_in : in std_logic_vector(7 downto 0);
+ hsync : in std_logic;
+ vsync : in std_logic;
+ blank : in std_logic;
+
+
+ r_p10 : out std_logic_vector(9 downto 0);
+ g_p10 : out std_logic_vector(9 downto 0);
+ b_p10 : out std_logic_vector(9 downto 0);
+ c_p10 : out std_logic_vector(9 downto 0)
+
+ );
+end tmds_encode;
+
+
+architecture beh of tmds_encode is
+ signal ctrl : std_logic_vector(1 downto 0);
+
+begin
+
+ c_p10 <= "1111100000";
+
+ ctrl <= vsync & hsync;
+
+
+ enc_r : entity work.tmds_encoder
+ port map (
+ sys_rst_n => sys_rst_n,
+ clk => pclk,
+ ctrl => ctrl,
+ blank => blank,
+ din => r_in,
+ dout => r_p10
+ );
+
+ enc_g : entity work.tmds_encoder
+ port map (
+ sys_rst_n => sys_rst_n,
+ clk => pclk,
+ ctrl => "11",
+ blank => blank,
+ din => g_in,
+ dout => g_p10
+ );
+
+
+
+ enc_b : entity work.tmds_encoder
+ port map (
+ sys_rst_n => sys_rst_n,
+ clk => pclk,
+ ctrl => "11",
+ blank => blank,
+ din => b_in,
+ dout => b_p10
+ );
+
+
+end beh;
+
+
diff --git a/fpga/hp_lcd_driver/tmds_encoder.vhdl b/fpga/hp_lcd_driver/tmds_encoder.vhdl
new file mode 100644
index 0000000..40f8dd4
--- /dev/null
+++ b/fpga/hp_lcd_driver/tmds_encoder.vhdl
@@ -0,0 +1,117 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tmds_encoder is
+ port (
+ clk : in std_logic;
+ sys_rst_n : in std_logic;
+ blank : in std_logic;
+ ctrl : in std_logic_vector(1 downto 0);
+ din : in std_logic_vector(7 downto 0);
+ dout : out std_logic_vector(9 downto 0)
+ );
+end tmds_encoder;
+
+architecture beh of tmds_encoder is
+ signal n_ones_din : integer range 0 to 8;
+
+ signal xored, xnored : std_logic_vector(8 downto 0);
+ signal q_m : std_logic_vector(8 downto 0);
+
+ -- a positive value represents the excess number of 1's that have been transmitted
+ -- a negative value represents the excess number of 0's that have been transmitted
+ signal disparity : signed(3 downto 0) := to_signed(0, 4);
+ -- difference between 1's and 0's (/2 since the last bit is never used)
+ signal diff : signed(3 downto 0) := to_signed(0, 4);
+
+begin
+
+ -- ones counter for input data
+ process(din) is
+ variable c : integer range 0 to 8;
+ begin
+ c := 0;
+ for i in 0 to 7 loop
+ if din(i) = '1' then
+ c := c + 1;
+ end if;
+ end loop;
+ n_ones_din <= c;
+ end process;
+
+ -- create xor encodings
+ xored(0) <= din(0);
+ encode_xor : for i in 1 to 7 generate
+ begin
+ xored(i) <= din(i) xor xored(i - 1);
+ end generate;
+ xored(8) <= '1';
+
+ -- create xnor encodings
+ xnored(0) <= din(0);
+ encode_xnor : for i in 1 to 7 generate
+ begin
+ xnored(i) <= din(i) xnor xnored(i - 1);
+ end generate;
+ xnored(8) <= '0';
+
+ -- use xnored or xored data based on the ones
+ q_m <= xnored when n_ones_din > 4 or (n_ones_din = 4 and din(0) = '0') else xored;
+
+ -- ones counter for internal data
+ process(q_m) is
+ variable c : integer range 0 to 8;
+ begin
+ c := 0;
+ for i in 0 to 7 loop
+ if q_m(i) = '1' then
+ c := c + 1;
+ end if;
+ end loop;
+ diff <= to_signed(c-4, 4);
+ end process;
+
+ process(clk) is
+ begin
+ if rising_edge(clk) then
+ if blank = '1' then
+ case ctrl is
+ when "00" => dout <= "1101010100";
+ when "01" => dout <= "0010101011";
+ when "10" => dout <= "0101010100";
+ when others => dout <= "1010101011";
+ end case;
+ disparity <= (others => '0');
+ else
+ if disparity = 0 or diff = 0 then
+ -- xnored data
+ if q_m(8) = '0' then
+ dout <= "10" & not q_m(7 downto 0);
+ disparity <= disparity - diff;
+ -- xored data
+ else
+ dout <= "01" & q_m(7 downto 0);
+ disparity <= disparity + diff;
+ end if;
+ elsif (diff(diff'left) = '0' and disparity(disparity'left) = '0') or
+ (diff(diff'left) = '1' and disparity(disparity'left) = '1') then
+ dout <= '1' & q_m(8) & not q_m(7 downto 0);
+ if q_m(8) = '1' then
+ disparity <= disparity + 1 - diff;
+ else
+ disparity <= disparity - diff;
+ end if;
+ else
+ dout <= '0' & q_m;
+ if q_m(8) = '1' then
+ disparity <= disparity + diff;
+ else
+ disparity <= disparity - 1 + diff;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+end beh;
+
diff --git a/fpga/hp_lcd_driver/tmds_output_cyclone4.vhdl b/fpga/hp_lcd_driver/tmds_output_cyclone4.vhdl
new file mode 100644
index 0000000..8d71bd8
--- /dev/null
+++ b/fpga/hp_lcd_driver/tmds_output_cyclone4.vhdl
@@ -0,0 +1,95 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity tmds_output is
+ port (
+ sys_rst_n : in std_logic;
+ pclk_locked : in std_logic;
+ pclk : in std_logic;
+ pclk_x2 : in std_logic;
+ pclk_phy : in std_logic;
+
+ r_p10 : in std_logic_vector(9 downto 0);
+ g_p10 : in std_logic_vector(9 downto 0);
+ b_p10 : in std_logic_vector(9 downto 0);
+ c_p10 : in std_logic_vector(9 downto 0);
+
+
+ tmds_c_out_p : out std_logic;
+ tmds_c_out_n : out std_logic;
+ tmds_r_out_p : out std_logic;
+ tmds_r_out_n : out std_logic;
+ tmds_g_out_p : out std_logic;
+ tmds_g_out_n : out std_logic;
+ tmds_b_out_p : out std_logic;
+ tmds_b_out_n : out std_logic
+ );
+end tmds_output;
+
+
+architecture beh of tmds_output is
+
+ signal b : natural := 0;
+
+begin
+
+
+
+ process (pclk_phy, b, sys_rst_n)
+ begin
+ if sys_rst_n = '0' then
+ b <= 0;
+ elsif rising_edge(pclk_phy) then
+ if b = 4 then
+ b <= 0;
+ else
+ b <= b+1;
+ end if;
+ end if;
+ end process;
+
+
+ phy_c : entity work.tmds_phy_cyclone4
+ port map (
+ sys_rst_n => sys_rst_n,
+ pclk_phy => pclk_phy,
+ b => b,
+ din => c_p10,
+ tmds_out_p => tmds_c_out_p,
+ tmds_out_n => tmds_c_out_n
+ );
+
+ phy_r : entity work.tmds_phy_cyclone4
+ port map (
+ sys_rst_n => sys_rst_n,
+ pclk_phy => pclk_phy,
+ b => b,
+ din => r_p10,
+ tmds_out_p => tmds_r_out_p,
+ tmds_out_n => tmds_r_out_n
+ );
+
+
+ phy_g : entity work.tmds_phy_cyclone4
+ port map (
+ sys_rst_n => sys_rst_n,
+ pclk_phy => pclk_phy,
+ b => b,
+ din => g_p10,
+ tmds_out_p => tmds_g_out_p,
+ tmds_out_n => tmds_g_out_n
+ );
+
+
+ phy_b : entity work.tmds_phy_cyclone4
+ port map (
+ sys_rst_n => sys_rst_n,
+ pclk_phy => pclk_phy,
+ b => b,
+ din => b_p10,
+ tmds_out_p => tmds_b_out_p,
+ tmds_out_n => tmds_b_out_n
+ );
+
+end beh;
diff --git a/fpga/hp_lcd_driver/tmds_output_spartan6.vhdl b/fpga/hp_lcd_driver/tmds_output_spartan6.vhdl
new file mode 100644
index 0000000..9307563
--- /dev/null
+++ b/fpga/hp_lcd_driver/tmds_output_spartan6.vhdl
@@ -0,0 +1,121 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+entity tmds_output is
+ port (
+ sys_rst_n : in std_logic;
+ pclk_locked : in std_logic;
+ pclk : in std_logic;
+ pclk_x2 : in std_logic;
+ pclk_phy : in std_logic;
+
+ r_p10 : in std_logic_vector(9 downto 0);
+ g_p10 : in std_logic_vector(9 downto 0);
+ b_p10 : in std_logic_vector(9 downto 0);
+ c_p10 : in std_logic_vector(9 downto 0);
+
+
+ tmds_c_out_p : out std_logic;
+ tmds_c_out_n : out std_logic;
+ tmds_r_out_p : out std_logic;
+ tmds_r_out_n : out std_logic;
+ tmds_g_out_p : out std_logic;
+ tmds_g_out_n : out std_logic;
+ tmds_b_out_p : out std_logic;
+ tmds_b_out_n : out std_logic
+ );
+end tmds_output;
+
+
+architecture beh of tmds_output is
+
+
+ signal phy_reset : std_logic;
+ signal upper : std_logic;
+ signal pll_locked : std_logic;
+ signal ioclk : std_logic;
+ signal serdesstrobe : std_logic;
+
+begin
+ phy_reset <= not sys_rst_n or not pll_locked;
+
+ process (pclk_x2, phy_reset)
+ begin
+ if phy_reset = '1' then
+ upper <= '1';
+ elsif rising_edge(pclk_x2) then
+ upper <= not upper;
+ end if;
+ end process;
+
+
+ ioclk_buf : BUFPLL generic map (DIVIDE => 5)
+ port map (
+ PLLIN => pclk_phy,
+ GCLK => pclk_x2,
+ LOCKED => pclk_locked,
+ IOCLK => ioclk,
+ SERDESSTROBE => serdesstrobe,
+ LOCK => pll_locked);
+
+
+ phy_c : entity work.tmds_phy_spartan6
+ port map (
+ reset => phy_reset,
+ pclk_x2 => pclk_x2,
+ serdesstrobe => serdesstrobe,
+ ioclk => ioclk,
+ upper => upper,
+ din => c_p10,
+ tmds_out_p => tmds_c_out_p,
+ tmds_out_n => tmds_c_out_n
+ );
+
+ phy_r : entity work.tmds_phy_spartan6
+ port map (
+ reset => phy_reset,
+ pclk_x2 => pclk_x2,
+ serdesstrobe => serdesstrobe,
+ ioclk => ioclk,
+ upper => upper,
+ din => r_p10,
+ tmds_out_p => tmds_r_out_p,
+ tmds_out_n => tmds_r_out_n
+ );
+
+
+ phy_g : entity work.tmds_phy_spartan6
+ port map (
+ reset => phy_reset,
+ pclk_x2 => pclk_x2,
+ serdesstrobe => serdesstrobe,
+ ioclk => ioclk,
+ upper => upper,
+ din => g_p10,
+ tmds_out_p => tmds_g_out_p,
+ tmds_out_n => tmds_g_out_n
+ );
+
+
+ phy_b : entity work.tmds_phy_spartan6
+ port map (
+ reset => phy_reset,
+ pclk_x2 => pclk_x2,
+ serdesstrobe => serdesstrobe,
+ ioclk => pclk_phy,
+ upper => upper,
+ din => b_p10,
+ tmds_out_p => tmds_b_out_p,
+ tmds_out_n => tmds_b_out_n
+ );
+
+
+
+
+
+end beh;
diff --git a/fpga/hp_lcd_driver/tmds_phy_cyclone4.vhdl b/fpga/hp_lcd_driver/tmds_phy_cyclone4.vhdl
new file mode 100644
index 0000000..6160636
--- /dev/null
+++ b/fpga/hp_lcd_driver/tmds_phy_cyclone4.vhdl
@@ -0,0 +1,91 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+library altera_mf;
+use altera_mf.altera_mf_components.all;
+
+entity tmds_phy_cyclone4 is
+ port (
+ sys_rst_n : in std_logic;
+ pclk_phy : in std_logic;
+ b : natural;
+ din : in std_logic_vector(9 downto 0);
+ tmds_out_p : out std_logic;
+ tmds_out_n : out std_logic
+ );
+end tmds_phy_cyclone4;
+
+
+architecture beh of tmds_phy_cyclone4 is
+
+
+ signal d_rise : std_logic_vector(4 downto 0);
+ signal d_fall : std_logic_vector(4 downto 0);
+
+ signal out_p : std_logic_vector(0 downto 0);
+ signal out_n : std_logic_vector(0 downto 0);
+
+ signal bb : natural;
+
+begin
+
+
+ process (pclk_phy)
+ begin
+ if rising_edge(pclk_phy) then
+ if b = 4 then
+ d_rise <= (4 => din(8), 3 => din(6), 2 => din(4), 1 => din(2), 0 => din(0));
+ d_fall <= (4 => din(9), 3 => din(7), 2 => din(5), 1 => din(3), 0 => din(1));
+ --d_rise <= (4 => din(1), 3 => din(3), 2 => din(5), 1 => din(7), 0 => din(9));
+ --d_fall <= (4 => din(0), 3 => din(2), 2 => din(4), 1 => din(6), 0 => din(8));
+ else
+ d_rise(3 downto 0) <= d_rise(4 downto 1);
+ d_fall(3 downto 0) <= d_fall(4 downto 1);
+ end if;
+ end if;
+ end process;
+
+
+ obuf_p : ALTDDIO_OUT
+ generic map (
+ extend_oe_disable => "OFF",
+ intended_device_family => "Cyclone IV E",
+ invert_output => "OFF",
+ lpm_hint => "UNUSED",
+ lpm_type => "altddio_out",
+ oe_reg => "UNREGISTERED",
+ power_up_high => "OFF",
+ width => 1
+ )
+ port map (
+ aclr => not sys_rst_n,
+ datain_h => d_rise(0 downto 0),
+ datain_l => d_fall(0 downto 0),
+ outclock => not pclk_phy,
+ dataout => out_p
+ );
+ tmds_out_p <= out_p(0);
+
+ obuf_n : ALTDDIO_OUT
+ generic map (
+ extend_oe_disable => "OFF",
+ intended_device_family => "Cyclone IV E",
+ invert_output => "OFF",
+ lpm_hint => "UNUSED",
+ lpm_type => "altddio_out",
+ oe_reg => "UNREGISTERED",
+ power_up_high => "OFF",
+ width => 1
+ )
+ port map (
+ aclr => not sys_rst_n,
+ datain_h => not d_rise(0 downto 0),
+ datain_l => not d_fall(0 downto 0),
+ outclock => not pclk_phy,
+ dataout => out_n
+ );
+ tmds_out_n <= out_n(0);
+
+
+end beh;
diff --git a/fpga/hp_lcd_driver/tmds_phy_spartan6.vhdl b/fpga/hp_lcd_driver/tmds_phy_spartan6.vhdl
new file mode 100644
index 0000000..1f3d77e
--- /dev/null
+++ b/fpga/hp_lcd_driver/tmds_phy_spartan6.vhdl
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity tmds_phy_spartan6 is
+ port (
+ reset : in std_logic;
+ pclk_x2 : in std_logic;
+ ioclk : in std_logic;
+ serdesstrobe : in std_logic;
+ din : in std_logic_vector(9 downto 0);
+ upper : in std_logic;
+ tmds_out_p : out std_logic;
+ tmds_out_n : out std_logic
+ );
+end tmds_phy_spartan6;
+
+
+architecture beh of tmds_phy_spartan6 is
+
+ signal din_s : std_logic_vector(9 downto 0);
+ signal p5_n : std_logic_vector(4 downto 0);
+ signal p5 : std_logic_vector(4 downto 0);
+ signal s : std_logic;
+
+
+
+begin
+
+ process (pclk_x2)
+ begin
+ if rising_edge(pclk_x2) then
+ if upper = '1' then
+ din_s <= din;
+ p5 <= din_s(9 downto 5);
+ p5_n <= din_s(4 downto 0);
+ else
+ p5 <= p5_n;
+ end if;
+ end if;
+ end process;
+
+
+ serdes : entity work.serdes_n_to_1_spartan6
+ generic map(SF => 5)
+ port map (
+ ioclk => ioclk,
+ serdesstrobe => serdesstrobe,
+ reset => reset,
+ gclk => pclk_x2,
+ datain => p5,
+ iob_data_out => s
+ );
+
+ obuf : OBUFDS
+ generic map (IOSTANDARD => "TMDS_33")
+ port map (
+ I => s,
+ O => tmds_out_p,
+ OB => tmds_out_n
+ );
+
+
+end beh;
diff --git a/fpga/hp_lcd_driver/vram_cyclone4.vhdl b/fpga/hp_lcd_driver/vram_cyclone4.vhdl
new file mode 100644
index 0000000..bafb6b5
--- /dev/null
+++ b/fpga/hp_lcd_driver/vram_cyclone4.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vram is
+ generic (
+ addr_width : natural := 17;
+ video_width : natural := 2
+ );
+ port (
+ wr_clk : in std_logic;
+ wr_en : in std_logic;
+ wr_addr : in std_logic_vector(addr_width-1 downto 0);
+ wr_data : in std_logic_vector(video_width-1 downto 0);
+ rd_clk : in std_logic;
+ rd_addr : in std_logic_vector(addr_width-1 downto 0);
+ rd_data : out std_logic_vector(video_width-1 downto 0)
+ );
+end vram;
+
+architecture beh of vram is
+begin
+
+
+
+ vram_impl0 : entity work.vram_cyclone4_impl
+ port map (
+ wrclock => wr_clk,
+ wren => wr_en,
+ wraddress => wr_addr,
+ data => wr_data,
+ rdclock => rd_clk,
+ q => rd_data,
+ rdaddress => rd_addr
+ );
+end beh;
diff --git a/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl b/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl
new file mode 100644
index 0000000..aea5b80
--- /dev/null
+++ b/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl
@@ -0,0 +1,231 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram
+
+-- ============================================================
+-- File Name: vram_cyclone4_impl.vhd
+-- Megafunction Name(s):
+-- altsyncram
+--
+-- Simulation Library Files(s):
+--
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY vram_cyclone4_impl IS
+ PORT
+ (
+ data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ rdaddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+ rdclock : IN STD_LOGIC ;
+ wraddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+ wrclock : IN STD_LOGIC := '1';
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+ );
+END vram_cyclone4_impl;
+
+
+ARCHITECTURE SYN OF vram_cyclone4_impl IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+
+
+
+ COMPONENT altsyncram
+ GENERIC (
+ address_aclr_b : STRING;
+ address_reg_b : STRING;
+ clock_enable_input_a : STRING;
+ clock_enable_input_b : STRING;
+ clock_enable_output_b : STRING;
+ intended_device_family : STRING;
+ lpm_type : STRING;
+ numwords_a : NATURAL;
+ numwords_b : NATURAL;
+ operation_mode : STRING;
+ outdata_aclr_b : STRING;
+ outdata_reg_b : STRING;
+ power_up_uninitialized : STRING;
+ widthad_a : NATURAL;
+ widthad_b : NATURAL;
+ width_a : NATURAL;
+ width_b : NATURAL;
+ width_byteena_a : NATURAL
+ );
+ PORT (
+ address_a : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+ clock0 : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ wren_a : IN STD_LOGIC ;
+ address_b : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+ clock1 : IN STD_LOGIC
+ );
+ END COMPONENT;
+
+BEGIN
+ q <= sub_wire0(1 DOWNTO 0);
+
+ altsyncram_component : altsyncram
+ GENERIC MAP (
+ address_aclr_b => "NONE",
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ intended_device_family => "Cyclone IV E",
+ lpm_type => "altsyncram",
+ numwords_a => 228096,
+ numwords_b => 228096,
+ operation_mode => "DUAL_PORT",
+ outdata_aclr_b => "NONE",
+ outdata_reg_b => "UNREGISTERED",
+ power_up_uninitialized => "FALSE",
+ widthad_a => 18,
+ widthad_b => 18,
+ width_a => 2,
+ width_b => 2,
+ width_byteena_a => 1
+ )
+ PORT MAP (
+ address_a => wraddress,
+ clock0 => wrclock,
+ data_a => data,
+ wren_a => wren,
+ address_b => rdaddress,
+ clock1 => rdclock,
+ q_b => sub_wire0
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "1"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "456192"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "2"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "2"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "2"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "2"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "228096"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "228096"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "18"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "18"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "2"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "2"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]"
+-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]"
+-- Retrieval info: USED_PORT: rdaddress 0 0 18 0 INPUT NODEFVAL "rdaddress[17..0]"
+-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
+-- Retrieval info: USED_PORT: wraddress 0 0 18 0 INPUT NODEFVAL "wraddress[17..0]"
+-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 18 0 wraddress 0 0 18 0
+-- Retrieval info: CONNECT: @address_b 0 0 18 0 rdaddress 0 0 18 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 2 0 data 0 0 2 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 2 0 @q_b 0 0 2 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.vhd FALSE
diff --git a/fpga/hp_lcd_driver/vram_spartan6.vhdl b/fpga/hp_lcd_driver/vram_spartan6.vhdl
new file mode 100644
index 0000000..801cc0a
--- /dev/null
+++ b/fpga/hp_lcd_driver/vram_spartan6.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vram is
+ generic (
+ addr_width : natural := 17;
+ video_width : natural := 2
+ );
+ port (
+ wr_clk : in std_logic;
+ wr_en : in std_logic;
+ wr_addr : in std_logic_vector(addr_width-1 downto 0);
+ wr_data : in std_logic_vector(video_width-1 downto 0);
+ rd_clk : in std_logic;
+ rd_addr : in std_logic_vector(addr_width-1 downto 0);
+ rd_data : out std_logic_vector(video_width-1 downto 0)
+ );
+end vram;
+
+architecture beh of vram is
+ signal wr_en_v : std_logic_vector(0 downto 0);
+begin
+
+ wr_en_v(0) <= wr_en;
+
+ vram_impl0 : entity work.vram_spartan6_impl
+ port map (
+ clka => wr_clk,
+ wea => wr_en_v,
+ addra => wr_addr,
+ dina => wr_data,
+ clkb => rd_clk,
+ doutb => rd_data,
+ addrb => rd_addr
+ );
+end beh;
diff --git a/fpga/hp_lcd_driver/vram_spartan6_impl.xco b/fpga/hp_lcd_driver/vram_spartan6_impl.xco
new file mode 100644
index 0000000..131955a
--- /dev/null
+++ b/fpga/hp_lcd_driver/vram_spartan6_impl.xco
@@ -0,0 +1,108 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Mon Apr 28 10:29:36 2025
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=vram_spartan6_impl
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Always_Enabled
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET mem_file=no_Mem_file_loaded
+CSET memory_type=Simple_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=2
+CSET read_width_b=2
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_bram_block=Stand_Alone
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=228096
+CSET write_width_a=2
+CSET write_width_b=2
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T16:22:25Z
+# END Extra information
+GENERATE
+# CRC: 10ea0a8c
diff --git a/fpga/hp_lcd_driver/xilinx_ise_vivado_license.lic b/fpga/hp_lcd_driver/xilinx_ise_vivado_license.lic
new file mode 100644
index 0000000..7bbf3f3
--- /dev/null
+++ b/fpga/hp_lcd_driver/xilinx_ise_vivado_license.lic
@@ -0,0 +1,868 @@
+
+INCREMENT VIVADO_HLS xilinxd 2037.05 permanent uncounted AF3E86892AA2 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER="Xilinx \
+ Inc" START=19-May-2016 TS_OK
+INCREMENT Vivado_System_Edition xilinxd 2037.05 permanent uncounted \
+ A1074C37F742 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER="Xilinx Inc" START=19-May-2016 TS_OK
+PACKAGE Vivado_System_Edition xilinxd 2037.05 DFF4A65E0A68 \
+ COMPONENTS="ISIM ChipScopePro_SIOTK PlanAhead ChipscopePro XPS \
+ ISE HLS_Synthesis AccelDSP Vivado Rodin_Synthesis \
+ Rodin_Implementation Rodin_SystemBuilder \
+ PartialReconfiguration AUTOESL_FLOW AUTOESL_CC AUTOESL_OPT \
+ AUTOESL_SC AUTOESL_XILINX petalinux_arch_ppc \
+ petalinux_arch_microblaze petalinux_arch_zynq ap_sdsoc SDK \
+ SysGen Simulation Implementation Analyzer HLS Synthesis \
+ VIVADO_HLS" OPTIONS=SUITE
+
+
+# 2037年之前的任何ISE_Vivado版本（包括HLS、AccelDSP、System Generator、软硬CPU、SOC、嵌入式Linux、重配置等等功能）都是永久使用。使用本license文件时要改名，文件名不能有汉字和空格。
+
+#MAIN
+INCREMENT System_Edition xilinxd 2025.01 permanent uncounted \
+ 6C8EE4B2A5BE \
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+ 4CB6784CF723 \
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+PACKAGE System_Edition xilinxd 2025.01 51F6657975B5 COMPONENTS="SDK \
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+ OPTIONS=SUITE
+PACKAGE Web_Package xilinxd 2025.01 D1C67FF037CB \
+ COMPONENTS="PlanAhead WebPACK" OPTIONS=SUITE
+#EDK
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+ B72B1D505BFB \
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+ F313A29B6200 \
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+ 2E4EA3E01CCA \
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+ 9E0A2391B893 \
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+#IP CORES
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+ ISSUER=TBE TS_OK
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+ ISSUER=TBE TS_OK
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+ ISSUER=TBE TS_OK
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+ 8D06BF0FF2CB VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
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+ ISSUER=TBE TS_OK
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+FEATURE opb_uart16550_v1_00_c xilinxd 1.0 permanent uncounted \
+ CA1CF007709B VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE opb_usb2_device_v1 xilinxd 1.0 permanent uncounted \
+ 456AFEF10E09 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
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+FEATURE pci32_v4 xilinxd 1.0 permanent uncounted 1B7B5C5454FA \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pci32_vx_v3_0 xilinxd 1.0 permanent uncounted 5DA21C837B61 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pci32_vx_v3_1 xilinxd 1.0 permanent uncounted 2197482D4A2E \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pci64_sp_v3_0 xilinxd 1.0 permanent uncounted F48202EAA461 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pci64_sp_v3_1 xilinxd 1.0 permanent uncounted 33A18EF8F930 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pci64_v3_0 xilinxd 1.0 permanent uncounted 820C2FFB2D7B \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pci64_v3_1 xilinxd 1.0 permanent uncounted 42CC9AF42DE4 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pci64_v4 xilinxd 1.0 permanent uncounted DF558BE27D63 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pci64_vx_v3_0 xilinxd 1.0 permanent uncounted 866F0C4B54B5 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pci64_vx_v3_1 xilinxd 1.0 permanent uncounted 26AD3021DBFE \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pci_express_v3 xilinxd 1.0 permanent uncounted 411DF26D12AC \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pcie_blk_plus_v1 xilinxd 1.0 permanent uncounted A0F69789D453 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pcie_pipe_v1 xilinxd 1.0 permanent uncounted 4718088F9ED0 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pcix64_v5_0 xilinxd 1.0 permanent uncounted 6D318519D8A7 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pcix64_v5_1 xilinxd 1.0 permanent uncounted D0989320B8AD \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pcix_v6 xilinxd 1.0 permanent uncounted C3D5C1B1832F \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pcix_v6 xilinxd 1.0 permanent uncounted C3D5C1B1832F \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pl4_lite_v3 xilinxd 1.0 permanent uncounted B8111115AB1F \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pl4_lite_v4 xilinxd 1.0 permanent uncounted 3954CB3063E1 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pl4_v6 xilinxd 1.0 permanent uncounted 7FF4667FB12C \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pl4_v7_0 xilinxd 1.0 permanent uncounted 0FF066DE534B \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pl4_v7_1 xilinxd 1.0 permanent uncounted EF9E3283CCA8 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pl4_v7_2 xilinxd 1.0 permanent uncounted 581C3664E14D \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pl4_v7_3 xilinxd 1.0 permanent uncounted 5B895A813AE2 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pl4_v7_4 xilinxd 1.0 permanent uncounted CC056E528F67 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pl4_v8 xilinxd 1.0 permanent uncounted AE85EE354D70 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE pl4_v9 xilinxd 1.0 permanent uncounted 6A65864AD564 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE plb_ethernet_v1 xilinxd 1.0 permanent uncounted DAB487807E2C \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE plb_ethernet_v1_00_a xilinxd 1.0 permanent uncounted \
+ AFAA62330628 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE plb_pci_v1 xilinxd 1.0 permanent uncounted 78DFC23D19A7 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE plb_temac_v1 xilinxd 1.0 permanent uncounted 23DAFBF08E01 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE plb_uart16550_v1_00_b xilinxd 1.0 permanent uncounted \
+ E5601D14673E VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE plb_uart16550_v1_00_c xilinxd 1.0 permanent uncounted \
+ 7E98F1EA2A1B VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE plbv46_pci_v1 xilinxd 1.0 permanent uncounted 56FD6B9024B2 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rach_3gpp_v1 xilinxd 1.0 permanent uncounted 92A5C704F378 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rio_log_io_v3 xilinxd 1.0 permanent uncounted 28AF836971F0 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rio_log_io_v4 xilinxd 1.0 permanent uncounted 32A3975FB68F \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rio_log_io_v5 xilinxd 1.0 permanent uncounted 4834D359A3B2 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rs_decoder_v4_0 xilinxd 1.0 permanent uncounted F16B5F2BDBD0 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rs_decoder_v4_1 xilinxd 1.0 permanent uncounted C6E6BCAC888D \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rs_decoder_v5_0 xilinxd 1.0 permanent uncounted 5C72ED9FEE3B \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rs_decoder_v5_1 xilinxd 1.0 permanent uncounted B7EEFEA4C3C4 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rs_decoder_v6 xilinxd 1.0 permanent uncounted 5DE6AA5A935B \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rs_encoder_v4_0 xilinxd 1.0 permanent uncounted 84728CBDBE09 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rs_encoder_v4_1 xilinxd 1.0 permanent uncounted 76D6F3A40130 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rs_encoder_v5_0 xilinxd 1.0 permanent uncounted 227AA68D35A0 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE rs_encoder_v6 xilinxd 1.0 permanent uncounted 799525121092 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE s6_pcie_v1 xilinxd 1.0 permanent uncounted E9E23E29A077 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE searcher_3gpp_v1 xilinxd 1.0 permanent uncounted 267795F52001 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE sid_v3_0 xilinxd 1.0 permanent uncounted 91826E4DCAC5 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE sid_v3_1 xilinxd 1.0 permanent uncounted 98269EF471E8 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE sid_v4_0 xilinxd 1.0 permanent uncounted D4C022AC0485 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE sid_v5 xilinxd 1.0 permanent uncounted 2D591CC91654 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE soft_temac_wrap_v2 xilinxd 1.0 permanent uncounted \
+ 37A8FB9B23BB VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE soft_temac_wrap_v2 xilinxd 1.0 permanent uncounted \
+ 37A8FB9B23BB VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE soft_temac_wrap_v2 xilinxd 1.0 permanent uncounted \
+ 37A8FB9B23BB VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE spi3_link_v4 xilinxd 1.0 permanent uncounted 6550AE2CC217 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE spi3_link_v5 xilinxd 1.0 permanent uncounted 22535DFC8904 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE srio_phy_v3 xilinxd 1.0 permanent uncounted 34E2C6A82394 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE srio_phy_v4 xilinxd 1.0 permanent uncounted 261404DFFBD2 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE srio_phy_v5 xilinxd 1.0 permanent uncounted F945D29A3318 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE tcc_dec_802_16e_v3 xilinxd 1.0 permanent uncounted \
+ FC46344344AC VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_decoder_3gpp_v1 xilinxd 1.0 permanent uncounted \
+ 761B026F8431 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_decoder_3gpp_v2 xilinxd 1.0 permanent uncounted \
+ 220CD044F00B VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_decoder_3gpp_v3 xilinxd 1.0 permanent uncounted \
+ C277560D4485 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_decoder_v1_0 xilinxd 1.0 permanent uncounted B3CD1B8D082D \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE tcc_decoder_v2 xilinxd 1.0 permanent uncounted 78B087547630 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE tcc_enc_802_16e_v1 xilinxd 1.0 permanent uncounted \
+ B13AE37DF0F3 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_enc_802_16e_v2 xilinxd 1.0 permanent uncounted \
+ A8110686F018 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_enc_802_16e_v3 xilinxd 1.0 permanent uncounted \
+ 5542B94784B9 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_encoder_3gpp2_v2 xilinxd 1.0 permanent uncounted \
+ 55E5506FF871 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_encoder_3gpp_v1 xilinxd 1.0 permanent uncounted \
+ 7E9021CF8A68 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_encoder_3gpp_v2 xilinxd 1.0 permanent uncounted \
+ 37DAC3400AE6 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_encoder_3gpp_v3 xilinxd 1.0 permanent uncounted \
+ D05CED8DEA04 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_encoder_3gpplte_v1 xilinxd 1.0 permanent uncounted \
+ FA954EDC6644 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_encoder_3gpplte_v2 xilinxd 1.0 permanent uncounted \
+ AF13A26D2A84 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_encoder_3gpplte_v3 xilinxd 1.0 permanent uncounted \
+ B8AEC6BA9228 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tcc_encoder_v1_0 xilinxd 1.0 permanent uncounted 10A6DCAD9032 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE tcc_encoder_v2 xilinxd 1.0 permanent uncounted C6303E8E8AB7 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE ten_gig_eth_mac_v3_0 xilinxd 1.0 permanent uncounted \
+ FE7FA96DC209 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE ten_gig_eth_mac_v4_0 xilinxd 1.0 permanent uncounted \
+ 3D78BE7FFB09 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE ten_gig_eth_mac_v5_0 xilinxd 1.0 permanent uncounted \
+ D9F32B313CF9 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE ten_gig_eth_mac_v6 xilinxd 1.0 permanent uncounted \
+ 52B1F49A5E44 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE ten_gig_eth_mac_v7 xilinxd 1.0 permanent uncounted \
+ 54D45175AACB VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE ten_gig_eth_mac_v8 xilinxd 1.0 permanent uncounted \
+ CF5B3E18723E VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE ten_gig_eth_mac_v9 xilinxd 1.0 permanent uncounted \
+ D7585BCBE6BD VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tri_mode_eth_mac_v1_1 xilinxd 1.0 permanent uncounted \
+ C7CEA08BDCFC VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tri_mode_eth_mac_v2 xilinxd 1.0 permanent uncounted \
+ ABE76A88CA6E VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tri_mode_eth_mac_v3 xilinxd 1.0 permanent uncounted \
+ 5CDF9C53F240 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE tri_mode_eth_mac_v4 xilinxd 1.0 permanent uncounted \
+ 7D33C6DEFA42 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE usb2_device_v1 xilinxd 1.0 permanent uncounted 413A962BB3B5 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v4_emac_v4 xilinxd 1.0 permanent uncounted E8CD590D5F95 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v5_emac_v1 xilinxd 1.0 permanent uncounted 6B43DBDEA624 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v6_emac_v1 xilinxd 1.0 permanent uncounted 3389D292C586 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v6_pcie_v1 xilinxd 1.0 permanent uncounted 66C26376108D \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_ccm_v1 xilinxd 1.0 permanent uncounted FC78EA17EC44 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_cfa_v1 xilinxd 1.0 permanent uncounted CCE695B50743 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_gamma_v1 xilinxd 1.0 permanent uncounted 7D443B085222 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_manr_v1_0 xilinxd 1.0 permanent uncounted B69F9899DF26 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_osd_v1_0 xilinxd 1.0 permanent uncounted 922B5A27966E \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_rgb2ycrcb_v2 xilinxd 1.0 permanent uncounted 5A9EC2D65098 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_scaler_v1_0 xilinxd 1.0 permanent uncounted 839E598E6B7E \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_spc_v1 xilinxd 1.0 permanent uncounted AEDBBF85573B \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_stats xilinxd 1.0 permanent uncounted 45D5B2867638 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_vdma_v1_0 xilinxd 1.0 permanent uncounted 6D2FE7B1C430 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE v_ycrcb2rgb_v2 xilinxd 1.0 permanent uncounted 2199142CE967 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE viterbi_v3_0 xilinxd 1.0 permanent uncounted 1C1BD96E4B3F \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE viterbi_v4_0 xilinxd 1.0 permanent uncounted 80C17A0C8067 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE viterbi_v5 xilinxd 1.0 permanent uncounted 7CB89938A6A7 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE viterbi_v6 xilinxd 1.0 permanent uncounted 4BB4AA973E36 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE viterbi_v7 xilinxd 1.0 permanent uncounted CD72C7F24265 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xaui_v3_0 xilinxd 1.0 permanent uncounted 84FF2CB438C8 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xaui_v4_0 xilinxd 1.0 permanent uncounted 1A3375A18383 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xaui_v5_0 xilinxd 1.0 permanent uncounted 73A816BAEAD6 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xaui_v6 xilinxd 1.0 permanent uncounted 0A133CCB48BE \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xaui_v7 xilinxd 1.0 permanent uncounted ABE4EFB22B11 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xaui_v8 xilinxd 1.0 permanent uncounted 95611EC9AE30 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xps_ethernetlite_v1 xilinxd 1.0 permanent uncounted \
+ 0DCC01521040 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE xps_iic_v1 xilinxd 1.0 permanent uncounted EED8E0E0018C \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xps_iic_v2 xilinxd 1.0 permanent uncounted 63E02FDD85DD \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xps_ll_temac_v1 xilinxd 1.0 permanent uncounted 7E111B83BB69 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xps_ll_temac_v2 xilinxd 1.0 permanent uncounted 88BD20FC443A \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xps_most_nic_v1 xilinxd 1.0 permanent uncounted BA4709E5F490 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xps_uart16550_v1 xilinxd 1.0 permanent uncounted 0C6D10C38436 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+FEATURE xps_usb2_device_v1 xilinxd 1.0 permanent uncounted \
+ 141B341EFE6A VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE xps_usb2_device_v2 xilinxd 1.0 permanent uncounted \
+ D92DB54D5681 VENDOR_STRING=License_Type:Bought HOSTID=ANY \
+ ISSUER=TBE TS_OK
+FEATURE xps_usb_host_v1 xilinxd 1.0 permanent uncounted 6F1DA718F354 \
+ VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT 10_100_mb_eth_mac xilinxd 2025.01 permanent uncounted \
+ 530B99880011 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,10_100_mb_eth_mac,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT apu_fpu_sp xilinxd 2025.01 permanent uncounted 90804736A408 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,apu_fpu_sp,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT aurora xilinxd 2025.01 permanent uncounted 565A2C0C7C2A \
+ VENDOR_STRING=License_Type:Bought;something@my.door,aurora,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT aurora_64b66b xilinxd 2025.01 permanent uncounted \
+ 591AA0BA6328 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,aurora_64b66b,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT aurora_8b10b xilinxd 2025.01 permanent uncounted \
+ 727E982720ED \
+ VENDOR_STRING=License_Type:Bought;something@my.door,aurora_8b10b,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT axi_ethernet_avb xilinxd 2025.01 permanent uncounted \
+ 39CB8CC302D3 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,axi_ethernet_avb,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT axi_ethernet_soft_10_100 xilinxd 2025.01 permanent \
+ uncounted 16BEB38BF8D3 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,axi_ethernet_soft_10_100,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT axi_ethernet_soft_tri_mode xilinxd 2025.01 permanent \
+ uncounted 989C71D32E5A \
+ VENDOR_STRING=License_Type:Bought;something@my.door,axi_ethernet_soft_tri_mode,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT axi_usb2_device xilinxd 2025.01 permanent uncounted \
+ 9EB8203C9277 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,axi_usb2_device,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT displayport xilinxd 2025.01 permanent uncounted \
+ D667271F21FE \
+ VENDOR_STRING=License_Type:Bought;something@my.door,displayport,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT dvb_s2_fec_encoder xilinxd 2025.01 permanent uncounted \
+ 57185A1B59B9 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,dvb_s2_fec_encoder,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT eth_avb_endpoint xilinxd 2025.01 permanent uncounted \
+ 89D4AEC801FA \
+ VENDOR_STRING=License_Type:Bought;something@my.door,eth_avb_endpoint,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT ethernet_statistics xilinxd 2025.01 permanent uncounted \
+ C7EF53BEE7E4 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,ethernet_statistics,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT gig_eth_pcs_pma xilinxd 2025.01 permanent uncounted \
+ 22DFD29A428C \
+ VENDOR_STRING=License_Type:Bought;something@my.door,gig_eth_pcs_pma,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT most_nic xilinxd 2025.01 permanent uncounted 16479405C7AB \
+ VENDOR_STRING=License_Type:Bought;something@my.door,most_nic,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT opb_ethernet xilinxd 2025.01 permanent uncounted \
+ 18DF3A8D91C0 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,opb_ethernet,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT opb_ethernetlite xilinxd 2025.01 permanent uncounted \
+ 1D4861BF7952 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,opb_ethernetlite,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT opb_iic xilinxd 2025.01 permanent uncounted CEB24EBEE09C \
+ VENDOR_STRING=License_Type:Bought;something@my.door,opb_iic,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT opb_pci xilinxd 2025.01 permanent uncounted D3F0B6E440EC \
+ VENDOR_STRING=License_Type:Bought;something@my.door,opb_pci,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT opb_uart16550 xilinxd 2025.01 permanent uncounted \
+ 586CAB028EB2 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,opb_uart16550,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT opb_usb2_device xilinxd 2025.01 permanent uncounted \
+ 136E687A284D \
+ VENDOR_STRING=License_Type:Bought;something@my.door,opb_usb2_device,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pci32 xilinxd 2025.01 permanent uncounted A19660B1DB76 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pci32,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pci32_sp xilinxd 2025.01 permanent uncounted 7BE9110B4E9F \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pci32_sp,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pci32_spng xilinxd 2025.01 permanent uncounted E20287D573B4 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pci32_spng,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pci32_vx xilinxd 2025.01 permanent uncounted 7747B83629D8 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pci32_vx,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pci64 xilinxd 2025.01 permanent uncounted 977B6022A12C \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pci64,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pci64_sp xilinxd 2025.01 permanent uncounted 5DC2AE9517C3 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pci64_sp,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pci64_vx xilinxd 2025.01 permanent uncounted B69DB7C2BAA8 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pci64_vx,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pci_express xilinxd 2025.01 permanent uncounted \
+ 6B3F1FF99514 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pci_express,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pcie_blk_plus xilinxd 2025.01 permanent uncounted \
+ E72DFF1F5861 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pcie_blk_plus,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pcie_pipe xilinxd 2025.01 permanent uncounted 225F733BB141 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pcie_pipe,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pcix xilinxd 2025.01 permanent uncounted 23DE4C46E618 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pcix,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pcix64 xilinxd 2025.01 permanent uncounted EA7B350C665D \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pcix64,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pl4 xilinxd 2025.01 permanent uncounted 8106EA66CAE8 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pl4,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT pl4_lite xilinxd 2025.01 permanent uncounted 995F5573B6F6 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,pl4_lite,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT plb_ethernet xilinxd 2025.01 permanent uncounted \
+ 007A7B1D125D \
+ VENDOR_STRING=License_Type:Bought;something@my.door,plb_ethernet,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT plb_pci xilinxd 2025.01 permanent uncounted 32EC1D310E24 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,plb_pci,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT plb_temac xilinxd 2025.01 permanent uncounted CBE222B89778 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,plb_temac,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT plb_uart16550 xilinxd 2025.01 permanent uncounted \
+ 7015A7B42C58 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,plb_uart16550,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT plbv46_pci xilinxd 2025.01 permanent uncounted 3048B0E79082 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,plbv46_pci,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT rach_3gpp xilinxd 2025.01 permanent uncounted D4E3EEF966F9 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,rach_3gpp,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT rio_log_io xilinxd 2025.01 permanent uncounted D03DCAAD36DF \
+ VENDOR_STRING=License_Type:Bought;something@my.door,rio_log_io,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT rs_decoder xilinxd 2025.01 permanent uncounted 323D14438FEA \
+ VENDOR_STRING=License_Type:Bought;something@my.door,rs_decoder,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT rs_encoder xilinxd 2025.01 permanent uncounted 270050C8EE93 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,rs_encoder,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT rxaui xilinxd 2025.01 permanent uncounted 52919CF58879 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,rxaui,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT s6_pcie xilinxd 2025.01 permanent uncounted 727B47881BC5 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,s6_pcie,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT searcher_3gpp xilinxd 2025.01 permanent uncounted \
+ A65E15863F63 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,searcher_3gpp,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT sid xilinxd 2025.01 permanent uncounted DD18B1416F16 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,sid,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT soft_temac_wrap xilinxd 2025.01 permanent uncounted \
+ C20E0610E84C \
+ VENDOR_STRING=License_Type:Bought;something@my.door,soft_temac_wrap,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT spi3_link xilinxd 2025.01 permanent uncounted A17BEC2CF1A1 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,spi3_link,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT srio_phy xilinxd 2025.01 permanent uncounted 66BC4648C9E1 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,srio_phy,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT tcc_dec_802_16e xilinxd 2025.01 permanent uncounted \
+ C77D9486CA92 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,tcc_dec_802_16e,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT tcc_decoder xilinxd 2025.01 permanent uncounted \
+ 536133697041 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,tcc_decoder,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT tcc_decoder_3gpp xilinxd 2025.01 permanent uncounted \
+ 7C7749FC55D3 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,tcc_decoder_3gpp,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT tcc_enc_802_16e xilinxd 2025.01 permanent uncounted \
+ F62DF6802691 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,tcc_enc_802_16e,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT tcc_encoder xilinxd 2025.01 permanent uncounted \
+ 86740946E9B5 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,tcc_encoder,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT tcc_encoder_3gpp xilinxd 2025.01 permanent uncounted \
+ 1A29EB794DE3 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,tcc_encoder_3gpp,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT tcc_encoder_3gpp2 xilinxd 2025.01 permanent uncounted \
+ 4C9F3033B817 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,tcc_encoder_3gpp2,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT tcc_encoder_3gpplte xilinxd 2025.01 permanent uncounted \
+ 40068708EF3E \
+ VENDOR_STRING=License_Type:Bought;something@my.door,tcc_encoder_3gpplte,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT ten_gig_eth_mac xilinxd 2025.01 permanent uncounted \
+ 1FAAC4242080 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,ten_gig_eth_mac,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT ten_gig_eth_pcs_pma xilinxd 2025.01 permanent uncounted \
+ 97D1736C43D5 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,ten_gig_eth_pcs_pma,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT tri_mode_eth_mac xilinxd 2025.01 permanent uncounted \
+ BCE4C86624FE \
+ VENDOR_STRING=License_Type:Bought;something@my.door,tri_mode_eth_mac,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT tri_mode_eth_mac xilinxd 2025.01 permanent uncounted \
+ BCE4C86624FE \
+ VENDOR_STRING=License_Type:Bought;something@my.door,tri_mode_eth_mac,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT usb2_device xilinxd 2025.01 permanent uncounted \
+ B492256307F9 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,usb2_device,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v4_emac xilinxd 2025.01 permanent uncounted 09145472B2AC \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v4_emac,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v5_emac xilinxd 2025.01 permanent uncounted B6F1D74BCB8A \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v5_emac,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v6_emac xilinxd 2025.01 permanent uncounted BD5156D8047C \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v6_emac,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v6_pcie xilinxd 2025.01 permanent uncounted E9D666E705A1 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v6_pcie,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_ccm xilinxd 2025.01 permanent uncounted 7AD010DD28C0 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_ccm,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_cfa xilinxd 2025.01 permanent uncounted 9F715C28A85E \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_cfa,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_enhance xilinxd 2025.01 permanent uncounted E574A01CAEA2 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_enhance,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_gamma xilinxd 2025.01 permanent uncounted 25C9831933DC \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_gamma,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_ic xilinxd 2025.01 permanent uncounted 7D9B9C609F81 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_ic,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_manr xilinxd 2025.01 permanent uncounted 4DEFCA0501FC \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_manr,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_noise xilinxd 2025.01 permanent uncounted AB4E3E6EFB2A \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_noise,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_osd xilinxd 2025.01 permanent uncounted 0081DED1457C \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_osd,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_rgb2ycrcb xilinxd 2025.01 permanent uncounted \
+ 72C4AD19C087 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_rgb2ycrcb,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_scaler xilinxd 2025.01 permanent uncounted B8AC427C142E \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_scaler,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_spc xilinxd 2025.01 permanent uncounted 8987C422925A \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_spc,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_stats xilinxd 2025.01 permanent uncounted 5B29F97906AE \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_stats,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_timebase xilinxd 2025.01 permanent uncounted F0A664DD3BC1 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_timebase,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_vdma xilinxd 2025.01 permanent uncounted A1178EBC0A71 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_vdma,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT v_ycrcb2rgb xilinxd 2025.01 permanent uncounted \
+ 275D6501AAFF \
+ VENDOR_STRING=License_Type:Bought;something@my.door,v_ycrcb2rgb,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT viterbi xilinxd 2025.01 permanent uncounted F1CE3A4935FB \
+ VENDOR_STRING=License_Type:Bought;something@my.door,viterbi,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT xaui xilinxd 2025.01 permanent uncounted 3F7D423C5949 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,xaui,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT xps_ethernetlite xilinxd 2025.01 permanent uncounted \
+ 1F541E037D3B \
+ VENDOR_STRING=License_Type:Bought;something@my.door,xps_ethernetlite,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT xps_iic xilinxd 2025.01 permanent uncounted ECE50E8A14D2 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,xps_iic,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT xps_ll_temac xilinxd 2025.01 permanent uncounted \
+ 9916DCBF4FFE \
+ VENDOR_STRING=License_Type:Bought;something@my.door,xps_ll_temac,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT xps_most_nic xilinxd 2025.01 permanent uncounted \
+ 808EB27FFF20 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,xps_most_nic,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT xps_uart16550 xilinxd 2025.01 permanent uncounted \
+ CA0CCA55C2E3 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,xps_uart16550,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT xps_usb2_device xilinxd 2025.01 permanent uncounted \
+ 21D83A343890 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,xps_usb2_device,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
+INCREMENT xps_usb_host xilinxd 2025.01 permanent uncounted \
+ 2170DE459192 \
+ VENDOR_STRING=License_Type:Bought;something@my.door,xps_usb_host,ip,permanent,_0_0_0 \
+ HOSTID=ANY ISSUER=TBE TS_OK
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-23 17:34:24 +0000