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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-02-09 23:02:49 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-02-09 23:02:49 +0000
commitc2d458110ccf32fd9c28850f5c953e12e4ef9b2c (patch)
tree0bd569cace42d16dee19e2624c084a14b2d871e2 /os/hal/platforms/STM32/i2c_lld.c
parent76bac6bb8704e039a7f9e4b34da7af3bd909c2bd (diff)
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I2C. Begin of 10-bit slave address realization.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@2727 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/i2c_lld.c')
-rw-r--r--os/hal/platforms/STM32/i2c_lld.c21
1 files changed, 17 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c
index 65cdec1b3..68e42972c 100644
--- a/os/hal/platforms/STM32/i2c_lld.c
+++ b/os/hal/platforms/STM32/i2c_lld.c
@@ -112,12 +112,25 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
if ((i2cp->id_state == I2C_READY) && (i2cp->id_i2c->SR1 & I2C_SR1_SB)){// start bit sent
i2cp->id_state = I2C_MACTIVE;
- //TODO: 10 bit address handling
- i2cp->id_i2c->DR = (i2cp->id_slave_config->addr7 << 1) |
+ /*TODO: 10 bit address handling
+ In 10-bit addressing mode,
+ – To enter Transmitter mode, a master sends the header (11110xx0) and then the
+ slave address, (where xx denotes the two most significant bits of the address).
+ – To enter Receiver mode, a master sends the header (11110xx0) and then the
+ slave address. Then it should send a repeated Start condition followed by the
+ header (11110xx1), (where xx denotes the two most significant bits of the
+ address).
+ The TRA bit indicates whether the master is in Receiver or Transmitter mode.*/
+
+ i2cp->id_i2c->DR = (i2cp->id_slave_config->address << 1) |
i2cp->id_slave_config->rw_bit; // write slave address in DR
return;
}
+ if ((i2cp->id_state == I2C_MACTIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADD10)){// header sent
+
+ }
+
// "wait" interrupt with ADDR flag
if ((i2cp->id_state == I2C_MACTIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){// address successfully sent
if(i2cp->id_i2c->SR2 & I2C_SR2_TRA){
@@ -468,7 +481,7 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t re
i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate start condition
while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)); // wait Address sent
- i2cp->id_i2c->DR = (i2cp->id_slave_config->addr7 << 1) | I2C_WRITE; // write slave addres in DR
+ i2cp->id_i2c->DR = (i2cp->id_slave_config->address << 1) | I2C_WRITE; // write slave addres in DR
while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)); // wait Address sent
i = i2cp->id_i2c->SR2;
i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit
@@ -505,7 +518,7 @@ void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
uint16_t i = 0;
// send slave addres with read-bit
- i2cp->id_i2c->DR = (i2cp->id_slave_config->addr7 << 1) | I2C_READ;
+ i2cp->id_i2c->DR = (i2cp->id_slave_config->address << 1) | I2C_READ;
while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)); // wait Address sent
i = i2cp->id_i2c->SR2;