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* AMD IOMMU: allocate IRTE entries instead of using a static mappingJan Beulich2013-07-161-0/+1
| | | | | | | | | | | For multi-vector MSI, where we surely don't want to allocate contiguous vectors and be able to set affinities of the individual vectors separately, we need to drop the use of the tuple of vector and delivery mode to determine the IRTE to use, and instead allocate IRTEs (which imo should have been done from the beginning). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
* AMD IOMMU: cover all functions of a device even if ACPI only tells us of func 0Jan Beulich2013-02-261-1/+1
| | | | | | | | | | | | | | This ought to work as all functions of a device have the same place in the bus topology, i.e. use the same IOMMU. Also fix the type of ivrs_bdf_entries (when it's 'unsigned short' and the last device found on a segment is ff:1f.x, it would otherwise end up being zero). And drop the bogus 'last_bdf' static variable, which conflicted anyway with various functions' parameters. Signed-off-by: Jan Beulich <jbeulich@suse.com>
* AMD IOMMU: include IOMMU interrupt information in 'M' debug key outputJan Beulich2012-11-281-2/+3
| | | | | | | | | | Note that this also adds a few pieces missing from c/s 25903:5e4a00b4114c (relevant only when the PCI MSI mask bit is supported by an IOMMU, which apparently isn't the case for existing implementations). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* amd iommu: use base platform MSI implementationJan Beulich2012-09-141-3/+1
| | | | | | | | | | | | | | | Given that here, other than for VT-d, the MSI interface gets surfaced through a normal PCI device, the code should use as much as possible of the "normal" MSI support code. Further, the code can (and should) follow the "normal" MSI code in distinguishing the maskable and non-maskable cases at the IRQ controller level rather than checking the respective flag in the individual actors. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Wei Wang <wei.wang2@amd.com> Acked-by: Keir Fraser <keir@xen.org>
* amd iommu: Introduce a new lock for event and ppr loggingWei Wang2012-03-011-0/+1
| | | | | | | | | | iommu->lock is used with irq disabled, so it cannot be used to protect ppr log. Otherwise, after c/s 24770, get_gfn will trigger a BUG() if called by parse_ppr_log_entry(). This patch adds an additional lock to protect ppr and event pointers in iommu_read_log(). signed-off-by: Wei Wang <wei.wang2@amd.com> Committed-by: Keir Fraser <keir@xen.org>
* amd iommu: disable iommu emulation on non-iommu systemsWei Wang2012-01-281-0/+2
| | | | | | | | | | | Introduce a new flag to disable iommu emulation on old iommu systems. This patch is taken from my v4 patch queue, which is till pending, to make old or non-iommu system to run cleanly without interfered by iommuv2 codes. This might be helpful to isolate iommuv2 code in debugging unstable regressions. The reset part of v4 will be re-based. Signed-off-by: Wei Wang <wei.wang2@amd.com> Committed-by: Keir Fraser <keir@xen.org>
* amd iommu: Enable ppr logWei Wang2012-01-121-0/+1
| | | | | | | | IOMMUv2 writes peripheral page service request (PPR) records into ppr log to report guest OS pending DMA page requests from ATS devices. Signed-off-by: Wei Wang <wei.wang2@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* amd iommu: Add iommu emulation for hvm guestWei Wang2012-01-121-0/+52
| | | | | | | | | | | | | | ATS device driver that support PASID [1] and PRI [2] capabilites needs to work with iommu driver in guest OS. We have to expose iommu functionality to HVM guest, if we want assign ATS device to it. A new hypervisor mmio handler is added to intercept iommu mmio accesses from guest. Signed-off-by: Wei Wang <wei.wang2@amd.com> [1] http://www.pcisig.com/specifications/pciexpress/specifications/ECN-PASID-ATS-2011-03-31.pdf [2] http://www.pcisig.com/members/downloads/specifications/iov/ats_r1.1_26Jan09.pdf Committed-by: Jan Beulich <jbeulich@suse.com>
* amd iommu: Refactoring iommu ring buffer definitionWei Wang2012-01-121-4/+32
| | | | | | | Introduce struct ring_buffer to represent iommu cmd buffer, event log and ppr log Signed-off-by: Wei Wang <wei.wang2@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* amd iommu: Advertise iommu extended feature bits to xen.Wei Wang2011-11-221-0/+1
| | | | | Signed-off-by: Wei Wang <wei.wang2@amd.com> Committed-by: Keir Fraser <keir@xen.org>
* amd iommu: Introduce iommu_has_cap() functionWei Wang2011-11-111-4/+0
| | | | | Signed-off-by: Wei Wang <wei.wang2@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* amd iommu: Compress hyper-transport flags into a single byteWei Wang2011-11-111-5/+1
| | | | | | | | | These flags are single bit, no need to be saved as integers. Add 3 inline helpers to make single bit access easier. Introduce iommu_has_ht_flag and set_iommu_ht_flags Signed-off-by: Wei Wang <wei.wang2@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* amd iommu: Simplify IVHD device flag handlingWei Wang2011-11-111-7/+2
| | | | | | | | These bits are aligned to corresponding fields in device table entry. They can be updated by a single device entry write. Signed-off-by: Wei Wang <wei.wang2@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* amd iommu: Cleanup iommu pci capabilites detectionWei Wang2011-11-111-4/+10
| | | | | | | | | | * Define new structure to represent capability block. * Remove unnecessary read for unused information. * Add sanity check into get_iommu_capabilities. * iommu capability offset is 16 bit not 8 bit, fix that. Signed-off-by: Wei Wang <wei.wang2@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* AMD-IOMMU: fix initialization order (after 23863:9e0259239822)Jan Beulich2011-09-271-1/+0
| | | | | | | | That original patch caused alloc_ivrs_mappings() to be called too early, so things get moved back to where they were, just converting the single call there to a loop over all IOMMUs. Signed-off-by: Jan Beulich <jbeulich@suse.com>
* PCI multi-seg: AMD-IOMMU specific adjustmentsJan Beulich2011-09-221-1/+6
| | | | | | | | | There are two places here where it is entirely unclear to me where the necessary PCI segment number should be taken from (as IVMD descriptors don't have such, only IVHD ones do). AMD confirmed that for the time being it is acceptable to imply that only segment 0 exists. Signed-off-by: Jan Beulich <jbeulich@suse.com>
* xen: remove more declarations from C files.Tim Deegan2011-05-271-0/+4
| | | | | | | | | | This patch moves some more, mostly data, extern declarations into header files. I haven't been as strict as I was with functions; in particular there are a number of declarations of assembler labels that are only used in one place. I've also left a few compat-mode tricks, and all the magic in symbols.c Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
* Scattered code arrangement cleanups.Keir Fraser2009-10-071-2/+0
| | | | | | | | - remove redundant declarations - add/move prototypes to headers - move things where they belong to Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* AMD IOMMU: Remove unused definitions.Keir Fraser2009-09-181-3/+0
| | | | Signed-off-by: Wei Wang <wei.wang2@amd.com>
* AMD IOMMU: Rework of interrupt remappingKeir Fraser2009-09-161-0/+11
| | | | | | | | | | | | | | 1) Parsing IVRS special device entry in order to handle ioapic remapping correctly. 2) Allocating per-device interrupt remapping tables instead of using a global interrupt remapping table. 3) Some system devices like io-apic for north-bridge cannot be discovered during pci device enumeration procedure. To remap interrupt of those devices, device table update is split into 2 steps, so that interrupt tables can be bound to device table entry earlier than I/O page tables. Signed-off-by: Wei Wang <wei.wang2@amd.com>
* x86: Change Xen hypervisor's interrupt infrastructureKeir Fraser2009-08-191-1/+1
| | | | | | | | | | | | | | from vector-based to IRQ-based. In per-cpu vector environment, vector space changes to multi-demension resource, so vector number is not appropriate to index irq_desc which stands for unique interrupt source. As Linux does, irq number is chosen to index irq_desc. This patch changes vector-based interrupt infrastructure to irq-based one. Mostly, it follows upstream linux's changes, and some parts are adapted for Xen. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
* AMD IOMMU: Miscellaneous fixes and cleanups.Keir Fraser2008-07-311-4/+4
| | | | Signed-off-by: Wei Wang <wei.wang2@amd.com>
* iommu: Consolidate iommu enablement logic. Now there is only oneKeir Fraser2008-04-211-1/+0
| | | | | | command-line parameter for disabling IOV/VTD: "iommu"/"no-iommu". Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* amd iommu: clean up debug information.Keir Fraser2008-04-211-1/+1
| | | | Signed-off-by: Wei Wang <wei.wang2@amd.com>
* AMD IOMMU: Add event logging support.Keir Fraser2008-04-161-0/+3
| | | | | | | | | MSI interrupt will be triggered on IO page fault and the fault address will be written into an in-memory event log buffer automatically by hardware. This patch handles the MSI interrupt simply by reading event log entry and printing out the parsed result. Signed-off-by: Wei Wang <wei.wang2@amd.com>
* Fix x86 build.Keir Fraser2008-02-281-2/+2
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* Add ACPI tables support for AMD IOMMUKeir Fraser2008-02-281-4/+28
| | | | | | | | Configuration information for AMD IOMMU control fields are descirbed by I/O virtualization Reporting Structure (IVRS) table, this patch set parses IVRS table and updates iommu control flags according to the result. Signed-off-by: Wei Wang <wei.wang2@amd.com>
* x86: allow pv guests to disable TSC for applicationsKeir Fraser2007-10-291-1/+1
| | | | | | | | | | | | | | | | | Linux, under CONFIG_SECCOMP, has been capable of hiding the TSC from processes for quite a while. This patch enables this to actually work for pv kernels, by allowing them to control CR4.TSD (and, as a simple thing to do at the same time, CR4.DE). Applies cleanly only on top of the previously submitted debug register handling patch. Signed-off-by: Jan Beulich <jbeulich@novell.com> Also clean up CR4 and EFER handling, and hack-n-slash header file inclusion madness to get the tree building again. Signed-off-by: Keir Fraser <keir@xensource.com>
* Add AMD IOMMU support into hypervisorKeir Fraser2007-09-211-0/+70
Signed-off-by: Wei Wang <wei.wang2@amd.com>
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