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authorJan Beulich <jbeulich@suse.com>2011-09-22 18:28:03 +0100
committerJan Beulich <jbeulich@suse.com>2011-09-22 18:28:03 +0100
commit7b5787b8f526f68bd283d977c46cf9c221f26a93 (patch)
tree1a8ea2fb9dc4cde4972ab760abf0ad80daa5a8b7 /xen/include/asm-x86/amd-iommu.h
parent2fd04c6c875dd0f309f114178943c61adb52d275 (diff)
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PCI multi-seg: AMD-IOMMU specific adjustments
There are two places here where it is entirely unclear to me where the necessary PCI segment number should be taken from (as IVMD descriptors don't have such, only IVHD ones do). AMD confirmed that for the time being it is acceptable to imply that only segment 0 exists. Signed-off-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'xen/include/asm-x86/amd-iommu.h')
-rw-r--r--xen/include/asm-x86/amd-iommu.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/xen/include/asm-x86/amd-iommu.h b/xen/include/asm-x86/amd-iommu.h
index 784c9d989b..ea40310c78 100644
--- a/xen/include/asm-x86/amd-iommu.h
+++ b/xen/include/asm-x86/amd-iommu.h
@@ -40,6 +40,7 @@ struct amd_iommu {
struct list_head list;
spinlock_t lock; /* protect iommu */
+ u16 seg;
u16 bdf;
u8 cap_offset;
u8 revision;
@@ -101,6 +102,10 @@ struct ivrs_mappings {
};
extern unsigned short ivrs_bdf_entries;
-extern struct ivrs_mappings *ivrs_mappings;
+
+int alloc_ivrs_mappings(u16 seg);
+struct ivrs_mappings *get_ivrs_mappings(u16 seg);
+int iterate_ivrs_mappings(int (*)(u16 seg, struct ivrs_mappings *));
+int iterate_ivrs_entries(int (*)(u16 seg, struct ivrs_mappings *));
#endif /* _ASM_X86_64_AMD_IOMMU_H */