aboutsummaryrefslogtreecommitdiffstats
path: root/xen/arch/x86/cpu
Commit message (Collapse)AuthorAgeFilesLines
* x86/mwait_idle: initial C8, C9, C10 supportLen Brown2013-08-301-0/+18
| | | | | | | | | | Allow mwait_idle to utilize C8, C9, C10 when they are present on... "Fourth Generation Intel(R) Core(TM) Processors", which are based on Intel(R) microarchitecture code name Haswell. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/mwait_idle: export both C1 and C1ELen Brown2013-08-301-5/+46
| | | | | | | | | | | | | | | | | | Here we disable HW promotion of C1 to C1E and export both C1 and C1E as distinct C-states. This allows a cpuidle governor to choose a lower latency C-state than C1E when necessary to satisfy performance and QOS constraints -- and still save power versus polling. This also corrects the erroneous latency previously reported for C1E -- it is 10usec, not 1usec. Signed-off-by: Len Brown <len.brown@intel.com> Avoided the effect of changing the meaning of "max_cstate=". Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/mwait_idle: remove assumption of one C-state per MWAIT flagLen Brown2013-08-301-56/+50
| | | | | | | | | | | | | | | | | | | Remove the assumption that cstate_tables are indexed by MWAIT flag values. Each entry identifies itself via its own flags value. This change is needed to support multiple states that share the same MWAIT flags. Note that this can have an effect on what state is described by 'N' on cmdline max_cstate=N on some systems. Signed-off-by: Len Brown <len.brown@intel.com> Avoided the effect of changing the meaning of "max_cstate=". Drop MWAIT_MAX_NUM_CSTATES (done differently in a prior patch on Linux). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/xsave: initialization improvementsJan Beulich2013-08-301-1/+1
| | | | | | | | | | - properly validate available feature set on APs - also validate xsaveopt availability on APs - properly indicate whether the initialization is on the BSP (we shouldn't be using "cpu == 0" checks for this) Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: remove PentiumPro checkMatt Wilson2013-08-301-4/+0
| | | | | | | ... as it's not a supported processor Signed-off-by: Matt Wilson <msw@amazon.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: remove X86_INTEL_USERCOPY codeMatt Wilson2013-08-301-21/+0
| | | | | | | | Nothing defines CONFIG_X86_INTEL_USERCOPY, and as far as I can tell it was never used even when Xen supported 32-bit x86. Signed-off-by: Matt Wilson <msw@amazon.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/MTRR: fix range check in mtrr_add_page()Jan Beulich2013-08-141-1/+1
| | | | | | | | | Extracted from Yinghai Lu's Linux commit d5c78673 ("x86: Fix /proc/mtrr with base/size more than 44bits"). Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/cpuidle: Change logging for unknown APIC IDsAndrew Cooper2013-07-171-1/+1
| | | | | | | | | | | | | | | Dom0 uses this hypercall to pass ACPI information to Xen. It is not very uncommon for more cpus to be listed in the ACPI tables than are present on the system, particularly on systems with a common BIOS for a 2 and 4 socket server varients. As Dom0 does not control the number of entries in the ACPI tables, and is required to pass everything it finds to Xen, change the logging. There is now an single unconditional warning for the first unknown ID, and further warnings if "cpuinfo" is requested by the user on the command line. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/MCE: disable if MCE banks are not presentAravindh Puthiyaparambil2013-06-031-1/+8
| | | | | | | | | | | | | | | | | When booting Xen on VMware ESX 5.1 and Workstation 9, you hit a GPF during MCE initialization. The culprit is line 631 in set_poll_bankmask(): bitmap_copy(mb->bank_map, mca_allbanks->bank_map, nr_mce_banks); What is happening is that in mca_cap_init(), nr_mce_banks is being set to 0. This causes the allocation of bank_map to be set to ZERO_BLOCK_PTR which is the return value for zero-size allocation by xzalloc_array()/_xmalloc(). This results in the bitmap_copy() to fail disastrously. The following patch fixes this issue. Signed-off-by: Aravindh Puthiyaparambil <aravindp@cisco.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Christoph Egger <chegger@amazon.de>
* x86/vMCE: remove is_vmce_ready checkLiu Jinsong2013-05-163-75/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove is_vmce_ready() check since 1. it's problematic and overkilled: it checks if virq bind to dom0 mcelog driver. That's not correct, since mcelog is just a dom0 driver used to log error info, irrelated to dom0 vmce injection. It's also overkilled, defaulty dom0 disabled mcelog driver, under such case this checking would resulting in system crash: (XEN) MCE: This error page is ownded by DOM 0 (XEN) DOM0 not ready for vMCE (XEN) domain_crash called from mcaction.c:133 (XEN) Domain 0 reported crashed by domain 32767 on cpu#31: (XEN) Domain 0 crashed: rebooting machine in 5 seconds. (XEN) Resetting with ACPI MEMORY or I/O RESET_REG. 2. it's redundant: hypervisor in fact has checked 1). whether dom0 vmce ready or not (at inject_vmce()), via checking vmce trap callback, to make sure vmce injection OK; 2). whether dom0 mcelog driver ready or not (at mce_softirq()), via virq binding, to make sure error log works; 3. it's deprecated: for hvm, it checks whether guest vcpu has different virtual family/model with that of host pcpu --> that's deprecated, since vMCE has changed a lot, not bound to host MCE any more. Signed-off-by: Liu Jinsong <jinsong.liu@intel.com> Acked-by: Christoph Egger <chegger@amazon.de>
* x86/vMCE: bugfix of vmce injectionLiu Jinsong2013-04-291-1/+1
| | | | | | | uint16_t is not suitable to store VMCE_INJECT_BROADCAST (which is defined as -1). Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
* x86/mwait_idle: support HaswellLen Brown2013-04-221-0/+36
| | | | | | | | | This patch enables intel_idle to run on the next-generation Intel(R) Microarchitecture code named "Haswell". Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: George Dunlap <george.dunlap@eu.citrix.com>
* x86/mwait_idle: stop using driver_data for static flagsLen Brown2013-04-221-25/+26
| | | | | | | | | | | | | | | | | | | The (Linux) commit 4202735e8ab6ecfb0381631a0d0b58fefe0bd4e2 (cpuidle: Split cpuidle_state structure and move per-cpu statistics fields) observed that the MWAIT flags for Cn on every processor to date were the same, and created get_driver_data() to supply them. Unfortunately, that assumption is false, going forward. So here we restore the MWAIT flags to the cpuidle_state table. However, instead restoring the old "driver_data" field, we put the flags into the existing "flags" field, where they probalby should have lived all along. This patch does not change any operation. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: George Dunlap <george.dunlap@eu.citrix.com>
* xen, libxc: rename xenctl_cpumap to xenctl_bitmapDario Faggioli2013-04-171-2/+1
| | | | | | | | | | | | | | | | | | More specifically: 1. replaces xenctl_cpumap with xenctl_bitmap 2. provides bitmap_to_xenctl_bitmap and the reverse; 3. re-implement cpumask_to_xenctl_bitmap with bitmap_to_xenctl_bitmap and the reverse; Other than #3, no functional changes. Interface only slightly afected. This is in preparation of introducing NUMA node-affinity maps. Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com> Acked-by: George Dunlap <george.dunlap@eu.citrix.com> Acked-by: Juergen Gross <juergen.gross@ts.fujitsu.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: allow AMD MSRs injected via xen-mceinjChristoph Egger2013-04-111-0/+9
| | | | Signed-off-by: Christoph Egger <chegger@amazon.de>
* x86: BITS_PER_LONG is now always 64Jan Beulich2013-03-201-5/+0
| | | | | Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/MCA: suppress bank clearing for certain injected eventsJan Beulich2013-03-122-9/+11
| | | | | | | | | | | | | | | | | | | As the bits indicating validity of the ADDR and MISC bank MSRs may be injected in a way that isn't consistent with what the underlying hardware implements (while the bank must be valid for injection to work, the auxiliary MSRs may not be implemented - and hence cause #GP upon access - if the hardware never sets the corresponding valid bits. Consequently we need to do the clearing writes only if no value was interposed for the respective MSR (which also makes sense the other way around: there's no point in clearing a hardware register when all data read came from software). Of course this all requires the injection tool to do things in a consistent way (but that had been a requirement before already). Signed-off-by: Jan Beulich <jbeulich@suse.com> Tested-by: Ren Yongjie <yongjie.ren@intel.com> Acked-by: Liu Jinsong <jinsong.liu@intel.com>
* x86: make x86_mcinfo_reserve() clear its result bufferJan Beulich2013-03-044-12/+6
| | | | | | | | | | | | ... instead of all but one of its callers. Also adjust the corresponding sizeof() expressions to specify the pointed-to type of the result variable rather than the literal type (so that a type change of the variable will imply the size to get adjusted too). Suggested-by: Ian Campbell <Ian.Campbell@citrix.com> Signed-off-by: Jan Beulich <jbeulich@suse.com>
* x86: fix CMCI injectionJan Beulich2013-02-263-9/+9
| | | | | | | | | | | | | | | | This fixes the wrong use of literal vector 0xF7 with an "int" instruction (invalidated by 25113:14609be41f36) and the fact that doing the injection via a software interrupt was never valid anyway (because cmci_interrupt() acks the LAPIC, which does the wrong thing if the interrupt didn't get delivered though it). In order to do latter, the patch introduces send_IPI_self(), at once removing two opend coded uses of "genapic" in the IRQ handling code. Reported-by: Yongjie Ren <yongjie.ren@intel.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> Tested-by: Yongjie Ren <yongjie.ren@intel.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: fix null pointer dereference in intel_get_extended_msrs()Xi Wang2013-02-251-1/+1
| | | | | | | `memset(&mc_ext, 0, ...)' leads to a buffer overflow and a subsequent null pointer dereference. Replace `&mc_ext' with `mc_ext'. Signed-off-by: Xi Wang <xi@mit.edu>
* x86/AMD: Enable WC+ memory type on family 10 processorsBoris Ostrovsky2013-01-181-0/+11
| | | | | | | | | | In some cases BIOS may not enable WC+ memory type on family 10 processors, instead converting what would be WC+ memory to CD type. On guests using nested pages this could result in performance degradation. This patch enables WC+. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* xen/xsm: Add xsm_default parameter to XSM hooksDaniel De Graaf2013-01-111-1/+1
| | | | | | | | | | | | | | Include the default XSM hook action as the first argument of the hook to facilitate quick understanding of how the call site is expected to be used (dom0-only, arbitrary guest, or device model). This argument does not solely define how a given hook is interpreted, since any changes to the hook's default action need to be made identically to all callers of a hook (if there are multiple callers; most hooks only have one), and may also require changing the arguments of the hook. Signed-off-by: Daniel De Graaf <dgdegra@tycho.nsa.gov> Acked-by: Tim Deegan <tim@xen.org> Committed-by: Keir Fraser <keir@xen.org>
* xen: use XSM instead of IS_PRIV where duplicatedDaniel De Graaf2013-01-111-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Xen hypervisor has two basic access control function calls: IS_PRIV and the xsm_* functions. Most privileged operations currently require that both checks succeed, and many times the checks are at different locations in the code. This patch eliminates the explicit and implicit IS_PRIV checks that are duplicated in XSM hooks. When XSM_ENABLE is not defined or when the dummy XSM module is used, this patch should not change any functionality. Because the locations of privilege checks have sometimes moved below argument validation, error returns of some functions may change from EPERM to EINVAL or ESRCH if called with invalid arguments and from a domain without permission to perform the operation. Some checks are removed due to non-obvious duplicates in their callers: * acpi_enter_sleep is checked in XENPF_enter_acpi_sleep * map_domain_pirq has IS_PRIV_FOR checked in its callers: * physdev_map_pirq checks when acquiring the RCU lock * ioapic_guest_write is checked in PHYSDEVOP_apic_write * PHYSDEVOP_{manage_pci_add,manage_pci_add_ext,pci_device_add} are checked by xsm_resource_plug_pci in pci_add_device * PHYSDEVOP_manage_pci_remove is checked by xsm_resource_unplug_pci in pci_remove_device * PHYSDEVOP_{restore_msi,restore_msi_ext} are checked by xsm_resource_setup_pci in pci_restore_msi_state * do_console_io has changed to IS_PRIV from an explicit domid==0 Signed-off-by: Daniel De Graaf <dgdegra@tycho.nsa.gov> Acked-by: Jan Beulich <jbeulich@suse.com> Committed-by: Keir Fraser <keir@xen.org>
* x86, amd: Disable way access filter on Piledriver CPUsAndre Przywara2012-12-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Way Access Filter in recent AMD CPUs may hurt the performance of some workloads, caused by aliasing issues in the L1 cache. This patch disables it on the affected CPUs. The issue is similar to that one of last year: http://lkml.indiana.edu/hypermail/linux/kernel/1107.3/00041.html This new patch does not replace the old one, we just need another quirk for newer CPUs. The performance penalty without the patch depends on the circumstances, but is a bit less than the last year's 3%. The workloads affected would be those that access code from the same physical page under different virtual addresses, so different processes using the same libraries with ASLR or multiple instances of PIE-binaries. The code needs to be accessed simultaneously from both cores of the same compute unit. More details can be found here: http://developer.amd.com/Assets/SharedL1InstructionCacheonAMD15hCPU.pdf CPUs affected are anything with the core known as Piledriver. That includes the new parts of the AMD A-Series (aka Trinity) and the just released new CPUs of the FX-Series (aka Vishera). The model numbering is a bit odd here: FX CPUs have model 2, A-Series has model 10h, with possible extensions to 1Fh. Hence the range of model ids. Signed-off-by: Andre Przywara <osp@andrep.de> Add and use MSR_AMD64_IC_CFG. Update the value whenever it is found to not have all bits set, rather than just when it's zero. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86/mwait-idle: enable Ivy Bridge Xeon supportJan Beulich2012-11-021-0/+1
| | | | | | | Matching a similar change in Linux 3.7-rc. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* ACPI/cpuidle: remove unused "power" field from Cx state dataJan Beulich2012-11-021-2/+0
| | | | | | | | It has never been used for anything, and Linux 3.7 doesn't propagate this information anymore. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* MCE: remove unused MCA_MCE_HANDLERChristoph Egger2012-10-292-2/+0
| | | | | | | Remove unused MCA_MCE_HANDLER. MCA_MCE_SCAN is used everywhere instead. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86/MCE: merge AMD quirksChristoph Egger2012-10-293-77/+59
| | | | | | | merge mce_amd_quirks.c into mce_amd.c Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86/MCE: remove K7 supportChristoph Egger2012-10-2910-116/+5
| | | | | | | Remove K7 support from MCE. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86/MCE: consolidate AMD initializationChristoph Egger2012-10-294-28/+31
| | | | | | | Move AMD specific initialization to AMD files. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86/MCE: Implement clearbank callback for AMDChristoph Egger2012-10-256-42/+60
| | | | | | | | | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Move initialization of mce_clear_banks into common code (would not get initialized on AMD CPUs otherwise). Mark per-CPU struct mce_bank pointers read-mostly. Signed-off-by: Jan Beulich <jbeulich@suse.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* vMCE: Implement AMD MSRsChristoph Egger2012-10-231-16/+35
| | | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Keir Fraser <keir@xen.org>
* xen: replace XEN_GUEST_HANDLE with XEN_GUEST_HANDLE_PARAM when appropriateStefano Stabellini2012-10-171-1/+1
| | | | | | | | | | | | Note: these changes don't make any difference on x86. Replace XEN_GUEST_HANDLE with XEN_GUEST_HANDLE_PARAM when it is used as an hypercall argument. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Keir Fraser <keir@xen.org> Committed-by: Ian Campbell <ian.campbell@citrix.com>
* x86/amd: Fix xen_apic_write warnings in Dom0Wei Wang2012-10-151-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ 0.020294] ------------[ cut here ]------------ [ 0.020311] WARNING: at arch/x86/xen/enlighten.c:730 xen_apic_write+0x15/0x17() [ 0.020318] Hardware name: empty [ 0.020323] Modules linked in: [ 0.020334] Pid: 1, comm: swapper/0 Not tainted 3.3.8 #7 [ 0.020340] Call Trace: [ 0.020354] [<ffffffff81050379>] warn_slowpath_common+0x80/0x98 [ 0.020369] [<ffffffff810503a6>] warn_slowpath_null+0x15/0x17 [ 0.020378] [<ffffffff810034df>] xen_apic_write+0x15/0x17 [ 0.020392] [<ffffffff8101cb2b>] perf_events_lapic_init+0x2e/0x30 [ 0.020410] [<ffffffff81ee4dd0>] init_hw_perf_events+0x250/0x407 [ 0.020419] [<ffffffff81ee4b80>] ? check_bugs+0x2d/0x2d [ 0.020430] [<ffffffff81002181>] do_one_initcall+0x7a/0x131 [ 0.020444] [<ffffffff81edbbf9>] kernel_init+0x91/0x15d [ 0.020456] [<ffffffff817caaa4>] kernel_thread_helper+0x4/0x10 [ 0.020471] [<ffffffff817c347c>] ? retint_restore_args+0x5/0x6 [ 0.020481] [<ffffffff817caaa0>] ? gs_change+0x13/0x13 [ 0.020500] ---[ end trace a7919e7f17c0a725 ]--- Kernel function check_hw_exists() writes 0xabcd to msr 0xc0010201 (Performance Event Counter 0) and read it again to check if it is running as dom0. Early amd cpus does not reset perf counters during warm reboot. If the kernel is booted with bare metal and then as a dom0, the content of msr 0xc0010201 will stay and the checking will pass and PMU will be enabled unexpectedly. Signed-off-by: Wei Wang <wei.wang2@amd.com> Don't reset the counters when used for the NMI watchdog. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Committed-by: Jan Beulich <jbeulich@suse.com>
* Implement page offline recovery action for AMDChristoph Egger2012-10-098-119/+204
| | | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Keir Fraser <keir@xen.org>
* x86/MCE: implement recoverscan for AMDChristoph Egger2012-10-056-8/+88
| | | | | | | Implement recoverable_scan() for AMD. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86: add sanity check and comments for vMCE injectionLiu, Jinsong2012-10-053-6/+16
| | | | | | | | | | | Add sanity check for input vcpu so that malicious value would not return 0. Add comments since vcpu=-1 (broadcast) is some implicit to code reader. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Suggested-by: Christoph Egger <Christoph.Egger@amd.com> Acked-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86: get the MWAIT idle driver in sync with the ACPI oneJan Beulich2012-10-041-4/+7
| | | | | | | | | .. with respect to behavior when there is no HPET broadcast support (for using the PIT broadcast instead, it requires explicitly enabling CPU idle management). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* Revert 25960:6bf8b882df8f (x86: default-disable MWAIT-based idle driver ...)Jan Beulich2012-09-281-8/+1
| | | | | | The problem this was working around should be resolved with c/s 25961:6a5812129094 (x86/HPET: don't disable interrupt delivery right after setting it up).
* x86: remove further code applicable to 32-bit CPUs onlyJan Beulich2012-09-282-80/+3
| | | | | | | | | | | On the AMD side, anything prior to family 0xf can now be ignored, as well as very low model numbers of family 6 on the Intel side. Apart from that, there were several made up CPU features that turned out entirely unused throughout the tree. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: default-disable MWAIT-based idle driver for CPUs without ARATJan Beulich2012-09-261-1/+8
| | | | | | | | | | Without ARAT, and apparently only when using HPET broadcast mode as replacement, CPUs occasionally fail to wake up, causing the system to (transiently) hang. Until the reason is understood, disable the driver on such systems. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/vMCE: Add AMD supportChristoph Egger2012-09-268-20/+67
| | | | | | | | | | | | | Add vMCE support for AMD. Add vmce namespace to Intel specific vMCE MSR functions. Move vMCE prototypes from mce.h to vmce.h. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> - fix inverted return values from vmce_amd_{rd,wr}msr() - remove bogus printk()-s from those functions Signed-off-by: Jan Beulich <jbeulich@suse.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86: vMCE save and restoreLiu, Jinsong2012-09-261-8/+14
| | | | | | | | | | | | | | | | | | | This patch provides vMCE save/restore when migration. 1. MCG_CAP is well-defined. However, considering future cap extension, we keep save/restore logic that Jan implement at c/s 24887; 2. MCi_CTL2 initialized by guestos when booting, so need save/restore otherwise guest would surprise; 3. Other MSRs do not need save/restore since they are either error- related and pointless to save/restore, or, unified among all vMCE platform; Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> - fix handling of partial data in XEN_DOMCTL_set_ext_vcpucontext - fix adjustment of xen_domctl_ext_vcpucontext Signed-off-by: Jan Beulich <jbeulich@suse.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86: vMCE injectionLiu, Jinsong2012-09-263-38/+26
| | | | | | | | | | | | | | | | | | | | | | | | In our test for win8 guest mce, we find a bug that no matter what SRAO/SRAR error xen inject to win8 guest, it always reboot. The root cause is, current Xen vMCE logic inject vMCE# only to vcpu0, this is not correct for Intel MCE (Under Intel arch, h/w generate MCE# to all CPUs). This patch fixes vMCE injection bug, injecting vMCE# to all vcpus on Intel platforms. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> - increase flexibility be making new second argument of inject_vmce() a VCPU ID rather than just a boolean Acked-by: Christoph Egger <Christoph.Egger@amd.com> (on just this change) - fix condition evaluation order in inject_vmce() Signed-off-by: Jan Beulich <jbeulich@suse.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86: vMCE emulationLiu, Jinsong2012-09-263-249/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides virtual MCE support to guest. It emulates a simple and clean MCE MSRs interface to guest by faking caps to guest if needed and masking caps if unnecessary: 1. Providing a well-defined MCG_CAP to guest, filter out un-necessary caps and provide only guest needed caps; 2. Disabling MCG_CTL to avoid model specific; 3. Sticking all 1's to MCi_CTL to guest to avoid model specific; 4. Enabling CMCI cap but never really inject to guest to prevent polling periodically; 5. Masking MSCOD field of MCi_STATUS to avoid model specific; 6. Keeping natural semantics by per-vcpu instead of per-domain variables; 7. Using bank1 and reserving bank0 to work around 'bank0 quirk' of some very old processors; 8. Cleaning some vMCE# injection logic which shared by Intel and AMD but useless under new vMCE implement; 9. Keeping compatilbe w/ old xen version which has been backported to SLES11 SP2, so that old vMCE would not blocked when migrate to new vMCE; Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> - make printing consistent (and non-exploitable) - fix return values of intel_mce_{rd,wr}msr() for out of range banks - miscellaneous cleanup Signed-off-by: Jan Beulich <jbeulich@suse.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86: fix MWAIT-based idle driver for CPUs without ARATJan Beulich2012-09-251-0/+7
| | | | | | | | lapic_timer_{on,off} need to get initialized in this case. This in turn requires getting HPET broadcast setup to be carried out earlier (and hence preventing double initialization there). Signed-off-by: Jan Beulich <jbeulich@suse.com>
* x86: enable VIA CPU supportJan Beulich2012-09-213-34/+5
| | | | | | | | | | | | | Newer VIA CPUs have both 64-bit and VMX support. Enable them to be recognized for these purposes, at once stripping off any 32-bit CPU only bits from the respective CPU support file, and adding 64-bit ones found in recent Linux. This particularly implies untying the VMX == Intel assumption in a few places. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: eliminate code affecting only 64-bit-incapable CPUsJan Beulich2012-09-213-97/+3
| | | | | Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* printk: prefer %#x et at over 0x%xJan Beulich2012-09-214-15/+14
| | | | | | | | | Performance is not an issue with printk(), so let the function do minimally more work and instead save a byte per affected format specifier. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: introduce MWAIT-based, ACPI-less CPU idle driverJan Beulich2012-09-212-0/+514
| | | | | | | This is a port of Linux'es intel-idle driver serving the same purpose. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-03 07:11:11 +0000