vMCE: Implement AMD MSRs

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
Committed-by: Keir Fraser <keir@xen.org>

1 files changed, 35 insertions, 16 deletions

diff --git a/xen/arch/x86/cpu/mcheck/amd_f10.c b/xen/arch/x86/cpu/mcheck/amd_f10.c
index 1d9067c3f7..487fbce893 100644
--- a/xen/arch/x86/cpu/mcheck/amd_f10.c
+++ b/xen/arch/x86/cpu/mcheck/amd_f10.c
@@ -106,24 +106,43 @@ enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c)
 /* amd specific MCA MSR */
 int vmce_amd_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
 {
-        switch (msr) {
-        case MSR_F10_MC4_MISC1:
-        case MSR_F10_MC4_MISC2:
-        case MSR_F10_MC4_MISC3:
-                break;
-        }
-
-        return 1;
+	switch (msr) {
+	case MSR_F10_MC4_MISC1: /* DRAM error type */
+		v->arch.vmce.bank[1].mci_misc = val; 
+		mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val);
+		break;
+	case MSR_F10_MC4_MISC2: /* Link error type */
+	case MSR_F10_MC4_MISC3: /* L3 cache error type */
+		/* ignore write: we do not emulate link and l3 cache errors
+		 * to the guest.
+		 */
+		mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val);
+		break;
+	default:
+		return 0;
+	}
+
+	return 1;
 }
 
 int vmce_amd_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
 {
-        switch (msr) {
-        case MSR_F10_MC4_MISC1:
-        case MSR_F10_MC4_MISC2:
-        case MSR_F10_MC4_MISC3:
-                break;
-        }
-
-        return 1;
+	switch (msr) {
+	case MSR_F10_MC4_MISC1: /* DRAM error type */
+		*val = v->arch.vmce.bank[1].mci_misc;
+		mce_printk(MCE_VERBOSE, "MCE: rd msr %#"PRIx64"\n", *val);
+		break;
+	case MSR_F10_MC4_MISC2: /* Link error type */
+	case MSR_F10_MC4_MISC3: /* L3 cache error type */
+		/* we do not emulate link and l3 cache
+		 * errors to the guest.
+		 */
+		*val = 0;
+		mce_printk(MCE_VERBOSE, "MCE: rd msr %#"PRIx64"\n", *val);
+		break;
+	default:
+		return 0;
+	}
+
+	return 1;
 }