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author | Jan Beulich <jbeulich@suse.com> | 2012-09-21 17:02:46 +0200 |
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committer | Jan Beulich <jbeulich@suse.com> | 2012-09-21 17:02:46 +0200 |
commit | 1b33d3acd1a7550b858379f38e01e085dc444d08 (patch) | |
tree | 7c97db23a20fa3e9c258e53e81952cabddd4702a /xen/arch/x86/cpu | |
parent | 508609eec58f748a1f86953322e6ac32ae0b3c19 (diff) | |
download | xen-1b33d3acd1a7550b858379f38e01e085dc444d08.tar.gz xen-1b33d3acd1a7550b858379f38e01e085dc444d08.tar.bz2 xen-1b33d3acd1a7550b858379f38e01e085dc444d08.zip |
x86: enable VIA CPU support
Newer VIA CPUs have both 64-bit and VMX support. Enable them to be
recognized for these purposes, at once stripping off any 32-bit CPU
only bits from the respective CPU support file, and adding 64-bit ones
found in recent Linux.
This particularly implies untying the VMX == Intel assumption in a few
places.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
Diffstat (limited to 'xen/arch/x86/cpu')
-rw-r--r-- | xen/arch/x86/cpu/Makefile | 4 | ||||
-rw-r--r-- | xen/arch/x86/cpu/centaur.c | 34 | ||||
-rw-r--r-- | xen/arch/x86/cpu/common.c | 1 |
3 files changed, 5 insertions, 34 deletions
diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index 98f283682b..d73d93a6b7 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -2,10 +2,8 @@ subdir-y += mcheck subdir-y += mtrr obj-y += amd.o +obj-y += centaur.o obj-y += common.o obj-y += intel.o obj-y += intel_cacheinfo.o obj-y += mwait-idle.o - -# Keeping around for VIA support (JBeulich) -# obj-$(x86_32) += centaur.o diff --git a/xen/arch/x86/cpu/centaur.c b/xen/arch/x86/cpu/centaur.c index ffebba9908..4aaa144363 100644 --- a/xen/arch/x86/cpu/centaur.c +++ b/xen/arch/x86/cpu/centaur.c @@ -45,51 +45,25 @@ static void __init init_c3(struct cpuinfo_x86 *c) c->x86_capability[5] = cpuid_edx(0xC0000001); } - /* Cyrix III family needs CX8 & PGE explicity enabled. */ - if (c->x86_model >=6 && c->x86_model <= 9) { - rdmsrl(MSR_VIA_FCR, msr_content); - wrmsrl(MSR_VIA_FCR, msr_content | (1ULL << 1 | 1ULL << 7)); - set_bit(X86_FEATURE_CX8, c->x86_capability); + if (c->x86 == 0x6 && c->x86_model >= 0xf) { + c->x86_cache_alignment = c->x86_clflush_size * 2; + set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); } - /* Before Nehemiah, the C3's had 3dNOW! */ - if (c->x86_model >=6 && c->x86_model <9) - set_bit(X86_FEATURE_3DNOW, c->x86_capability); - get_model_name(c); display_cacheinfo(c); } static void __init init_centaur(struct cpuinfo_x86 *c) { - /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; - 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ - clear_bit(0*32+31, c->x86_capability); - if (c->x86 == 6) init_c3(c); } -static unsigned int centaur_size_cache(struct cpuinfo_x86 * c, unsigned int size) -{ - /* VIA C3 CPUs (670-68F) need further shifting. */ - if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) - size >>= 8; - - /* VIA also screwed up Nehemiah stepping 1, and made - it return '65KB' instead of '64KB' - - Note, it seems this may only be in engineering samples. */ - if ((c->x86==6) && (c->x86_model==9) && (c->x86_mask==1) && (size==65)) - size -=1; - - return size; -} - static struct cpu_dev centaur_cpu_dev __cpuinitdata = { .c_vendor = "Centaur", .c_ident = { "CentaurHauls" }, .c_init = init_centaur, - .c_size_cache = centaur_size_cache, }; int __init centaur_init_cpu(void) @@ -97,5 +71,3 @@ int __init centaur_init_cpu(void) cpu_devs[X86_VENDOR_CENTAUR] = ¢aur_cpu_dev; return 0; } - -//early_arch_initcall(centaur_init_cpu); diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 28a51f5890..5e8a75848e 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -522,6 +522,7 @@ void __init early_cpu_init(void) { intel_cpu_init(); amd_init_cpu(); + centaur_init_cpu(); early_cpu_detect(); } /* |