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* x86/xsave: also save/restore XCR0 across suspend (ACPI S3)Jan Beulich2013-10-211-0/+7
| | | | | | Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: use {rd,wr}{fs,gs}base when availableJan Beulich2013-10-111-4/+4
| | | | | | | | | | | | ... as being intended to be faster than MSR reads/writes. In the case of emulate_privileged_op() also use these in favor of the cached (but possibly stale) addresses from arch.pv_vcpu. This allows entirely removing the code that was the subject of XSA-67. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: enable VIA CPU supportJan Beulich2012-09-211-2/+4
| | | | | | | | | | | | | Newer VIA CPUs have both 64-bit and VMX support. Enable them to be recognized for these purposes, at once stripping off any 32-bit CPU only bits from the respective CPU support file, and adding 64-bit ones found in recent Linux. This particularly implies untying the VMX == Intel assumption in a few places. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* xen: Remove x86_32 build target.Keir Fraser2012-09-121-10/+0
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* x86/fpu: clean up FPU context save functionWei Huang2011-05-091-1/+1
| | | | | | | | | | This patch cleans up context save function. It renames the save function to vcpu_save_fpu() because existing function name is confusion. It also extracts FPU context save code (fsave, fxsave, xsave) into seperate functions. vcpu_save_fpu() will call corresponding sub-function depending on CPU's capability. Signed-off-by: Wei Huang <wei.huang2@amd.com>
* x86: split struct vcpuJan Beulich2011-04-051-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | This is accomplished by splitting the guest_context member, which by itself is larger than a page on x86-64. Quite a number of fields of this structure is completely meaningless for HVM guests, and thus a new struct pv_vcpu gets introduced, which is being overlaid with struct hvm_vcpu in struct arch_vcpu. The one member that is mostly responsible for the large size is trap_ctxt, which now gets allocated separately (unless fitting on the same page as struct arch_vcpu, as is currently the case for x86-32), and only for non-hvm, non-idle domains. This change pointed out a latent problem in arch_set_info_guest(), which is permitted to be called on already initialized vCPU-s, but so far copied the new state into struct arch_vcpu without (in this case) actually going through all the necessary accounting/validation steps. The logic gets changed so that the pieces that bypass accounting will at least be verified to be no different from the currently active bits, and the whole change will fail in case they are. The logic does *not* get adjusted here to do full error recovery, that is, partially modified state continues to not get unrolled in case of failure. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: add explicit size suffixes to some assembly instructions.Tim Deegan2011-03-071-2/+2
| | | | | | | This is needed to compile xen with clang. Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86 fpu: Code clean up. Eliminate per-cpu xsave init verbosity.Keir Fraser2011-01-141-2/+1
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* x86: Avoid assumptions about C struct layouts from asm code.Keir Fraser2010-07-131-9/+32
| | | | | | Largely this involves avoiding assumptions about 'struct cpu_info'. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: fix dom0 S3 when x2apic is used.Keir Fraser2010-03-181-1/+0
| | | | | | | | | | | | 1) Some variables and functions in xen/arch/x86/genapic/x2apic.c should not be marked with __init* as they will be used during s3 resume; 2) In do_suspend_lowlevel -> restore_rest_processor_state -> mcheck_init, lapic is accessed, but x2apic hasn't been re-enabled yet (x2apic is re-enabled() in device_power_up -> lapic_resume). The patch moves mcheck_init to a later place. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* x86: Remove EF_* duplicate defs for X86_EFLAGS_*.Keir Fraser2009-08-141-1/+4
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: CPU synchronization while doing MTRR register updateKeir Fraser2009-08-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The current Xen code does not synchronize all the cpus while initializing MTRR registers when a cpu comes up.=20 As per IA32 SDM vol 3: Section: 10.11.8 MTRR Considerations in MP Systems, all the processors should be synchronized while updating MTRRs. Processors starting with westmere are caching VMCS data for better VMX performance. These processors also has Hyper-threading support. With hyper-threading, when one thread's cache is disabled, it also disables cache for the sibling threads. And MTRR register updating procedure involves cache disabling. So if cpus are not synchronized, updating MTRR registers on a thread, results in the VMCS data from sibling threads becoming inaccessible, and it causes system failure. With this patch while updating the MTRR registers, all the cpus are synchronized as per the IA32 SDM. Also at the boot time and resume time when multiple cpus are brought up, an optimization is added to delay the MTRR initialization until all the cpus are up, to avoid multiple times cpu synchronization. Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com> Signed-off-by: Suresh B Siddha <suresh.b.siddha@intel.com> Signed-off-by: Asit K Mallick <asit.k.mallick@intel.com>
* x86: move init_tss into per-CPU spaceKeir Fraser2009-07-131-1/+1
| | | | Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: Enable S3 for 32bit dom0 on 64bit XenKeir Fraser2009-03-311-0/+14
| | | | | | | | | Three SYSENTER MSRs should be taken care of at save/restore BSP context, or else 32bit dom0 rejects working after S3 resume. Thanks for Jan's help to find this missing part. Signed-off-by: Guanqun Lu <guanqun.lu@intel.com> Signed-off-by: Kevin Tian <kevin.tian@intel.com>
* x86: Fix the 32-bit build after c/s 19400.Keir Fraser2009-03-201-1/+1
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: Ensure we execute LTR when running on non-compat GDT which hasKeir Fraser2009-03-191-5/+1
| | | | | | busy bit clear in TSS descriptor. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: recover pat value for bsp after S3 resume.Keir Fraser2009-02-051-0/+3
| | | | | | | | | | host pat is set to cover all memory types by Xen, which is necessary to support guest mtrr/pat, especially when device is passthroughed with VT-d. However pat on bsp is not=20 recovered which could make assigned device defunct after S3 resume Signed-off-by Kevin Tian <kevin.tian@intel.com>
* x86: Fix various problems with debug-register handling.Keir Fraser2007-11-011-10/+7
| | | | | Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Keir Fraser <keir@xensource.com>
* Xen PM: Remove useless __sync_lazy_execstate().kfraser@localhost.localdomain2007-07-201-0/+1
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* xen: Clean up code style.kfraser@localhost.localdomain2007-07-191-20/+10
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* [host s3] Retrieve necessary sleep information from plain-text ACPIkfraser@localhost.localdomain2007-07-191-3/+0
| | | | | | | | | tables (FADT/FACS), and keep one hypercall remained for sleep notification. Signed-off-by: Ke Yu <ke.yu@intel.com> Signed-off-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Keir Fraser <keir@xensource.com>
* Provide basic Xen PM infrastructurekfraser@localhost.localdomain2007-07-111-0/+85
Basic infrastructure for Xen S3 support with a common CPU context save/restore logic for both 32bit and 64bit. Wakeup code is split into two parts: - the first locates after trampoline code, to share all the tricks on the latter, like relocation base and identy mapping - the 2nd part locates in xen code segment, to do the actual CPU context restore Signed-off-by Ke Yu <ke.yu@intel.com> Signed-off-by Kevin Tian <kevin.tian@intel.com>
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