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| author | Keir Fraser <keir.fraser@citrix.com> | 2009-03-31 13:28:45 +0100 |
|---|---|---|
| committer | Keir Fraser <keir.fraser@citrix.com> | 2009-03-31 13:28:45 +0100 |
| commit | e24c23a5110ee350c95ed7400f8270e4bb4d9f33 (patch) | |
| tree | a6cb267d0e8b7333638f256d9286a9173ec510dc /xen/arch/x86/acpi/suspend.c | |
| parent | 539cb7fec62a287be5e71badd4875f791ef80c0b (diff) | |
| download | xen-e24c23a5110ee350c95ed7400f8270e4bb4d9f33.tar.gz xen-e24c23a5110ee350c95ed7400f8270e4bb4d9f33.tar.bz2 xen-e24c23a5110ee350c95ed7400f8270e4bb4d9f33.zip | |
x86: Enable S3 for 32bit dom0 on 64bit Xen
Three SYSENTER MSRs should be taken care of at save/restore BSP
context, or else 32bit dom0 rejects working after S3 resume. Thanks
for Jan's help to find this missing part.
Signed-off-by: Guanqun Lu <guanqun.lu@intel.com>
Signed-off-by: Kevin Tian <kevin.tian@intel.com>
Diffstat (limited to 'xen/arch/x86/acpi/suspend.c')
| -rw-r--r-- | xen/arch/x86/acpi/suspend.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/xen/arch/x86/acpi/suspend.c b/xen/arch/x86/acpi/suspend.c index 0aac31da68..bcb3e83bde 100644 --- a/xen/arch/x86/acpi/suspend.c +++ b/xen/arch/x86/acpi/suspend.c @@ -16,6 +16,7 @@ #if defined(CONFIG_X86_64) static unsigned long saved_lstar, saved_cstar; +static unsigned long saved_sysenter_esp, saved_sysenter_eip; #endif void save_rest_processor_state(void) @@ -26,6 +27,11 @@ void save_rest_processor_state(void) #if defined(CONFIG_X86_64) rdmsrl(MSR_CSTAR, saved_cstar); rdmsrl(MSR_LSTAR, saved_lstar); + if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) + { + rdmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp); + rdmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip); + } #endif } @@ -41,6 +47,14 @@ void restore_rest_processor_state(void) wrmsrl(MSR_CSTAR, saved_cstar); wrmsr(MSR_STAR, 0, (FLAT_RING3_CS32<<16) | __HYPERVISOR_CS); wrmsr(MSR_SYSCALL_MASK, EF_VM|EF_RF|EF_NT|EF_DF|EF_IE|EF_TF, 0U); + + if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) + { + /* Recover sysenter MSRs */ + wrmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp); + wrmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip); + wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0); + } #else /* !defined(CONFIG_X86_64) */ if ( supervisor_mode_kernel && cpu_has_sep ) wrmsr(MSR_IA32_SYSENTER_ESP, &init_tss[smp_processor_id()].esp1, 0); |