CFE from danitool [without hostTools dir]: https://mega.nz/#!mwZyFK7a!CPT3BKC8dEw29kubtdYxhB91G9vIIismTkgzQ3iUy3k

11 files changed, 10212 insertions, 0 deletions

diff --git a/shared/broadcom/include/bcm963xx/6328_common.h b/shared/broadcom/include/bcm963xx/6328_common.h
new file mode 100755
index 0000000..4d36942
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/6328_common.h
@@ -0,0 +1,299 @@
+/*
+<:copyright-broadcom 
+ 
+ Copyright (c) 2007 Broadcom Corporation 
+ All Rights Reserved 
+ No portions of this material may be reproduced in any form without the 
+ written permission of: 
+          Broadcom Corporation 
+          16215 Alton Parkway 
+          Irvine, California 92619 
+ All information contained in this document is Broadcom Corporation 
+ company private, proprietary, and trade secret. 
+ 
+:>
+*/
+/***********************************************************************/
+/*                                                                     */
+/*   MODULE:  6328_common.h                                             */
+/*   DATE:    02/01/08                                                 */
+/*   PURPOSE: Define addresses of major hardware components of         */
+/*            BCM6328                                                  */
+/*                                                                     */
+/***********************************************************************/
+#ifndef __BCM6328_MAP_COMMON_H
+#define __BCM6328_MAP_COMMON_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PERF_BASE            0xb0000000  /* chip control registers */
+#define TIMR_BASE            0xb0000040  /* timer registers */
+#define NAND_INTR_BASE       0xb0000070  /* nand interrupt control registers */
+#define GPIO_BASE            0xb0000080  /* gpio registers */
+#define UART_BASE            0xb0000100  /* uart registers */
+#define UART1_BASE           0xb0000120  /* uart registers */
+#define NAND_REG_BASE        0xb0000200
+#define NAND_CACHE_BASE      0xb0000400
+#define OTP_BASE             0xb0000600
+#define LED_BASE             0xb0000800  /* LED control registers */
+#define HSSPIM_BASE          0xb0001000  /* High-Speed SPI registers */
+#define MISC_BASE            0xb0001800  /* Miscellaneous Registers */
+#define ADSL_CTRL_BASE       0xb0001900
+#define USB_CTL_BASE         0xb0002400  /* USB 2.0 device control registers */
+#define USB_EHCI_BASE        0x10002500  /* USB host registers */
+#define USB_OHCI_BASE        0x10002600  /* USB host registers */
+#define USBH_CFG_BASE        0xb0002700
+#define DDR_BASE             0xb0003000  /* Memory control registers */
+#define PCM_BASE             0xb000a000
+#define PCM_DMA_BASE         0xb000a800  /* PCM UIDMA register base */
+#define SAR_DMA_BASE         0xb000b800  /* ATM SAR DMA control registers */
+#define USB_DMA_BASE         0xb000c000  /* USB 2.0 device DMA regiseters */
+#define SWITCH_DMA_BASE      0xb000d800
+#define SWITCH_BASE          0xb0e00000
+#define PCIE_BASE            0xb0e40000
+
+
+/*
+#####################################################################
+# System PLL Control Register
+#####################################################################
+*/
+
+/*
+#####################################################################
+# GPIO Control Registers
+#####################################################################
+*/
+
+/*
+#####################################################################
+# Miscellaneous Registers
+#####################################################################
+*/
+#define MISC_MEMC_CONTROL		0x0c
+#define MISC_STRAP_BUS			0x240
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT      7
+
+/*
+#####################################################################
+# OTP Registers
+#####################################################################
+*/
+#define OTP_USER_BITS           0x20
+#define OTP_TP1_DISABLE_BIT     9
+
+/*
+#####################################################################
+# Memory Control Registers
+#####################################################################
+*/
+#define DDR_CTL_CNFG                             0x000 
+#define DDR_CTL_CSST                             0x004 
+#define DDR_CTL_CSEND                            0x008 
+#define DDR_CTL_ROW00_0                          0x010 
+#define DDR_CTL_ROW00_1                          0x014 
+#define DDR_CTL_ROW01_0                          0x018 
+#define DDR_CTL_ROW01_1                          0x01c 
+#define DDR_CTL_ROW20_0                          0x030 
+#define DDR_CTL_ROW20_1                          0x034 
+#define DDR_CTL_ROW21_0                          0x038 
+#define DDR_CTL_ROW21_1                          0x03c 
+#define DDR_CTL_COL00_0                          0x050 
+#define DDR_CTL_COL00_1                          0x054 
+#define DDR_CTL_COL01_0                          0x058 
+#define DDR_CTL_COL01_1                          0x05c 
+#define DDR_CTL_COL20_0                          0x070 
+#define DDR_CTL_COL20_1                          0x074 
+#define DDR_CTL_COL21_0                          0x078 
+#define DDR_CTL_COL21_1                          0x07c 
+#define DDR_CTL_BNK10                            0x090 
+#define DDR_CTL_BNK32                            0x094 
+#define DDR_CTL_DCMD                             0x100 
+#define DDR_CTL_DMODE_0                          0x104 
+#define DDR_CTL_DMODE_1                          0x108 
+#define DDR_CTL_CLKS                             0x10c 
+#define DDR_CTL_ODT                              0x110 
+#define DDR_CTL_TIM1_0                           0x114 
+#define DDR_CTL_TIM1_1                           0x118 
+#define DDR_CTL_TIM2                             0x11c 
+#define DDR_CTL_CTL_CRC                          0x120 
+#define DDR_CTL_DOUT_CRC                         0x124 
+#define DDR_CTL_DIN_CRC                          0x128 
+#define PHY_CONTROL_REGS_REVISION                0x200 
+#define PHY_CONTROL_REGS_CLK_PM_CTRL             0x204 
+#define PHY_CONTROL_REGS_PLL_STATUS              0x210 
+#define PHY_CONTROL_REGS_PLL_CONFIG              0x214 
+#define PHY_CONTROL_REGS_PLL_PRE_DIVIDER         0x218 
+#define PHY_CONTROL_REGS_PLL_DIVIDER             0x21c 
+#define PHY_CONTROL_REGS_PLL_CONTROL1            0x220 
+#define PHY_CONTROL_REGS_PLL_CONTROL2            0x224 
+#define PHY_CONTROL_REGS_PLL_SS_EN               0x228 
+#define PHY_CONTROL_REGS_PLL_SS_CFG              0x22c 
+#define PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE     0x230 
+#define PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE    0x234 
+#define PHY_CONTROL_REGS_IDLE_PAD_CONTROL        0x238 
+#define PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL         0x23c 
+#define PHY_CONTROL_REGS_DRIVE_PAD_CTL           0x240 
+#define PHY_CONTROL_REGS_CLOCK_REG_CONTROL       0x244 
+
+#define PHY_BYTE_LANE_0_REVISION                 0x300 
+#define PHY_BYTE_LANE_0_VDL_CALIBRATE            0x304 
+#define PHY_BYTE_LANE_0_VDL_STATUS               0x308 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_0           0x310 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_1           0x314 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_2           0x318 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_3           0x31c 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_4           0x320 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_5           0x324 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_6           0x328 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_7           0x32c 
+#define PHY_BYTE_LANE_0_READ_CONTROL             0x330 
+#define PHY_BYTE_LANE_0_READ_FIFO_STATUS         0x334 
+#define PHY_BYTE_LANE_0_READ_FIFO_CLEAR          0x338 
+#define PHY_BYTE_LANE_0_IDLE_PAD_CONTROL         0x33c 
+#define PHY_BYTE_LANE_0_DRIVE_PAD_CTL            0x340 
+#define PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE        0x344 
+#define PHY_BYTE_LANE_0_WR_PREAMBLE_MODE         0x348 
+#define PHY_BYTE_LANE_0_CLOCK_REG_CONTROL        0x34c 
+
+#define PHY_BYTE_LANE_1_REVISION                 0x400 
+#define PHY_BYTE_LANE_1_VDL_CALIBRATE            0x404 
+#define PHY_BYTE_LANE_1_VDL_STATUS               0x408 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_0           0x410 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_1           0x414 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_2           0x418 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_3           0x41c 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_4           0x420 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_5           0x424 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_6           0x428 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_7           0x42c 
+#define PHY_BYTE_LANE_1_READ_CONTROL             0x430 
+#define PHY_BYTE_LANE_1_READ_FIFO_STATUS         0x434 
+#define PHY_BYTE_LANE_1_READ_FIFO_CLEAR          0x438 
+#define PHY_BYTE_LANE_1_IDLE_PAD_CONTROL         0x43c 
+#define PHY_BYTE_LANE_1_DRIVE_PAD_CTL            0x440 
+#define PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE        0x444 
+#define PHY_BYTE_LANE_1_WR_PREAMBLE_MODE         0x448 
+#define PHY_BYTE_LANE_1_CLOCK_REG_CONTROL        0x44c 
+
+#define PHY_BYTE_LANE_2_REVISION                 0x500 
+#define PHY_BYTE_LANE_2_VDL_CALIBRATE            0x504 
+#define PHY_BYTE_LANE_2_VDL_STATUS               0x508 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_0           0x510 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_1           0x514 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_2           0x518 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_3           0x51c 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_4           0x520 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_5           0x524 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_6           0x528 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_7           0x52c 
+#define PHY_BYTE_LANE_2_READ_CONTROL             0x530 
+#define PHY_BYTE_LANE_2_READ_FIFO_STATUS         0x534 
+#define PHY_BYTE_LANE_2_READ_FIFO_CLEAR          0x538 
+#define PHY_BYTE_LANE_2_IDLE_PAD_CONTROL         0x53c 
+#define PHY_BYTE_LANE_2_DRIVE_PAD_CTL            0x540 
+#define PHY_BYTE_LANE_2_CLOCK_PAD_DISABLE        0x544 
+#define PHY_BYTE_LANE_2_WR_PREAMBLE_MODE         0x548 
+#define PHY_BYTE_LANE_2_CLOCK_REG_CONTROL        0x54c 
+
+#define PHY_BYTE_LANE_3_REVISION                 0x600 
+#define PHY_BYTE_LANE_3_VDL_CALIBRATE            0x604 
+#define PHY_BYTE_LANE_3_VDL_STATUS               0x608 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_0           0x610 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_1           0x614 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_2           0x618 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_3           0x61c 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_4           0x620 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_5           0x624 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_6           0x628 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_7           0x62c 
+#define PHY_BYTE_LANE_3_READ_CONTROL             0x630 
+#define PHY_BYTE_LANE_3_READ_FIFO_STATUS         0x634 
+#define PHY_BYTE_LANE_3_READ_FIFO_CLEAR          0x638 
+#define PHY_BYTE_LANE_3_IDLE_PAD_CONTROL         0x63c 
+#define PHY_BYTE_LANE_3_DRIVE_PAD_CTL            0x640 
+#define PHY_BYTE_LANE_3_CLOCK_PAD_DISABLE        0x644 
+#define PHY_BYTE_LANE_3_WR_PREAMBLE_MODE         0x648 
+#define PHY_BYTE_LANE_3_CLOCK_REG_CONTROL        0x64c 
+
+#define DDR_CTL_GCFG                             0x800 
+#define DDR_CTL_LBIST_CFG                        0x804 
+#define DDR_CTL_LBIST_SEED                       0x808 
+#define DDR_CTL_ARB                              0x80c 
+#define DDR_CTL_PI_GCF                           0x810 
+#define DDR_CTL_PI_UBUS_CTL                      0x814 
+#define DDR_CTL_PI_MIPS_CTL                      0x818 
+#define DDR_CTL_PI_DSL_MIPS_CTL                  0x81c 
+#define DDR_CTL_PI_DSL_PHY_CTL                   0x820 
+#define DDR_CTL_PI_UBUS_ST                       0x824 
+#define DDR_CTL_PI_MIPS_ST                       0x828 
+#define DDR_CTL_PI_DSL_MIPS_ST                   0x82c 
+#define DDR_CTL_PI_DSL_PHY_ST                    0x830 
+#define DDR_CTL_PI_UBUS_SMPL                     0x834 
+#define DDR_CTL_TESTMODE                         0x838 
+#define DDR_CTL_TEST_CFG1                        0x83c 
+#define DDR_CTL_TEST_PAT                         0x840 
+#define DDR_CTL_TEST_COUNT                       0x844 
+#define DDR_CTL_TEST_CURR_COUNT                  0x848 
+#define DDR_CTL_TEST_ADDR_UPDT                   0x84c 
+#define DDR_CTL_TEST_ADDR                        0x850 
+#define DDR_CTL_TEST_DATA0                       0x854 
+#define DDR_CTL_TEST_DATA1                       0x858 
+#define DDR_CTL_TEST_DATA2                       0x85c 
+#define DDR_CTL_TEST_DATA3                       0x860 
+
+
+/*
+#####################################################################
+# UART Control Registers
+#####################################################################
+*/
+#define UART0CONTROL     0x01
+#define UART0CONFIG      0x02
+#define UART0RXTIMEOUT   0x03
+#define UART0BAUD        0x04
+#define UART0FIFOCFG     0x0a
+#define UART0INTMASK     0x10
+#define UART0INTSTAT     0x12
+#define UART0DATA        0x17
+
+#define BRGEN            0x80   /* Control register bit defs */
+#define TXEN             0x40
+#define RXEN             0x20
+#define LOOPBK           0x10
+#define TXPARITYEN       0x08
+#define TXPARITYEVEN     0x04
+#define RXPARITYEN       0x02
+#define RXPARITYEVEN     0x01
+
+#define XMITBREAK        0x40   /* Config register */
+#define BITS5SYM         0x00
+#define BITS6SYM         0x10
+#define BITS7SYM         0x20
+#define BITS8SYM         0x30
+#define ONESTOP          0x07
+#define TWOSTOP          0x0f
+
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/shared/broadcom/include/bcm963xx/6328_map.h b/shared/broadcom/include/bcm963xx/6328_map.h
new file mode 100755
index 0000000..246d211
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/6328_map.h
@@ -0,0 +1,1886 @@
+/*
+<:copyright-broadcom 
+ 
+ Copyright (c) 2007 Broadcom Corporation 
+ All Rights Reserved 
+ No portions of this material may be reproduced in any form without the 
+ written permission of: 
+          Broadcom Corporation 
+          16215 Alton Parkway 
+          Irvine, California 92619 
+ All information contained in this document is Broadcom Corporation 
+ company private, proprietary, and trade secret. 
+ 
+:>
+*/
+/***********************************************************************/
+/*                                                                     */
+/*   MODULE:  6328_map.h                                               */
+/*   DATE:    05/30/08                                                 */
+/*   PURPOSE: Define addresses of major hardware components of         */
+/*            BCM6328                                                  */
+/*                                                                     */
+/***********************************************************************/
+#ifndef __BCM6328_MAP_H
+#define __BCM6328_MAP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bcmtypes.h"
+#include "6328_common.h"
+#include "6328_intr.h"
+
+/* macro to convert logical data addresses to physical */
+/* DMA hardware must see physical address */
+#define LtoP( x )       ( (uint32)x & 0x1fffffff )
+#define PtoL( x )       ( LtoP(x) | 0xa0000000 )
+
+typedef struct DDRPhyControl {
+    uint32 REVISION;               /* 0x00 */
+    uint32 CLK_PM_CTRL;            /* 0x04 */
+    uint32 unused0[2];             /* 0x08-0x10 */
+    uint32 PLL_STATUS;             /* 0x10 */
+    uint32 PLL_CONFIG;             /* 0x14 */
+    uint32 PLL_PRE_DIVIDER;        /* 0x18 */
+    uint32 PLL_DIVIDER;            /* 0x1c */
+    uint32 PLL_CONTROL1;           /* 0x20 */
+    uint32 PLL_CONTROL2;           /* 0x24 */
+    uint32 PLL_SS_EN;              /* 0x28 */
+    uint32 PLL_SS_CFG;             /* 0x2c */
+    uint32 STATIC_VDL_OVERRIDE;    /* 0x30 */
+    uint32 DYNAMIC_VDL_OVERRIDE;   /* 0x34 */
+    uint32 IDLE_PAD_CONTROL;       /* 0x38 */
+    uint32 ZQ_PVT_COMP_CTL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;          /* 0x40 */
+    uint32 CLOCK_REG_CONTROL;      /* 0x44 */
+    uint32 unused1[46];
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+    uint32 REVISION;                /* 0x00 */
+    uint32 VDL_CALIBRATE;           /* 0x04 */
+    uint32 VDL_STATUS;              /* 0x08 */
+    uint32 unused;                  /* 0x0c */
+    uint32 VDL_OVERRIDE_0;          /* 0x10 */
+    uint32 VDL_OVERRIDE_1;          /* 0x14 */
+    uint32 VDL_OVERRIDE_2;          /* 0x18 */
+    uint32 VDL_OVERRIDE_3;          /* 0x1c */
+    uint32 VDL_OVERRIDE_4;          /* 0x20 */
+    uint32 VDL_OVERRIDE_5;          /* 0x24 */
+    uint32 VDL_OVERRIDE_6;          /* 0x28 */
+    uint32 VDL_OVERRIDE_7;          /* 0x2c */
+    uint32 READ_CONTROL;            /* 0x30 */
+    uint32 READ_FIFO_STATUS;        /* 0x34 */
+    uint32 READ_FIFO_CLEAR;         /* 0x38 */
+    uint32 IDLE_PAD_CONTROL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;           /* 0x40 */
+    uint32 CLOCK_PAD_DISABLE;       /* 0x44 */
+    uint32 WR_PREAMBLE_MODE;        /* 0x48 */
+    uint32 CLOCK_REG_CONTROL;       /* 0x4C */
+    uint32 unused0[44];
+} DDRPhyByteLaneControl;
+
+typedef struct DDRControl {
+    uint32 CNFG;                            /* 0x000 */
+    uint32 CSST;                            /* 0x004 */
+    uint32 CSEND;                           /* 0x008 */
+    uint32 unused;                          /* 0x00c */
+    uint32 ROW00_0;                         /* 0x010 */
+    uint32 ROW00_1;                         /* 0x014 */
+    uint32 ROW01_0;                         /* 0x018 */
+    uint32 ROW01_1;                         /* 0x01c */
+    uint32 unused0[4];
+    uint32 ROW20_0;                         /* 0x030 */
+    uint32 ROW20_1;                         /* 0x034 */
+    uint32 ROW21_0;                         /* 0x038 */
+    uint32 ROW21_1;                         /* 0x03c */
+    uint32 unused1[4];
+    uint32 COL00_0;                         /* 0x050 */
+    uint32 COL00_1;                         /* 0x054 */
+    uint32 COL01_0;                         /* 0x058 */
+    uint32 COL01_1;                         /* 0x05c */
+    uint32 unused2[4];
+    uint32 COL20_0;                         /* 0x070 */
+    uint32 COL20_1;                         /* 0x074 */
+    uint32 COL21_0;                         /* 0x078 */
+    uint32 COL21_1;                         /* 0x07c */
+    uint32 unused3[4];
+    uint32 BNK10;                           /* 0x090 */
+    uint32 BNK32;                           /* 0x094 */
+    uint32 unused4[26];
+    uint32 DCMD;                            /* 0x100 */
+#define DCMD_CS1          (1 << 5)
+#define DCMD_CS0          (1 << 4)
+#define DCMD_SET_SREF     4
+    uint32 DMODE_0;                         /* 0x104 */
+    uint32 DMODE_1;                         /* 0x108 */
+#define DMODE_1_DRAMSLEEP (1 << 11)
+    uint32 CLKS;                            /* 0x10c */
+    uint32 ODT;                             /* 0x110 */
+    uint32 TIM1_0;                          /* 0x114 */
+    uint32 TIM1_1;                          /* 0x118 */
+    uint32 TIM2;                            /* 0x11c */
+    uint32 CTL_CRC;                         /* 0x120 */
+    uint32 DOUT_CRC;                        /* 0x124 */
+    uint32 DIN_CRC;                         /* 0x128 */
+    uint32 unused5[53];
+
+    DDRPhyControl           PhyControl;             /* 0x200 */
+    DDRPhyByteLaneControl   PhyByteLane0Control;    /* 0x300 */
+    DDRPhyByteLaneControl   PhyByteLane1Control;    /* 0x400 */
+    DDRPhyByteLaneControl   PhyByteLane2Control;    /* 0x500 */
+    DDRPhyByteLaneControl   PhyByteLane3Control;    /* 0x600 */
+    uint32 unused6[64];
+
+    uint32 GCFG;                            /* 0x800 */
+    uint32 LBIST_CFG;                       /* 0x804 */
+    uint32 LBIST_SEED;                      /* 0x808 */
+    uint32 ARB;                             /* 0x80c */
+    uint32 PI_GCF;                          /* 0x810 */
+    uint32 PI_UBUS_CTL;                     /* 0x814 */
+    uint32 PI_MIPS_CTL;                     /* 0x818 */
+    uint32 PI_DSL_MIPS_CTL;                 /* 0x81c */
+    uint32 PI_DSL_PHY_CTL;                  /* 0x820 */
+    uint32 PI_UBUS_ST;                      /* 0x824 */
+    uint32 PI_MIPS_ST;                      /* 0x828 */
+    uint32 PI_DSL_MIPS_ST;                  /* 0x82c */
+    uint32 PI_DSL_PHY_ST;                   /* 0x830 */
+    uint32 PI_UBUS_SMPL;                    /* 0x834 */
+    uint32 TESTMODE;                        /* 0x838 */
+    uint32 TEST_CFG1;                       /* 0x83c */
+    uint32 TEST_PAT;                        /* 0x840 */
+    uint32 TEST_COUNT;                      /* 0x844 */
+    uint32 TEST_CURR_COUNT;                 /* 0x848 */
+    uint32 TEST_ADDR_UPDT;                  /* 0x84c */
+    uint32 TEST_ADDR;                       /* 0x850 */
+    uint32 TEST_DATA0;                      /* 0x854 */
+    uint32 TEST_DATA1;                      /* 0x858 */
+    uint32 TEST_DATA2;                      /* 0x85c */
+    uint32 TEST_DATA3;                      /* 0x860 */
+} DDRControl;
+
+#define DDR ((volatile DDRControl * const) DDR_BASE)
+
+/*
+** Peripheral Controller
+*/
+
+#define IRQ_BITS 64
+typedef struct  {
+    uint64        IrqMask;
+    uint64        IrqStatus;
+} IrqControl_t;
+
+typedef struct PerfControl {
+    uint32        RevID;             /* (00) word 0 */
+    uint32        blkEnables;        /* (04) word 1 */
+#define ROBOSW_CLK_EN    (1 << 11)
+#define PCIE_CLK_EN      (1 << 10)
+#define HS_SPI_CLK_EN    (1 << 9)
+#define USBH_CLK_EN      (1 << 8)
+#define USBD_CLK_EN      (1 << 7)
+#define PCM_CLK_EN       (1 << 6)
+#define SAR_CLK_EN       (1 << 5)
+#define MIPS_CLK_EN      (1 << 4)
+#define ADSL_CLK_EN      (1 << 3)
+#define ADSL_AFE_EN      (1 << 2)
+#define ADSL_QPROC_EN    (1 << 1)
+#define PHYMIPS_CLK_EN   (1 << 0)
+
+    uint32        unused0;           /* (08) word 2 */
+    uint32        deviceTimeoutEn;   /* (0c) word 3 */
+    uint32        softResetB;        /* (10) word 4 */
+#define SOFT_RST_PCIE_HARD      (1 << 10)
+#define SOFT_RST_PCIE_EXT       (1 << 9)
+#define SOFT_RST_PCIE           (1 << 8)
+#define SOFT_RST_PCIE_CORE      (1 << 7)
+#define SOFT_RST_PCM            (1 << 6)
+#define SOFT_RST_USBH           (1 << 5)
+#define SOFT_RST_USBD           (1 << 4)
+#define SOFT_RST_SWITCH         (1 << 3)
+#define SOFT_RST_SAR            (1 << 2)
+#define SOFT_RST_EPHY           (1 << 1)
+#define SOFT_RST_SPI            (1 << 0)
+
+    uint32        diagControl;        /* (14) word 5 */
+    uint32        ExtIrqCfg;          /* (18) word 6*/
+    uint32        unused1;            /* (1c) word 7 */
+#define EI_SENSE_SHFT   0
+#define EI_STATUS_SHFT  4
+#define EI_CLEAR_SHFT   8
+#define EI_MASK_SHFT    12
+#define EI_INSENS_SHFT  16
+#define EI_LEVEL_SHFT   20
+
+     IrqControl_t IrqControl[2];
+} PerfControl;
+
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+/*
+** Timer
+*/
+typedef struct Timer {
+    uint16        unused0;
+    byte          TimerMask;
+#define TIMER0EN        0x01
+#define TIMER1EN        0x02
+#define TIMER2EN        0x04
+    byte          TimerInts;
+#define TIMER0          0x01
+#define TIMER1          0x02
+#define TIMER2          0x04
+#define WATCHDOG        0x08
+    uint32        TimerCtl0;
+    uint32        TimerCtl1;
+    uint32        TimerCtl2;
+#define TIMERENABLE     0x80000000
+#define RSTCNTCLR       0x40000000
+    uint32        TimerCnt0;
+    uint32        TimerCnt1;
+    uint32        TimerCnt2;
+    uint32        WatchDogDefCount;
+
+    /* Write 0xff00 0x00ff to Start timer
+     * Write 0xee00 0x00ee to Stop and re-load default count
+     * Read from this register returns current watch dog count
+     */
+    uint32        WatchDogCtl;
+
+    /* Number of 50-MHz ticks for WD Reset pulse to last */
+    uint32        WDResetCount;
+
+    uint32        SoftRst;
+#define SOFT_RESET              0x00000001      // 0
+} Timer;
+
+#define TIMER ((volatile Timer * const) TIMR_BASE)
+
+/*
+** UART
+*/
+typedef struct UartChannel {
+    byte          unused0;
+    byte          control;
+#define BRGEN           0x80    /* Control register bit defs */
+#define TXEN            0x40
+#define RXEN            0x20
+#define LOOPBK          0x10
+#define TXPARITYEN      0x08
+#define TXPARITYEVEN    0x04
+#define RXPARITYEN      0x02
+#define RXPARITYEVEN    0x01
+
+    byte          config;
+#define XMITBREAK       0x40
+#define BITS5SYM        0x00
+#define BITS6SYM        0x10
+#define BITS7SYM        0x20
+#define BITS8SYM        0x30
+#define ONESTOP         0x07
+#define TWOSTOP         0x0f
+    /* 4-LSBS represent STOP bits/char
+     * in 1/8 bit-time intervals.  Zero
+     * represents 1/8 stop bit interval.
+     * Fifteen represents 2 stop bits.
+     */
+    byte          fifoctl;
+#define RSTTXFIFOS      0x80
+#define RSTRXFIFOS      0x40
+    /* 5-bit TimeoutCnt is in low bits of this register.
+     *  This count represents the number of characters
+     *  idle times before setting receive Irq when below threshold
+     */
+    uint32        baudword;
+    /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
+     */
+
+    byte          txf_levl;       /* Read-only fifo depth */
+    byte          rxf_levl;       /* Read-only fifo depth */
+    byte          fifocfg;        /* Upper 4-bits are TxThresh, Lower are
+                                   *      RxThreshold.  Irq can be asserted
+                                   *      when rx fifo> thresh, txfifo<thresh
+                                   */
+    byte          prog_out;       /* Set value of DTR (Bit0), RTS (Bit1)
+                                   *  if these bits are also enabled to GPIO_o
+                                   */
+#define DTREN   0x01
+#define RTSEN   0x02
+
+    byte          unused1;
+    byte          DeltaIPEdgeNoSense;     /* Low 4-bits, set corr bit to 1 to
+                                           * detect irq on rising AND falling
+                                           * edges for corresponding GPIO_i
+                                           * if enabled (edge insensitive)
+                                           */
+    byte          DeltaIPConfig_Mask;     /* Upper 4 bits: 1 for posedge sense
+                                           *      0 for negedge sense if
+                                           *      not configured for edge
+                                           *      insensitive (see above)
+                                           * Lower 4 bits: Mask to enable change
+                                           *  detection IRQ for corresponding
+                                           *  GPIO_i
+                                           */
+    byte          DeltaIP_SyncIP;         /* Upper 4 bits show which bits
+                                           *  have changed (may set IRQ).
+                                           *  read automatically clears bit
+                                           * Lower 4 bits are actual status
+                                           */
+
+    uint16        intMask;                /* Same Bit defs for Mask and status */
+    uint16        intStatus;
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+    uint16        unused2;
+    uint16        Data;                   /* Write to TX, Read from RX */
+                                          /* bits 11:8 are BRK,PAR,FRM errors */
+
+    uint32        unused3;
+    uint32        unused4;
+} Uart;
+
+#define UART ((volatile Uart * const) UART_BASE)
+
+/*
+** Gpio Controller
+*/
+
+#pragma pack(push, 4)
+typedef struct GpioControl {
+    uint32      GPIODirHi;                  /* 0 */
+    uint32      GPIODir;                    /* 4 */
+    uint32      GPIOioHi;                   /* 8 */
+    uint32      GPIOio;                     /* C */
+    uint32      unused0;                    /* 10 */
+    uint32      SpiSlaveCfg;                /* 14 */
+    uint32      GPIOMode;                   /* 18 */
+    uint64      PinMuxSel;                  /* 1C */
+#define SERIAL_LED_DATA     6
+#define SERIAL_LED_CLK      7
+#define INET_ACT_LED        11
+#define EPHY0_SPD_LED       17
+#define EPHY1_SPD_LED       18
+#define EPHY2_SPD_LED       19
+#define EPHY3_SPD_LED       20
+#define EPHY0_ACT_LED       25
+#define EPHY1_ACT_LED       26
+#define EPHY2_ACT_LED       27
+#define EPHY3_ACT_LED       28
+
+#define PINMUX_SERIAL_LED_DATA  ((uint64)2 << (SERIAL_LED_DATA << 1))
+#define PINMUX_SERIAL_LED_CLK   ((uint64)2 << (SERIAL_LED_CLK << 1))
+#define PINMUX_INET_ACT_LED     ((uint64)1 << (INET_ACT_LED << 1))
+#define PINMUX_EPHY0_ACT_LED    ((uint64)1 << (EPHY0_ACT_LED << 1))
+#define PINMUX_EPHY1_ACT_LED    ((uint64)1 << (EPHY1_ACT_LED << 1))
+#define PINMUX_EPHY2_ACT_LED    ((uint64)1 << (EPHY2_ACT_LED << 1))
+#define PINMUX_EPHY3_ACT_LED    ((uint64)1 << (EPHY3_ACT_LED << 1))
+
+    uint32      PinMuxSelOther;             /* 24 */
+#define SEL_USB                 12
+#define PINMUX_SEL_USB_MASK     (3 << SEL_USB)
+#define PINMUX_SEL_USB_HOST     (1 << SEL_USB)
+#define PINMUX_SEL_USB_DEV      (2 << SEL_USB)
+
+    uint32      TestControl;                /* 28 */
+    uint32      unused2;                    /* 2C */
+    uint32      RoboSWLEDControl;           /* 30 */
+    uint32      RoboSWLEDLSR;               /* 34 */
+    uint32      unused3;                    /* 38 */
+    uint32      RoboswEphyCtrl;             /* 3C */
+#define EPHY_AUTO_PWR_DOWN_EN   (1<<29)
+#define EPHY_IDDQ_FROM_PHY      (1<<28)
+#define EPHY_PLL_LOCK           (1<<27)
+#define EPHY_ATEST_25MHZ_EN     (1<<26)
+#define EPHY_PWR_DOWN_DLL       (1<<25)
+#define EPHY_PWR_DOWN_BIAS      (1<<24)
+#define EPHY_PWR_DOWN_TX_4      (1<<23)
+#define EPHY_PWR_DOWN_TX_3      (1<<22)
+#define EPHY_PWR_DOWN_TX_2      (1<<21)
+#define EPHY_PWR_DOWN_TX_1      (1<<20)
+#define EPHY_PWR_DOWN_RX_4      (1<<19)
+#define EPHY_PWR_DOWN_RX_3      (1<<18)
+#define EPHY_PWR_DOWN_RX_2      (1<<17)
+#define EPHY_PWR_DOWN_RX_1      (1<<16)
+#define EPHY_PWR_DOWN_SD_4      (1<<15)
+#define EPHY_PWR_DOWN_SD_3      (1<<14)
+#define EPHY_PWR_DOWN_SD_2      (1<<13)
+#define EPHY_PWR_DOWN_SD_1      (1<<12)
+#define EPHY_PWR_DOWN_RD_4      (1<<11)
+#define EPHY_PWR_DOWN_RD_3      (1<<10)
+#define EPHY_PWR_DOWN_RD_2      (1<<9)
+#define EPHY_PWR_DOWN_RD_1      (1<<8)
+#define EPHY_PWR_DOWN_4         (1<<7)
+#define EPHY_PWR_DOWN_3         (1<<6)
+#define EPHY_PWR_DOWN_2         (1<<5)
+#define EPHY_PWR_DOWN_1         (1<<4)
+#define EPHY_RST_4              (1<<3)
+#define EPHY_RST_3              (1<<2)
+#define EPHY_RST_2              (1<<1)
+#define EPHY_RST_1              (1<<0)
+    uint32      RoboswSwitchCtrl;           /* 40 */
+#define RSW_SPI_MODE            (1<<11)
+#define RSW_BC_SUPP_EN          (1<<10)
+#define RSW_CLK_FREQ_MASK       (3<<8)
+#define RSW_ENF_DFX_FLOW        (1<<7)
+#define RSW_ENH_DFX_FLOW        (1<<6)
+#define RSW_GRX_0_SETUP         (1<<5)
+#define RSW_GTX_0_SETUP         (1<<4)
+#define RSW_HW_FWDG_EN          (1<<3)
+#define RSW_QOS_EN              (1<<2)
+#define RSW_WD_CLR_EN           (1<<1)
+#define RSW_MII_DUMB_FWDG_EN    (1<<0)
+
+    uint32      RegFileTmCtl;               /* 44 */
+
+    uint32      RingOscCtrl0;               /* 48 */
+#define RING_OSC_256_CYCLES         8
+#define RING_OSC_512_CYCLES         9
+#define RING_OSC_1024_CYCLES        10
+
+    uint32      RingOscCtrl1;               /* 4C */
+#define RING_OSC_ENABLE_MASK        (0x0f<<24)
+#define RING_OSC_ENABLE_SHIFT       24
+#define RING_OSC_MAX                4
+#define RING_OSC_COUNT_RESET        (0x1<<23)
+#define RING_OSC_SELECT_MASK        (0x7<<20)
+#define RING_OSC_SELECT_SHIFT       20
+#define RING_OSC_IRQ                (0x1<<18)
+#define RING_OSC_COUNTER_OVERFLOW   (0x1<<17)
+#define RING_OSC_COUNTER_BUSY       (0x1<<16)
+#define RING_OSC_COUNT_MASK         0x0000ffff
+
+    uint32      unused4[6];                 /* 50 - 64 */
+    uint32      DieRevID;                   /* 68 */
+    uint32      unused5;                    /* 6c */
+    uint32      DiagSelControl;             /* 70 */
+    uint32      DiagReadBack;               /* 74 */
+    uint32      DiagReadBackHi;             /* 78 */
+    uint32      DiagMiscControl;            /* 7c */
+} GpioControl;
+#pragma pack(pop)
+
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/* Number to mask conversion macro used for GPIODir and GPIOio */
+#define GPIO_NUM_MAX                    32
+#define GPIO_NUM_TO_MASK(X)             ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (1 << ((X) & BP_GPIO_NUM_MASK)) : (0) )
+
+/*
+** High-Speed SPI Controller
+*/
+
+#define __mask(end, start)      (((1 << ((end - start) + 1)) - 1) << start)
+typedef struct HsSpiControl {
+
+  uint32    hs_spiGlobalCtrl;   // 0x0000
+#define HS_SPI_MOSI_IDLE        (1 << 18)
+#define HS_SPI_CLK_POLARITY      (1 << 17)
+#define HS_SPI_CLK_GATE_SSOFF       (1 << 16)
+#define HS_SPI_PLL_CLK_CTRL     (8)
+#define HS_SPI_PLL_CLK_CTRL_MASK    __mask(15, HS_SPI_PLL_CLK_CTRL)
+#define HS_SPI_SS_POLARITY      (0)
+#define HS_SPI_SS_POLARITY_MASK     __mask(7, HS_SPI_SS_POLARITY)
+
+  uint32    hs_spiExtTrigCtrl;  // 0x0004
+#define HS_SPI_TRIG_RAW_STATE   (24)
+#define HS_SPI_TRIG_RAW_STATE_MASK  __mask(31, HS_SPI_TRIG_RAW_STATE)
+#define HS_SPI_TRIG_LATCHED     (16)
+#define HS_SPI_TRIG_LATCHED_MASK    __mask(23, HS_SPI_TRIG_LATCHED)
+#define HS_SPI_TRIG_SENSE       (8)
+#define HS_SPI_TRIG_SENSE_MASK      __mask(15, HS_SPI_TRIG_SENSE)
+#define HS_SPI_TRIG_TYPE        (0)
+#define HS_SPI_TRIG_TYPE_MASK       __mask(7, HS_SPI_TRIG_TYPE)
+#define HS_SPI_TRIG_TYPE_EDGE       (0)
+#define HS_SPI_TRIG_TYPE_LEVEL      (1)
+
+  uint32    hs_spiIntStatus;    // 0x0008
+#define HS_SPI_IRQ_PING1_USER       (28)
+#define HS_SPI_IRQ_PING1_USER_MASK  __mask(31, HS_SPI_IRQ_PING1_USER)
+#define HS_SPI_IRQ_PING0_USER       (24)
+#define HS_SPI_IRQ_PING0_USER_MASK  __mask(27, HS_SPI_IRQ_PING0_USER)
+
+#define HS_SPI_IRQ_PING1_CTRL_INV   (1 << 12)
+#define HS_SPI_IRQ_PING1_POLL_TOUT  (1 << 11)
+#define HS_SPI_IRQ_PING1_TX_UNDER   (1 << 10)
+#define HS_SPI_IRQ_PING1_RX_OVER    (1 << 9)
+#define HS_SPI_IRQ_PING1_CMD_DONE   (1 << 8)
+
+#define HS_SPI_IRQ_PING0_CTRL_INV   (1 << 4)
+#define HS_SPI_IRQ_PING0_POLL_TOUT  (1 << 3)
+#define HS_SPI_IRQ_PING0_TX_UNDER   (1 << 2)
+#define HS_SPI_IRQ_PING0_RX_OVER    (1 << 1)
+#define HS_SPI_IRQ_PING0_CMD_DONE   (1 << 0)
+
+  uint32    hs_spiIntStatusMasked;  // 0x000C
+#define HS_SPI_IRQSM__PING1_USER    (28)
+#define HS_SPI_IRQSM__PING1_USER_MASK   __mask(31, HS_SPI_IRQSM__PING1_USER)
+#define HS_SPI_IRQSM__PING0_USER    (24)
+#define HS_SPI_IRQSM__PING0_USER_MASK   __mask(27, HS_SPI_IRQSM__PING0_USER)
+
+#define HS_SPI_IRQSM__PING1_CTRL_INV    (1 << 12)
+#define HS_SPI_IRQSM__PING1_POLL_TOUT   (1 << 11)
+#define HS_SPI_IRQSM__PING1_TX_UNDER    (1 << 10)
+#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9)
+#define HS_SPI_IRQSM__PING1_CMD_DONE    (1 << 8)
+
+#define HS_SPI_IRQSM__PING0_CTRL_INV    (1 << 4)
+#define HS_SPI_IRQSM__PING0_POLL_TOUT   (1 << 3)
+#define HS_SPI_IRQSM__PING0_TX_UNDER    (1 << 2)
+#define HS_SPI_IRQSM__PING0_RX_OVER     (1 << 1)
+#define HS_SPI_IRQSM__PING0_CMD_DONE    (1 << 0)
+
+  uint32    hs_spiIntMask;      // 0x0010
+#define HS_SPI_IRQM_PING1_USER      (28)
+#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER)
+#define HS_SPI_IRQM_PING0_USER      (24)
+#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER)
+
+#define HS_SPI_IRQM_PING1_CTRL_INV  (1 << 12)
+#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11)
+#define HS_SPI_IRQM_PING1_TX_UNDER  (1 << 10)
+#define HS_SPI_IRQM_PING1_RX_OVER   (1 << 9)
+#define HS_SPI_IRQM_PING1_CMD_DONE  (1 << 8)
+
+#define HS_SPI_IRQM_PING0_CTRL_INV  (1 << 4)
+#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3)
+#define HS_SPI_IRQM_PING0_TX_UNDER  (1 << 2)
+#define HS_SPI_IRQM_PING0_RX_OVER   (1 << 1)
+#define HS_SPI_IRQM_PING0_CMD_DONE  (1 << 0)
+
+#define HS_SPI_INTR_CLEAR_ALL       (0xFF001F1F)
+
+  uint32    hs_spiFlashCtrl;    // 0x0014
+#define HS_SPI_FCTRL_MB_ENABLE      (1 << 23)
+#define HS_SPI_FCTRL_SS_NUM         (20)
+#define HS_SPI_FCTRL_SS_NUM_MASK    __mask(22, HS_SPI_FCTRL_SS_NUM)
+#define HS_SPI_FCTRL_PROFILE_NUM    (16)
+#define HS_SPI_FCTRL_PROFILE_NUM_MASK   __mask(18, HS_SPI_FCTRL_PROFILE_NUM)
+#define HS_SPI_FCTRL_DUMMY_BYTES    (10)
+#define HS_SPI_FCTRL_DUMMY_BYTES_MASK   __mask(11, HS_SPI_FCTRL_DUMMY_BYTES)
+#define HS_SPI_FCTRL_ADDR_BYTES     (8)
+#define HS_SPI_FCTRL_ADDR_BYTES_MASK    __mask(9, HS_SPI_FCTRL_ADDR_BYTES)
+#define HS_SPI_FCTRL_ADDR_BYTES_2   (0)
+#define HS_SPI_FCTRL_ADDR_BYTES_3   (1)
+#define HS_SPI_FCTRL_ADDR_BYTES_4   (2)
+#define HS_SPI_FCTRL_READ_OPCODE    (0)
+#define HS_SPI_FCTRL_READ_OPCODE_MASK   __mask(7, HS_SPI_FCTRL_READ_OPCODE)
+
+  uint32    hs_spiFlashAddrBase;    // 0x0018
+
+  char      fill0[0x80 - 0x18];
+
+  uint32    hs_spiPP_0_Cmd;     // 0x0080
+#define HS_SPI_PP_SS_NUM        (12)
+#define HS_SPI_PP_SS_NUM_MASK       __mask(14, HS_SPI_PP_SS_NUM)
+#define HS_SPI_PP_PROFILE_NUM       (8)
+#define HS_SPI_PP_PROFILE_NUM_MASK  __mask(10, HS_SPI_PP_PROFILE_NUM)
+
+} HsSpiControl;
+
+typedef struct HsSpiPingPong {
+
+    uint32 command;
+#define HS_SPI_SS_NUM (12)
+#define HS_SPI_PROFILE_NUM (8)
+#define HS_SPI_TRIGGER_NUM (4)
+#define HS_SPI_COMMAND_VALUE (0)
+    #define HS_SPI_COMMAND_NOOP (0)
+    #define HS_SPI_COMMAND_START_NOW (1)
+    #define HS_SPI_COMMAND_START_TRIGGER (2)
+    #define HS_SPI_COMMAND_HALT (3)
+    #define HS_SPI_COMMAND_FLUSH (4)
+
+    uint32 status;
+#define HS_SPI_ERROR_BYTE_OFFSET (16)
+#define HS_SPI_WAIT_FOR_TRIGGER (2)
+#define HS_SPI_SOURCE_BUSY (1)
+#define HS_SPI_SOURCE_GNT (0)
+
+    uint32 fifo_status;
+    uint32 control;
+
+} HsSpiPingPong;
+
+typedef struct HsSpiProfile {
+
+    uint32 clk_ctrl;
+#define HS_SPI_ACCUM_RST_ON_LOOP (15)
+#define HS_SPI_SPI_CLK_2X_SEL (14)
+#define HS_SPI_FREQ_CTRL_WORD (0)
+    
+    uint32 signal_ctrl;
+#define	HS_SPI_ASYNC_INPUT_PATH (1 << 16)
+#define	HS_SPI_LAUNCH_RISING    (1 << 13)
+#define	HS_SPI_LATCH_RISING     (1 << 12)
+
+    uint32 mode_ctrl;
+#define HS_SPI_PREPENDBYTE_CNT (24)
+#define HS_SPI_MODE_ONE_WIRE (20)
+#define HS_SPI_MULTIDATA_WR_SIZE (18)
+#define HS_SPI_MULTIDATA_RD_SIZE (16)
+#define HS_SPI_MULTIDATA_WR_STRT (12)
+#define HS_SPI_MULTIDATA_RD_STRT (8)
+#define HS_SPI_FILLBYTE (0)
+
+    uint32 polling_config;
+    uint32 polling_and_mask;
+    uint32 polling_compare;
+    uint32 polling_timeout;
+    uint32 reserved;
+
+} HsSpiProfile;
+
+#define HS_SPI_OP_CODE 13
+    #define HS_SPI_OP_SLEEP (0)
+    #define HS_SPI_OP_READ_WRITE (1)
+    #define HS_SPI_OP_WRITE (2)
+    #define HS_SPI_OP_READ (3)
+    #define HS_SPI_OP_SETIRQ (4)
+
+#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE)
+#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80))
+#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0))
+#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100))
+#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200))
+#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400))
+
+
+/*
+** Misc Register Set Definitions.
+*/
+
+typedef struct Misc {
+  uint32        miscSerdesCtrl;                 /* 0x0000 */
+#define SERDES_PCIE_ENABLE                      0x00000001
+#define SERDES_PCIE_EXD_ENABLE                  (1<<15)
+    
+  uint32        miscSerdesSts;                  /* 0x0004 */
+  uint32        miscIrqOutMask;                 /* 0x0008 */
+#define MISC_PCIE_EP_IRQ_MASK0                  (1<<0)
+#define MISC_PCIE_EP_IRQ_MASK1                  (1<<1)
+
+  uint32        miscMemcControl;                /* 0x000c */
+#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE    (1<<3)
+#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE     (1<<2)
+#define MISC_MEMC_CONTROL_DDR_TEST_DONE         (1<<1)
+#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE      (1<<0)
+
+  uint32        unused0[2];                     /* 0x0010 */
+
+  uint32        miscVregCtrl0;                  /* 0x0018 */
+#define VREG_VSEL1P2_SHIFT      0
+#define VREG_VSEL1P2_MASK       0x1f
+#define VREG_VSEL1P2_MIDDLE     0x0f
+
+  uint32        miscVregCtrl1;                  /* 0x001c */
+  uint32        miscVregCtrl2;                  /* 0x0020 */
+  uint32        miscLedXorReg;                  /* 0x0024 */
+  uint32        miscExtra2ChipIrqMask;          /* 0x0028 */
+  uint32        miscExtra2ChipIrqStatus;        /* 0x002c */
+  uint32        miscExtra2ChipIrqMask1;         /* 0x0030 */
+  uint32        miscExtra2ChipIrqStatus1;       /* 0x0034 */
+  uint32        miscDdrPllTestCtrl;             /* 0x0038 */
+  uint32        miscPadCtrlLow;                 /* 0x003c */
+  uint32        miscPadCtrlHigh;                /* 0x0040 */
+#define MISC_MII_SEL_SHIFT      30
+#define MISC_MII_SEL_3P3V       0
+#define MISC_MII_SEL_2P5V       1
+#define MISC_MII_SEL_1P5V       2
+  uint32        miscPeriphEcoReg;               /* 0x0044 */
+
+  uint32        miscIddqCtrl;                   /* 0x0048 */
+#define MISC_IDDQ_CONTROL_USBH    (1<<6)
+#define MISC_IDDQ_CONTROL_USBD    (1<<5)
+
+  uint32        miscAdslClkSample;              /* 0x004c */
+
+  uint32        unused3[(0x0100 - 0x0050) / 4]; /* 0x0050 */
+  uint32        miscAdslCtrl;                   /* 0x0100 */
+  uint32        unused4[(0x0180 - 0x0104) / 4]; /* 0x0104 */
+  uint32        miscMipsTestCtrl;               /* 0x0180 */
+  uint32        miscMipsTestStatus;             /* 0x0184 */
+  uint32        unused5[(0x0200 - 0x0188) / 4]; /* 0x0188 */
+  uint32        miscPllCtrlSysPll0;             /* 0x0200 */
+  uint32        miscPllCtrlSysPll1;             /* 0x0204 */
+  uint32        miscPllCtrlSysPll2;             /* 0x0208 */
+  uint32        miscPllCtrlSysPll3;             /* 0x020c */
+  uint32        miscPllCtrlDdrPll;              /* 0x0210 */
+  uint32        miscPllCtrlXtalEcoReg;          /* 0x0214 */
+  uint32        unused6[(0x0240 - 0x0218) / 4]; /* 0x0218 */
+  uint32        miscStrapBus;                   /* 0x0240 */
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           18
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x1<<MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SERIAL              0x01
+#define MISC_STRAP_BUS_BOOT_NAND                0x00
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT      7
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK       (0x1F<<MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT)
+
+  uint32        miscStrapOverride;              /* 0x0244 */
+  uint32        unused7[(0x0280 - 0x0248) / 4]; /* 0x0248 */
+  uint32        miscRtcSleepModeEn;             /* 0x0280 */
+  uint32        miscRtcSleepRtcEn;              /* 0x0284 */
+  uint32        miscRtcSleepRtcCountLow;        /* 0x0288 */
+  uint32        miscRtcSleepRtcCountHigh;       /* 0x028c */
+  uint32        miscRtcSleepRtcEvent;           /* 0x0290 */
+  uint32        miscRtcSleepWakeupMask;         /* 0x0294 */
+  uint32        miscRtcSleepWakeupStatus;       /* 0x0298 */
+  uint32        miscRtcSleepDebounceCtrl;       /* 0x029c */
+  uint32        miscRtcSleepCpuScratchPad;      /* 0x02a0 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+/*
+** LedControl Register Set Definitions.
+*/
+
+#pragma pack(push, 4)
+typedef struct LedControl {
+    uint32  ledInit;
+#define LED_LED_TEST                (1 << 31)
+#define LED_SHIFT_TEST              (1 << 30)
+#define LED_SERIAL_LED_SHIFT_DIR    (1 << 16)
+#define LED_SERIAL_LED_DATA_PPOL    (1 << 15)
+#define LEDSERIAL_LED_CLK_NPOL      (1 << 14)
+#define LED_SERIAL_LED_MUX_SEL      (1 << 13)
+#define LED_SERIAL_LED_EN           (1 << 12)
+#define LED_FAST_INTV_SHIFT         6
+#define LED_FAST_INTV_MASK          (0x3F<<LED_FAST_INTV_SHIFT)
+#define LED_SLOW_INTV_SHIFT         0
+#define LED_SLOW_INTV_MASK          (0x3F<<LED_SLOW_INTV_SHIFT)
+#define LED_INTERVAL_20MS           1
+
+    uint64  ledMode;
+#define LED_MODE_MASK               (uint64)0x3
+#define LED_MODE_OFF                (uint64)0x0
+#define LED_MODE_FLASH              (uint64)0x1
+#define LED_MODE_BLINK              (uint64)0x2
+#define LED_MODE_ON                 (uint64)0x3
+
+    uint32  ledHWDis;
+    uint32  ledStrobe;
+    uint32  ledLinkActSelHigh;
+#define LED_ENET0                   4
+#define LED_ENET1                   5
+#define LED_ENET2                   6
+#define LED_ENET3                   7
+#define LED_4_ACT_SHIFT             0
+#define LED_5_ACT_SHIFT             4
+#define LED_6_ACT_SHIFT             8
+#define LED_7_ACT_SHIFT             12
+#define LED_4_LINK_SHIFT            16
+#define LED_5_LINK_SHIFT            20
+#define LED_6_LINK_SHIFT            24
+#define LED_7_LINK_SHIFT            28
+    uint32  ledLinkActSelLow;
+#define LED_INET                    0
+#define LED_0_ACT_SHIFT             0
+#define LED_1_ACT_SHIFT             4
+#define LED_2_ACT_SHIFT             8
+#define LED_3_ACT_SHIFT             12
+#define LED_0_LINK_SHIFT            16
+#define LED_1_LINK_SHIFT            20
+#define LED_2_LINK_SHIFT            24
+#define LED_3_LINK_SHIFT            28
+
+    uint32  ledReadback;
+    uint32  ledSerialMuxSelect;
+} LedControl;
+#pragma pack(pop)
+
+#define LED ((volatile LedControl * const) LED_BASE)
+
+#define GPIO_NUM_TO_LED_MODE_SHIFT(X) \
+    ((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \
+    ((((X) & BP_GPIO_NUM_MASK) - 8) << 1))
+
+/*
+** Pcm Controller
+*/
+
+typedef struct PcmControlRegisters
+{
+    uint32 pcm_ctrl;                            // 00 offset from PCM_BASE
+#define  PCM_ENABLE              0x80000000     // PCM block master enable
+#define  PCM_ENABLE_SHIFT        31
+#define  PCM_SLAVE_SEL           0x40000000     // PCM TDM slave mode select (1 - TDM slave, 0 - TDM master)
+#define  PCM_SLAVE_SEL_SHIFT     30
+#define  PCM_CLOCK_INV           0x20000000     // PCM SCLK invert select (1 - invert, 0 - normal)
+#define  PCM_CLOCK_INV_SHIFT     29
+#define  PCM_FS_INVERT           0x10000000     // PCM FS invert select (1 - invert, 0 - normal)
+#define  PCM_FS_INVERT_SHIFT     28
+#define  PCM_FS_FREQ_16_8        0x08000000     // PCM FS 16/8 Khz select (1 - 16Khz, 0 - 8Khz)
+#define  PCM_FS_FREQ_16_8_SHIFT  27
+#define  PCM_FS_LONG             0x04000000     // PCM FS long/short select (1 - long FS, 0 - short FS)
+#define  PCM_FS_LONG_SHIFT       26
+#define  PCM_FS_TRIG             0x02000000     // PCM FS trigger (1 - falling edge, 0 - rising edge trigger)
+#define  PCM_FS_TRIG_SHIFT       25
+#define  PCM_DATA_OFF            0x01000000     // PCM data offset from FS (1 - one clock from FS, 0 - no offset)
+#define  PCM_DATA_OFF_SHIFT      24
+#define  PCM_DATA_16_8           0x00800000     // PCM data word length (1 - 16 bits, 0 - 8 bits)
+#define  PCM_DATA_16_8_SHIFT     23
+#define  PCM_CLOCK_SEL           0x00700000     // PCM SCLK freq select
+#define  PCM_CLOCK_SEL_SHIFT     20
+                                                  // 000 - 8192 Khz
+                                                  // 001 - 4096 Khz
+                                                  // 010 - 2048 Khz
+                                                  // 011 - 1024 Khz
+                                                  // 100 - 512 Khz
+                                                  // 101 - 256 Khz
+                                                  // 110 - 128 Khz
+                                                  // 111 - reserved
+#define  PCM_LSB_FIRST           0x00040000     // PCM shift direction (1 - LSBit first, 0 - MSBit first)
+#define  PCM_LSB_FIRST_SHIFT     18
+#define  PCM_LOOPBACK            0x00020000     // PCM diagnostic loobback enable
+#define  PCM_LOOPBACK_SHIFT      17
+#define  PCM_EXTCLK_SEL          0x00010000     // PCM external timing clock select -- Maybe removed in 6328
+#define  PCM_EXTCLK_SEL_SHIFT    16
+#define  PCM_NTR_ENABLE          0x00008000     // PCM NTR counter enable -- Nayve removed in 6328
+#define  PCM_NTR_ENABLE_SHIFT    15
+#define  PCM_BITS_PER_FRAME_1024 0x00000400     // 1024 - Max
+#define  PCM_BITS_PER_FRAME_256  0x00000100     // 256
+#define  PCM_BITS_PER_FRAME_8    0x00000008     // 8    - Min
+
+    uint32 pcm_chan_ctrl;                       // 04
+#define  PCM_TX0_EN              0x00000001     // PCM transmit channel 0 enable
+#define  PCM_TX1_EN              0x00000002     // PCM transmit channel 1 enable
+#define  PCM_TX2_EN              0x00000004     // PCM transmit channel 2 enable
+#define  PCM_TX3_EN              0x00000008     // PCM transmit channel 3 enable
+#define  PCM_TX4_EN              0x00000010     // PCM transmit channel 4 enable
+#define  PCM_TX5_EN              0x00000020     // PCM transmit channel 5 enable
+#define  PCM_TX6_EN              0x00000040     // PCM transmit channel 6 enable
+#define  PCM_TX7_EN              0x00000080     // PCM transmit channel 7 enable
+#define  PCM_RX0_EN              0x00000100     // PCM receive channel 0 enable
+#define  PCM_RX1_EN              0x00000200     // PCM receive channel 1 enable
+#define  PCM_RX2_EN              0x00000400     // PCM receive channel 2 enable
+#define  PCM_RX3_EN              0x00000800     // PCM receive channel 3 enable
+#define  PCM_RX4_EN              0x00001000     // PCM receive channel 4 enable
+#define  PCM_RX5_EN              0x00002000     // PCM receive channel 5 enable
+#define  PCM_RX6_EN              0x00004000     // PCM receive channel 6 enable
+#define  PCM_RX7_EN              0x00008000     // PCM receive channel 7 enable
+#define  PCM_RX_PACKET_SIZE      0x00ff0000     // PCM Rx DMA quasi-packet size
+#define  PCM_RX_PACKET_SIZE_SHIFT  16
+
+    uint32 pcm_int_pending;                     // 08
+    uint32 pcm_int_mask;                        // 0c
+#define  PCM_TX_UNDERFLOW        0x00000001     // PCM DMA receive overflow
+#define  PCM_RX_OVERFLOW         0x00000002     // PCM DMA transmit underflow
+#define  PCM_TDM_FRAME           0x00000004     // PCM frame boundary
+#define  PCM_RX_IRQ              0x00000008     // IUDMA interrupts
+#define  PCM_TX_IRQ              0x00000010
+
+    uint32 pcm_pll_ctrl1;                       // 10
+#define  PCM_PLL_PWRDN           0x80000000     // PLL PWRDN
+#define  PCM_PLL_PWRDN_CH1       0x40000000     // PLL CH PWRDN
+#define  PCM_PLL_REFCMP_PWRDN    0x20000000     // PLL REFCMP PWRDN
+#define  PCM_CLK16_RESET         0x10000000     // 16.382 MHz PCM interface circuitry reset. 
+#define  PCM_PLL_ARESET          0x08000000     // PLL Analog Reset
+#define  PCM_PLL_DRESET          0x04000000     // PLL Digital Reset
+
+    uint32 pcm_pll_ctrl2;                       // 14
+    uint32 pcm_pll_ctrl3;                       // 18
+    uint32 pcm_pll_ctrl4;                       // 1c
+
+    uint32 pcm_pll_stat;                        // 20
+#define  PCM_PLL_LOCK            0x00000001     // Asserted when PLL is locked to programmed frequency
+
+    uint32 pcm_ntr_counter;                     // 24
+
+    uint32 unused[6];
+#define  PCM_MAX_TIMESLOT_REGS   16             // Number of PCM time slot registers in the table.
+                                                // Each register provides the settings for 8 timeslots (4 bits per timeslot)
+    uint32 pcm_slot_alloc_tbl[PCM_MAX_TIMESLOT_REGS];
+#define  PCM_TS_VALID            0x8            // valid marker for TS alloc ram entry
+
+    uint32 pcm_pll_ch2_ctrl;                    // +0xa080
+    uint32 pcm_msif_intf;                       // +0xa084
+} PcmControlRegisters;
+
+#define PCM ((volatile PcmControlRegisters * const) PCM_BASE)
+
+
+typedef struct PcmIudmaRegisters
+{
+    uint16 reserved0;
+    uint16 ctrlConfig;
+#define BCM6328_IUDMA_REGS_CTRLCONFIG_MASTER_EN        0x0001
+#define BCM6328_IUDMA_REGS_CTRLCONFIG_FLOWC_CH1_EN     0x0002
+#define BCM6328_IUDMA_REGS_CTRLCONFIG_FLOWC_CH3_EN     0x0004
+#define BCM6328_IUDMA_REGS_CTRLCONFIG_FLOWC_CH5_EN     0x0008
+#define BCM6328_IUDMA_REGS_CTRLCONFIG_FLOWC_CH7_EN     0x0010
+
+    // Flow control Ch1
+    uint16 reserved1;
+    uint16 ch1_FC_Low_Thr;
+
+    uint16 reserved2;
+    uint16 ch1_FC_High_Thr;
+
+    uint16 reserved3;
+    uint16 ch1_Buff_Alloc;
+
+    // Flow control Ch3
+    uint16 reserved4;
+    uint16 ch3_FC_Low_Thr;
+
+    uint16 reserved5;
+    uint16 ch3_FC_High_Thr;
+
+    uint16 reserved6;
+    uint16 ch3_Buff_Alloc;
+
+    // Flow control Ch5
+    uint16 reserved7;
+    uint16 ch5_FC_Low_Thr;
+
+    uint16 reserved8;
+    uint16 ch5_FC_High_Thr;
+
+    uint16 reserved9;
+    uint16 ch5_Buff_Alloc;
+
+    // Flow control Ch7
+    uint16 reserved10;
+    uint16 ch7_FC_Low_Thr;
+
+    uint16 reserved11;
+    uint16 ch7_FC_High_Thr;
+
+    uint16 reserved12;
+    uint16 ch7_Buff_Alloc;
+
+    // Channel resets
+    uint16 reserved13;
+    uint16 channel_reset;
+    
+    uint16 reserved14;
+    uint16 channel_debug;
+    
+    // Spare register
+    uint32 dummy1;
+    
+    // Interrupt status registers
+    uint16 reserved15;
+    uint16 gbl_int_stat;
+    
+    // Interrupt mask registers
+    uint16 reserved16;
+    uint16 gbl_int_mask;
+} PcmIudmaRegisters;
+
+
+typedef struct PcmIudmaChannelCtrl
+{
+    uint16 reserved1;
+    uint16 config;
+#define BCM6328_IUDMA_CONFIG_ENDMA       0x0001
+#define BCM6328_IUDMA_CONFIG_PKTHALT     0x0002
+#define BCM6328_IUDMA_CONFIG_BURSTHALT   0x0004
+
+    uint16 reserved2;
+    uint16 intStat;
+#define BCM6328_IUDMA_INTSTAT_BDONE   0x0001
+#define BCM6328_IUDMA_INTSTAT_PDONE   0x0002
+#define BCM6328_IUDMA_INTSTAT_NOTVLD  0x0004
+#define BCM6328_IUDMA_INTSTAT_MASK    0x0007
+#define BCM6328_IUDMA_INTSTAT_ALL     BCM6328_IUDMA_INTSTAT_MASK
+
+    uint16 reserved3;
+    uint16 intMask;
+#define BCM6328_IUDMA_INTMASK_BDONE   0x0001
+#define BCM6328_IUDMA_INTMASK_PDONE   0x0002
+#define BCM6328_IUDMA_INTMASK_NOTVLD  0x0004
+
+    uint32 maxBurst;
+#define BCM6328_IUDMA_MAXBURST_SIZE 16 /* 32-bit words */
+
+} PcmIudmaChannelCtrl;
+
+
+typedef struct PcmIudmaStateRam
+{
+   uint32 baseDescPointer;                /* pointer to first buffer descriptor */
+
+   uint32 stateBytesDoneRingOffset;       /* state info: how manu bytes done and the offset of the
+                                             current descritor in process */
+#define BCM6328_IUDMA_STRAM_DESC_RING_OFFSET 0x3fff
+
+
+   uint32 flagsLengthStatus;              /* Length and status field of the current descriptor */
+
+   uint32 currentBufferPointer;           /* pointer to the current descriptor */
+
+} PcmIudmaStateRam;
+
+#define BCM6328_MAX_PCM_DMA_CHANNELS 2
+
+typedef struct PcmIudma
+{
+   PcmIudmaRegisters regs;                                        // 
+   uint32 reserved1[110];                                         //            
+   PcmIudmaChannelCtrl ctrl[BCM6328_MAX_PCM_DMA_CHANNELS];        //
+   uint32 reserved2[120];                                         //
+   PcmIudmaStateRam stram[BCM6328_MAX_PCM_DMA_CHANNELS];          //
+
+} PcmIudma;
+
+#define PCM_IUDMA ((volatile PcmIudma * const) PCM_DMA_BASE)
+
+
+#define IUDMA_MAX_CHANNELS          32
+
+/*
+** DMA Channel Configuration (1 .. 32)
+*/
+typedef struct DmaChannelCfg {
+  uint32        cfg;                    /* (00) assorted configuration */
+#define         DMA_ENABLE      0x00000001  /* set to enable channel */
+#define         DMA_PKT_HALT    0x00000002  /* idle after an EOP flag is detected */
+#define         DMA_BURST_HALT  0x00000004  /* idle after finish current memory burst */
+  uint32        intStat;                /* (04) interrupts control and status */
+  uint32        intMask;                /* (08) interrupts mask */
+#define         DMA_BUFF_DONE   0x00000001  /* buffer done */
+#define         DMA_DONE        0x00000002  /* packet xfer complete */
+#define         DMA_NO_DESC     0x00000004  /* no valid descriptors */
+  uint32        maxBurst;               /* (0C) max burst length permitted */
+#define         DMA_DESCSIZE_SEL 0x00040000  /* DMA Descriptor Size Selection */
+} DmaChannelCfg;
+
+/*
+** DMA State RAM (1 .. 16)
+*/
+typedef struct DmaStateRam {
+  uint32        baseDescPtr;            /* (00) descriptor ring start address */
+  uint32        state_data;             /* (04) state/bytes done/ring offset */
+  uint32        desc_len_status;        /* (08) buffer descriptor status and len */
+  uint32        desc_base_bufptr;       /* (0C) buffer descrpitor current processing */
+} DmaStateRam;
+
+
+/*
+** DMA Registers
+*/
+typedef struct DmaRegs {
+    uint32 controller_cfg;              /* (00) controller configuration */
+#define DMA_MASTER_EN           0x00000001
+#define DMA_FLOWC_CH1_EN        0x00000002
+#define DMA_FLOWC_CH3_EN        0x00000004
+
+    // Flow control Ch1
+    uint32 flowctl_ch1_thresh_lo;           /* 004 */
+    uint32 flowctl_ch1_thresh_hi;           /* 008 */
+    uint32 flowctl_ch1_alloc;               /* 00c */
+#define DMA_BUF_ALLOC_FORCE     0x80000000
+
+    // Flow control Ch3
+    uint32 flowctl_ch3_thresh_lo;           /* 010 */
+    uint32 flowctl_ch3_thresh_hi;           /* 014 */
+    uint32 flowctl_ch3_alloc;               /* 018 */
+
+    // Flow control Ch5
+    uint32 flowctl_ch5_thresh_lo;           /* 01C */
+    uint32 flowctl_ch5_thresh_hi;           /* 020 */
+    uint32 flowctl_ch5_alloc;               /* 024 */
+
+    // Flow control Ch7
+    uint32 flowctl_ch7_thresh_lo;           /* 028 */
+    uint32 flowctl_ch7_thresh_hi;           /* 02C */
+    uint32 flowctl_ch7_alloc;               /* 030 */
+
+    uint32 ctrl_channel_reset;              /* 034 */
+    uint32 ctrl_channel_debug;              /* 038 */
+    uint32 reserved1;                       /* 03C */
+    uint32 ctrl_global_interrupt_status;    /* 040 */
+    uint32 ctrl_global_interrupt_mask;      /* 044 */
+
+    // Unused words
+    uint8 reserved2[0x200-0x48];
+
+    // Per channel registers/state ram
+    DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */
+    union {
+        DmaStateRam     s[IUDMA_MAX_CHANNELS];
+        uint32          u32[4 * IUDMA_MAX_CHANNELS];
+    } stram;                                /* (400-5FF) state ram */
+} DmaRegs;
+
+#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE)
+
+/*
+** DMA Buffer
+*/
+typedef struct DmaDesc {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM    0x8000
+#define          DMA_DESC_MULTICAST 0x4000
+#define          DMA_DESC_BUFLENGTH 0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                /* address of data */
+} DmaDesc;
+
+/*
+** 16 Byte DMA Buffer 
+*/
+typedef struct {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM        0x8000
+#define          DMA_DESC_MULTICAST     0x4000
+#define          DMA_DESC_BUFLENGTH     0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                 /* address of data */
+  uint32        control;
+#define         GEM_ID_MASK             0x001F
+  uint32        reserved;
+} DmaDesc16;
+
+
+/*
+** USB 2.0 Device Registers
+*/
+typedef struct UsbRegisters {
+#define USBD_CONTROL_APP_DONECSR                0x0001
+#define USBD_CONTROL_APP_RESUME                 0x0002
+#define USBD_CONTROL_APP_RXFIFIO_INIT           0x0040
+#define USBD_CONTROL_APP_TXFIFIO_INIT           0x0080
+#define USBD_CONTROL_APP_FIFO_SEL_SHIFT         0x8
+#define USBD_CONTROL_APP_FIFO_INIT_SEL(x)       (((x)&0x0f)<<USBD_CONTROL_APP_FIFO_SEL_SHIFT)
+#define USBD_CONTROL_APP_AUTO_CSRS              0x2000
+#define USBD_CONTROL_APP_AUTO_INS_ZERO_LEN_PKT  0x4000
+#define EN_TXZLENINS                            (1<<14)
+#define EN_RXZSCFG                              (1<<12)
+#define APPSETUPERRLOCK                         (1<<5)
+    uint32 usbd_control ;
+#define USBD_STRAPS_APP_SELF_PWR                0x0400
+#define USBD_STRAPS_APP_DEV_DISCON              0x0200
+#define USBD_STRAPS_APP_CSRPRG_SUP              0x0100
+#define USBD_STRAPS_APP_RAM_IF                  0x0080
+#define USBD_STRAPS_APP_DEV_RMTWKUP             0x0040
+#define USBD_STRAPS_APP_PHYIF_8BIT              0x0004
+#define USBD_STRAPS_FULL_SPEED                  0x0003
+#define USBD_STRAPS_LOW_SPEED                   0x0002
+#define USBD_STRAPS_HIGH_SPEED                  0x0000
+#define APPUTMIDIR(x)                           ((x&1)<<3)
+#define UNIDIR                                  0
+    uint32 usbd_straps;
+#define USB_ENDPOINT_0                          0x01
+    uint32 usbd_stall;
+#define USBD_ENUM_SPEED_SHIFT                   12
+#define USBD_ENUM_SPEED                         0x3000
+#define UDC20_ALTINTF(x)                        ((x>>8)&0xf)
+#define UDC20_INTF(x)                           ((x>>4)&0xf)
+#define UDC20_CFG(x)                            ((x>>0)&0xf)
+    uint32 usbd_status;
+#define USBD_LINK                   (0x1<<10)
+#define USBD_SET_CSRS                           0x40
+#define USBD_SUSPEND                            0x20
+#define USBD_EARLY_SUSPEND                      0x10
+#define USBD_SOF                                0x08
+#define USBD_ENUMON                             0x04
+#define USBD_SETUP                              0x02
+#define USBD_USBRESET                           0x01
+    uint32 usbd_events;
+    uint32 usbd_events_irq;
+#define UPPER(x)                                (16+x)
+#define ENABLE(x)                               (1<<x)
+#define SWP_TXBSY                               (15)
+#define SWP_RXBSY                               (14)
+#define SETUP_ERR                               (13)
+#define APPUDCSTALLCHG                          (12)
+#define BUS_ERR                                 (11)
+#define USB_LINK                                (10)
+#define HST_SETCFG                              (9)
+#define HST_SETINTF                             (8)
+#define ERRATIC_ERR                             (7)
+#define SET_CSRS                                (6)
+#define SUSPEND                                 (5)
+#define ERLY_SUSPEND                            (4)
+#define SOF                                     (3)
+#define ENUM_ON                                 (2)
+#define SETUP                                   (1)
+#define USB_RESET                               (0)
+#define RISING(x)                               (0x0<<2*x)
+#define FALLING(x)                              (0x1<<2*x)
+#define USBD_IRQCFG_ENUM_ON_FALLING_EDGE        0x00000010
+    uint32 usbd_irqcfg_hi ;
+    uint32 usbd_irqcfg_lo ;
+#define USBD_USB_RESET_IRQ                      0x00000001
+#define USBD_USB_SETUP_IRQ                      0x00000002 // non-standard setup cmd rcvd
+#define USBD_USB_ENUM_ON_IRQ                    0x00000004
+#define USBD_USB_SOF_IRQ                        0x00000008
+#define USBD_USB_EARLY_SUSPEND_IRQ              0x00000010
+#define USBD_USB_SUSPEND_IRQ                    0x00000020 // non-standard setup cmd rcvd
+#define USBD_USB_SET_CSRS_IRQ                   0x00000040
+#define USBD_USB_ERRATIC_ERR_IRQ                0x00000080
+#define USBD_USB_SETCFG_IRQ                     0x00000200
+#define USBD_USB_LINK_IRQ                       0x00000400
+    uint32 usbd_events_irq_mask;
+    uint32 usbd_swcfg;
+    uint32 usbd_swtxctl;
+    uint32 usbd_swrxctl;
+    uint32 usbd_txfifo_rwptr;
+    uint32 usbd_rxfifo_rwptr;
+    uint32 usbd_txfifo_st_rwptr;
+    uint32 usbd_rxfifo_st_rwptr;
+    uint32 usbd_txfifo_config ;
+    uint32 usbd_rxfifo_config ;
+    uint32 usbd_txfifo_epsize ;
+    uint32 usbd_rxfifo_epsize ;
+#define USBD_EPNUM_CTRL                         0x0
+#define USBD_EPNUM_ISO                          0x1
+#define USBD_EPNUM_BULK                         0x2
+#define USBD_EPNUM_IRQ                          0x3
+#define USBD_EPNUM_EPTYPE(x)                    (((x)&0x3)<<8)
+#define USBD_EPNUM_EPDMACHMAP(x)                (((x)&0xf)<<0)
+    uint32 usbd_epnum_typemap ;
+    uint32 usbd_reserved [0xB] ;
+    uint32 usbd_csr_setupaddr ;
+#define USBD_EPNUM_MASK                         0xf
+#define USBD_EPNUM(x)                           ((x&USBD_EPNUM_MASK)<<0)
+#define USBD_EPDIR_IN                           (1<<4)
+#define USBD_EPDIR_OUT                          (0<<4)
+#define USBD_EPTYP_CTRL                         (USBD_EPNUM_CTRL<<5)
+#define USBD_EPTYP_ISO                          (USBD_EPNUM_ISO<<5)
+#define USBD_EPTYP_BULK                         (USBD_EPNUM_BULK<<5)
+#define USBD_EPTYP_IRQ                          (USBD_EPNUM_IRQ<<5)
+#define USBD_EPCFG_MASK                         0xf
+#define USBD_EPCFG(x)                           ((x&USBD_EPCFG_MASK)<<7)
+#define USBD_EPINTF_MASK                        0xf
+#define USBD_EPINTF(x)                          ((x&USBD_EPINTF_MASK)<<11)
+#define USBD_EPAINTF_MASK                       0xf
+#define USBD_EPAINTF(x)                         ((x&USBD_EPAINTF_MASK)<<15)
+#define USBD_EPMAXPKT_MSK                       0x7ff
+#define USBD_EPMAXPKT(x)                        ((x&USBD_EPMAXPKT_MSK)<<19)
+#define USBD_EPISOPID_MASK                      0x3
+#define USBD_EPISOPID(x)                        ((x&USBD_ISOPID_MASK)<<30)
+    uint32 usbd_csr_ep [5] ;
+} UsbRegisters;
+
+#define USB ((volatile UsbRegisters * const) USB_CTL_BASE)
+
+typedef struct USBControl {
+    uint32 BrtControl1;
+    uint32 BrtControl2;
+    uint32 BrtStatus1;
+    uint32 BrtStatus2;
+    uint32 UTMIControl1;
+#define USB_DEVICE_MODE_SEL     (1<<0)
+    uint32 TestPortControl;
+    uint32 PllControl1;
+    uint32 SwapControl;
+#define USB_DEVICE_SEL          (1<<6)
+#define EHCI_LOGICAL_ADDRESS_EN (1<<5)
+#define EHCI_ENDIAN_SWAP        (1<<4)
+#define EHCI_DATA_SWAP          (1<<3)
+#define OHCI_LOGICAL_ADDRESS_EN (1<<2)
+#define OHCI_ENDIAN_SWAP        (1<<1)
+#define OHCI_DATA_SWAP          (1<<0)
+    uint32 GenericControl;
+#define PLL_SUSPEND_EN          (1<<1)
+    uint32 FrameAdjustValue;
+    uint32 Setup;
+#define USBH_IOC                (1<<4)
+    uint32 MDIO;
+    uint32 MDIO32;
+    uint32 USBSimControl;
+} USBControl;
+
+#define USBH ((volatile USBControl * const) USBH_CFG_BASE)
+
+typedef struct EthSwRegs{
+    byte port_traffic_ctrl[9]; /* 0x00 - 0x08 */
+    byte reserved1[2]; /* 0x09 - 0x0a */
+    byte switch_mode; /* 0x0b */
+    unsigned short pause_quanta; /*0x0c */
+    byte imp_port_state; /*0x0e */
+    byte led_refresh; /* 0x0f */
+    unsigned short led_function[2]; /* 0x10 */
+    unsigned short led_function_map; /* 0x14 */
+    unsigned short led_enable_map; /* 0x16 */
+    unsigned short led_mode_map0; /* 0x18 */
+    unsigned short led_function_map1; /* 0x1a */
+    byte reserved2[5]; /* 0x1b - 0x20 */
+    byte port_forward_ctrl; /* 0x21 */ 
+    byte reserved3[2]; /* 0x22 - 0x23 */
+    unsigned short protected_port_selection; /* 0x24 */
+    unsigned short wan_port_select; /* 0x26 */
+    unsigned int pause_capability; /* 0x28 */
+    byte reserved4[3]; /* 0x2c - 0x2e */
+    byte reserved_multicast_control; /* 0x2f */
+    byte reserved5; /* 0x30 */
+    byte txq_flush_mode_control; /* 0x31 */
+    unsigned short ulf_forward_map; /* 0x32 */
+    unsigned short mlf_forward_map; /* 0x34 */
+    unsigned short mlf_impc_forward_map; /* 0x36 */
+    unsigned short pause_pass_through_for_rx; /* 0x38 */
+    unsigned short pause_pass_through_for_tx; /* 0x3a */
+    unsigned short disable_learning; /* 0x3c */
+    byte reserved6[26]; /* 0x3e - 0x57 */
+    byte port_state_override[8]; /* 0x58 - 0x5f */
+    byte reserved7[4]; /* 0x60 - 0x63 */
+    byte imp_rgmii_ctrl_p4; /* 0x64 */
+    byte imp_rgmii_ctrl_p5; /* 0x65 */
+    byte reserved8[6]; /* 0x66 - 0x6b */
+    byte rgmii_timing_delay_p4; /* 0x6c */
+    byte gmii_timing_delay_p5; /* 0x6d */
+    byte reserved9[11]; /* 0x6e - 0x78 */
+    byte software_reset; /* 0x79 */
+    byte reserved13[6]; /* 0x7a - 0x7f */
+    byte pause_frame_detection; /* 0x80 */
+    byte reserved10[7]; /* 0x81 - 0x87 */
+    byte fast_aging_ctrl; /* 0x88 */
+    byte fast_aging_port; /* 0x89 */
+    byte fast_aging_vid; /* 0x8a */
+    byte reserved11[21]; /* 0x8b - 0x9f */
+    unsigned int swpkt_ctrl_sar; /*0xa0 */
+    unsigned int swpkt_ctrl_usb; /*0xa4 */
+    unsigned int iudma_ctrl; /*0xa8 */
+    unsigned int rxfilt_ctrl; /*0xac */
+    unsigned int mdio_ctrl; /*0xb0 */
+    unsigned int mdio_data; /*0xb4 */
+    byte reserved12[42]; /* 0xb6 - 0xdf */
+    unsigned int sw_mem_test; /*0xe0 */
+} EthSwRegs;
+
+#define ETHSWREG ((volatile EthSwRegs * const) SWITCH_BASE)
+
+typedef struct EthSwMIBRegs {
+    unsigned int TxOctetsLo;
+    unsigned int TxOctetsHi;
+    unsigned int TxDropPkts;
+    unsigned int TxQoSPkts;
+    unsigned int TxBroadcastPkts;
+    unsigned int TxMulticastPkts;
+    unsigned int TxUnicastPkts;
+    unsigned int TxCol;
+    unsigned int TxSingleCol;
+    unsigned int TxMultipleCol;
+    unsigned int TxDeferredTx;
+    unsigned int TxLateCol;
+    unsigned int TxExcessiveCol;
+    unsigned int TxFrameInDisc;
+    unsigned int TxPausePkts;
+    unsigned int TxQoSOctetsLo;
+    unsigned int TxQoSOctetsHi;
+    unsigned int RxOctetsLo;
+    unsigned int RxOctetsHi;
+    unsigned int RxUndersizePkts;
+    unsigned int RxPausePkts;
+    unsigned int Pkts64Octets;
+    unsigned int Pkts65to127Octets;
+    unsigned int Pkts128to255Octets;
+    unsigned int Pkts256to511Octets;
+    unsigned int Pkts512to1023Octets;
+    unsigned int Pkts1024to1522Octets;
+    unsigned int RxOversizePkts;
+    unsigned int RxJabbers;
+    unsigned int RxAlignErrs;
+    unsigned int RxFCSErrs;
+    unsigned int RxGoodOctetsLo;
+    unsigned int RxGoodOctetsHi;
+    unsigned int RxDropPkts;
+    unsigned int RxUnicastPkts;
+    unsigned int RxMulticastPkts;
+    unsigned int RxBroadcastPkts;
+    unsigned int RxSAChanges;
+    unsigned int RxFragments;
+    unsigned int RxExcessSizeDisc;
+    unsigned int RxSymbolError;
+    unsigned int RxQoSPkts;
+    unsigned int RxQoSOctetsLo;
+    unsigned int RxQoSOctetsHi;
+    unsigned int Pkts1523to2047;
+    unsigned int Pkts2048to4095;
+    unsigned int Pkts4096to8191;
+    unsigned int Pkts8192to9728;
+} EthSwMIBRegs;
+
+#define ETHSWMIBREG ((volatile EthSwMIBRegs * const) (SWITCH_BASE + 0x2000))
+
+/*
+** NAND Interrupt Controller Registers
+*/
+typedef struct NandIntrCtrlRegs {
+    uint32 NandInterrupt;
+#define NINT_ENABLE_MASK    0xffff0000
+#define NINT_STS_MASK       0x00000fff
+#define NINT_ECC_ERROR_CORR 0x00000080
+#define NINT_ECC_ERROR_UNC  0x00000040
+#define NINT_DEV_RBPIN      0x00000020
+#define NINT_CTRL_READY     0x00000010
+#define NINT_PAGE_PGM       0x00000008
+#define NINT_COPY_BACK      0x00000004
+#define NINT_BLOCK_ERASE    0x00000002
+#define NINT_NP_READ        0x00000001
+
+    uint32 NandBaseAddr0;   /* Default address when booting from NAND flash */
+    uint32 reserved;
+    uint32 NandBaseAddr1;   /* Secondary base address for NAND flash */
+} NandIntrCtrlRegs;
+
+#define NAND_INTR ((volatile NandIntrCtrlRegs * const) NAND_INTR_BASE)
+
+/*
+** NAND Controller Registers
+*/
+typedef struct NandCtrlRegs {
+    uint32 NandRevision;            /* NAND Revision */
+    uint32 NandCmdStart;            /* Nand Flash Command Start */
+#define NCMD_MASK           0x0f000000
+#define NCMD_BLK_LOCK_STS   0x0d000000
+#define NCMD_BLK_UNLOCK     0x0c000000
+#define NCMD_BLK_LOCK_DOWN  0x0b000000
+#define NCMD_BLK_LOCK       0x0a000000
+#define NCMD_FLASH_RESET    0x09000000
+#define NCMD_BLOCK_ERASE    0x08000000
+#define NCMD_DEV_ID_READ    0x07000000
+#define NCMD_COPY_BACK      0x06000000
+#define NCMD_PROGRAM_SPARE  0x05000000
+#define NCMD_PROGRAM_PAGE   0x04000000
+#define NCMD_STS_READ       0x03000000
+#define NCMD_SPARE_READ     0x02000000
+#define NCMD_PAGE_READ      0x01000000
+
+    uint32 NandCmdExtAddr;          /* Nand Flash Command Extended Address */
+    uint32 NandCmdAddr;             /* Nand Flash Command Address */
+    uint32 NandCmdEndAddr;          /* Nand Flash Command End Address */
+    uint32 NandNandBootConfig;      /* Nand Flash Boot Config */
+#define NBC_CS_LOCK         0x80000000
+#define NBC_AUTO_DEV_ID_CFG 0x40000000
+#define NBC_WR_PROT_BLK0    0x10000000
+
+    uint32 NandCsNandXor;           /* Nand Flash EBI CS Address XOR with */
+                                    /*   1FC0 Control */
+    uint32 NandReserved;
+    uint32 NandSpareAreaReadOfs0;   /* Nand Flash Spare Area Read Bytes 0-3 */
+    uint32 NandSpareAreaReadOfs4;   /* Nand Flash Spare Area Read Bytes 4-7 */
+    uint32 NandSpareAreaReadOfs8;   /* Nand Flash Spare Area Read Bytes 8-11 */
+    uint32 NandSpareAreaReadOfsC;   /* Nand Flash Spare Area Read Bytes 12-15*/
+    uint32 NandSpareAreaWriteOfs0;  /* Nand Flash Spare Area Write Bytes 0-3 */
+    uint32 NandSpareAreaWriteOfs4;  /* Nand Flash Spare Area Write Bytes 4-7 */
+    uint32 NandSpareAreaWriteOfs8;  /* Nand Flash Spare Area Write Bytes 8-11*/
+    uint32 NandSpareAreaWriteOfsC;  /* Nand Flash Spare Area Write Bytes12-15*/
+    uint32 NandAccControl;          /* Nand Flash Access Control */
+    uint32 NandConfig;              /* Nand Flash Config */
+#define NC_CONFIG_LOCK      0x80000000
+#define NC_PG_SIZE_MASK     0x00300000
+#define NC_PG_SIZE_2K       0x00100000
+#define NC_PG_SIZE_512B     0x00000000
+#define NC_BLK_SIZE_MASK    0x30000000
+#define NC_BLK_SIZE_512K    0x30000000
+#define NC_BLK_SIZE_128K    0x10000000
+#define NC_BLK_SIZE_16K     0x00000000
+#define NC_BLK_SIZE_8K      0x20000000
+#define NC_DEV_SIZE_MASK    0x0f000000
+#define NC_DEV_SIZE_SHIFT   24
+#define NC_DEV_WIDTH_MASK   0x00800000
+#define NC_DEV_WIDTH_16     0x00800000
+#define NC_DEV_WIDTH_8      0x00000000
+#define NC_FUL_ADDR_MASK    0x00070000
+#define NC_FUL_ADDR_SHIFT   16
+#define NC_BLK_ADDR_MASK    0x00000700
+#define NC_BLK_ADDR_SHIFT   8
+
+    uint32 NandTiming1;             /* Nand Flash Timing Parameters 1 */
+    uint32 NandTiming2;             /* Nand Flash Timing Parameters 2 */
+    uint32 NandSemaphore;           /* Semaphore */
+    uint32 NandFlashDeviceId;       /* Nand Flash Device ID */
+    uint32 NandBlockLockStatus;     /* Nand Flash Block Lock Status */
+    uint32 NandIntfcStatus;         /* Nand Flash Interface Status */
+#define NIS_CTLR_READY      0x80000000
+#define NIS_FLASH_READY     0x40000000
+#define NIS_CACHE_VALID     0x20000000
+#define NIS_SPARE_VALID     0x10000000
+#define NIS_FLASH_STS_MASK  0x000000ff
+#define NIS_WRITE_PROTECT   0x00000080
+#define NIS_DEV_READY       0x00000040
+#define NIS_PGM_ERASE_ERROR 0x00000001
+
+    uint32 NandEccCorrExtAddr;      /* ECC Correctable Error Extended Address*/
+    uint32 NandEccCorrAddr;         /* ECC Correctable Error Address */
+    uint32 NandEccUncExtAddr;       /* ECC Uncorrectable Error Extended Addr */
+    uint32 NandEccUncAddr;          /* ECC Uncorrectable Error Address */
+    uint32 NandFlashReadExtAddr;    /* Flash Read Data Extended Address */
+    uint32 NandFlashReadAddr;       /* Flash Read Data Address */
+    uint32 NandProgramPageExtAddr;  /* Page Program Extended Address */
+    uint32 NandProgramPageAddr;     /* Page Program Address */
+    uint32 NandCopyBackExtAddr;     /* Copy Back Extended Address */
+    uint32 NandCopyBackAddr;        /* Copy Back Address */
+    uint32 NandBlockEraseExtAddr;   /* Block Erase Extended Address */
+    uint32 NandBlockEraseAddr;      /* Block Erase Address */
+    uint32 NandInvReadExtAddr;      /* Flash Invalid Data Extended Address */
+    uint32 NandInvReadAddr;         /* Flash Invalid Data Address */
+    uint32 NandBlkWrProtect;        /* Block Write Protect Enable and Size */
+                                    /*   for EBI_CS0b */
+} NandCtrlRegs;
+
+#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE)
+
+#define NAND_CACHE ((volatile uint8 * const) NAND_CACHE_BASE)
+
+/*
+** PCI-E
+*/
+typedef struct PcieRegs{
+  uint32 devVenID;
+  uint16 command;
+  uint16 status;
+  uint32 revIdClassCode;
+  uint32 headerTypeLatCacheLineSize;
+  uint32 bar1;
+  uint32 bar2;
+  uint32 priSecBusNo;
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK              0x00ff0000
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT             16  
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK              0x0000ff00
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT             8
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK              0x000000ff
+
+  uint32 ioBaseLimit;
+  uint32 secStatus;
+  uint32 rcMemBaseLimit;
+  uint32 rcPrefBaseLimit;
+  uint32 rcPrefBaseHi;
+  uint32 rcPrefLimitHi;
+  uint32 rcIoBaseLimit;
+  uint32 capPointer;
+  uint32 expRomBase;
+  uint32 brdigeCtrlIntPinIntLine;
+  uint32 bridgeCtrl;
+  uint32 unused1[27];
+
+  /* PcieExpressCtrlRegs */
+  uint16 pciExpressCap;
+  uint16 pcieCapabilitiy;
+  uint32 deviceCapability;
+  uint16 deviceControl;
+  uint16 deviceStatus;
+  uint32 linkCapability;
+  uint16 linkControl;
+  uint16 linkStatus;
+  uint32 slotCapability;
+  uint16 slotControl;
+  uint16 slotStatus;
+  uint16 rootControl;
+  uint16 rootCap;
+  uint32 rootStatus;
+  uint32 deviceCapability2;
+  uint16 deviceControl2;
+  uint16 deviceStatus2;
+  uint32 linkCapability2;
+  uint16 linkControl2;
+  uint16 linkStatus2;
+  uint32 slotCapability2;
+  uint16 slotControl2;
+  uint16 slotStatus2;
+  uint32 unused2[6];
+
+  /* PcieErrorRegs */
+  uint16 advErrCapId;
+  uint16 advErrCapOff;
+  uint32 ucErrStatus;
+  uint32 ucorrErrMask;
+  uint32 ucorrErrSevr;
+  uint32 corrErrStatus;
+  uint32 corrErrMask;
+  uint32 advErrCapControl;
+  uint32 headerLog1;
+  uint32 headerLog2;
+  uint32 headerLog3;
+  uint32 headerLog4;
+  uint32 rootErrorCommand;
+  uint32 rootErrorStatus;
+  uint32 rcCorrId;
+  uint32 rcFatalNonfatalId;
+  uint32 unused3[10];
+
+  /* PcieVcRegs */
+  uint16 vcCapId;
+  uint16 vcCapOffset;
+  uint32 prtVcCapability;
+  uint32 portVcCapability2;
+  uint16 portVcControl;
+  uint16 portVcCtatus;
+  uint32 portArbStatus;
+  uint32 vcRsrcControl;
+  uint32 vcRsrcStatus;
+  uint32 unused4[1];
+
+  /* PcieVendor */
+  uint32 vendorCapability;
+  uint32 vendorSpecificHdr;
+} PcieRegs;
+
+typedef struct PcieBlk404Regs{
+  uint32 unused;          /* 0x404 */
+  uint32 config2;         /* 0x408 */
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK         0x0000000f
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE           0  
+  uint32 config3;         /* 0x40c */
+  uint32 pmDataA;         /* 0x410 */
+  uint32 pmDataB;         /* 0x414 */
+} PcieBlk404Regs;
+
+typedef struct PcieBlk428Regs{
+  uint32 vpdIntf;        /* 0x428 */
+  uint16 unused_g;       /* 0x42c */
+  uint16 vpdAddrFlag;    /* 0x42e */
+  uint32 vpdData;        /* 0x430 */
+  uint32 idVal1;         /* 0x434 */
+  uint32 idVal2;         /* 0x438 */
+  uint32 idVal3;         /* 0x43c */
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK                    0xff000000
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT                   24
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK                     0x00ffffff
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT                    16
+#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT                 8
+
+  uint32 idVal4;
+  uint32 idVal5;
+  uint32 unused_h;
+  uint32 idVal6;
+  uint32 msiData;
+  uint32 msiAddr_h;
+  uint32 msiAddr_l;
+  uint32 msiMask;
+  uint32 msiPend;
+  uint32 pmData_c;
+  uint32 msixControl;
+  uint32 msixTblOffBir;
+  uint32 msixPbaOffBit;
+  uint32 unused_k;
+  uint32 pcieCapability;
+  uint32 deviceCapability;
+  uint32 unused_l;
+  uint32 linkCapability;
+  uint32 bar2Config;
+  uint32 pcieDeviceCapability2;
+  uint32 pcieLinkCapability2;
+  uint32 pcieLinkControl;
+  uint32 pcieLinkCapabilityRc;
+  uint32 bar3Config;
+  uint32 rootCap;
+  uint32 devSerNumCapId;
+  uint32 lowerSerNum;
+  uint32 upperSerNum;
+  uint32 advErrCap;
+  uint32 pwrBdgtData0;
+  uint32 pwrBdgtData1;
+  uint32 pwrBdgtData2;
+  uint32 pwdBdgtData3;
+  uint32 pwrBdgtData4;
+  uint32 pwrBdgtData5;
+  uint32 pwrBdgtData6;
+  uint32 pwrBdgtData7;
+  uint32 pwrBdgtCapability;
+  uint32 vsecHdr;
+  uint32 rcUserMemLo1;
+  uint32 rcUserMemHi1;
+  uint32 rcUserMemLo2;
+  uint32 rcUserMemHi2;
+}PcieBlk428Regs;
+
+typedef struct PcieBlk800Regs{
+#define NUM_PCIE_BLK_800_CTRL_REGS  6
+  uint32 tlControl[NUM_PCIE_BLK_800_CTRL_REGS];
+  uint32 tlCtlStat0;
+  uint32 pmStatus0;
+  uint32 pmStatus1;
+
+#define NUM_PCIE_BLK_800_TAGS       32
+  uint32 tlStatus[NUM_PCIE_BLK_800_TAGS];
+  uint32 tlHdrFcStatus;
+  uint32 tlDataFcStatus;
+  uint32 tlHdrFcconStatus;
+  uint32 tlDataFcconStatus;
+  uint32 tlTargetCreditStatus;
+  uint32 tlCreditAllocStatus;
+  uint32 tlSmlogicStatus;
+} PcieBlk800Regs;
+
+
+typedef struct PcieBlk1000Regs{
+#define NUM_PCIE_BLK_1000_PDL_CTRL_REGS  16
+  uint32 pdlControl[NUM_PCIE_BLK_1000_PDL_CTRL_REGS];
+  uint32 dlattnVec;
+  uint32 dlAttnMask;
+  uint32 dlStatus;        /* 0x1048 */
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK                   0x00002000
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT                  13   
+  uint32 dlTxChecksum;
+  uint32 dlForcedUpdateGen1;
+  uint32 mdioAddr;
+  uint32 mdioWrData;
+  uint32 mdioRdData;
+  uint32 dlRxPFcCl;
+  uint32 dlRxCFcCl;
+  uint32 dlRxAckNack;
+  uint32 dlTxRxSeqnb;
+  uint32 dlTxPFcAl;
+  uint32 dlTxNpFcAl;
+  uint32 regDlSpare;
+  uint32 dlRegSpare;
+  uint32 dlTxRxSeq;
+  uint32 dlRxNpFcCl;
+}PcieBlk1000Regs;
+
+typedef struct PcieBlk1800Regs{
+#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS         5
+  uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS];
+#define REG_POWERDOWN_P1PLL_ENA                      (1<<12)
+  uint32 phyErrorAttnVec;
+  uint32 phyErrorAttnMask;
+  uint32 phyReceivedMcpErrors;
+  uint32 phyTransmittedMcpErrors;
+  uint32 phyGenDebug;
+  uint32 phyRecoveryHist;
+#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS   3
+  uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS];
+#define NUM_PCIE_BLK_1800_PHY_DBG_REGS          11
+  uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS];
+} PcieBlk1800Regs;
+
+typedef struct PcieBridgeRegs{
+   uint32 bar1Remap;       /* 0x0818*/
+#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK                    0xffff0000
+#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK_SHIFT              16
+#define PCIE_BRIDGE_BAR1_REMAP_remap_enable                 (1<<1)
+#define PCIE_BRIDGE_BAR1_REMAP_swap_enable                  1
+   
+   uint32 bar2Remap;       /* 0x081c*/
+#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK                    0xffff0000
+#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK_SHIFT              16
+#define PCIE_BRIDGE_BAR2_REMAP_remap_enable                 (1<<1)
+#define PCIE_BRIDGE_BAR2_REMAP_swap_enable                  1
+   
+   uint32 bridgeOptReg1;   /* 0x0820*/
+#define PCIE_BRIDGE_OPT_REG1_en_l1_int_status_mask_polarity  (1<<12)
+#define PCIE_BRIDGE_OPT_REG1_en_pcie_bridge_hole_detection   (1<<11)
+#define PCIE_BRIDGE_OPT_REG1_en_rd_reply_be_fix              (1<<9)
+#define PCIE_BRIDGE_OPT_REG1_enable_rd_be_opt                (1<<7)
+   
+   uint32 bridgeOptReg2;    /* 0x0824*/
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK    0xe0000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT   29
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK     0x1f000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT    24
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK     0x00ff0000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT    16
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK     0x00000080
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT    7
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK     0x00000040
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT    6
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK       0x00000020
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT      5
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK    0x00000010
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT   4
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK   0x00000004
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT  2
+#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK         0x0000ff0b
+
+   uint32 Ubus2PcieBar0BaseMask; /* 0x0828 */
+#define PCIE_BRIDGE_BAR0_BASE_base_MASK                     0xfff00000
+#define PCIE_BRIDGE_BAR0_BASE_base_MASK_SHIFT               20
+#define PCIE_BRIDGE_BAR0_BASE_mask_MASK                     0x0000fff0
+#define PCIE_BRIDGE_BAR0_BASE_mask_MASK_SHIFT               4
+#define PCIE_BRIDGE_BAR0_BASE_swap_enable                   (1<<1)
+#define PCIE_BRIDGE_BAR0_BASE_remap_enable                  1
+
+   uint32 Ubus2PcieBar0RemapAdd; /* 0x082c */   
+#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_MASK               0xfff00000
+#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_SHIFT              20
+   
+   uint32 Ubus2PcieBar1BaseMask; /* 0x0830 */
+#define PCIE_BRIDGE_BAR1_BASE_base_MASK                     0xfff00000
+#define PCIE_BRIDGE_BAR1_BASE_base_MASK_SHIFT               20
+#define PCIE_BRIDGE_BAR1_BASE_mask_MASK                     0x0000fff0
+#define PCIE_BRIDGE_BAR1_BASE_mask_MASK_SHIFT               4
+#define PCIE_BRIDGE_BAR1_BASE_swap_enable                   (1<<1)
+#define PCIE_BRIDGE_BAR1_BASE_remap_enable                  1   
+   
+   uint32 Ubus2PcieBar1RemapAdd; /* 0x0834 */
+#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_MASK               0xfff00000
+#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_SHIFT              20
+   
+   uint32 bridgeErrStatus;       /* 0x0838 */
+   uint32 bridgeErrMask;         /* 0x083c */   
+   uint32 coreErrStatus2;        /* 0x0840 */
+   uint32 coreErrMask2;          /* 0x0844 */
+   uint32 coreErrStatus1;        /* 0x0848 */
+   uint32 coreErrMask1;          /* 0x084c */
+   uint32 rcInterruptStatus;     /* 0x0850 */
+   uint32 rcInterruptMask;       /* 0x0854 */
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_a_MASK   (1<<0)
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_b_MASK   (1<<1)   
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_c_MASK   (1<<2)   
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_d_MASK   (1<<3)   
+      
+}PcieBridgeRegs;
+
+#define PCIEH_DEV_OFFSET              0x8000
+#define PCIEH                         ((volatile uint32 * const) PCIE_BASE)
+#define PCIEH_REGS                    ((volatile PcieRegs * const) PCIE_BASE)
+
+#define PCIEH_BLK_404_REGS            ((volatile PcieBlk404Regs * const) \
+                                        (PCIE_BASE+0x404))
+#define PCIEH_BLK_428_REGS            ((volatile PcieBlk428Regs * const) \
+                                        (PCIE_BASE+0x428))
+#define PCIEH_BLK_800_REGS            ((volatile PcieBlk800Regs * const) \
+                                        (PCIE_BASE+0x800))
+#define PCIEH_BLK_1000_REGS           ((volatile PcieBlk1000Regs * const) \
+                                        (PCIE_BASE+0x1000))
+#define PCIEH_BLK_1800_REGS           ((volatile PcieBlk1800Regs * const) \
+                                        (PCIE_BASE+0x1800))
+#define PCIEH_BRIDGE_REGS             ((volatile PcieBridgeRegs * const)  \
+                                        (PCIE_BASE+0x2818))
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/shared/broadcom/include/bcm963xx/6362_common.h b/shared/broadcom/include/bcm963xx/6362_common.h
new file mode 100755
index 0000000..843355a
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/6362_common.h
@@ -0,0 +1,326 @@
+/*
+<:copyright-broadcom 
+ 
+ Copyright (c) 2007 Broadcom Corporation 
+ All Rights Reserved 
+ No portions of this material may be reproduced in any form without the 
+ written permission of: 
+          Broadcom Corporation 
+          16215 Alton Parkway 
+          Irvine, California 92619 
+ All information contained in this document is Broadcom Corporation 
+ company private, proprietary, and trade secret. 
+ 
+:>
+*/
+/***********************************************************************/
+/*                                                                     */
+/*   MODULE:  6362_common.h                                             */
+/*   DATE:    02/01/08                                                 */
+/*   PURPOSE: Define addresses of major hardware components of         */
+/*            BCM6362                                                  */
+/*                                                                     */
+/***********************************************************************/
+#ifndef __BCM6362_MAP_COMMON_H
+#define __BCM6362_MAP_COMMON_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PERF_BASE            0xb0000000  /* chip control registers */
+#define TIMR_BASE            0xb0000040  /* timer registers */
+#define NAND_INTR_BASE       0xb0000070  /* nand interrupt control registers */
+#define GPIO_BASE            0xb0000080  /* gpio registers */
+#define UART_BASE            0xb0000100  /* uart registers */
+#define UART1_BASE           0xb0000120  /* uart registers */
+#define NAND_REG_BASE        0xb0000200
+#define OTP_BASE             0xb0000400
+#define UBUS_STAT_BASE       0xb0000500
+#define NAND_CACHE_BASE      0xb0000600
+#define SPI_BASE             0xb0000800  /* SPI master controller registers */
+#define HSSPIM_BASE          0xb0001000  /* High-Speed SPI registers */
+#define ADSL_CTRL_BASE       0xb0001800
+#define MISC_BASE            0xb0001800  /* Miscellaneous Registers */
+#define LED_BASE             0xb0001900  /* LED control registers */
+#define USB_CTL_BASE         0xb0002400  /* USB 2.0 device control registers */
+#define USB_EHCI_BASE        0x10002500  /* USB host registers */
+#define USB_OHCI_BASE        0x10002600  /* USB host registers */
+#define USBH_CFG_BASE        0xb0002700
+#define IPSEC_BASE           0xb0002800
+#define DDR_BASE             0xb0003000  /* Memory control registers */
+#define WLAN_CHIPC_BASE      0x10004000  /* WLAN ChipCommon registers, use 1xxx for ioremap */
+#define WLAN_MAC_BASE        0x10005000  /* WLAN d11mac registers */
+#define WLAN_SHIM_BASE       0xb0007000  /* shim interface to WLAN */
+#define PCM_BASE             0xb000a000
+#define PCM_DMA_BASE         0xb000a800  /* PCM UIDMA register base */
+#define SAR_DMA_BASE         0xb000b800  /* ATM SAR DMA control registers */
+#define USB_DMA_BASE         0xb000c000  /* USB 2.0 device DMA regiseters */
+#define IPSEC_DMA_BASE       0xb000d000
+#define SWITCH_DMA_BASE      0xb000d800
+#define SWITCH_BASE          0xb0e00000
+#define PCIE_BASE            0xb0e40000
+#define DECT_SHIM_CTRL_BASE         0xb000b000
+#define DECT_SHIM_DMA_CTRL_BASE     0xb000b050
+#define DECT_SHIM_TEST_BASE         0xb000b0f0
+#define DECT_APB_REG_BASE           0xb000e000
+#define DECT_AHB_SHARED_RAM_BASE    0xb0e50000
+#define DECT_AHB_REG_BASE           0xb0e57f80
+
+
+/*
+#####################################################################
+# System PLL Control Register
+#####################################################################
+*/
+
+/*
+#####################################################################
+# GPIO Control Registers
+#####################################################################
+*/
+/*
+#####################################################################
+# Miscellaneous Registers
+#####################################################################
+*/
+#define MISC_MEMC_CONTROL		0x10
+#define MISC_STRAP_BUS			0x14
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT	1
+
+#define MISC_VREG_CONTROL0		0x1C
+#define MISC_VREG_CONTROL0_VREG_ADJ_SHIFT       8
+#define MISC_VREG_CONTROL0_VREG_OSC1P2_SHIFT	20
+#define MISC_VREG_CONTROL0_VREG_OSC1P8_SHIFT	22
+#define MISC_VREG_CONTROL0_VREG_RAMP1P2_SHIFT	26
+#define MISC_VREG_CONTROL0_VREG_RAMP1P8_SHIFT	29
+    
+#define MISC_VREG_CONTROL1		0x20
+#define MISC_VREG_CONTROL1_VREG_ISEL2P5_SHIFT   13
+#define MISC_VREG_CONTROL1_VREG_ISEL2P5_MASK    0x0001e000
+#define MISC_VREG_LDO_2P61       			    1
+
+#define MISC_VREG_CONTROL2		0x24
+
+/*
+#####################################################################
+# Memory Control Registers
+#####################################################################
+*/
+#define DDR_CTL_CNFG                             0x000 
+#define DDR_CTL_CSST                             0x004 
+#define DDR_CTL_CSEND                            0x008 
+#define DDR_CTL_ROW00_0                          0x010 
+#define DDR_CTL_ROW00_1                          0x014 
+#define DDR_CTL_ROW01_0                          0x018 
+#define DDR_CTL_ROW01_1                          0x01c 
+#define DDR_CTL_ROW20_0                          0x030 
+#define DDR_CTL_ROW20_1                          0x034 
+#define DDR_CTL_ROW21_0                          0x038 
+#define DDR_CTL_ROW21_1                          0x03c 
+#define DDR_CTL_COL00_0                          0x050 
+#define DDR_CTL_COL00_1                          0x054 
+#define DDR_CTL_COL01_0                          0x058 
+#define DDR_CTL_COL01_1                          0x05c 
+#define DDR_CTL_COL20_0                          0x070 
+#define DDR_CTL_COL20_1                          0x074 
+#define DDR_CTL_COL21_0                          0x078 
+#define DDR_CTL_COL21_1                          0x07c 
+#define DDR_CTL_BNK10                            0x090 
+#define DDR_CTL_BNK32                            0x094 
+#define DDR_CTL_DCMD                             0x100 
+#define DDR_CTL_DMODE_0                          0x104 
+#define DDR_CTL_DMODE_1                          0x108 
+#define DDR_CTL_CLKS                             0x10c 
+#define DDR_CTL_ODT                              0x110 
+#define DDR_CTL_TIM1_0                           0x114 
+#define DDR_CTL_TIM1_1                           0x118 
+#define DDR_CTL_TIM2                             0x11c 
+#define DDR_CTL_CTL_CRC                          0x120 
+#define DDR_CTL_DOUT_CRC                         0x124 
+#define DDR_CTL_DIN_CRC                          0x128 
+#define PHY_CONTROL_REGS_REVISION                0x200 
+#define PHY_CONTROL_REGS_CLK_PM_CTRL             0x204 
+#define PHY_CONTROL_REGS_PLL_STATUS              0x210 
+#define PHY_CONTROL_REGS_PLL_CONFIG              0x214 
+#define PHY_CONTROL_REGS_PLL_PRE_DIVIDER         0x218 
+#define PHY_CONTROL_REGS_PLL_DIVIDER             0x21c 
+#define PHY_CONTROL_REGS_PLL_CONTROL1            0x220 
+#define PHY_CONTROL_REGS_PLL_CONTROL2            0x224 
+#define PHY_CONTROL_REGS_PLL_SS_EN               0x228 
+#define PHY_CONTROL_REGS_PLL_SS_CFG              0x22c 
+#define PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE     0x230 
+#define PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE    0x234 
+#define PHY_CONTROL_REGS_IDLE_PAD_CONTROL        0x238 
+#define PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL         0x23c 
+#define PHY_CONTROL_REGS_DRIVE_PAD_CTL           0x240 
+#define PHY_BYTE_LANE_0_REVISION                 0x300 
+#define PHY_BYTE_LANE_0_VDL_CALIBRATE            0x304 
+#define PHY_BYTE_LANE_0_VDL_STATUS               0x308 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_0           0x310 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_1           0x314 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_2           0x318 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_3           0x31c 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_4           0x320 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_5           0x324 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_6           0x328 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_7           0x32c 
+#define PHY_BYTE_LANE_0_READ_CONTROL             0x330 
+#define PHY_BYTE_LANE_0_READ_FIFO_STATUS         0x334 
+#define PHY_BYTE_LANE_0_READ_FIFO_CLEAR          0x338 
+#define PHY_BYTE_LANE_0_IDLE_PAD_CONTROL         0x33c 
+#define PHY_BYTE_LANE_0_DRIVE_PAD_CTL            0x340 
+#define PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE        0x344 
+#define PHY_BYTE_LANE_0_WR_PREAMBLE_MODE         0x348 
+#define PHY_BYTE_LANE_1_REVISION                 0x400 
+#define PHY_BYTE_LANE_1_VDL_CALIBRATE            0x404 
+#define PHY_BYTE_LANE_1_VDL_STATUS               0x408 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_0           0x410 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_1           0x414 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_2           0x418 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_3           0x41c 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_4           0x420 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_5           0x424 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_6           0x428 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_7           0x42c 
+#define PHY_BYTE_LANE_1_READ_CONTROL             0x430 
+#define PHY_BYTE_LANE_1_READ_FIFO_STATUS         0x434 
+#define PHY_BYTE_LANE_1_READ_FIFO_CLEAR          0x438 
+#define PHY_BYTE_LANE_1_IDLE_PAD_CONTROL         0x43c 
+#define PHY_BYTE_LANE_1_DRIVE_PAD_CTL            0x440 
+#define PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE        0x444 
+#define PHY_BYTE_LANE_1_WR_PREAMBLE_MODE         0x448 
+#define PHY_BYTE_LANE_2_REVISION                 0x500 
+#define PHY_BYTE_LANE_2_VDL_CALIBRATE            0x504 
+#define PHY_BYTE_LANE_2_VDL_STATUS               0x508 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_0           0x510 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_1           0x514 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_2           0x518 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_3           0x51c 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_4           0x520 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_5           0x524 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_6           0x528 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_7           0x52c 
+#define PHY_BYTE_LANE_2_READ_CONTROL             0x530 
+#define PHY_BYTE_LANE_2_READ_FIFO_STATUS         0x534 
+#define PHY_BYTE_LANE_2_READ_FIFO_CLEAR          0x538 
+#define PHY_BYTE_LANE_2_IDLE_PAD_CONTROL         0x53c 
+#define PHY_BYTE_LANE_2_DRIVE_PAD_CTL            0x540 
+#define PHY_BYTE_LANE_2_CLOCK_PAD_DISABLE        0x544 
+#define PHY_BYTE_LANE_2_WR_PREAMBLE_MODE         0x548 
+#define PHY_BYTE_LANE_3_REVISION                 0x600 
+#define PHY_BYTE_LANE_3_VDL_CALIBRATE            0x604 
+#define PHY_BYTE_LANE_3_VDL_STATUS               0x608 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_0           0x610 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_1           0x614 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_2           0x618 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_3           0x61c 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_4           0x620 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_5           0x624 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_6           0x628 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_7           0x62c 
+#define PHY_BYTE_LANE_3_READ_CONTROL             0x630 
+#define PHY_BYTE_LANE_3_READ_FIFO_STATUS         0x634 
+#define PHY_BYTE_LANE_3_READ_FIFO_CLEAR          0x638 
+#define PHY_BYTE_LANE_3_IDLE_PAD_CONTROL         0x63c 
+#define PHY_BYTE_LANE_3_DRIVE_PAD_CTL            0x640 
+#define PHY_BYTE_LANE_3_CLOCK_PAD_DISABLE        0x644 
+#define PHY_BYTE_LANE_3_WR_PREAMBLE_MODE         0x648 
+#define DDR_CTL_GCFG                             0x800 
+#define DDR_CTL_LBIST_CFG                        0x804 
+#define DDR_CTL_LBIST_SEED                       0x808 
+#define DDR_CTL_ARB                              0x80c 
+#define DDR_CTL_PI_GCF                           0x810 
+#define DDR_CTL_PI_UBUS_CTL                      0x814 
+#define DDR_CTL_PI_MIPS_CTL                      0x818 
+#define DDR_CTL_PI_DSL_MIPS_CTL                  0x81c 
+#define DDR_CTL_PI_DSL_PHY_CTL                   0x820 
+#define DDR_CTL_PI_UBUS_ST                       0x824 
+#define DDR_CTL_PI_MIPS_ST                       0x828 
+#define DDR_CTL_PI_DSL_MIPS_ST                   0x82c 
+#define DDR_CTL_PI_DSL_PHY_ST                    0x830 
+#define DDR_CTL_PI_UBUS_SMPL                     0x834 
+#define DDR_CTL_TESTMODE                         0x838 
+#define DDR_CTL_TEST_CFG1                        0x83c 
+#define DDR_CTL_TEST_PAT                         0x840 
+#define DDR_CTL_TEST_COUNT                       0x844 
+#define DDR_CTL_TEST_CURR_COUNT                  0x848 
+#define DDR_CTL_TEST_ADDR_UPDT                   0x84c 
+#define DDR_CTL_TEST_ADDR                        0x850 
+#define DDR_CTL_TEST_DATA0                       0x854 
+#define DDR_CTL_TEST_DATA1                       0x858 
+#define DDR_CTL_TEST_DATA2                       0x85c 
+#define DDR_CTL_TEST_DATA3                       0x860 
+
+
+/*
+#####################################################################
+# UART Control Registers
+#####################################################################
+*/
+#define UART0CONTROL     0x01
+#define UART0CONFIG      0x02
+#define UART0RXTIMEOUT   0x03
+#define UART0BAUD        0x04
+#define UART0FIFOCFG     0x0a
+#define UART0INTMASK     0x10
+#define UART0INTSTAT     0x12
+#define UART0DATA        0x17
+
+#define BRGEN            0x80   /* Control register bit defs */
+#define TXEN             0x40
+#define RXEN             0x20
+#define LOOPBK           0x10
+#define TXPARITYEN       0x08
+#define TXPARITYEVEN     0x04
+#define RXPARITYEN       0x02
+#define RXPARITYEVEN     0x01
+
+#define XMITBREAK        0x40   /* Config register */
+#define BITS5SYM         0x00
+#define BITS6SYM         0x10
+#define BITS7SYM         0x20
+#define BITS8SYM         0x30
+#define ONESTOP          0x07
+#define TWOSTOP          0x0f
+
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+
+/*
+#####################################################################
+# DECT IP Control Registers
+#####################################################################
+*/
+#define DECT_STARTCTL   0xb0e50818
+#define PCM_BUFF_CTL3   0xb0e5082c
+#define PCM_BUFF_CTL7   0xb0e5083c
+#define DECT_AHB_CHAN0_RX  0xb0e50a20
+#define DECT_AHB_CHAN1_RX  0xb0e50de0
+#define DECT_AHB_CHAN2_RX  0xb0e511a0
+#define DECT_AHB_CHAN3_RX  0xb0e51560
+#define DECT_AHB_CHAN0_TX  0xb0e50840
+#define DECT_AHB_CHAN1_TX  0xb0e50c00
+#define DECT_AHB_CHAN2_TX  0xb0e50fc0
+#define DECT_AHB_CHAN3_TX  0xb0e51380
+#define DECT_CLKEN         0x00000040   
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/shared/broadcom/include/bcm963xx/6362_map.h b/shared/broadcom/include/bcm963xx/6362_map.h
new file mode 100755
index 0000000..d0fa38f
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/6362_map.h
@@ -0,0 +1,2251 @@
+/*
+<:copyright-broadcom 
+ 
+ Copyright (c) 2007 Broadcom Corporation 
+ All Rights Reserved 
+ No portions of this material may be reproduced in any form without the 
+ written permission of: 
+          Broadcom Corporation 
+          16215 Alton Parkway 
+          Irvine, California 92619 
+ All information contained in this document is Broadcom Corporation 
+ company private, proprietary, and trade secret. 
+ 
+:>
+*/
+/***********************************************************************/
+/*                                                                     */
+/*   MODULE:  6362_map.h                                               */
+/*   DATE:    05/30/08                                                 */
+/*   PURPOSE: Define addresses of major hardware components of         */
+/*            BCM6362                                                  */
+/*                                                                     */
+/***********************************************************************/
+#ifndef __BCM6362_MAP_H
+#define __BCM6362_MAP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include "bcmtypes.h"
+#include "6362_common.h"
+#include "6362_intr.h"
+
+/* macro to convert logical data addresses to physical */
+/* DMA hardware must see physical address */
+#define LtoP( x )       ( (uint32)x & 0x1fffffff )
+#define PtoL( x )       ( LtoP(x) | 0xa0000000 )
+
+typedef struct DDRPhyControl {
+    uint32 REVISION;               /* 0x00 */
+    uint32 CLK_PM_CTRL;            /* 0x04 */
+    uint32 unused0[2];             /* 0x08-0x10 */
+    uint32 PLL_STATUS;             /* 0x10 */
+    uint32 PLL_CONFIG;             /* 0x14 */
+    uint32 PLL_PRE_DIVIDER;        /* 0x18 */
+    uint32 PLL_DIVIDER;            /* 0x1c */
+    uint32 PLL_CONTROL1;           /* 0x20 */
+    uint32 PLL_CONTROL2;           /* 0x24 */
+    uint32 PLL_SS_EN;              /* 0x28 */
+    uint32 PLL_SS_CFG;             /* 0x2c */
+    uint32 STATIC_VDL_OVERRIDE;    /* 0x30 */
+    uint32 DYNAMIC_VDL_OVERRIDE;   /* 0x34 */
+    uint32 IDLE_PAD_CONTROL;       /* 0x38 */
+    uint32 ZQ_PVT_COMP_CTL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;          /* 0x40 */
+    uint32 CLOCK_REG_CONTROL;      /* 0x44 */
+    uint32 unused1[46];
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+    uint32 REVISION;                /* 0x00 */
+    uint32 VDL_CALIBRATE;           /* 0x04 */
+    uint32 VDL_STATUS;              /* 0x08 */
+    uint32 unused;                  /* 0x0c */
+    uint32 VDL_OVERRIDE_0;          /* 0x10 */
+    uint32 VDL_OVERRIDE_1;          /* 0x14 */
+    uint32 VDL_OVERRIDE_2;          /* 0x18 */
+    uint32 VDL_OVERRIDE_3;          /* 0x1c */
+    uint32 VDL_OVERRIDE_4;          /* 0x20 */
+    uint32 VDL_OVERRIDE_5;          /* 0x24 */
+    uint32 VDL_OVERRIDE_6;          /* 0x28 */
+    uint32 VDL_OVERRIDE_7;          /* 0x2c */
+    uint32 READ_CONTROL;            /* 0x30 */
+    uint32 READ_FIFO_STATUS;        /* 0x34 */
+    uint32 READ_FIFO_CLEAR;         /* 0x38 */
+    uint32 IDLE_PAD_CONTROL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;           /* 0x40 */
+    uint32 CLOCK_PAD_DISABLE;       /* 0x44 */
+    uint32 WR_PREAMBLE_MODE;        /* 0x48 */
+    uint32 CLOCK_REG_CONTROL;       /* 0x4C */
+    uint32 unused0[44];
+} DDRPhyByteLaneControl;
+
+typedef struct DDRControl {
+    uint32 CNFG;                            /* 0x000 */
+    uint32 CSST;                            /* 0x004 */
+    uint32 CSEND;                           /* 0x008 */
+    uint32 unused;                          /* 0x00c */
+    uint32 ROW00_0;                         /* 0x010 */
+    uint32 ROW00_1;                         /* 0x014 */
+    uint32 ROW01_0;                         /* 0x018 */
+    uint32 ROW01_1;                         /* 0x01c */
+    uint32 unused0[4];
+    uint32 ROW20_0;                         /* 0x030 */
+    uint32 ROW20_1;                         /* 0x034 */
+    uint32 ROW21_0;                         /* 0x038 */
+    uint32 ROW21_1;                         /* 0x03c */
+    uint32 unused1[4];
+    uint32 COL00_0;                         /* 0x050 */
+    uint32 COL00_1;                         /* 0x054 */
+    uint32 COL01_0;                         /* 0x058 */
+    uint32 COL01_1;                         /* 0x05c */
+    uint32 unused2[4];
+    uint32 COL20_0;                         /* 0x070 */
+    uint32 COL20_1;                         /* 0x074 */
+    uint32 COL21_0;                         /* 0x078 */
+    uint32 COL21_1;                         /* 0x07c */
+    uint32 unused3[4];
+    uint32 BNK10;                           /* 0x090 */
+    uint32 BNK32;                           /* 0x094 */
+    uint32 unused4[26];
+    uint32 DCMD;                            /* 0x100 */
+#define DCMD_CS1          (1 << 5)
+#define DCMD_CS0          (1 << 4)
+#define DCMD_SET_SREF     4
+    uint32 DMODE_0;                         /* 0x104 */
+    uint32 DMODE_1;                         /* 0x108 */
+#define DMODE_1_DRAMSLEEP (1 << 11)
+    uint32 CLKS;                            /* 0x10c */
+    uint32 ODT;                             /* 0x110 */
+    uint32 TIM1_0;                          /* 0x114 */
+    uint32 TIM1_1;                          /* 0x118 */
+    uint32 TIM2;                            /* 0x11c */
+    uint32 CTL_CRC;                         /* 0x120 */
+    uint32 DOUT_CRC;                        /* 0x124 */
+    uint32 DIN_CRC;                         /* 0x128 */
+    uint32 unused5[53];
+
+    DDRPhyControl           PhyControl;             /* 0x200 */
+    DDRPhyByteLaneControl   PhyByteLane0Control;    /* 0x300 */
+    DDRPhyByteLaneControl   PhyByteLane1Control;    /* 0x400 */
+    DDRPhyByteLaneControl   PhyByteLane2Control;    /* 0x500 */
+    DDRPhyByteLaneControl   PhyByteLane3Control;    /* 0x600 */
+    uint32 unused6[64];
+
+    uint32 GCFG;                            /* 0x800 */
+    uint32 LBIST_CFG;                       /* 0x804 */
+    uint32 LBIST_SEED;                      /* 0x808 */
+    uint32 ARB;                             /* 0x80c */
+    uint32 PI_GCF;                          /* 0x810 */
+    uint32 PI_UBUS_CTL;                     /* 0x814 */
+    uint32 PI_MIPS_CTL;                     /* 0x818 */
+    uint32 PI_DSL_MIPS_CTL;                 /* 0x81c */
+    uint32 PI_DSL_PHY_CTL;                  /* 0x820 */
+    uint32 PI_UBUS_ST;                      /* 0x824 */
+    uint32 PI_MIPS_ST;                      /* 0x828 */
+    uint32 PI_DSL_MIPS_ST;                  /* 0x82c */
+    uint32 PI_DSL_PHY_ST;                   /* 0x830 */
+    uint32 PI_UBUS_SMPL;                    /* 0x834 */
+    uint32 TESTMODE;                        /* 0x838 */
+    uint32 TEST_CFG1;                       /* 0x83c */
+    uint32 TEST_PAT;                        /* 0x840 */
+    uint32 TEST_COUNT;                      /* 0x844 */
+    uint32 TEST_CURR_COUNT;                 /* 0x848 */
+    uint32 TEST_ADDR_UPDT;                  /* 0x84c */
+    uint32 TEST_ADDR;                       /* 0x850 */
+    uint32 TEST_DATA0;                      /* 0x854 */
+    uint32 TEST_DATA1;                      /* 0x858 */
+    uint32 TEST_DATA2;                      /* 0x85c */
+    uint32 TEST_DATA3;                      /* 0x860 */
+} DDRControl;
+
+#define DDR ((volatile DDRControl * const) DDR_BASE)
+
+/*
+** Peripheral Controller
+*/
+
+#define IRQ_BITS 64
+typedef struct  {
+    uint64        IrqMask;
+    uint64        IrqStatus;
+} IrqControl_t;
+
+typedef struct PerfControl {
+    uint32        RevID;             /* (00) word 0 */
+    uint32        blkEnables;        /* (04) word 1 */
+#define NAND_CLK_EN      (1 << 20)
+#define PHYMIPS_CLK_EN   (1 << 19)
+#define FAP_CLK_EN       (1 << 18)
+#define PCIE_CLK_EN      (1 << 17)
+#define HS_SPI_CLK_EN    (1 << 16)
+#define SPI_CLK_EN       (1 << 15)
+#define IPSEC_CLK_EN     (1 << 14)
+#define USBH_CLK_EN      (1 << 13)
+#define USBD_CLK_EN      (1 << 12)
+#define PCM_CLK_EN       (1 << 11)
+#define ROBOSW_CLK_EN    (1 << 10)
+#define SAR_CLK_EN       (1 << 9)
+#define SWPKT_SAR_CLK_EN (1 << 8)
+#define SWPKT_USB_CLK_EN (1 << 7)
+#define WLAN_OCP_CLK_EN  (1 << 5)
+#define MIPS_CLK_EN      (1 << 4)
+#define ADSL_CLK_EN      (1 << 3)
+#define ADSL_AFE_EN      (1 << 2)
+#define ADSL_QPROC_EN    (1 << 1)
+#define DISABLE_GLESS    (1 << 0)
+
+    uint32        pll_control;       /* (08) word 2 */
+#define SOFT_RESET              0x00000001      // 0
+
+    uint32        deviceTimeoutEn;   /* (0c) word 3 */
+    uint32        softResetB;        /* (10) word 4 */
+#define SOFT_RST_WLAN_SHIM_UBUS (1 << 14)
+#define SOFT_RST_FAP            (1 << 13)
+#define SOFT_RST_DDR_PHY        (1 << 12)
+#define SOFT_RST_WLAN_SHIM      (1 << 11)
+#define SOFT_RST_PCIE_EXT       (1 << 10)
+#define SOFT_RST_PCIE           (1 << 9)
+#define SOFT_RST_PCIE_CORE      (1 << 8)
+#define SOFT_RST_PCM            (1 << 7)
+#define SOFT_RST_USBH           (1 << 6)
+#define SOFT_RST_USBD           (1 << 5)
+#define SOFT_RST_SWITCH         (1 << 4)
+#define SOFT_RST_SAR            (1 << 3)
+#define SOFT_RST_EPHY           (1 << 2)
+#define SOFT_RST_IPSEC          (1 << 1)
+#define SOFT_RST_SPI            (1 << 0)
+
+    uint32        diagControl;        /* (14) word 5 */
+    uint32        ExtIrqCfg;          /* (18) word 6*/
+    uint32        unused1;            /* (1c) word 7 */
+#define EI_SENSE_SHFT   0
+#define EI_STATUS_SHFT  4
+#define EI_CLEAR_SHFT   8
+#define EI_MASK_SHFT    12
+#define EI_INSENS_SHFT  16
+#define EI_LEVEL_SHFT   20
+
+     IrqControl_t IrqControl[2];
+} PerfControl;
+
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+/*
+** Timer
+*/
+typedef struct Timer {
+    uint16        unused0;
+    byte          TimerMask;
+#define TIMER0EN        0x01
+#define TIMER1EN        0x02
+#define TIMER2EN        0x04
+    byte          TimerInts;
+#define TIMER0          0x01
+#define TIMER1          0x02
+#define TIMER2          0x04
+#define WATCHDOG        0x08
+    uint32        TimerCtl0;
+    uint32        TimerCtl1;
+    uint32        TimerCtl2;
+#define TIMERENABLE     0x80000000
+#define RSTCNTCLR       0x40000000
+    uint32        TimerCnt0;
+    uint32        TimerCnt1;
+    uint32        TimerCnt2;
+    uint32        WatchDogDefCount;
+
+    /* Write 0xff00 0x00ff to Start timer
+     * Write 0xee00 0x00ee to Stop and re-load default count
+     * Read from this register returns current watch dog count
+     */
+    uint32        WatchDogCtl;
+
+    /* Number of 50-MHz ticks for WD Reset pulse to last */
+    uint32        WDResetCount;
+} Timer;
+
+#define TIMER ((volatile Timer * const) TIMR_BASE)
+
+/*
+** UART
+*/
+typedef struct UartChannel {
+    byte          unused0;
+    byte          control;
+#define BRGEN           0x80    /* Control register bit defs */
+#define TXEN            0x40
+#define RXEN            0x20
+#define LOOPBK          0x10
+#define TXPARITYEN      0x08
+#define TXPARITYEVEN    0x04
+#define RXPARITYEN      0x02
+#define RXPARITYEVEN    0x01
+
+    byte          config;
+#define XMITBREAK       0x40
+#define BITS5SYM        0x00
+#define BITS6SYM        0x10
+#define BITS7SYM        0x20
+#define BITS8SYM        0x30
+#define ONESTOP         0x07
+#define TWOSTOP         0x0f
+    /* 4-LSBS represent STOP bits/char
+     * in 1/8 bit-time intervals.  Zero
+     * represents 1/8 stop bit interval.
+     * Fifteen represents 2 stop bits.
+     */
+    byte          fifoctl;
+#define RSTTXFIFOS      0x80
+#define RSTRXFIFOS      0x40
+    /* 5-bit TimeoutCnt is in low bits of this register.
+     *  This count represents the number of characters
+     *  idle times before setting receive Irq when below threshold
+     */
+    uint32        baudword;
+    /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
+     */
+
+    byte          txf_levl;       /* Read-only fifo depth */
+    byte          rxf_levl;       /* Read-only fifo depth */
+    byte          fifocfg;        /* Upper 4-bits are TxThresh, Lower are
+                                   *      RxThreshold.  Irq can be asserted
+                                   *      when rx fifo> thresh, txfifo<thresh
+                                   */
+    byte          prog_out;       /* Set value of DTR (Bit0), RTS (Bit1)
+                                   *  if these bits are also enabled to GPIO_o
+                                   */
+#define DTREN   0x01
+#define RTSEN   0x02
+
+    byte          unused1;
+    byte          DeltaIPEdgeNoSense;     /* Low 4-bits, set corr bit to 1 to
+                                           * detect irq on rising AND falling
+                                           * edges for corresponding GPIO_i
+                                           * if enabled (edge insensitive)
+                                           */
+    byte          DeltaIPConfig_Mask;     /* Upper 4 bits: 1 for posedge sense
+                                           *      0 for negedge sense if
+                                           *      not configured for edge
+                                           *      insensitive (see above)
+                                           * Lower 4 bits: Mask to enable change
+                                           *  detection IRQ for corresponding
+                                           *  GPIO_i
+                                           */
+    byte          DeltaIP_SyncIP;         /* Upper 4 bits show which bits
+                                           *  have changed (may set IRQ).
+                                           *  read automatically clears bit
+                                           * Lower 4 bits are actual status
+                                           */
+
+    uint16        intMask;                /* Same Bit defs for Mask and status */
+    uint16        intStatus;
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+    uint16        unused2;
+    uint16        Data;                   /* Write to TX, Read from RX */
+                                          /* bits 11:8 are BRK,PAR,FRM errors */
+
+    uint32        unused3;
+    uint32        unused4;
+} Uart;
+
+#define UART ((volatile Uart * const) UART_BASE)
+
+/*
+** Gpio Controller
+*/
+
+typedef struct GpioControl {
+    uint64      GPIODir;                    /* 0 */
+    uint64      GPIOio;                     /* 8 */
+    uint32      LEDCtrl;                    /* 10 */
+    uint32      SpiSlaveCfg;                /* 14 */
+    uint32      GPIOMode;                   /* 18 */
+#define GPIO_MODE_EXT_IRQ3          (1<<27)
+#define GPIO_MODE_EXT_IRQ2          (1<<26)
+#define GPIO_MODE_EXT_IRQ1          (1<<25)
+#define GPIO_MODE_EXT_IRQ0          (1<<24)
+#define GPIO_MODE_EPHY3_LED         (1<<23)
+#define GPIO_MODE_EPHY2_LED         (1<<22)
+#define GPIO_MODE_EPHY1_LED         (1<<21)
+#define GPIO_MODE_EPHY0_LED         (1<<20)
+#define GPIO_MODE_ADSL_SPI_SSB      (1<<19)
+#define GPIO_MODE_ADSL_SPI_CLK      (1<<18)
+#define GPIO_MODE_ADSL_SPI_MOSI     (1<<17)
+#define GPIO_MODE_ADSL_SPI_MISO     (1<<16)
+#define GPIO_MODE_UART2_SDOUT       (1<<15)
+#define GPIO_MODE_UART2_SDIN        (1<<14)
+#define GPIO_MODE_UART2_SRTS        (1<<13)
+#define GPIO_MODE_UART2_SCTS        (1<<12)
+#define GPIO_MODE_NTR_PULSE         (1<<11)
+#define GPIO_MODE_LS_SPIM_SSB3      (1<<10)
+#define GPIO_MODE_LS_SPIM_SSB2      (1<<9)
+#define GPIO_MODE_INET_LED          (1<<8)
+#define GPIO_MODE_ROBOSW_LED1       (1<<7)
+#define GPIO_MODE_ROBOSW_LED0       (1<<6)
+#define GPIO_MODE_ROBOSW_LED_CLK    (1<<5)
+#define GPIO_MODE_ROBOSW_LED_DATA   (1<<4)
+#define GPIO_MODE_SERIAL_LED_DATA   (1<<3)
+#define GPIO_MODE_SERIAL_LED_CLK    (1<<2)
+#define GPIO_MODE_SYS_IRQ           (1<<1)
+#define GPIO_MODE_USBD_LED          (1<<0)
+
+    uint32      GPIOCtrl;                   /* 1C */
+    uint32      unused3[2];                 /* 20 - 24*/
+    uint32      TestControl;                /* 28 */
+    uint32      OscControl;                 /* 2C */
+    uint32      RoboSWLEDControl;           /* 30 */
+    uint32      RoboSWLEDLSR;               /* 34 */
+    uint32      GPIOBaseMode;               /* 38 */
+#define NAND_GPIO_OVERRIDE      (1<<2)
+    uint32      RoboswEphyCtrl;             /* 3C */
+#define EPHY_PLL_LOCK           (1<<27)
+#define EPHY_ATEST_25MHZ_EN     (1<<26)
+#define EPHY_PWR_DOWN_DLL       (1<<25)
+#define EPHY_PWR_DOWN_BIAS      (1<<24)
+#define EPHY_PWR_DOWN_TX_4      (1<<23)
+#define EPHY_PWR_DOWN_TX_3      (1<<22)
+#define EPHY_PWR_DOWN_TX_2      (1<<21)
+#define EPHY_PWR_DOWN_TX_1      (1<<20)
+#define EPHY_PWR_DOWN_RX_4      (1<<19)
+#define EPHY_PWR_DOWN_RX_3      (1<<18)
+#define EPHY_PWR_DOWN_RX_2      (1<<17)
+#define EPHY_PWR_DOWN_RX_1      (1<<16)
+#define EPHY_PWR_DOWN_SD_4      (1<<15)
+#define EPHY_PWR_DOWN_SD_3      (1<<14)
+#define EPHY_PWR_DOWN_SD_2      (1<<13)
+#define EPHY_PWR_DOWN_SD_1      (1<<12)
+#define EPHY_PWR_DOWN_RD_4      (1<<11)
+#define EPHY_PWR_DOWN_RD_3      (1<<10)
+#define EPHY_PWR_DOWN_RD_2      (1<<9)
+#define EPHY_PWR_DOWN_RD_1      (1<<8)
+#define EPHY_PWR_DOWN_4         (1<<7)
+#define EPHY_PWR_DOWN_3         (1<<6)
+#define EPHY_PWR_DOWN_2         (1<<5)
+#define EPHY_PWR_DOWN_1         (1<<4)
+#define EPHY_RST_4              (1<<3)
+#define EPHY_RST_3              (1<<2)
+#define EPHY_RST_2              (1<<1)
+#define EPHY_RST_1              (1<<0)
+    uint32      RoboswSwitchCtrl;           /* 40 */
+#define RSW_MII_2_IFC_EN        (1<<23)
+#define RSW_MII_2_AMP_EN        (1<<22)
+#define RSW_MII_2_SEL_SHIFT     20
+#define RSW_MII_SEL_3P3V        0
+#define RSW_MII_SEL_2P5V        1
+#define RSW_MII_SEL_1P5V        2
+#define RSW_MII_AMP_EN          (1<<18)
+#define RSW_MII_SEL_SHIFT       16
+#define RSW_SPI_MODE            (1<<11)
+#define RSW_BC_SUPP_EN          (1<<10)
+#define RSW_CLK_FREQ_MASK       (3<<8)
+#define RSW_ENF_DFX_FLOW        (1<<7)
+#define RSW_ENH_DFX_FLOW        (1<<6)
+#define RSW_GRX_0_SETUP         (1<<5)
+#define RSW_GTX_0_SETUP         (1<<4)
+#define RSW_HW_FWDG_EN          (1<<3)
+#define RSW_QOS_EN              (1<<2)
+#define RSW_WD_CLR_EN           (1<<1)
+#define RSW_MII_DUMB_FWDG_EN    (1<<0)
+
+    uint32      RegFileTmCtl;               /* 44 */
+
+    uint32      RingOscCtrl0;               /* 48 */
+#define RING_OSC_256_CYCLES         8
+#define RING_OSC_512_CYCLES         9
+#define RING_OSC_1024_CYCLES        10
+
+    uint32      RingOscCtrl1;               /* 4C */
+#define RING_OSC_ENABLE_MASK        (0x0f<<24)
+#define RING_OSC_ENABLE_SHIFT       24
+#define RING_OSC_MAX                4
+#define RING_OSC_COUNT_RESET        (0x1<<23)
+#define RING_OSC_SELECT_MASK        (0x7<<20)
+#define RING_OSC_SELECT_SHIFT       20
+#define RING_OSC_IRQ                (0x1<<18)
+#define RING_OSC_COUNTER_OVERFLOW   (0x1<<17)
+#define RING_OSC_COUNTER_BUSY       (0x1<<16)
+#define RING_OSC_COUNT_MASK         0x0000ffff
+
+    uint32      unused4[6];                 /* 50 - 64 */
+    uint32      DieRevID;                   /* 68 */
+    uint32      unused5;                    /* 6c */
+    uint32      DiagSelControl;             /* 70 */
+    uint32      DiagReadBack;               /* 74 */
+    uint32      DiagReadBackHi;             /* 78 */
+    uint32      DiagMiscControl;            /* 7c */
+} GpioControl;
+
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/* Number to mask conversion macro used for GPIODir and GPIOio */
+#define GPIO_NUM_MAX                    48
+#define GPIO_NUM_TO_MASK(X)             ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) )
+
+/*
+** OTP
+*/
+typedef struct Otp {
+    uint32      Config;                 /* 0x0 */
+    uint32      Control;                /* 0x4 */
+    uint32      Addr;                   /* 0x8 */
+    uint32      WriteData;              /* 0xc */
+    uint32      Status;                 /* 0x10 */
+    uint32      DOut;                   /* 0x14 */
+    uint32      UserBits[8];            /* 0x18 - 0x34 */
+#define OTP_WLAN_DISABLE                34
+#define OTP_DECT_DISABLE                38
+#define OTP_IPSED_DISABLE               39
+    uint32      unused[2];              /* 0x38 - 0x3c */
+    uint32      RAMRepair[16];          /* 0x40 - 0x7c */
+} Otp;
+
+#define OTP ((volatile Otp * const) OTP_BASE)
+
+/* Word order is reversed for User OTP bits */
+#define OTP_GET_USER_BIT(x)             ((OTP->UserBits[((sizeof(OTP->UserBits)/4) - (x)/32 - 1)] >> ((x) % 32)) & 1)
+
+/*
+** Spi Controller
+*/
+
+typedef struct SpiControl {
+  uint16        spiMsgCtl;              /* (0x0) control byte */
+#define FULL_DUPLEX_RW                  0
+#define HALF_DUPLEX_W                   1
+#define HALF_DUPLEX_R                   2
+#define SPI_MSG_TYPE_SHIFT              14
+#define SPI_BYTE_CNT_SHIFT              0
+  byte          spiMsgData[0x21e];      /* (0x02 - 0x21f) msg data */
+  byte          unused0[0x1e0];
+  byte          spiRxDataFifo[0x220];   /* (0x400 - 0x61f) rx data */
+  byte          unused1[0xe0];
+
+  uint16        spiCmd;                 /* (0x700): SPI command */
+#define SPI_CMD_NOOP                    0
+#define SPI_CMD_SOFT_RESET              1
+#define SPI_CMD_HARD_RESET              2
+#define SPI_CMD_START_IMMEDIATE         3
+
+#define SPI_CMD_COMMAND_SHIFT           0
+#define SPI_CMD_COMMAND_MASK            0x000f
+
+#define SPI_CMD_DEVICE_ID_SHIFT         4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
+#define SPI_CMD_ONE_BYTE_SHIFT          11
+#define SPI_CMD_ONE_WIRE_SHIFT          12
+#define SPI_DEV_ID_0                    0
+#define SPI_DEV_ID_1                    1
+#define SPI_DEV_ID_2                    2
+#define SPI_DEV_ID_3                    3
+
+  byte          spiIntStatus;           /* (0x702): SPI interrupt status */
+  byte          spiMaskIntStatus;       /* (0x703): SPI masked interrupt status */
+
+  byte          spiIntMask;             /* (0x704): SPI interrupt mask */
+#define SPI_INTR_CMD_DONE               0x01
+#define SPI_INTR_RX_OVERFLOW            0x02
+#define SPI_INTR_INTR_TX_UNDERFLOW      0x04
+#define SPI_INTR_TX_OVERFLOW            0x08
+#define SPI_INTR_RX_UNDERFLOW           0x10
+#define SPI_INTR_CLEAR_ALL              0x1f
+
+  byte          spiStatus;              /* (0x705): SPI status */
+#define SPI_RX_EMPTY                    0x02
+#define SPI_CMD_BUSY                    0x04
+#define SPI_SERIAL_BUSY                 0x08
+
+  byte          spiClkCfg;              /* (0x706): SPI clock configuration */
+#define SPI_CLK_0_391MHZ                1
+#define SPI_CLK_0_781MHZ                2 /* default */
+#define SPI_CLK_1_563MHZ                3
+#define SPI_CLK_3_125MHZ                4
+#define SPI_CLK_6_250MHZ                5
+#define SPI_CLK_12_50MHZ                6
+#define SPI_CLK_MASK                    0x07
+#define SPI_SSOFFTIME_MASK              0x38
+#define SPI_SSOFFTIME_SHIFT             3
+#define SPI_BYTE_SWAP                   0x80
+
+  byte          spiFillByte;            /* (0x707): SPI fill byte */
+  byte          unused2;
+  byte          spiMsgTail;             /* (0x709): msgtail */
+  byte          unused3;
+  byte          spiRxTail;              /* (0x70B): rxtail */
+} SpiControl;
+
+#define SPI ((volatile SpiControl * const) SPI_BASE)
+
+
+/*
+** High-Speed SPI Controller
+*/
+
+#define __mask(end, start)      (((1 << ((end - start) + 1)) - 1) << start)
+typedef struct HsSpiControl {
+
+  uint32    hs_spiGlobalCtrl;   // 0x0000
+#define HS_SPI_MOSI_IDLE        (1 << 18)
+#define HS_SPI_CLK_POLARITY      (1 << 17)
+#define HS_SPI_CLK_GATE_SSOFF       (1 << 16)
+#define HS_SPI_PLL_CLK_CTRL     (8)
+#define HS_SPI_PLL_CLK_CTRL_MASK    __mask(15, HS_SPI_PLL_CLK_CTRL)
+#define HS_SPI_SS_POLARITY      (0)
+#define HS_SPI_SS_POLARITY_MASK     __mask(7, HS_SPI_SS_POLARITY)
+
+  uint32    hs_spiExtTrigCtrl;  // 0x0004
+#define HS_SPI_TRIG_RAW_STATE   (24)
+#define HS_SPI_TRIG_RAW_STATE_MASK  __mask(31, HS_SPI_TRIG_RAW_STATE)
+#define HS_SPI_TRIG_LATCHED     (16)
+#define HS_SPI_TRIG_LATCHED_MASK    __mask(23, HS_SPI_TRIG_LATCHED)
+#define HS_SPI_TRIG_SENSE       (8)
+#define HS_SPI_TRIG_SENSE_MASK      __mask(15, HS_SPI_TRIG_SENSE)
+#define HS_SPI_TRIG_TYPE        (0)
+#define HS_SPI_TRIG_TYPE_MASK       __mask(7, HS_SPI_TRIG_TYPE)
+#define HS_SPI_TRIG_TYPE_EDGE       (0)
+#define HS_SPI_TRIG_TYPE_LEVEL      (1)
+
+  uint32    hs_spiIntStatus;    // 0x0008
+#define HS_SPI_IRQ_PING1_USER       (28)
+#define HS_SPI_IRQ_PING1_USER_MASK  __mask(31, HS_SPI_IRQ_PING1_USER)
+#define HS_SPI_IRQ_PING0_USER       (24)
+#define HS_SPI_IRQ_PING0_USER_MASK  __mask(27, HS_SPI_IRQ_PING0_USER)
+
+#define HS_SPI_IRQ_PING1_CTRL_INV   (1 << 12)
+#define HS_SPI_IRQ_PING1_POLL_TOUT  (1 << 11)
+#define HS_SPI_IRQ_PING1_TX_UNDER   (1 << 10)
+#define HS_SPI_IRQ_PING1_RX_OVER    (1 << 9)
+#define HS_SPI_IRQ_PING1_CMD_DONE   (1 << 8)
+
+#define HS_SPI_IRQ_PING0_CTRL_INV   (1 << 4)
+#define HS_SPI_IRQ_PING0_POLL_TOUT  (1 << 3)
+#define HS_SPI_IRQ_PING0_TX_UNDER   (1 << 2)
+#define HS_SPI_IRQ_PING0_RX_OVER    (1 << 1)
+#define HS_SPI_IRQ_PING0_CMD_DONE   (1 << 0)
+
+  uint32    hs_spiIntStatusMasked;  // 0x000C
+#define HS_SPI_IRQSM__PING1_USER    (28)
+#define HS_SPI_IRQSM__PING1_USER_MASK   __mask(31, HS_SPI_IRQSM__PING1_USER)
+#define HS_SPI_IRQSM__PING0_USER    (24)
+#define HS_SPI_IRQSM__PING0_USER_MASK   __mask(27, HS_SPI_IRQSM__PING0_USER)
+
+#define HS_SPI_IRQSM__PING1_CTRL_INV    (1 << 12)
+#define HS_SPI_IRQSM__PING1_POLL_TOUT   (1 << 11)
+#define HS_SPI_IRQSM__PING1_TX_UNDER    (1 << 10)
+#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9)
+#define HS_SPI_IRQSM__PING1_CMD_DONE    (1 << 8)
+
+#define HS_SPI_IRQSM__PING0_CTRL_INV    (1 << 4)
+#define HS_SPI_IRQSM__PING0_POLL_TOUT   (1 << 3)
+#define HS_SPI_IRQSM__PING0_TX_UNDER    (1 << 2)
+#define HS_SPI_IRQSM__PING0_RX_OVER     (1 << 1)
+#define HS_SPI_IRQSM__PING0_CMD_DONE    (1 << 0)
+
+  uint32    hs_spiIntMask;      // 0x0010
+#define HS_SPI_IRQM_PING1_USER      (28)
+#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER)
+#define HS_SPI_IRQM_PING0_USER      (24)
+#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER)
+
+#define HS_SPI_IRQM_PING1_CTRL_INV  (1 << 12)
+#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11)
+#define HS_SPI_IRQM_PING1_TX_UNDER  (1 << 10)
+#define HS_SPI_IRQM_PING1_RX_OVER   (1 << 9)
+#define HS_SPI_IRQM_PING1_CMD_DONE  (1 << 8)
+
+#define HS_SPI_IRQM_PING0_CTRL_INV  (1 << 4)
+#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3)
+#define HS_SPI_IRQM_PING0_TX_UNDER  (1 << 2)
+#define HS_SPI_IRQM_PING0_RX_OVER   (1 << 1)
+#define HS_SPI_IRQM_PING0_CMD_DONE  (1 << 0)
+
+#define HS_SPI_INTR_CLEAR_ALL       (0xFF001F1F)
+
+  uint32    hs_spiFlashCtrl;    // 0x0014
+#define HS_SPI_FCTRL_MB_ENABLE      (1 << 23)
+#define HS_SPI_FCTRL_SS_NUM         (20)
+#define HS_SPI_FCTRL_SS_NUM_MASK    __mask(22, HS_SPI_FCTRL_SS_NUM)
+#define HS_SPI_FCTRL_PROFILE_NUM    (16)
+#define HS_SPI_FCTRL_PROFILE_NUM_MASK   __mask(18, HS_SPI_FCTRL_PROFILE_NUM)
+#define HS_SPI_FCTRL_DUMMY_BYTES    (10)
+#define HS_SPI_FCTRL_DUMMY_BYTES_MASK   __mask(11, HS_SPI_FCTRL_DUMMY_BYTES)
+#define HS_SPI_FCTRL_ADDR_BYTES     (8)
+#define HS_SPI_FCTRL_ADDR_BYTES_MASK    __mask(9, HS_SPI_FCTRL_ADDR_BYTES)
+#define HS_SPI_FCTRL_ADDR_BYTES_2   (0)
+#define HS_SPI_FCTRL_ADDR_BYTES_3   (1)
+#define HS_SPI_FCTRL_ADDR_BYTES_4   (2)
+#define HS_SPI_FCTRL_READ_OPCODE    (0)
+#define HS_SPI_FCTRL_READ_OPCODE_MASK   __mask(7, HS_SPI_FCTRL_READ_OPCODE)
+
+  uint32    hs_spiFlashAddrBase;    // 0x0018
+
+  char      fill0[0x80 - 0x18];
+
+  uint32    hs_spiPP_0_Cmd;     // 0x0080
+#define HS_SPI_PP_SS_NUM        (12)
+#define HS_SPI_PP_SS_NUM_MASK       __mask(14, HS_SPI_PP_SS_NUM)
+#define HS_SPI_PP_PROFILE_NUM       (8)
+#define HS_SPI_PP_PROFILE_NUM_MASK  __mask(10, HS_SPI_PP_PROFILE_NUM)
+
+} HsSpiControl;
+
+typedef struct HsSpiPingPong {
+
+    uint32 command;
+#define HS_SPI_SS_NUM (12)
+#define HS_SPI_PROFILE_NUM (8)
+#define HS_SPI_TRIGGER_NUM (4)
+#define HS_SPI_COMMAND_VALUE (0)
+    #define HS_SPI_COMMAND_NOOP (0)
+    #define HS_SPI_COMMAND_START_NOW (1)
+    #define HS_SPI_COMMAND_START_TRIGGER (2)
+    #define HS_SPI_COMMAND_HALT (3)
+    #define HS_SPI_COMMAND_FLUSH (4)
+
+    uint32 status;
+#define HS_SPI_ERROR_BYTE_OFFSET (16)
+#define HS_SPI_WAIT_FOR_TRIGGER (2)
+#define HS_SPI_SOURCE_BUSY (1)
+#define HS_SPI_SOURCE_GNT (0)
+
+    uint32 fifo_status;
+    uint32 control;
+
+} HsSpiPingPong;
+
+typedef struct HsSpiProfile {
+
+    uint32 clk_ctrl;
+#define HS_SPI_ACCUM_RST_ON_LOOP (15)
+#define HS_SPI_SPI_CLK_2X_SEL (14)
+#define HS_SPI_FREQ_CTRL_WORD (0)
+    
+    uint32 signal_ctrl;
+#define	HS_SPI_ASYNC_INPUT_PATH (1 << 16)
+#define	HS_SPI_LAUNCH_RISING    (1 << 13)
+#define	HS_SPI_LATCH_RISING     (1 << 12)
+
+    uint32 mode_ctrl;
+#define HS_SPI_PREPENDBYTE_CNT (24)
+#define HS_SPI_MODE_ONE_WIRE (20)
+#define HS_SPI_MULTIDATA_WR_SIZE (18)
+#define HS_SPI_MULTIDATA_RD_SIZE (16)
+#define HS_SPI_MULTIDATA_WR_STRT (12)
+#define HS_SPI_MULTIDATA_RD_STRT (8)
+#define HS_SPI_FILLBYTE (0)
+
+    uint32 polling_config;
+    uint32 polling_and_mask;
+    uint32 polling_compare;
+    uint32 polling_timeout;
+    uint32 reserved;
+
+} HsSpiProfile;
+
+#define HS_SPI_OP_CODE 13
+    #define HS_SPI_OP_SLEEP (0)
+    #define HS_SPI_OP_READ_WRITE (1)
+    #define HS_SPI_OP_WRITE (2)
+    #define HS_SPI_OP_READ (3)
+    #define HS_SPI_OP_SETIRQ (4)
+
+#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE)
+#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80))
+#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0))
+#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100))
+#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200))
+#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400))
+
+
+/*
+** Misc Register Set Definitions.
+*/
+
+typedef struct Misc {
+    uint32  unused1;                            /* 0x00 */
+    uint32  miscSerdesCtrl;                     /* 0x04 */
+#define SERDES_PCIE_ENABLE                      0x00000001
+#define SERDES_PCIE_EXD_ENABLE                  (1<<15)
+    
+    uint32  miscSerdesSts;                      /* 0x08 */
+    uint32  miscIrqOutMask;                     /* 0x0C */
+#define MISC_PCIE_EP_IRQ_MASK0                  (1<<0)
+#define MISC_PCIE_EP_IRQ_MASK1                  (1<<1)
+
+    uint32  miscMemcControl;                    /* 0x10 */
+#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE    (1<<3)
+#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE     (1<<2)
+#define MISC_MEMC_CONTROL_DDR_TEST_DONE         (1<<1)
+#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE      (1<<0)
+
+    uint32  miscStrapBus;                       /* 0x14 */
+#define MISC_STRAP_BUS_RESET_CFG_DELAY          (1<<18)
+#define MISC_STRAP_BUS_RESET_OUT_SHIFT          16
+#define MISC_STRAP_BUS_RESET_OUT_MASK           (3<<MISC_STRAP_BUS_RESET_OUT_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           15
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x1<<MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SERIAL              0x01
+#define MISC_STRAP_BUS_BOOT_NAND                0x00
+#define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR   (1<<14)
+#define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR   (1<<14)
+#define MISC_STRAP_BUS_HS_SPIM_CLK_SLOW_N_FAST  (1<<13)
+#define MISC_STRAP_BUS_LS_SPIM_CLK_FAST_N_SLOW  (1<<12)
+#define MISC_STRAP_BUS_LS_SPI_MASTER_N_SLAVE    (1<<11)
+#define MISC_STRAP_BUS_PLL_USE_LOCK             (1<<10)
+#define MISC_STRAP_BUS_PLL_MIPS_WAIT_FAST_N     (1<<9)
+#define MISC_STRAP_BUS_ROBOSW_P4_MODE_SHIFT     7
+#define MISC_STRAP_BUS_ROBOSW_P4_MODE_MASK      (3<<MISC_STRAP_BUS_ROBOSW_P4_MODE_SHIFT)
+#define MISC_STRAP_BUS_HARD_RESET_DELAY         (1<<6)
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT      1
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK       (0x1F<<MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT)
+#define MISC_STRAP_BUS_PCIE_ROOT_COMPLEX        (1<<0)
+
+    uint32  miscStrapOverride;              /* 0x18 */
+    uint32  miscVregCtrl0;                  /* 0x1C */
+
+    uint32  miscVregCtrl1;                  /* 0x20 */
+#define VREG_VSEL1P2_SHIFT        0
+#define VREG_VSEL1P2_MASK         0x1f
+#define VREG_VSEL1P2_MIDDLE       0x0f
+
+    uint32  miscVregCtrl2;                  /* 0x24 */
+    uint32  miscExtra2ChipsIrqMask;         /* 0x28 */
+    uint32  miscExtra2ChipsIrqSts;          /* 0x2C */
+    uint32  miscExtra2ChipsIrqMask1;        /* 0x30 */
+    uint32  miscExtra2ChipsIrqSts1;         /* 0x34 */
+    uint32  miscFapIrqMask;                 /* 0x38 */
+    uint32  miscExtraFapIrqMask;            /* 0x3C */
+    uint32  miscExtra2FapIrqMask;           /* 0x40 */
+    uint32  miscAdsl_clock_sample;          /* 0x44 */
+
+    uint32  miscIddqCtrl;                   /* 0x48 */
+#define MISC_IDDQ_CONTROL_USBD    (1<<5)
+#define MISC_IDDQ_CONTROL_USBH    (1<<4)
+
+    uint32  miscSleep;                      /* 0x4C */
+    uint32  miscRtc_enable;                 /* 0x50 */
+    uint32  miscRtc_count_L;                /* 0x54 */
+    uint32  miscRtc_count_H;                /* 0x58 */
+    uint32  miscRtc_event;                  /* 0x5C */
+    uint32  miscWakeup_mask;                /* 0x60 */
+    uint32  miscWakeup_status;              /* 0x64 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+/*
+** LedControl Register Set Definitions.
+*/
+
+#pragma pack(push, 4)
+typedef struct LedControl {
+    uint32  ledInit;
+#define LED_LED_TEST                (1 << 31)
+#define LED_SHIFT_TEST              (1 << 30)
+#define LED_SERIAL_LED_SHIFT_DIR    (1 << 16)
+#define LED_SERIAL_LED_DATA_PPOL    (1 << 15)
+#define LEDSERIAL_LED_CLK_NPOL      (1 << 14)
+#define LED_SERIAL_LED_MUX_SEL      (1 << 13)
+#define LED_SERIAL_LED_EN           (1 << 12)
+#define LED_FAST_INTV_SHIFT         6
+#define LED_FAST_INTV_MASK          (0x3F<<LED_FAST_INTV_SHIFT)
+#define LED_SLOW_INTV_SHIFT         0
+#define LED_SLOW_INTV_MASK          (0x3F<<LED_SLOW_INTV_SHIFT)
+#define LED_INTERVAL_20MS           1
+
+    uint64  ledMode;
+#define LED_MODE_MASK               (uint64)0x3
+#define LED_MODE_OFF                (uint64)0x0
+#define LED_MODE_FLASH              (uint64)0x1
+#define LED_MODE_BLINK              (uint64)0x2
+#define LED_MODE_ON                 (uint64)0x3
+
+    uint32  ledHWDis;
+    uint32  ledStrobe;
+    uint32  ledLinkActSelHigh;
+#define LED_ENET0                   4
+#define LED_ENET1                   5
+#define LED_ENET2                   6
+#define LED_ENET3                   7
+#define LED_4_ACT_SHIFT             0
+#define LED_5_ACT_SHIFT             4
+#define LED_6_ACT_SHIFT             8
+#define LED_7_ACT_SHIFT             12
+#define LED_4_LINK_SHIFT            16
+#define LED_5_LINK_SHIFT            20
+#define LED_6_LINK_SHIFT            24
+#define LED_7_LINK_SHIFT            28
+    uint32  ledLinkActSelLow;
+#define LED_USB                     0
+#define LED_INET                    1
+#define LED_0_ACT_SHIFT             0
+#define LED_1_ACT_SHIFT             4
+#define LED_2_ACT_SHIFT             8
+#define LED_3_ACT_SHIFT             12
+#define LED_0_LINK_SHIFT            16
+#define LED_1_LINK_SHIFT            20
+#define LED_2_LINK_SHIFT            24
+#define LED_3_LINK_SHIFT            28
+
+    uint32  ledReadback;
+    uint32  ledSerialMuxSelect;
+} LedControl;
+#pragma pack(pop)
+
+#define LED ((volatile LedControl * const) LED_BASE)
+
+#define GPIO_NUM_TO_LED_MODE_SHIFT(X) \
+    ((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \
+    (((X) & BP_GPIO_SERIAL) ? ((((X) & BP_GPIO_NUM_MASK) - 8) << 1) : \
+    (((X) & BP_GPIO_NUM_MASK) < 16) ? (32 + ((((X) & BP_GPIO_NUM_MASK) - 8) << 1)) : \
+    ((((X) & BP_GPIO_NUM_MASK) - 16) << 1)))
+
+/*
+** Pcm Controller
+*/
+
+typedef struct PcmControlRegisters
+{
+    uint32 pcm_ctrl;                            // 00 offset from PCM_BASE
+#define  PCM_ENABLE              0x80000000     // PCM block master enable
+#define  PCM_ENABLE_SHIFT        31
+#define  PCM_SLAVE_SEL           0x40000000     // PCM TDM slave mode select (1 - TDM slave, 0 - TDM master)
+#define  PCM_SLAVE_SEL_SHIFT     30
+#define  PCM_CLOCK_INV           0x20000000     // PCM SCLK invert select (1 - invert, 0 - normal)
+#define  PCM_CLOCK_INV_SHIFT     29
+#define  PCM_FS_INVERT           0x10000000     // PCM FS invert select (1 - invert, 0 - normal)
+#define  PCM_FS_INVERT_SHIFT     28
+#define  PCM_FS_FREQ_16_8        0x08000000     // PCM FS 16/8 Khz select (1 - 16Khz, 0 - 8Khz)
+#define  PCM_FS_FREQ_16_8_SHIFT  27
+#define  PCM_FS_LONG             0x04000000     // PCM FS long/short select (1 - long FS, 0 - short FS)
+#define  PCM_FS_LONG_SHIFT       26
+#define  PCM_FS_TRIG             0x02000000     // PCM FS trigger (1 - falling edge, 0 - rising edge trigger)
+#define  PCM_FS_TRIG_SHIFT       25
+#define  PCM_DATA_OFF            0x01000000     // PCM data offset from FS (1 - one clock from FS, 0 - no offset)
+#define  PCM_DATA_OFF_SHIFT      24
+#define  PCM_DATA_16_8           0x00800000     // PCM data word length (1 - 16 bits, 0 - 8 bits)
+#define  PCM_DATA_16_8_SHIFT     23
+#define  PCM_CLOCK_SEL           0x00700000     // PCM SCLK freq select
+#define  PCM_CLOCK_SEL_SHIFT     20
+                                                  // 000 - 8192 Khz
+                                                  // 001 - 4096 Khz
+                                                  // 010 - 2048 Khz
+                                                  // 011 - 1024 Khz
+                                                  // 100 - 512 Khz
+                                                  // 101 - 256 Khz
+                                                  // 110 - 128 Khz
+                                                  // 111 - reserved
+#define  PCM_LSB_FIRST           0x00040000     // PCM shift direction (1 - LSBit first, 0 - MSBit first)
+#define  PCM_LSB_FIRST_SHIFT     18
+#define  PCM_LOOPBACK            0x00020000     // PCM diagnostic loobback enable
+#define  PCM_LOOPBACK_SHIFT      17
+#define  PCM_EXTCLK_SEL          0x00010000     // PCM external timing clock select -- Maybe removed in 6362
+#define  PCM_EXTCLK_SEL_SHIFT    16
+#define  PCM_NTR_ENABLE          0x00008000     // PCM NTR counter enable -- Nayve removed in 6362
+#define  PCM_NTR_ENABLE_SHIFT    15
+#define  PCM_BITS_PER_FRAME_1024 0x00000400     // 1024 - Max
+#define  PCM_BITS_PER_FRAME_256  0x00000100     // 256
+#define  PCM_BITS_PER_FRAME_8    0x00000008     // 8    - Min
+
+    uint32 pcm_chan_ctrl;                       // 04
+#define  PCM_TX0_EN              0x00000001     // PCM transmit channel 0 enable
+#define  PCM_TX1_EN              0x00000002     // PCM transmit channel 1 enable
+#define  PCM_TX2_EN              0x00000004     // PCM transmit channel 2 enable
+#define  PCM_TX3_EN              0x00000008     // PCM transmit channel 3 enable
+#define  PCM_TX4_EN              0x00000010     // PCM transmit channel 4 enable
+#define  PCM_TX5_EN              0x00000020     // PCM transmit channel 5 enable
+#define  PCM_TX6_EN              0x00000040     // PCM transmit channel 6 enable
+#define  PCM_TX7_EN              0x00000080     // PCM transmit channel 7 enable
+#define  PCM_RX0_EN              0x00000100     // PCM receive channel 0 enable
+#define  PCM_RX1_EN              0x00000200     // PCM receive channel 1 enable
+#define  PCM_RX2_EN              0x00000400     // PCM receive channel 2 enable
+#define  PCM_RX3_EN              0x00000800     // PCM receive channel 3 enable
+#define  PCM_RX4_EN              0x00001000     // PCM receive channel 4 enable
+#define  PCM_RX5_EN              0x00002000     // PCM receive channel 5 enable
+#define  PCM_RX6_EN              0x00004000     // PCM receive channel 6 enable
+#define  PCM_RX7_EN              0x00008000     // PCM receive channel 7 enable
+#define  PCM_RX_PACKET_SIZE      0x00ff0000     // PCM Rx DMA quasi-packet size
+#define  PCM_RX_PACKET_SIZE_SHIFT  16
+
+    uint32 pcm_int_pending;                     // 08
+    uint32 pcm_int_mask;                        // 0c
+#define  PCM_TX_UNDERFLOW        0x00000001     // PCM DMA receive overflow
+#define  PCM_RX_OVERFLOW         0x00000002     // PCM DMA transmit underflow
+#define  PCM_TDM_FRAME           0x00000004     // PCM frame boundary
+#define  PCM_RX_IRQ              0x00000008     // IUDMA interrupts
+#define  PCM_TX_IRQ              0x00000010
+
+    uint32 pcm_pll_ctrl1;                       // 10
+#define  PCM_PLL_PWRDN           0x80000000     // PLL PWRDN
+#define  PCM_PLL_PWRDN_CH1       0x40000000     // PLL CH PWRDN
+#define  PCM_PLL_REFCMP_PWRDN    0x20000000     // PLL REFCMP PWRDN
+#define  PCM_CLK16_RESET         0x10000000     // 16.382 MHz PCM interface circuitry reset. 
+#define  PCM_PLL_ARESET          0x08000000     // PLL Analog Reset
+#define  PCM_PLL_DRESET          0x04000000     // PLL Digital Reset
+
+    uint32 pcm_pll_ctrl2;                       // 14
+    uint32 pcm_pll_ctrl3;                       // 18
+    uint32 pcm_pll_ctrl4;                       // 1c
+
+    uint32 pcm_pll_stat;                        // 20
+#define  PCM_PLL_LOCK            0x00000001     // Asserted when PLL is locked to programmed frequency
+
+    uint32 pcm_ntr_counter;                     // 24
+
+    uint32 unused[6];
+#define  PCM_MAX_TIMESLOT_REGS   16             // Number of PCM time slot registers in the table.
+                                                // Each register provides the settings for 8 timeslots (4 bits per timeslot)
+    uint32 pcm_slot_alloc_tbl[PCM_MAX_TIMESLOT_REGS];
+#define  PCM_TS_VALID            0x8            // valid marker for TS alloc ram entry
+    
+    uint32 pcm_pll_ch2_ctrl;                    // +0xa080
+    uint32 pcm_msif_intf;                       // +0xa084
+} PcmControlRegisters;
+
+#define PCM ((volatile PcmControlRegisters * const) PCM_BASE)
+
+
+typedef struct PcmIudmaRegisters
+{
+    uint16 reserved0;
+    uint16 ctrlConfig;
+#define BCM6362_IUDMA_REGS_CTRLCONFIG_MASTER_EN        0x0001
+#define BCM6362_IUDMA_REGS_CTRLCONFIG_FLOWC_CH1_EN     0x0002
+#define BCM6362_IUDMA_REGS_CTRLCONFIG_FLOWC_CH3_EN     0x0004
+#define BCM6362_IUDMA_REGS_CTRLCONFIG_FLOWC_CH5_EN     0x0008
+#define BCM6362_IUDMA_REGS_CTRLCONFIG_FLOWC_CH7_EN     0x0010
+
+    // Flow control Ch1
+    uint16 reserved1;
+    uint16 ch1_FC_Low_Thr;
+
+    uint16 reserved2;
+    uint16 ch1_FC_High_Thr;
+
+    uint16 reserved3;
+    uint16 ch1_Buff_Alloc;
+
+    // Flow control Ch3
+    uint16 reserved4;
+    uint16 ch3_FC_Low_Thr;
+
+    uint16 reserved5;
+    uint16 ch3_FC_High_Thr;
+
+    uint16 reserved6;
+    uint16 ch3_Buff_Alloc;
+
+    // Flow control Ch5
+    uint16 reserved7;
+    uint16 ch5_FC_Low_Thr;
+
+    uint16 reserved8;
+    uint16 ch5_FC_High_Thr;
+
+    uint16 reserved9;
+    uint16 ch5_Buff_Alloc;
+
+    // Flow control Ch7
+    uint16 reserved10;
+    uint16 ch7_FC_Low_Thr;
+
+    uint16 reserved11;
+    uint16 ch7_FC_High_Thr;
+
+    uint16 reserved12;
+    uint16 ch7_Buff_Alloc;
+
+    // Channel resets
+    uint16 reserved13;
+    uint16 channel_reset;
+    
+    uint16 reserved14;
+    uint16 channel_debug;
+    
+    // Spare register
+    uint32 dummy1;
+    
+    // Interrupt status registers
+    uint16 reserved15;
+    uint16 gbl_int_stat;
+    
+    // Interrupt mask registers
+    uint16 reserved16;
+    uint16 gbl_int_mask;
+} PcmIudmaRegisters;
+
+
+typedef struct PcmIudmaChannelCtrl
+{
+    uint16 reserved1;
+    uint16 config;
+#define BCM6362_IUDMA_CONFIG_ENDMA       0x0001
+#define BCM6362_IUDMA_CONFIG_PKTHALT     0x0002
+#define BCM6362_IUDMA_CONFIG_BURSTHALT   0x0004
+
+    uint16 reserved2;
+    uint16 intStat;
+#define BCM6362_IUDMA_INTSTAT_BDONE   0x0001
+#define BCM6362_IUDMA_INTSTAT_PDONE   0x0002
+#define BCM6362_IUDMA_INTSTAT_NOTVLD  0x0004
+#define BCM6362_IUDMA_INTSTAT_MASK    0x0007
+#define BCM6362_IUDMA_INTSTAT_ALL     BCM6362_IUDMA_INTSTAT_MASK
+
+    uint16 reserved3;
+    uint16 intMask;
+#define BCM6362_IUDMA_INTMASK_BDONE   0x0001
+#define BCM6362_IUDMA_INTMASK_PDONE   0x0002
+#define BCM6362_IUDMA_INTMASK_NOTVLD  0x0004
+
+    uint32 maxBurst;
+#define BCM6362_IUDMA_MAXBURST_SIZE 16 /* 32-bit words */
+
+} PcmIudmaChannelCtrl;
+
+
+typedef struct PcmIudmaStateRam
+{
+   uint32 baseDescPointer;                /* pointer to first buffer descriptor */
+
+   uint32 stateBytesDoneRingOffset;       /* state info: how manu bytes done and the offset of the
+                                             current descritor in process */
+#define BCM6362_IUDMA_STRAM_DESC_RING_OFFSET 0x3fff
+
+
+   uint32 flagsLengthStatus;              /* Length and status field of the current descriptor */
+
+   uint32 currentBufferPointer;           /* pointer to the current descriptor */
+
+} PcmIudmaStateRam;
+
+#define BCM6362_MAX_PCM_DMA_CHANNELS 2
+
+typedef struct PcmIudma
+{
+   PcmIudmaRegisters regs;                                        // 
+   uint32 reserved1[110];                                         //            
+   PcmIudmaChannelCtrl ctrl[BCM6362_MAX_PCM_DMA_CHANNELS];        //
+   uint32 reserved2[120];                                         //
+   PcmIudmaStateRam stram[BCM6362_MAX_PCM_DMA_CHANNELS];          //
+
+} PcmIudma;
+
+#define PCM_IUDMA ((volatile PcmIudma * const) PCM_DMA_BASE)
+
+
+#define IUDMA_MAX_CHANNELS          32
+
+/*
+** DMA Channel Configuration (1 .. 32)
+*/
+typedef struct DmaChannelCfg {
+  uint32        cfg;                    /* (00) assorted configuration */
+#define         DMA_ENABLE      0x00000001  /* set to enable channel */
+#define         DMA_PKT_HALT    0x00000002  /* idle after an EOP flag is detected */
+#define         DMA_BURST_HALT  0x00000004  /* idle after finish current memory burst */
+  uint32        intStat;                /* (04) interrupts control and status */
+  uint32        intMask;                /* (08) interrupts mask */
+#define         DMA_BUFF_DONE   0x00000001  /* buffer done */
+#define         DMA_DONE        0x00000002  /* packet xfer complete */
+#define         DMA_NO_DESC     0x00000004  /* no valid descriptors */
+  uint32        maxBurst;               /* (0C) max burst length permitted */
+#define         DMA_DESCSIZE_SEL 0x00040000  /* DMA Descriptor Size Selection */
+} DmaChannelCfg;
+
+/*
+** DMA State RAM (1 .. 16)
+*/
+typedef struct DmaStateRam {
+  uint32        baseDescPtr;            /* (00) descriptor ring start address */
+  uint32        state_data;             /* (04) state/bytes done/ring offset */
+  uint32        desc_len_status;        /* (08) buffer descriptor status and len */
+  uint32        desc_base_bufptr;       /* (0C) buffer descrpitor current processing */
+} DmaStateRam;
+
+
+/*
+** DMA Registers
+*/
+typedef struct DmaRegs {
+    uint32 controller_cfg;              /* (00) controller configuration */
+#define DMA_MASTER_EN           0x00000001
+#define DMA_FLOWC_CH1_EN        0x00000002
+#define DMA_FLOWC_CH3_EN        0x00000004
+
+    // Flow control Ch1
+    uint32 flowctl_ch1_thresh_lo;           /* 004 */
+    uint32 flowctl_ch1_thresh_hi;           /* 008 */
+    uint32 flowctl_ch1_alloc;               /* 00c */
+#define DMA_BUF_ALLOC_FORCE     0x80000000
+
+    // Flow control Ch3
+    uint32 flowctl_ch3_thresh_lo;           /* 010 */
+    uint32 flowctl_ch3_thresh_hi;           /* 014 */
+    uint32 flowctl_ch3_alloc;               /* 018 */
+
+    // Flow control Ch5
+    uint32 flowctl_ch5_thresh_lo;           /* 01C */
+    uint32 flowctl_ch5_thresh_hi;           /* 020 */
+    uint32 flowctl_ch5_alloc;               /* 024 */
+
+    // Flow control Ch7
+    uint32 flowctl_ch7_thresh_lo;           /* 028 */
+    uint32 flowctl_ch7_thresh_hi;           /* 02C */
+    uint32 flowctl_ch7_alloc;               /* 030 */
+
+    uint32 ctrl_channel_reset;              /* 034 */
+    uint32 ctrl_channel_debug;              /* 038 */
+    uint32 reserved1;                       /* 03C */
+    uint32 ctrl_global_interrupt_status;    /* 040 */
+    uint32 ctrl_global_interrupt_mask;      /* 044 */
+
+    // Unused words
+    uint8 reserved2[0x200-0x48];
+
+    // Per channel registers/state ram
+    DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */
+    union {
+        DmaStateRam     s[IUDMA_MAX_CHANNELS];
+        uint32          u32[4 * IUDMA_MAX_CHANNELS];
+    } stram;                                /* (400-5FF) state ram */
+} DmaRegs;
+
+#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE)
+
+/*
+** DMA Buffer
+*/
+typedef struct DmaDesc {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM    0x8000
+#define          DMA_DESC_MULTICAST 0x4000
+#define          DMA_DESC_BUFLENGTH 0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                /* address of data */
+} DmaDesc;
+
+/*
+** 16 Byte DMA Buffer 
+*/
+typedef struct {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM        0x8000
+#define          DMA_DESC_MULTICAST     0x4000
+#define          DMA_DESC_BUFLENGTH     0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                 /* address of data */
+  uint32        control;
+#define         GEM_ID_MASK             0x001F
+  uint32        reserved;
+} DmaDesc16;
+
+
+/*
+** USB 2.0 Device Registers
+*/
+typedef struct UsbRegisters {
+#define USBD_CONTROL_APP_DONECSR                0x0001
+#define USBD_CONTROL_APP_RESUME                 0x0002
+#define USBD_CONTROL_APP_RXFIFIO_INIT           0x0040
+#define USBD_CONTROL_APP_TXFIFIO_INIT           0x0080
+#define USBD_CONTROL_APP_FIFO_SEL_SHIFT         0x8
+#define USBD_CONTROL_APP_FIFO_INIT_SEL(x)       (((x)&0x0f)<<USBD_CONTROL_APP_FIFO_SEL_SHIFT)
+#define USBD_CONTROL_APP_AUTO_CSRS              0x2000
+#define USBD_CONTROL_APP_AUTO_INS_ZERO_LEN_PKT  0x4000
+#define EN_TXZLENINS                            (1<<14)
+#define EN_RXZSCFG                              (1<<12)
+#define APPSETUPERRLOCK                         (1<<5)
+    uint32 usbd_control ;
+#define USBD_STRAPS_APP_SELF_PWR                0x0400
+#define USBD_STRAPS_APP_DEV_DISCON              0x0200
+#define USBD_STRAPS_APP_CSRPRG_SUP              0x0100
+#define USBD_STRAPS_APP_RAM_IF                  0x0080
+#define USBD_STRAPS_APP_DEV_RMTWKUP             0x0040
+#define USBD_STRAPS_APP_PHYIF_8BIT              0x0004
+#define USBD_STRAPS_FULL_SPEED                  0x0003
+#define USBD_STRAPS_LOW_SPEED                   0x0002
+#define USBD_STRAPS_HIGH_SPEED                  0x0000
+#define APPUTMIDIR(x)                           ((x&1)<<3)
+#define UNIDIR                                  0
+    uint32 usbd_straps;
+#define USB_ENDPOINT_0                          0x01
+    uint32 usbd_stall;
+#define USBD_ENUM_SPEED_SHIFT                   12
+#define USBD_ENUM_SPEED                         0x3000
+#define UDC20_ALTINTF(x)                        ((x>>8)&0xf)
+#define UDC20_INTF(x)                           ((x>>4)&0xf)
+#define UDC20_CFG(x)                            ((x>>0)&0xf)
+    uint32 usbd_status;
+#define USBD_LINK                   (0x1<<10)
+#define USBD_SET_CSRS                           0x40
+#define USBD_SUSPEND                            0x20
+#define USBD_EARLY_SUSPEND                      0x10
+#define USBD_SOF                                0x08
+#define USBD_ENUMON                             0x04
+#define USBD_SETUP                              0x02
+#define USBD_USBRESET                           0x01
+    uint32 usbd_events;
+    uint32 usbd_events_irq;
+#define UPPER(x)                                (16+x)
+#define ENABLE(x)                               (1<<x)
+#define SWP_TXBSY                               (15)
+#define SWP_RXBSY                               (14)
+#define SETUP_ERR                               (13)
+#define APPUDCSTALLCHG                          (12)
+#define BUS_ERR                                 (11)
+#define USB_LINK                                (10)
+#define HST_SETCFG                              (9)
+#define HST_SETINTF                             (8)
+#define ERRATIC_ERR                             (7)
+#define SET_CSRS                                (6)
+#define SUSPEND                                 (5)
+#define ERLY_SUSPEND                            (4)
+#define SOF                                     (3)
+#define ENUM_ON                                 (2)
+#define SETUP                                   (1)
+#define USB_RESET                               (0)
+#define RISING(x)                               (0x0<<2*x)
+#define FALLING(x)                              (0x1<<2*x)
+#define USBD_IRQCFG_ENUM_ON_FALLING_EDGE        0x00000010
+    uint32 usbd_irqcfg_hi ;
+    uint32 usbd_irqcfg_lo ;
+#define USBD_USB_RESET_IRQ                      0x00000001
+#define USBD_USB_SETUP_IRQ                      0x00000002 // non-standard setup cmd rcvd
+#define USBD_USB_ENUM_ON_IRQ                    0x00000004
+#define USBD_USB_SOF_IRQ                        0x00000008
+#define USBD_USB_EARLY_SUSPEND_IRQ              0x00000010
+#define USBD_USB_SUSPEND_IRQ                    0x00000020 // non-standard setup cmd rcvd
+#define USBD_USB_SET_CSRS_IRQ                   0x00000040
+#define USBD_USB_ERRATIC_ERR_IRQ                0x00000080
+#define USBD_USB_SETCFG_IRQ                     0x00000200
+#define USBD_USB_LINK_IRQ                       0x00000400
+    uint32 usbd_events_irq_mask;
+    uint32 usbd_swcfg;
+    uint32 usbd_swtxctl;
+    uint32 usbd_swrxctl;
+    uint32 usbd_txfifo_rwptr;
+    uint32 usbd_rxfifo_rwptr;
+    uint32 usbd_txfifo_st_rwptr;
+    uint32 usbd_rxfifo_st_rwptr;
+    uint32 usbd_txfifo_config ;
+    uint32 usbd_rxfifo_config ;
+    uint32 usbd_txfifo_epsize ;
+    uint32 usbd_rxfifo_epsize ;
+#define USBD_EPNUM_CTRL                         0x0
+#define USBD_EPNUM_ISO                          0x1
+#define USBD_EPNUM_BULK                         0x2
+#define USBD_EPNUM_IRQ                          0x3
+#define USBD_EPNUM_EPTYPE(x)                    (((x)&0x3)<<8)
+#define USBD_EPNUM_EPDMACHMAP(x)                (((x)&0xf)<<0)
+    uint32 usbd_epnum_typemap ;
+    uint32 usbd_reserved [0xB] ;
+    uint32 usbd_csr_setupaddr ;
+#define USBD_EPNUM_MASK                         0xf
+#define USBD_EPNUM(x)                           ((x&USBD_EPNUM_MASK)<<0)
+#define USBD_EPDIR_IN                           (1<<4)
+#define USBD_EPDIR_OUT                          (0<<4)
+#define USBD_EPTYP_CTRL                         (USBD_EPNUM_CTRL<<5)
+#define USBD_EPTYP_ISO                          (USBD_EPNUM_ISO<<5)
+#define USBD_EPTYP_BULK                         (USBD_EPNUM_BULK<<5)
+#define USBD_EPTYP_IRQ                          (USBD_EPNUM_IRQ<<5)
+#define USBD_EPCFG_MASK                         0xf
+#define USBD_EPCFG(x)                           ((x&USBD_EPCFG_MASK)<<7)
+#define USBD_EPINTF_MASK                        0xf
+#define USBD_EPINTF(x)                          ((x&USBD_EPINTF_MASK)<<11)
+#define USBD_EPAINTF_MASK                       0xf
+#define USBD_EPAINTF(x)                         ((x&USBD_EPAINTF_MASK)<<15)
+#define USBD_EPMAXPKT_MSK                       0x7ff
+#define USBD_EPMAXPKT(x)                        ((x&USBD_EPMAXPKT_MSK)<<19)
+#define USBD_EPISOPID_MASK                      0x3
+#define USBD_EPISOPID(x)                        ((x&USBD_ISOPID_MASK)<<30)
+    uint32 usbd_csr_ep [5] ;
+} UsbRegisters;
+
+#define USB ((volatile UsbRegisters * const) USB_CTL_BASE)
+
+typedef struct USBControl {
+    uint32 BrtControl1;
+    uint32 BrtControl2;
+    uint32 BrtStatus1;
+    uint32 BrtStatus2;
+    uint32 UTMIControl1;
+    uint32 TestPortControl;
+    uint32 PllControl1;
+    uint32 SwapControl;
+#define USB_DEVICE_SEL          (1<<6)
+#define EHCI_LOGICAL_ADDRESS_EN (1<<5)
+#define EHCI_ENDIAN_SWAP        (1<<4)
+#define EHCI_DATA_SWAP          (1<<3)
+#define OHCI_LOGICAL_ADDRESS_EN (1<<2)
+#define OHCI_ENDIAN_SWAP        (1<<1)
+#define OHCI_DATA_SWAP          (1<<0)
+    uint32 unused1;
+    uint32 FrameAdjustValue;
+    uint32 Setup;
+#define USBH_IOC                (1<<4)
+    uint32 MDIO;
+    uint32 MDIO32;
+    uint32 USBSimControl;
+} USBControl;
+
+#define USBH ((volatile USBControl * const) USBH_CFG_BASE)
+
+typedef struct EthSwRegs{
+    byte port_traffic_ctrl[9]; /* 0x00 - 0x08 */
+    byte reserved1[2]; /* 0x09 - 0x0a */
+    byte switch_mode; /* 0x0b */
+    unsigned short pause_quanta; /*0x0c */
+    byte imp_port_state; /*0x0e */
+    byte led_refresh; /* 0x0f */
+    unsigned short led_function[2]; /* 0x10 */
+    unsigned short led_function_map; /* 0x14 */
+    unsigned short led_enable_map; /* 0x16 */
+    unsigned short led_mode_map0; /* 0x18 */
+    unsigned short led_function_map1; /* 0x1a */
+    byte reserved2[5]; /* 0x1b - 0x20 */
+    byte port_forward_ctrl; /* 0x21 */ 
+    byte reserved3[2]; /* 0x22 - 0x23 */
+    unsigned short protected_port_selection; /* 0x24 */
+    unsigned short wan_port_select; /* 0x26 */
+    unsigned int pause_capability; /* 0x28 */
+    byte reserved4[3]; /* 0x2c - 0x2e */
+    byte reserved_multicast_control; /* 0x2f */
+    byte reserved5; /* 0x30 */
+    byte txq_flush_mode_control; /* 0x31 */
+    unsigned short ulf_forward_map; /* 0x32 */
+    unsigned short mlf_forward_map; /* 0x34 */
+    unsigned short mlf_impc_forward_map; /* 0x36 */
+    unsigned short pause_pass_through_for_rx; /* 0x38 */
+    unsigned short pause_pass_through_for_tx; /* 0x3a */
+    unsigned short disable_learning; /* 0x3c */
+    byte reserved6[26]; /* 0x3e - 0x57 */
+    byte port_state_override[8]; /* 0x58 - 0x5f */
+    byte reserved7[4]; /* 0x60 - 0x63 */
+    byte imp_rgmii_ctrl_p4; /* 0x64 */
+    byte imp_rgmii_ctrl_p5; /* 0x65 */
+    byte reserved8[6]; /* 0x66 - 0x6b */
+    byte rgmii_timing_delay_p4; /* 0x6c */
+    byte gmii_timing_delay_p5; /* 0x6d */
+    byte reserved9[11]; /* 0x6e - 0x78 */
+    byte software_reset; /* 0x79 */
+    byte reserved13[6]; /* 0x7a - 0x7f */
+    byte pause_frame_detection; /* 0x80 */
+    byte reserved10[7]; /* 0x81 - 0x87 */
+    byte fast_aging_ctrl; /* 0x88 */
+    byte fast_aging_port; /* 0x89 */
+    byte fast_aging_vid; /* 0x8a */
+    byte reserved11[21]; /* 0x8b - 0x9f */
+    unsigned int swpkt_ctrl_sar; /*0xa0 */
+    unsigned int swpkt_ctrl_usb; /*0xa4 */
+    unsigned int iudma_ctrl; /*0xa8 */
+    unsigned int rxfilt_ctrl; /*0xac */
+    unsigned int mdio_ctrl; /*0xb0 */
+    unsigned int mdio_data; /*0xb4 */
+    byte reserved12[42]; /* 0xb6 - 0xdf */
+    unsigned int sw_mem_test; /*0xe0 */
+} EthSwRegs;
+
+#define ETHSWREG ((volatile EthSwRegs * const) SWITCH_BASE)
+
+typedef struct EthSwMIBRegs {
+    unsigned int TxOctetsLo;
+    unsigned int TxOctetsHi;
+    unsigned int TxDropPkts;
+    unsigned int TxQoSPkts;
+    unsigned int TxBroadcastPkts;
+    unsigned int TxMulticastPkts;
+    unsigned int TxUnicastPkts;
+    unsigned int TxCol;
+    unsigned int TxSingleCol;
+    unsigned int TxMultipleCol;
+    unsigned int TxDeferredTx;
+    unsigned int TxLateCol;
+    unsigned int TxExcessiveCol;
+    unsigned int TxFrameInDisc;
+    unsigned int TxPausePkts;
+    unsigned int TxQoSOctetsLo;
+    unsigned int TxQoSOctetsHi;
+    unsigned int RxOctetsLo;
+    unsigned int RxOctetsHi;
+    unsigned int RxUndersizePkts;
+    unsigned int RxPausePkts;
+    unsigned int Pkts64Octets;
+    unsigned int Pkts65to127Octets;
+    unsigned int Pkts128to255Octets;
+    unsigned int Pkts256to511Octets;
+    unsigned int Pkts512to1023Octets;
+    unsigned int Pkts1024to1522Octets;
+    unsigned int RxOversizePkts;
+    unsigned int RxJabbers;
+    unsigned int RxAlignErrs;
+    unsigned int RxFCSErrs;
+    unsigned int RxGoodOctetsLo;
+    unsigned int RxGoodOctetsHi;
+    unsigned int RxDropPkts;
+    unsigned int RxUnicastPkts;
+    unsigned int RxMulticastPkts;
+    unsigned int RxBroadcastPkts;
+    unsigned int RxSAChanges;
+    unsigned int RxFragments;
+    unsigned int RxExcessSizeDisc;
+    unsigned int RxSymbolError;
+    unsigned int RxQoSPkts;
+    unsigned int RxQoSOctetsLo;
+    unsigned int RxQoSOctetsHi;
+    unsigned int Pkts1523to2047;
+    unsigned int Pkts2048to4095;
+    unsigned int Pkts4096to8191;
+    unsigned int Pkts8192to9728;
+} EthSwMIBRegs;
+
+#define ETHSWMIBREG ((volatile EthSwMIBRegs * const) (SWITCH_BASE + 0x2000))
+
+/*
+** NAND Interrupt Controller Registers
+*/
+typedef struct NandIntrCtrlRegs {
+    uint32 NandInterrupt;
+#define NINT_ENABLE_MASK    0xffff0000
+#define NINT_STS_MASK       0x00000fff
+#define NINT_ECC_ERROR_CORR 0x00000080
+#define NINT_ECC_ERROR_UNC  0x00000040
+#define NINT_DEV_RBPIN      0x00000020
+#define NINT_CTRL_READY     0x00000010
+#define NINT_PAGE_PGM       0x00000008
+#define NINT_COPY_BACK      0x00000004
+#define NINT_BLOCK_ERASE    0x00000002
+#define NINT_NP_READ        0x00000001
+
+    uint32 NandBaseAddr0;   /* Default address when booting from NAND flash */
+    uint32 reserved;
+    uint32 NandBaseAddr1;   /* Secondary base address for NAND flash */
+} NandIntrCtrlRegs;
+
+#define NAND_INTR ((volatile NandIntrCtrlRegs * const) NAND_INTR_BASE)
+
+/*
+** NAND Controller Registers
+*/
+typedef struct NandCtrlRegs {
+    uint32 NandRevision;            /* NAND Revision */
+    uint32 NandCmdStart;            /* Nand Flash Command Start */
+#define NCMD_MASK           0x0f000000
+#define NCMD_BLK_LOCK_STS   0x0d000000
+#define NCMD_BLK_UNLOCK     0x0c000000
+#define NCMD_BLK_LOCK_DOWN  0x0b000000
+#define NCMD_BLK_LOCK       0x0a000000
+#define NCMD_FLASH_RESET    0x09000000
+#define NCMD_BLOCK_ERASE    0x08000000
+#define NCMD_DEV_ID_READ    0x07000000
+#define NCMD_COPY_BACK      0x06000000
+#define NCMD_PROGRAM_SPARE  0x05000000
+#define NCMD_PROGRAM_PAGE   0x04000000
+#define NCMD_STS_READ       0x03000000
+#define NCMD_SPARE_READ     0x02000000
+#define NCMD_PAGE_READ      0x01000000
+
+    uint32 NandCmdExtAddr;          /* Nand Flash Command Extended Address */
+    uint32 NandCmdAddr;             /* Nand Flash Command Address */
+    uint32 NandCmdEndAddr;          /* Nand Flash Command End Address */
+    uint32 NandNandBootConfig;      /* Nand Flash Boot Config */
+#define NBC_CS_LOCK         0x80000000
+#define NBC_AUTO_DEV_ID_CFG 0x40000000
+#define NBC_WR_PROT_BLK0    0x10000000
+
+    uint32 NandCsNandXor;           /* Nand Flash EBI CS Address XOR with */
+                                    /*   1FC0 Control */
+    uint32 NandReserved;
+    uint32 NandSpareAreaReadOfs0;   /* Nand Flash Spare Area Read Bytes 0-3 */
+    uint32 NandSpareAreaReadOfs4;   /* Nand Flash Spare Area Read Bytes 4-7 */
+    uint32 NandSpareAreaReadOfs8;   /* Nand Flash Spare Area Read Bytes 8-11 */
+    uint32 NandSpareAreaReadOfsC;   /* Nand Flash Spare Area Read Bytes 12-15*/
+    uint32 NandSpareAreaWriteOfs0;  /* Nand Flash Spare Area Write Bytes 0-3 */
+    uint32 NandSpareAreaWriteOfs4;  /* Nand Flash Spare Area Write Bytes 4-7 */
+    uint32 NandSpareAreaWriteOfs8;  /* Nand Flash Spare Area Write Bytes 8-11*/
+    uint32 NandSpareAreaWriteOfsC;  /* Nand Flash Spare Area Write Bytes12-15*/
+    uint32 NandAccControl;          /* Nand Flash Access Control */
+    uint32 NandConfig;              /* Nand Flash Config */
+#define NC_CONFIG_LOCK      0x80000000
+#define NC_PG_SIZE_MASK     0x00300000
+#define NC_PG_SIZE_2K       0x00100000
+#define NC_PG_SIZE_512B     0x00000000
+#define NC_BLK_SIZE_MASK    0x30000000
+#define NC_BLK_SIZE_512K    0x30000000
+#define NC_BLK_SIZE_128K    0x10000000
+#define NC_BLK_SIZE_16K     0x00000000
+#define NC_BLK_SIZE_8K      0x20000000
+#define NC_DEV_SIZE_MASK    0x0f000000
+#define NC_DEV_SIZE_SHIFT   24
+#define NC_DEV_WIDTH_MASK   0x00800000
+#define NC_DEV_WIDTH_16     0x00800000
+#define NC_DEV_WIDTH_8      0x00000000
+#define NC_FUL_ADDR_MASK    0x00070000
+#define NC_FUL_ADDR_SHIFT   16
+#define NC_BLK_ADDR_MASK    0x00000700
+#define NC_BLK_ADDR_SHIFT   8
+
+    uint32 NandTiming1;             /* Nand Flash Timing Parameters 1 */
+    uint32 NandTiming2;             /* Nand Flash Timing Parameters 2 */
+    uint32 NandSemaphore;           /* Semaphore */
+    uint32 NandFlashDeviceId;       /* Nand Flash Device ID */
+    uint32 NandBlockLockStatus;     /* Nand Flash Block Lock Status */
+    uint32 NandIntfcStatus;         /* Nand Flash Interface Status */
+#define NIS_CTLR_READY      0x80000000
+#define NIS_FLASH_READY     0x40000000
+#define NIS_CACHE_VALID     0x20000000
+#define NIS_SPARE_VALID     0x10000000
+#define NIS_FLASH_STS_MASK  0x000000ff
+#define NIS_WRITE_PROTECT   0x00000080
+#define NIS_DEV_READY       0x00000040
+#define NIS_PGM_ERASE_ERROR 0x00000001
+
+    uint32 NandEccCorrExtAddr;      /* ECC Correctable Error Extended Address*/
+    uint32 NandEccCorrAddr;         /* ECC Correctable Error Address */
+    uint32 NandEccUncExtAddr;       /* ECC Uncorrectable Error Extended Addr */
+    uint32 NandEccUncAddr;          /* ECC Uncorrectable Error Address */
+    uint32 NandFlashReadExtAddr;    /* Flash Read Data Extended Address */
+    uint32 NandFlashReadAddr;       /* Flash Read Data Address */
+    uint32 NandProgramPageExtAddr;  /* Page Program Extended Address */
+    uint32 NandProgramPageAddr;     /* Page Program Address */
+    uint32 NandCopyBackExtAddr;     /* Copy Back Extended Address */
+    uint32 NandCopyBackAddr;        /* Copy Back Address */
+    uint32 NandBlockEraseExtAddr;   /* Block Erase Extended Address */
+    uint32 NandBlockEraseAddr;      /* Block Erase Address */
+    uint32 NandInvReadExtAddr;      /* Flash Invalid Data Extended Address */
+    uint32 NandInvReadAddr;         /* Flash Invalid Data Address */
+    uint32 NandBlkWrProtect;        /* Block Write Protect Enable and Size */
+                                    /*   for EBI_CS0b */
+} NandCtrlRegs;
+
+#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE)
+
+#define NAND_CACHE ((volatile uint8 * const) NAND_CACHE_BASE)
+
+/*
+** PCI-E
+*/
+typedef struct PcieRegs{
+  uint32 devVenID;
+  uint16 command;
+  uint16 status;
+  uint32 revIdClassCode;
+  uint32 headerTypeLatCacheLineSize;
+  uint32 bar1;
+  uint32 bar2;
+  uint32 priSecBusNo;
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK              0x00ff0000
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT             16  
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK              0x0000ff00
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT             8
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK              0x000000ff
+
+  uint32 ioBaseLimit;
+  uint32 secStatus;
+  uint32 rcMemBaseLimit;
+  uint32 rcPrefBaseLimit;
+  uint32 rcPrefBaseHi;
+  uint32 rcPrefLimitHi;
+  uint32 rcIoBaseLimit;
+  uint32 capPointer;
+  uint32 expRomBase;
+  uint32 brdigeCtrlIntPinIntLine;
+  uint32 bridgeCtrl;
+  uint32 unused1[27];
+
+  /* PcieExpressCtrlRegs */
+  uint16 pciExpressCap;
+  uint16 pcieCapabilitiy;
+  uint32 deviceCapability;
+  uint16 deviceControl;
+  uint16 deviceStatus;
+  uint32 linkCapability;
+  uint16 linkControl;
+  uint16 linkStatus;
+  uint32 slotCapability;
+  uint16 slotControl;
+  uint16 slotStatus;
+  uint16 rootControl;
+  uint16 rootCap;
+  uint32 rootStatus;
+  uint32 deviceCapability2;
+  uint16 deviceControl2;
+  uint16 deviceStatus2;
+  uint32 linkCapability2;
+  uint16 linkControl2;
+  uint16 linkStatus2;
+  uint32 slotCapability2;
+  uint16 slotControl2;
+  uint16 slotStatus2;
+  uint32 unused2[6];
+
+  /* PcieErrorRegs */
+  uint16 advErrCapId;
+  uint16 advErrCapOff;
+  uint32 ucErrStatus;
+  uint32 ucorrErrMask;
+  uint32 ucorrErrSevr;
+  uint32 corrErrStatus;
+  uint32 corrErrMask;
+  uint32 advErrCapControl;
+  uint32 headerLog1;
+  uint32 headerLog2;
+  uint32 headerLog3;
+  uint32 headerLog4;
+  uint32 rootErrorCommand;
+  uint32 rootErrorStatus;
+  uint32 rcCorrId;
+  uint32 rcFatalNonfatalId;
+  uint32 unused3[10];
+
+  /* PcieVcRegs */
+  uint16 vcCapId;
+  uint16 vcCapOffset;
+  uint32 prtVcCapability;
+  uint32 portVcCapability2;
+  uint16 portVcControl;
+  uint16 portVcCtatus;
+  uint32 portArbStatus;
+  uint32 vcRsrcControl;
+  uint32 vcRsrcStatus;
+  uint32 unused4[1];
+
+  /* PcieVendor */
+  uint32 vendorCapability;
+  uint32 vendorSpecificHdr;
+} PcieRegs;
+
+typedef struct PcieBlk404Regs{
+  uint32 unused;          /* 0x404 */
+  uint32 config2;         /* 0x408 */
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK         0x0000000f
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE           0  
+  uint32 config3;         /* 0x40c */
+  uint32 pmDataA;         /* 0x410 */
+  uint32 pmDataB;         /* 0x414 */
+} PcieBlk404Regs;
+
+typedef struct PcieBlk428Regs{
+  uint32 vpdIntf;        /* 0x428 */
+  uint16 unused_g;       /* 0x42c */
+  uint16 vpdAddrFlag;    /* 0x42e */
+  uint32 vpdData;        /* 0x430 */
+  uint32 idVal1;         /* 0x434 */
+  uint32 idVal2;         /* 0x438 */
+  uint32 idVal3;         /* 0x43c */
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK                    0xff000000
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT                   24
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK                     0x00ffffff
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT                    16
+#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT                 8
+
+  uint32 idVal4;
+  uint32 idVal5;
+  uint32 unused_h;
+  uint32 idVal6;
+  uint32 msiData;
+  uint32 msiAddr_h;
+  uint32 msiAddr_l;
+  uint32 msiMask;
+  uint32 msiPend;
+  uint32 pmData_c;
+  uint32 msixControl;
+  uint32 msixTblOffBir;
+  uint32 msixPbaOffBit;
+  uint32 unused_k;
+  uint32 pcieCapability;
+  uint32 deviceCapability;
+  uint32 unused_l;
+  uint32 linkCapability;
+  uint32 bar2Config;
+  uint32 pcieDeviceCapability2;
+  uint32 pcieLinkCapability2;
+  uint32 pcieLinkControl;
+  uint32 pcieLinkCapabilityRc;
+  uint32 bar3Config;
+  uint32 rootCap;
+  uint32 devSerNumCapId;
+  uint32 lowerSerNum;
+  uint32 upperSerNum;
+  uint32 advErrCap;
+  uint32 pwrBdgtData0;
+  uint32 pwrBdgtData1;
+  uint32 pwrBdgtData2;
+  uint32 pwdBdgtData3;
+  uint32 pwrBdgtData4;
+  uint32 pwrBdgtData5;
+  uint32 pwrBdgtData6;
+  uint32 pwrBdgtData7;
+  uint32 pwrBdgtCapability;
+  uint32 vsecHdr;
+  uint32 rcUserMemLo1;
+  uint32 rcUserMemHi1;
+  uint32 rcUserMemLo2;
+  uint32 rcUserMemHi2;
+}PcieBlk428Regs;
+
+typedef struct PcieBlk800Regs{
+#define NUM_PCIE_BLK_800_CTRL_REGS  6
+  uint32 tlControl[NUM_PCIE_BLK_800_CTRL_REGS];
+  uint32 tlCtlStat0;
+  uint32 pmStatus0;
+  uint32 pmStatus1;
+
+#define NUM_PCIE_BLK_800_TAGS       32
+  uint32 tlStatus[NUM_PCIE_BLK_800_TAGS];
+  uint32 tlHdrFcStatus;
+  uint32 tlDataFcStatus;
+  uint32 tlHdrFcconStatus;
+  uint32 tlDataFcconStatus;
+  uint32 tlTargetCreditStatus;
+  uint32 tlCreditAllocStatus;
+  uint32 tlSmlogicStatus;
+} PcieBlk800Regs;
+
+
+typedef struct PcieBlk1000Regs{
+#define NUM_PCIE_BLK_1000_PDL_CTRL_REGS  16
+  uint32 pdlControl[NUM_PCIE_BLK_1000_PDL_CTRL_REGS];
+  uint32 dlattnVec;
+  uint32 dlAttnMask;
+  uint32 dlStatus;        /* 0x1048 */
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK                   0x00002000
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT                  13   
+  uint32 dlTxChecksum;
+  uint32 dlForcedUpdateGen1;
+  uint32 mdioAddr;
+  uint32 mdioWrData;
+  uint32 mdioRdData;
+  uint32 dlRxPFcCl;
+  uint32 dlRxCFcCl;
+  uint32 dlRxAckNack;
+  uint32 dlTxRxSeqnb;
+  uint32 dlTxPFcAl;
+  uint32 dlTxNpFcAl;
+  uint32 regDlSpare;
+  uint32 dlRegSpare;
+  uint32 dlTxRxSeq;
+  uint32 dlRxNpFcCl;
+}PcieBlk1000Regs;
+
+typedef struct PcieBlk1800Regs{
+#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS         5
+  uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS];
+#define REG_POWERDOWN_P1PLL_ENA                      (1<<12)
+  uint32 phyErrorAttnVec;
+  uint32 phyErrorAttnMask;
+  uint32 phyReceivedMcpErrors;
+  uint32 phyTransmittedMcpErrors;
+  uint32 phyGenDebug;
+  uint32 phyRecoveryHist;
+#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS   3
+  uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS];
+#define NUM_PCIE_BLK_1800_PHY_DBG_REGS          11
+  uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS];
+} PcieBlk1800Regs;
+
+typedef struct PcieBridgeRegs{
+   uint32 bar1Remap;       /* 0x0818*/
+#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK                    0xffff0000
+#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK_SHIFT              16
+#define PCIE_BRIDGE_BAR1_REMAP_remap_enable                 (1<<1)
+#define PCIE_BRIDGE_BAR1_REMAP_swap_enable                  1
+   
+   uint32 bar2Remap;       /* 0x081c*/
+#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK                    0xffff0000
+#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK_SHIFT              16
+#define PCIE_BRIDGE_BAR2_REMAP_remap_enable                 (1<<1)
+#define PCIE_BRIDGE_BAR2_REMAP_swap_enable                  1
+   
+   uint32 bridgeOptReg1;   /* 0x0820*/
+#define PCIE_BRIDGE_OPT_REG1_en_l1_int_status_mask_polarity  (1<<12)
+#define PCIE_BRIDGE_OPT_REG1_en_pcie_bridge_hole_detection   (1<<11)
+#define PCIE_BRIDGE_OPT_REG1_en_rd_reply_be_fix              (1<<9)
+#define PCIE_BRIDGE_OPT_REG1_enable_rd_be_opt                (1<<7)
+   
+   uint32 bridgeOptReg2;    /* 0x0824*/
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK    0xe0000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT   29
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK     0x1f000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT    24
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK     0x00ff0000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT    16
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK     0x00000080
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT    7
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK     0x00000040
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT    6
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK       0x00000020
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT      5
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK    0x00000010
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT   4
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK   0x00000004
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT  2
+#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK         0x0000ff0b
+
+   uint32 Ubus2PcieBar0BaseMask; /* 0x0828 */
+#define PCIE_BRIDGE_BAR0_BASE_base_MASK                     0xfff00000
+#define PCIE_BRIDGE_BAR0_BASE_base_MASK_SHIFT               20
+#define PCIE_BRIDGE_BAR0_BASE_mask_MASK                     0x0000fff0
+#define PCIE_BRIDGE_BAR0_BASE_mask_MASK_SHIFT               4
+#define PCIE_BRIDGE_BAR0_BASE_swap_enable                   (1<<1)
+#define PCIE_BRIDGE_BAR0_BASE_remap_enable                  1
+
+   uint32 Ubus2PcieBar0RemapAdd; /* 0x082c */   
+#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_MASK               0xfff00000
+#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_SHIFT              20
+   
+   uint32 Ubus2PcieBar1BaseMask; /* 0x0830 */
+#define PCIE_BRIDGE_BAR1_BASE_base_MASK                     0xfff00000
+#define PCIE_BRIDGE_BAR1_BASE_base_MASK_SHIFT               20
+#define PCIE_BRIDGE_BAR1_BASE_mask_MASK                     0x0000fff0
+#define PCIE_BRIDGE_BAR1_BASE_mask_MASK_SHIFT               4
+#define PCIE_BRIDGE_BAR1_BASE_swap_enable                   (1<<1)
+#define PCIE_BRIDGE_BAR1_BASE_remap_enable                  1   
+   
+   uint32 Ubus2PcieBar1RemapAdd; /* 0x0834 */
+#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_MASK               0xfff00000
+#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_SHIFT              20
+   
+   uint32 bridgeErrStatus;       /* 0x0838 */
+   uint32 bridgeErrMask;         /* 0x083c */   
+   uint32 coreErrStatus2;        /* 0x0840 */
+   uint32 coreErrMask2;          /* 0x0844 */
+   uint32 coreErrStatus1;        /* 0x0848 */
+   uint32 coreErrMask1;          /* 0x084c */
+   uint32 rcInterruptStatus;     /* 0x0850 */
+   uint32 rcInterruptMask;       /* 0x0854 */
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_a_MASK   (1<<0)
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_b_MASK   (1<<1)   
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_c_MASK   (1<<2)   
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_d_MASK   (1<<3)   
+      
+}PcieBridgeRegs;
+
+#define PCIEH_DEV_OFFSET              0x8000
+#define PCIEH                         ((volatile uint32 * const) PCIE_BASE)
+#define PCIEH_REGS                    ((volatile PcieRegs * const) PCIE_BASE)
+
+#define PCIEH_BLK_404_REGS            ((volatile PcieBlk404Regs * const) \
+                                        (PCIE_BASE+0x404))
+#define PCIEH_BLK_428_REGS            ((volatile PcieBlk428Regs * const) \
+                                        (PCIE_BASE+0x428))
+#define PCIEH_BLK_800_REGS            ((volatile PcieBlk800Regs * const) \
+                                        (PCIE_BASE+0x800))
+#define PCIEH_BLK_1000_REGS           ((volatile PcieBlk1000Regs * const) \
+                                        (PCIE_BASE+0x1000))
+#define PCIEH_BLK_1800_REGS           ((volatile PcieBlk1800Regs * const) \
+                                        (PCIE_BASE+0x1800))
+#define PCIEH_BRIDGE_REGS             ((volatile PcieBridgeRegs * const)  \
+                                        (PCIE_BASE+0x2818))
+
+typedef struct WlanShimRegs_a0 {
+    uint32 CcIdA;                               /* CC desc A */
+    uint32 CcIdB;                               /* CC desc B */
+    uint32 CcAddr;                              /* CC base addr */
+    uint32 MacIdA;                              /* MAC desc A */
+    uint32 MacIdB;                              /* MAC desc B */
+    uint32 MacAddr;                             /* MAC base addr */
+    uint32 ShimIdA;                             /* SHIM desc A */
+    uint32 ShimIdB;                             /* SHIM desc B */
+    uint32 ShimAddr;                            /* SHIM addr */
+    uint32 ShimEot;                             /* EOT */
+    uint32 CcControl;                           /* CC control */                                                
+    uint32 CcStatus;                            /* CC status */                                                
+    uint32 MacControl;                          /* MAC control */                                                
+    uint32 MacStatus;                           /* MAC status */    
+    uint32 ShimMisc;                            /* SHIM control registers */
+    uint32 ShimStatus;                          /* SHIM status */       
+}WlanShimRegs_a0;
+
+typedef struct WlanShimRegs_b0 {
+    uint32 ShimMisc;                            /* SHIM control registers */
+#define WLAN_SHIM_FORCE_CLOCKS_ON   (1 << 2)
+#define WLAN_SHIM_MACRO_DISABLE     (1 << 1)
+#define WLAN_SHIM_MACRO_SOFT_RESET  (1 << 0)
+
+    uint32 ShimStatus;                          /* SHIM status */       
+
+    uint32 CcControl;                           /* CC control */
+#define SICF_WOC_CORE_RESET         0x10000    
+#define SICF_BIST_EN                0x8000
+#define SICF_PME_EN                 0x4000      
+#define SICF_CORE_BITS              0x3ffc      
+#define SICF_FGC                    0x0002      
+#define SICF_CLOCK_EN               0x0001      
+
+    uint32 CcStatus;                            /* CC status */
+#define SISF_BIST_DONE              0x8000      
+#define SISF_BIST_ERROR             0x4000      
+#define SISF_GATED_CLK              0x2000      
+#define SISF_DMA64                  0x1000      
+#define SISF_CORE_BITS              0x0fff      
+
+    uint32 MacControl;                          /* MAC control */
+    uint32 MacStatus;                           /* MAC status */
+
+    uint32 CcIdA;                               /* CC desc A */
+    uint32 CcIdB;                               /* CC desc B */
+    uint32 CcAddr;                              /* CC base addr */
+    uint32 MacIdA;                              /* MAC desc A */
+    uint32 MacIdB;                              /* MAC desc B */
+    uint32 MacAddr;                             /* MAC base addr */
+    uint32 ShimIdA;                             /* SHIM desc A */
+    uint32 ShimIdB;                             /* SHIM desc B */
+    uint32 ShimAddr;                            /* SHIM addr */
+    uint32 ShimEot;                             /* EOT */                                                                                                                                            
+}WlanShimRegs_b0;
+
+typedef union WlanShimRegs {
+    WlanShimRegs_a0 a0;
+    WlanShimRegs_b0 b0;                            /* SHIM control registers */
+}WlanShimRegs;
+
+#define WLAN_SHIM                   ((volatile WlanShimRegs * const)WLAN_SHIM_BASE)
+
+/*
+** DECT IP Device Registers
+*/
+typedef enum  DECT_SHM_ENABLE_BITS
+{
+   DECT_SHM_IRQ_DSP_INT,
+   DECT_SHM_IRQ_DSP_IRQ_OUT,
+   DECT_SHM_IRQ_DIP_INT,
+   DECT_SHM_H2D_BUS_ERR,
+   DECT_SHM_IRQ_TX_DMA_DONE,                 
+   DECT_SHM_IRQ_RX_DMA_DONE,
+   DECT_SHM_IRQ_PLL_PHASE_LOCK = DECT_SHM_IRQ_RX_DMA_DONE + 2, /* Skip reserved bit */
+   DECT_SHM_REG_DSP_BREAK,
+   DECT_SHM_REG_DIP_BREAK,
+   DECT_SHM_REG_IRQ_TO_IP = DECT_SHM_REG_DIP_BREAK + 2, /* Skip reserved bit */
+   DECT_SHM_TX_DMA_DONE_TO_IP,
+   DECT_SHM_RX_DMA_DONE_TO_IP, 
+} DECT_SHM_ENABLE_BITS;
+
+typedef struct DECTShimControl 
+{
+   uint32 dect_shm_ctrl;                     /*  0xb000b000  DECT shim control registers                    */
+#define APB_SWAP_MASK             0x0000C000
+#define APB_SWAP_16_BIT           0x00000000
+#define APB_SWAP_8_BIT            0x00004000
+#define AHB_SWAP_MASK             0x00003000
+#define AHB_SWAP_16_BIT           0x00003000
+#define AHB_SWAP_8_BIT            0x00002000
+#define AHB_SWAP_ACCESS           0x00001000
+#define AHB_SWAP_NONE             0x00000000
+#define DECT_PULSE_COUNT_ENABLE   0x00000200
+#define PCM_PULSE_COUNT_ENABLE    0x00000100
+#define DECT_SOFT_RESET           0x00000010
+#define PHCNT_CLK_SRC_PLL         0x00000008
+#define PHCNT_CLK_SRC_XTAL        0x00000000
+#define DECT_CLK_OUT_PLL          0x00000004
+#define DECT_CLK_OUT_XTAL         0x00000000
+#define DECT_CLK_CORE_PCM         0x00000002
+#define DECT_CLK_CORE_DECT        0x00000000
+#define DECT_PLL_REF_PCM          0x00000001
+#define DECT_PLL_REF_DECT         0x00000000
+
+   uint32 dect_shm_pcm_clk_cntr;             /*  0xb000b004  PCM clock counter                              */
+   uint32 dect_shm_dect_clk_cntr;            /*  0xb000b008  DECT clock counter                             */
+   uint32 dect_shm_dect_clk_cntr_sh;         /*  0xb000b00c  DECT clock counter snapshot                    */
+   uint32 dect_shm_irq_enable;               /*  0xb000b010  DECT interrupt enable register                 */
+   uint32 dect_shm_irq_status;               /*  0xb000b014  DECT Interrupt status register                 */
+   uint32 dect_shm_irq_trig;                 /*  0xb000b018  DECT DSP ext IRQ trigger and IRQ test register */
+   uint32 dect_shm_dma_status;               /*  0xb000b01c  DECT DMA STATUS register                       */
+   uint32 dect_shm_xtal_ctrl;                /*  0xb000b020  DECT analog tunable XTAL control register      */
+   uint32 dect_shm_bandgap_ctrl;             /*  0xb000b024  DECT analog bandgap control register           */
+   uint32 dect_shm_afe_tx_ctrl;              /*  0xb000b028  DECT analog TX DAC control register            */
+   uint32 dect_shm_afe_test_ctrl;            /*  0xb000b02c  DECT analog test control register              */
+   uint32 dect_shm_pll_reg_0;                /*  0xb000b030  DECT PLL configuration register 0              */
+   uint32 dect_shm_pll_reg_1;                /*  0xb000b034  DECT PLL configuration register 1              */
+#define  PLL_PWRDWN                          0x01000000   
+#define  PLL_REFCOMP_PWRDOWN                 0x02000000
+#define  PLL_NDIV_PWRDOWN                    0x04000000
+#define  PLL_CH1_PWRDOWN                     0x08000000
+#define  PLL_CH2_PWRDOWN                     0x10000000
+#define  PLL_CH3_PWRDOWN                     0x20000000
+#define  PLL_DRESET                          0x40000000
+#define  PLL_ARESET                          0x80000000
+
+   uint32 dect_shm_pll_reg_2;                /*  0xb000b038  DECT PLL Ndiv configuration register           */
+   uint32 dect_shm_pll_reg_3;                /*  0xb000b03c  DECT PLL Pdiv and Mdiv configuration register  */
+} DECTShimControl;
+
+#define DECT_CTRL ((volatile DECTShimControl * const) DECT_SHIM_CTRL_BASE)
+
+typedef struct DECTShimDmaControl 
+{
+   uint32 dect_shm_dma_ctrl;                 /*  0xb000b050  DECT DMA control register                      */
+#define  DMA_CLEAR                           0x80000000
+#define  DMA_SWAP_16_BIT                     0x03000000
+#define  DMA_SWAP_8_BIT                      0x02000000
+#define  DMA_SWAP_NONE                       0x01000000
+#define  DMA_SUBWORD_SWAP_MASK               0x03000000
+#define  TRIG_CNT_CLK_SEL_PCM                0x00800000
+#define  TRIG_CNT_IRQ_EN                     0x00400000
+#define  RX_CNT_TRIG_EN                      0x00200000   
+#define  TX_CNT_TRIG_EN                      0x00100000 
+#define  RX_INT_TRIG_EN                      0x00080000 	
+#define  TX_INT_TRIG_EN                      0x00040000 	
+#define  RX_REG_TRIG_EN                      0x00020000 	
+#define  TX_REG_TRIG_EN                      0x00010000 
+#define  RX_TRIG_FIRST                       0x00008000
+#define  MAX_BURST_CYCLE_MASK                0x00001F00
+#define  MAX_BURST_CYCLE_SHIFT               8
+#define  RX_EN_3                             0x00000080   
+#define  RX_EN_2                             0x00000040   
+#define  RX_EN_1                             0x00000020   
+#define  RX_EN_0                             0x00000010   
+#define  TX_EN_3                             0x00000008   
+#define  TX_EN_2                             0x00000004   
+#define  TX_EN_1                             0x00000002   
+#define  TX_EN_0                             0x00000001   
+ 
+   uint32 dect_shm_dma_trig_cnt_preset;      /*  0xb000b054  DECT DMA trigger counter preset value                */
+   uint32 dect_shm_dma_ddr_saddr_tx_s0;      /*  0xb000b058  DECT DMA DDR buffer starting address for TX slot 0   */
+   uint32 dect_shm_dma_ddr_saddr_tx_s1;      /*  0xb000b05c  DECT DMA DDR buffer starting address for TX slot 1   */
+   uint32 dect_shm_dma_ddr_saddr_tx_s2;      /*  0xb000b060  DECT DMA DDR buffer starting address for TX slot 2   */
+   uint32 dect_shm_dma_ddr_saddr_tx_s3;      /*  0xb000b064  DECT DMA DDR buffer starting address for TX slot 3   */
+   uint32 dect_shm_dma_ddr_saddr_rx_s0;      /*  0xb000b068  DECT DMA DDR buffer starting address for RX slot 0   */
+   uint32 dect_shm_dma_ddr_saddr_rx_s1;      /*  0xb000b06c  DECT DMA DDR buffer starting address for RX slot 1   */
+   uint32 dect_shm_dma_ddr_saddr_rx_s2;      /*  0xb000b070  DECT DMA DDR buffer starting address for RX slot 2   */
+   uint32 dect_shm_dma_ddr_saddr_rx_s3;      /*  0xb000b074  DECT DMA DDR buffer starting address for RX slot 3   */
+   uint32 dect_shm_dma_ahb_saddr_tx_s01;     /*  0xb000b078  DECT DMA AHB shared memory buffer starting address for TX slots 0 and 1  */
+   uint32 dect_shm_dma_ahb_saddr_tx_s23;     /*  0xb000b07c  DECT DMA AHB shared memory buffer starting address for TX slots 2 and 3  */
+   uint32 dect_shm_dma_ahb_saddr_rx_s01;     /*  0xb000b080  DECT DMA AHB shared memory buffer starting address for RX slots 0 and 1  */
+   uint32 dect_shm_dma_ahb_saddr_rx_s23;     /*  0xb000b084  DECT DMA AHB shared memory buffer starting address for RX slots 2 and 3  */
+   uint32 dect_shm_dma_xfer_size_tx;         /*  0xb000b088  DECT DMA TX slots transfer size of each trigger      */
+   uint32 dect_shm_dma_xfer_size_rx;         /*  0xb000b08c  DECT DMA RX slots transfer size of each trigger      */
+   uint32 dect_shm_dma_buf_size_tx;          /*  0xb000b090  DECT DMA TX slots memory buffer size                 */
+   uint32 dect_shm_dma_buf_size_rx;          /*  0xb000b094  DECT DMA RX slots memory buffer size                 */
+   uint32 dect_shm_dma_offset_addr_tx_s01;   /*  0xb000b098  DECT DMA access offset address for TX slots 0 and 1  */
+   uint32 dect_shm_dma_offset_addr_tx_s23;   /*  0xb000b09c  DECT DMA access offset address for TX slots 2 and 3  */
+   uint32 dect_shm_dma_offset_addr_rx_s01;   /*  0xb000b0a0  DECT DMA access offset address for RX slots 0 and 1  */
+   uint32 dect_shm_dma_offset_addr_rx_s23;   /*  0xb000b0a4  DECT DMA access offset address for RX slots 2 and 3  */
+   uint32 dect_shm_dma_xfer_cntr_tx;         /*  0xb000b0a8  DECT DMA transfer count per slot in number of DMA transfer size */
+   uint32 dect_shm_dma_xfer_cntr_rx;         /*  0xb000b0a8  DECT DMA transfer count per slot in number of DMA transfer size */   
+} DECTShimDmaControl;
+
+#define DECT_DMA_CTRL ((volatile DECTShimDmaControl * const) DECT_SHIM_DMA_CTRL_BASE)
+
+
+typedef struct ahbRegisters
+{
+   uint16 dsp_main_sync0;     /* 0xb0e57f80 DSP main counter outputs sel reg 0 */
+   uint16 dsp_main_sync1;     /* 0xb0e57f82 DSP main counter outputs sel reg 1 */
+   uint16 dsp_main_cnt;       /* 0xb0e57f84 DSP main counter reg */
+   uint16 reserved1;          /* 0xb0e57f86 Reserved */
+   uint16 reserved2;          /* 0xb0e57f88 Reserved */
+   uint16 reserved3;          /* 0xb0e57f8a Reserved */
+   uint16 reserved4;          /* 0xb0e57f8c Reserved */
+   uint16 reserved5;          /* 0xb0e57f8e Reserved */
+   uint16 reserved6;          /* 0xb0e57f90 Reserved */
+   uint16 dsp_ram_out0;       /* 0xb0e57f92 DSP RAM output register 0 */
+   uint16 dsp_ram_out1;       /* 0xb0e57f94 DSP RAM output register 1 */
+   uint16 dsp_ram_out2;       /* 0xb0e57f96 DSP RAM output register 2 */
+   uint16 dsp_ram_out3;       /* 0xb0e57f98 DSP RAM output register 3 */
+   uint16 dsp_ram_in0;        /* 0xb0e57f9a DSP RAM input register 0 */
+   uint16 dsp_ram_in1;        /* 0xb0e57f9c DSP RAM input register 1 */
+   uint16 dsp_ram_in2;        /* 0xb0e57f9e DSP RAM input register 2 */
+   uint16 dsp_ram_in3;        /* 0xb0e57fa0 DSP RAM input register 3 */
+   uint16 dsp_zcross1_out;    /* 0xb0e57fa2 DSP RAM zero crossing 1 output reg */
+   uint16 dsp_zcross2_out;    /* 0xb0e57fa4 DSP RAM zero crossing 2 output reg */
+   uint16 reserved7;          /* 0xb0e57fa6 Reserved */
+   uint16 reserved8;          /* 0xb0e57fa8 Reserved */
+   uint16 reserved9;          /* 0xb0e57faa Reserved */
+   uint16 reserved10;         /* 0xb0e57fac Reserved */
+   uint16 reserved11;         /* 0xb0e57fae Reserved */
+   uint16 reserved12;         /* 0xb0e57fb0 Reserved */
+   uint16 reserved13;         /* 0xb0e57fb2 Reserved */
+   uint16 reserved14;         /* 0xb0e57fb4 Reserved */
+   uint16 reserved15;         /* 0xb0e57fb6 Reserved */
+   uint16 reserved16;         /* 0xb0e57fb8 Reserved */
+   uint16 reserved17;         /* 0xb0e57fba Reserved */
+   uint16 dsp_main_ctrl;      /* 0xb0e57fbc DSP main counter control and preset reg */
+   uint16 reserved18;         /* 0xb0e57fbe Reserved */
+   uint16 reserved19;         /* 0xb0e57fc0 Reserved */
+   uint16 reserved20;         /* 0xb0e57fc2 Reserved */
+   uint16 reserved21;         /* 0xb0e57fc4 Reserved */
+   uint16 reserved22;         /* 0xb0e57fc6 Reserved */
+   uint16 reserved23;         /* 0xb0e57fc8 Reserved */
+   uint16 reserved24;         /* 0xb0e57fca Reserved */
+   uint16 reserved25;         /* 0xb0e57fce Reserved */
+   uint16 dsp_ctrl;           /* 0xb0e57fd0 DSP control reg */
+   uint16 dsp_pc;             /* 0xb0e57fd2 DSP program counter */
+   uint16 dsp_pc_start;       /* 0xb0e57fd4 DSP program counter start */
+   uint16 dsp_irq_start;      /* 0xb0e57fd6 DSP interrupt vector start */
+   uint16 dsp_int;            /* 0xb0e57fd8 DSP to system bus interrupt vector */
+   uint16 dsp_int_mask;       /* 0xb0e57fda DSP to system bus interrupt vector mask */
+   uint16 dsp_int_prio1;      /* 0xb0e57fdc DSP interrupt mux 1 */
+   uint16 dsp_int_prio2;      /* 0xb0e57fde DSP interrupt mux 2 */
+   uint16 dsp_overflow;       /* 0xb0e57fe0 DSP to system bus interrupt overflow reg */
+   uint16 dsp_jtbl_start;     /* 0xb0e57fe2 DSP jump table start address */
+   uint16 reserved26;         /* 0xb0e57fe4 Reserved */
+   uint16 reserved27;         /* 0xb0e57fe6 Reserved */
+   uint16 reserved28;         /* 0xb0e57fe8 Reserved */
+   uint16 reserved29;         /* 0xb0e57fea Reserved */
+   uint16 reserved30;         /* 0xb0e57fec Reserved */
+   uint16 reserved31;         /* 0xb0e57fee Reserved */
+   uint16 dsp_debug_inst;     /* 0xb0e57ff0 DSP debug instruction register */
+   uint16 reserved32;         /* 0xb0e57ff2 Reserved */
+   uint16 dsp_debug_inout_l;  /* 0xb0e57ff4 DSP debug data (LSW) */
+   uint16 dsp_debug_inout_h;  /* 0xb0e57ff6 DSP debug data (MSW) */
+   uint16 reserved33;         /* 0xb0e57ff8 Reserved */
+   uint16 reserved34;         /* 0xb0e57ffa Reserved */
+   uint16 reserved35;         /* 0xb0e57ffc Reserved */
+   uint16 reserved36;         /* 0xb0e57ffe Reserved */
+} ahbRegisters;
+
+#define AHB_REGISTERS ((volatile ahbRegisters * const) DECT_AHB_REG_BASE)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/shared/broadcom/include/bcm963xx/6368_common.h b/shared/broadcom/include/bcm963xx/6368_common.h
new file mode 100755
index 0000000..1df5be5
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/6368_common.h
@@ -0,0 +1,270 @@
+/*
+<:copyright-broadcom 
+ 
+ Copyright (c) 2007 Broadcom Corporation 
+ All Rights Reserved 
+ No portions of this material may be reproduced in any form without the 
+ written permission of: 
+          Broadcom Corporation 
+          16215 Alton Parkway 
+          Irvine, California 92619 
+ All information contained in this document is Broadcom Corporation 
+ company private, proprietary, and trade secret. 
+ 
+:>
+*/
+/***********************************************************************/
+/*                                                                     */
+/*   MODULE:  6368_common.h                                             */
+/*   DATE:    02/06/07                                                 */
+/*   PURPOSE: Define addresses of major hardware components of         */
+/*            BCM6368                                                  */
+/*                                                                     */
+/***********************************************************************/
+#ifndef __BCM6368_MAP_COMMON_H
+#define __BCM6368_MAP_COMMON_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PERF_BASE            0xb0000000  /* chip control registers */
+#define TIMR_BASE            0xb0000040  /* timer registers */
+#define NAND_INTR_BASE       0xb0000070  /* nand interrupt control registers */
+#define GPIO_BASE            0xb0000080  /* gpio registers */
+#define UART_BASE            0xb0000100  /* uart registers */
+#define UART1_BASE           0xb0000120  /* uart registers */
+#define NAND_REG_BASE        0xb0000200
+#define NAND_SEC_BASE        0xb0000300
+#define OTP_BASE             0xb0000400
+#define UBUS_STAT_BASE       0xb0000500
+#define NAND_CACHE_BASE      0xb0000600
+#define SPI_BASE             0xb0000800  /* SPI master controller registers */
+#define MPI_BASE             0xb0001000  /* MPI control registers */
+#define MEMC_BASE            0xb0001200  /* Memory control registers */
+#define DDR_BASE             0xb0001280  /* DDR IO Buf Control registers */
+#define USB_CTL_BASE         0xb0001400  /* USB 2.0 device control registers */
+#define USB_EHCI_BASE        0x10001500  /* USB host registers */
+#define USB_OHCI_BASE        0x10001600  /* USB host registers */
+#define USBH_CFG_BASE        0xb0001700
+#define SAR_BASE             0xb0001800  /* ATM SAR control registers */
+#define SAR_CMF_BASE         0xb0002000  /* ATM SAR CMF control registers */
+#define PCM_BASE             0xb0004000  /* PCM control registers */
+#define IPSEC_BASE           0xb0004100
+#define USB_DMA_BASE         0xb0004800  /* USB 2.0 device DMA regiseters */
+#define SAR_DMA_BASE         0xb0005000  /* ATM SAR DMA control registers */
+#define PCM_DMA_BASE         0xb0005800  /* PCM UIDMA register base */
+#define IPSEC_DMA_BASE       0xb0006000
+#define SWITCH_DMA_BASE      0xb0006800
+#define SWITCH_BASE          0xb0f00000
+#define SWITCH_CMF_BASE      0xb0f0a000  /* Switch CMF register base */
+
+#define ADSL_PHY_BASE        0xb0f40000
+#define ADSL_ENUM_BASE       0xb0f56000
+#define ADSL_LMEM_BASE       0xb0f80000
+
+/*
+#####################################################################
+# System PLL Control Register
+#####################################################################
+*/
+
+
+/*
+#####################################################################
+# GPIO Control Registers
+#####################################################################
+*/
+
+
+/*
+#####################################################################
+# Memory Control Registers
+#####################################################################
+*/
+#define MEMC_CONTROL             0x0
+#define MEMC_CONFIG              0x4
+#define MEMC_REF_PD_CONTROL      0x8
+#define MEMC_BIST_STATUS         0xc
+#define MEMC_M_EM_BUF           0x10
+#define MEMC_BANK_CLS_TIM       0x14
+#define MEMC_PRIOR_INV_TIM      0x18
+#define MEMC_DRAM_TIM           0x1c
+#define MEMC_INT_STATUS         0x20
+#define MEMC_INT_MASK           0x24
+#define MEMC_INT_INFO           0x28
+#define MEMC_BARRIER            0x50
+#define MEMC_CORE_ID            0x54
+
+#define DDR_REV_ID               0x0
+#define DDR_PAD_SSTL_MODE        0x4
+#define DDR_CMD_PAD_CNTL         0x8
+#define DDR_DQ_PAD_CNTL          0xc
+#define DDR_DQS_PAD_CNTL        0x10    
+#define DDR_CLK_PAD_CNTL        0x14
+#define DDR_PLL_CNTL0           0x18
+#define DDR_PLL_CNTL1           0x1c
+#define DDR_MIPSDDR_PLL_CONFIG  0x20
+#define DDR_MIPSDDR_PLL_MDIV    0x24
+#define DDR_DSL_PHY_PHASE_CNTL  0x28
+#define DDR_DSL_CPU_PHASE_CNTL  0x2c
+#define DDR_MIPS_PHASE_CNTL     0x30
+#define DDR_DDR1_2_PHASE_CNTL   0x34
+#define DDR_DDR3_4_PHASE_CNTL   0x38    
+#define DDR_VCDL_PHASE_CNTL0    0x3c
+#define DDR_VCDL_PHASE_CNTL1    0x40
+#define DDR_BSLICE_CNTL         0x44
+#define DDR_DESKEW_DLL_CNTL     0x48
+#define DDR_DESKEW_DLL_RESET    0x4c
+#define DDR_DESKEW_DLL_PHASE    0x50
+#define DDR_ANALOG_TEST_CNTL    0x54
+#define DDR_RD_DQS_GATE_CNTL    0x58
+#define DDR_MISC                0x5c
+#define DDR_SPARE0              0x60
+#define DDR_SPARE1              0x64
+#define DDR_SPARE2              0x68
+#define DDR_CLBIST              0x6c    
+#define DDR_LBIST_CRC           0x70
+#define DDR_UBUS_PHASE_CNTR     0x74
+#define DDR_UBUS_PI_DSK0        0x78
+#define DDR_UBUS_PI_DSK1        0x7c
+
+// Some bit/field definitions for the MEMC_CONFIG register.
+#define MEMC_EARLY_HDR_CNT_SHFT 25
+#define MEMC_EARLY_HDR_CNT_MASK (0x7<<MEMC_EARLYHDRCNT_SHFT)
+#define MEMC_USE_HDR_CNT        (1<<24)
+#define MEMC_EN_FAST_REPLY      (1<<23)
+#define MEMC_RR_ARB             (1<<22)
+#define MEMC_SFX_NO_MRS2        (1<<21)
+#define MEMC_SFX_NO_DLL_RST     (1<<20)
+#define MEMC_LLMB_ONE_REQ       (1<<19)
+#define MEMC_SYS_PORT_CMD_MODE  (1<<18)
+#define MEMC_PAD_OP_MODE        (1<<17)
+#define MEMC_DQS_GATE_EN        (1<<16)
+#define MEMC_PRED_RD_STROBE_EN  (1<<15)
+#define MEMC_PRED_RD_LATENCY_SEL (1<<14)
+#define MEMC_UBUS_CLF_EN        (1<<8)
+
+#define MEMC_ROW_SHFT           6
+#define MEMC_ROW_MASK           (0x3<<MEMC_ROW_SHFT)
+#define MEMC_11BIT_ROW          0
+#define MEMC_12BIT_ROW          1
+#define MEMC_13BIT_ROW          2
+#define MEMC_14BIT_ROW          3
+
+#define MEMC_COL_SHFT           3
+#define MEMC_COL_MASK           (0x7<<MEMC_COL_SHFT)
+#define MEMC_8BIT_COL           0
+#define MEMC_9BIT_COL           1
+#define MEMC_10BIT_COL          2
+#define MEMC_11BIT_COL          3
+
+#define MEMC_SEL_PRIORITY       (1<<2)
+
+#define MEMC_WIDTH_SHFT         1
+#define MEMC_WIDTH_MASK         (0x1<<MEMC_WIDTH_SHFT)
+#define MEMC_32BIT_BUS          0
+#define MEMC_16BIT_BUS          1
+
+#define MEMC_MEMTYPE_SDR        (0<<0)
+#define MEMC_MEMTYPE_DDR        (1<<0)
+
+/*
+#####################################################################
+# MPI Control Registers
+#####################################################################
+*/
+#define CS0BASE         0x00
+#define CS0CNTL         0x04
+
+/*
+# CSxBASE settings
+#   Size in low 4 bits
+#   Base Address for match in upper 24 bits
+*/
+#define EBI_SIZE_8K         0
+#define EBI_SIZE_16K        1
+#define EBI_SIZE_32K        2
+#define EBI_SIZE_64K        3
+#define EBI_SIZE_128K       4
+#define EBI_SIZE_256K       5
+#define EBI_SIZE_512K       6
+#define EBI_SIZE_1M         7
+#define EBI_SIZE_2M         8
+#define EBI_SIZE_4M         9
+#define EBI_SIZE_8M         10
+#define EBI_SIZE_16M        11
+#define EBI_SIZE_32M        12
+#define EBI_SIZE_64M        13
+#define EBI_SIZE_128M       14
+#define EBI_SIZE_256M       15
+
+/* CSxCNTL settings */
+#define EBI_ENABLE          0x00000001  /* .. enable this range */
+#define EBI_WAIT_STATES     0x0000000e  /* .. mask for wait states */
+#define ZEROWT              0x00000000  /* ..  0 WS */
+#define ONEWT               0x00000002  /* ..  1 WS */
+#define TWOWT               0x00000004  /* ..  2 WS */
+#define THREEWT             0x00000006  /* ..  3 WS */
+#define FOURWT              0x00000008  /* ..  4 WS */
+#define FIVEWT              0x0000000a  /* ..  5 WS */
+#define SIXWT               0x0000000c  /* ..  6 WS */
+#define SEVENWT             0x0000000e  /* ..  7 WS */
+#define EBI_WORD_WIDE       0x00000010  /* .. 16-bit peripheral, else 8 */
+#define EBI_TS_TA_MODE      0x00000080  /* .. use TS/TA mode */
+#define EBI_TS_SEL          0x00000100  /* .. drive tsize, not bs_b */
+#define EBI_FIFO            0x00000200  /* .. enable fifo */
+#define EBI_RE              0x00000400  /* .. Reverse Endian */
+
+/*
+#####################################################################
+# UART Control Registers
+#####################################################################
+*/
+#define UART0CONTROL     0x01
+#define UART0CONFIG      0x02
+#define UART0RXTIMEOUT   0x03
+#define UART0BAUD        0x04
+#define UART0FIFOCFG     0x0a
+#define UART0INTMASK     0x10
+#define UART0INTSTAT     0x12
+#define UART0DATA        0x17
+
+#define BRGEN            0x80   /* Control register bit defs */
+#define TXEN             0x40
+#define RXEN             0x20
+#define LOOPBK           0x10
+#define TXPARITYEN       0x08
+#define TXPARITYEVEN     0x04
+#define RXPARITYEN       0x02
+#define RXPARITYEVEN     0x01
+
+#define XMITBREAK        0x40   /* Config register */
+#define BITS5SYM         0x00
+#define BITS6SYM         0x10
+#define BITS7SYM         0x20
+#define BITS8SYM         0x30
+#define ONESTOP          0x07
+#define TWOSTOP          0x0f
+
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/shared/broadcom/include/bcm963xx/6368_map.h b/shared/broadcom/include/bcm963xx/6368_map.h
new file mode 100755
index 0000000..590e06d
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/6368_map.h
@@ -0,0 +1,1592 @@
+/*
+<:copyright-broadcom 
+ 
+ Copyright (c) 2007 Broadcom Corporation 
+ All Rights Reserved 
+ No portions of this material may be reproduced in any form without the 
+ written permission of: 
+          Broadcom Corporation 
+          16215 Alton Parkway 
+          Irvine, California 92619 
+ All information contained in this document is Broadcom Corporation 
+ company private, proprietary, and trade secret. 
+ 
+:>
+*/
+/***********************************************************************/
+/*                                                                     */
+/*   MODULE:  6368_map.h                                               */
+/*   DATE:    02/06/07                                                 */
+/*   PURPOSE: Define addresses of major hardware components of         */
+/*            BCM6368                                                  */
+/*                                                                     */
+/***********************************************************************/
+#ifndef __BCM6368_MAP_H
+#define __BCM6368_MAP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bcmtypes.h"
+#include "6368_common.h"
+#include "6368_intr.h"
+
+/* macro to convert logical data addresses to physical */
+/* DMA hardware must see physical address */
+#define LtoP( x )       ( (uint32)x & 0x1fffffff )
+#define PtoL( x )       ( LtoP(x) | 0xa0000000 )
+
+typedef struct MemoryControl
+{
+    uint32 Control;             /* (00) */
+#define MEMC_SELF_REFRESH    (1<<6) // enable self refresh mode
+#define MEMC_MRS             (1<<4) // generate a mode register select cycle
+#define MEMC_PRECHARGE       (1<<3) // generate a precharge cycle
+#define MEMC_REFRESH         (1<<2) // generate an auto refresh cycle
+#define MEMC_SEQUENCE_ENABLE (1<<1) // enable memory controller sequencer
+#define MEMC_MASTER_ENABLE   (1<<0) // enable accesses to external sdram
+
+    uint32  Config;             /* (04) */
+#define MEMC_EARLY_HDR_CNT_SHFT 25
+#define MEMC_EARLY_HDR_CNT_MASK (0x7<<MEMC_EARLYHDRCNT_SHFT)
+#define MEMC_USE_HDR_CNT        (1<<24)
+#define MEMC_EN_FAST_REPLY      (1<<23)
+#define MEMC_RR_ARB             (1<<22)
+#define MEMC_SFX_NO_MRS2        (1<<21)
+#define MEMC_SFX_NO_DLL_RST     (1<<20)
+#define MEMC_LLMB_ONE_REQ       (1<<19)
+#define MEMC_SYS_PORT_CMD_MODE  (1<<18)
+#define MEMC_PAD_OP_MODE        (1<<17)
+#define MEMC_DQS_GATE_EN        (1<<16)
+#define MEMC_PRED_RD_STROBE_EN  (1<<15)
+#define MEMC_PRED_RD_LATENCY_SEL (1<<14)
+#define MEMC_UBUS_CLF_EN        (1<<8)
+
+#define MEMC_ROW_SHFT           6
+#define MEMC_ROW_MASK           (0x3<<MEMC_ROW_SHFT)
+#define MEMC_11BIT_ROW          0
+#define MEMC_12BIT_ROW          1
+#define MEMC_13BIT_ROW          2
+#define MEMC_14BIT_ROW          3
+
+#define MEMC_COL_SHFT           3
+#define MEMC_COL_MASK           (0x7<<MEMC_COL_SHFT)
+#define MEMC_8BIT_COL           0
+#define MEMC_9BIT_COL           1
+#define MEMC_10BIT_COL          2
+#define MEMC_11BIT_COL          3
+
+#define MEMC_SEL_PRIORITY       (1<<2)
+
+#define MEMC_WIDTH_SHFT         1
+#define MEMC_WIDTH_MASK         (0x1<<MEMC_WIDTH_SHFT)
+#define MEMC_32BIT_BUS          0
+#define MEMC_16BIT_BUS          1
+
+#define MEMC_MEMTYPE_SDR        (0<<0)
+#define MEMC_MEMTYPE_DDR        (1<<0)
+
+    uint32  RefreshPdControl;   /* (08) */ 
+#define MEMC_REFRESH_ENABLE     (1<<15)
+
+    uint32  BistStatus;         /* (0C) */
+    uint32  ExtendedModeBuffer; /* (10) */
+    uint32  BankClosingTimer;   /* (14) */
+    uint32  PriorityInversionTimer; /* (18) */
+
+    uint32  DramTiming;         /* (1c) */
+#define MEMC_WR_NOP_RD        (1<<23)
+#define MEMC_WR_NOP_WR        (1<<22)
+#define MEMC_RD_NOP_WR        (1<<21)
+#define MEMC_RD_NOP_RD        (1<<20)
+#define MEMC_CAS_LATENCY_2    (0)
+#define MEMC_CAS_LATENCY_2_5  (1)
+#define MEMC_CAS_LATENCY_3    (2)
+
+    uint32  IntStatus;          /* (20) */
+    uint32  IntMask;            /* (24) */
+#define MEMC_INT3             (1<<3)
+#define MEMC_INT2             (2<<3)
+#define MEMC_INT1             (1<<3)
+#define MEMC_INT0             (0<<3)
+
+    uint32  IntInfo;            /* (28) */
+    uint8   unused5[0x50-0x2c]; /* (2c) */
+    uint32  Barrier;            /* (50) */
+    uint32  CoreId;             /* (54) */
+} MemoryControl;
+
+#define MEMC ((volatile MemoryControl * const) MEMC_BASE)
+
+typedef struct DDRControl {
+    uint32    RevID;            /* 00 */
+    uint32    PadSSTLMode;      /* 04 */
+    uint32    CmdPadCntl;       /* 08 */
+    uint32    DQPadCntl;        /* 0c */
+    uint32    DQSPadCntl;       /* 10 */
+    uint32    ClkPadCntl0;      /* 14 */
+    uint32    MIPSDDRPLLCntl0;  /* 18 */
+    uint32    MIPSDDRPLLCntl1;  /* 1c */
+    uint32    MIPSDDRPLLConfig; /* 20 */
+#define MIPSDDR_NDIV_SHFT       16
+#define MIPSDDR_NDIV_MASK       (0x1ff<<MIPSDDR_NDIV_SHFT)
+#define REF_MDIV_SHFT           8
+#define REF_MDIV_MASK           (0xff<<REF_MDIV_SHFT)
+#define MIPSDDR_P2_SHFT         4
+#define MIPSDDR_P2_MASK         (0xf<<MIPSDDR_P2_SHFT)
+#define MIPSDDR_P1_SHFT         0
+#define MIPSDDR_P1_MASK         (0xf<<MIPSDDR_P1_SHFT)
+    uint32    MIPSDDRPLLMDiv;   /* 24 */
+#define DDR_MDIV_SHFT           8
+#define DDR_MDIV_MASK           (0xff<<DDR_MDIV_SHFT)
+#define MIPS_MDIV_SHFT          0
+#define MIPS_MDIV_MASK          (0xff<<MIPS_MDIV_SHFT)
+    uint32    DSLCorePhaseCntl; /* 28 */
+    uint32    DSLCpuPhaseCntr;  /* 2c */
+#define DSL_PHY_AFE_PI_CNTR_CYCLES_SHIFT    28
+#define DSL_PHY_AFE_PI_CNTR_CYCLES_MASK     (0xF << DSL_PHY_AFE_PI_CNTR_CYCLES_SHIFT)
+#define DSL_PHY_PI_CNTR_CYCLES_SHIFT        24
+#define DSL_PHY_PI_CNTR_CYCLES_MASK         (0xF << DSL_PHY_PI_CNTR_CYCLES_SHIFT)
+#define DSL_PHY_AFE_PI_CNTR_EN              (1 << 22)
+#define DSL_PHY_PI_CNTR_EN                  (1 << 21)
+#define DSL_CPU_PI_CNTR_EN                  (1 << 20)
+#define DSL_CPU_PI_CNTR_CYCLES_SHIFT    16
+#define DSL_CPU_PI_CNTR_CYCLES_MASK (0xF << DSL_CPU_PI_CNTR_CYCLES_SHIFT)
+    uint32    MIPSPhaseCntl;    /* 30 */
+#define PH_CNTR_EN              (1 << 20)
+    uint32    DDR1_2PhaseCntl0; /* 34 */
+    uint32    DDR3_4PhaseCntl0; /* 38 */
+    uint32    VCDLPhaseCntl0;   /* 3c */
+    uint32    VCDLPhaseCntl1;   /* 40 */
+    uint32    WSliceCntl;       /* 44 */
+    uint32    DeskewDLLCntl;    /* 48 */
+    uint32    DeskewDLLReset;   /* 4c */
+    uint32    DeskewDLLPhase;   /* 50 */
+    uint32    AnalogTestCntl;   /* 54 */
+    uint32    RdDQSGateCntl;    /* 58 */
+    uint32    PLLTestReg;       /* 5c */
+    uint32    Spare0;           /* 60 */
+    uint32    Spare1;           /* 64 */
+    uint32    Spare2;           /* 68 */
+    uint32    CLBist;           /* 6c */
+    uint32    LBistCRC;         /* 70 */
+    uint32    UBUSPhaseCntl;    /* 74 */
+    uint32    UBUSPIDeskewLLMB0; /* 78 */
+    uint32    UBUSPIDeskewLLMB1; /* 7C */
+
+} DDRControl;
+
+#define DDR ((volatile DDRControl * const) DDR_BASE)
+
+/*
+** Peripheral Controller
+*/
+
+#define IRQ_BITS 64
+typedef struct  {
+    uint64		  IrqMask;
+    uint64		  IrqStatus;
+} IrqControl_t;
+
+typedef struct PerfControl {
+     uint32        RevID;             /* (00) word 0 */
+     uint32        blkEnables;        /* (04) word 1 */
+#define USBH_IDDQ_EN     (1 << 19)
+#define IPSEC_CLK_EN     (1 << 18)
+#define NAND_CLK_EN      (1 << 17)
+#define DISABLE_GLESS    (1 << 16)
+#define USBH_CLK_EN      (1 << 15)
+#define PCM_CLK_EN       (1 << 14)
+#define UTOPIA_CLK_EN    (1 << 13)
+#define ROBOSW_CLK_EN    (1 << 12)
+#define SAR_CLK_EN       (1 << 11)
+#define USBD_CLK_EN      (1 << 10)
+#define SPI_CLK_EN       (1 << 9)
+#define SWPKT_SAR_CLK_EN (1 << 8)
+#define SWPKT_USB_CLK_EN (1 << 7)
+#define PHYMIPS_CLK_EN   (1 << 6)
+#define VDSL_CLK_EN      (1 << 5)
+#define VDSL_BONDING_EN  (1 << 4)
+#define VDSL_AFE_EN      (1 << 3)
+#define VDSL_QPROC_EN    (1 << 2)
+   
+     uint32        pll_control;       /* (08) word 2 */
+#define SOFT_RESET              0x00000001      // 0
+
+     uint32        deviceTimeoutEn;   /* (0c) word 3 */
+     uint32        softResetB;        /* (10) word 4 */
+#define SOFT_RST_PCM     (1 << 13)
+#define SOFT_RST_USBH    (1 << 12)
+#define SOFT_RST_USBD    (1 << 11)
+#define SOFT_RST_SWITCH  (1 << 10)
+#define SOFT_RST_SAR     (1 << 7)
+#define SOFT_RST_EPHY    (1 << 6)
+#define SOFT_RST_IPSEC   (1 << 4)
+#define SOFT_RST_MPI     (1 << 3)
+#define SOFT_RST_SPI     (1 << 0)
+
+    uint32        unused1;            /* (14) word 5 */
+    uint32        ExtIrqCfg;          /* (18) word 6*/
+    uint32        ExtIrqCfg1;         /* (1c) word 7 */
+#define EI_SENSE_SHFT   0
+#define EI_STATUS_SHFT  4
+#define EI_CLEAR_SHFT   8
+#define EI_MASK_SHFT    12
+#define EI_INSENS_SHFT  16
+#define EI_LEVEL_SHFT   20
+
+     IrqControl_t IrqControl[2];
+} PerfControl;
+
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+/*
+** Timer
+*/
+typedef struct Timer {
+    uint16        unused0;
+    byte          TimerMask;
+#define TIMER0EN        0x01
+#define TIMER1EN        0x02
+#define TIMER2EN        0x04
+    byte          TimerInts;
+#define TIMER0          0x01
+#define TIMER1          0x02
+#define TIMER2          0x04
+#define WATCHDOG        0x08
+    uint32        TimerCtl0;
+    uint32        TimerCtl1;
+    uint32        TimerCtl2;
+#define TIMERENABLE     0x80000000
+#define RSTCNTCLR       0x40000000      
+    uint32        TimerCnt0;
+    uint32        TimerCnt1;
+    uint32        TimerCnt2;
+    uint32        WatchDogDefCount;
+
+    /* Write 0xff00 0x00ff to Start timer
+     * Write 0xee00 0x00ee to Stop and re-load default count
+     * Read from this register returns current watch dog count
+     */
+    uint32        WatchDogCtl;
+
+    /* Number of 50-MHz ticks for WD Reset pulse to last */
+    uint32        WDResetCount;
+} Timer;
+
+#define TIMER ((volatile Timer * const) TIMR_BASE)
+
+/*
+** UART
+*/
+typedef struct UartChannel {
+    byte          unused0;
+    byte          control;
+#define BRGEN           0x80    /* Control register bit defs */
+#define TXEN            0x40
+#define RXEN            0x20
+#define LOOPBK          0x10
+#define TXPARITYEN      0x08
+#define TXPARITYEVEN    0x04
+#define RXPARITYEN      0x02
+#define RXPARITYEVEN    0x01
+
+    byte          config;
+#define XMITBREAK       0x40
+#define BITS5SYM        0x00
+#define BITS6SYM        0x10
+#define BITS7SYM        0x20
+#define BITS8SYM        0x30
+#define ONESTOP         0x07
+#define TWOSTOP         0x0f
+    /* 4-LSBS represent STOP bits/char
+     * in 1/8 bit-time intervals.  Zero
+     * represents 1/8 stop bit interval.
+     * Fifteen represents 2 stop bits.
+     */
+    byte          fifoctl;
+#define RSTTXFIFOS      0x80
+#define RSTRXFIFOS      0x40
+    /* 5-bit TimeoutCnt is in low bits of this register.
+     *  This count represents the number of characters 
+     *  idle times before setting receive Irq when below threshold
+     */
+    uint32        baudword;
+    /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
+     */
+
+    byte          txf_levl;       /* Read-only fifo depth */
+    byte          rxf_levl;       /* Read-only fifo depth */
+    byte          fifocfg;        /* Upper 4-bits are TxThresh, Lower are
+                                   *      RxThreshold.  Irq can be asserted
+                                   *      when rx fifo> thresh, txfifo<thresh
+                                   */
+    byte          prog_out;       /* Set value of DTR (Bit0), RTS (Bit1)
+                                   *  if these bits are also enabled to GPIO_o
+                                   */
+#define DTREN   0x01
+#define RTSEN   0x02
+
+    byte          unused1;
+    byte          DeltaIPEdgeNoSense;     /* Low 4-bits, set corr bit to 1 to 
+                                           * detect irq on rising AND falling 
+                                           * edges for corresponding GPIO_i
+                                           * if enabled (edge insensitive)
+                                           */
+    byte          DeltaIPConfig_Mask;     /* Upper 4 bits: 1 for posedge sense
+                                           *      0 for negedge sense if
+                                           *      not configured for edge
+                                           *      insensitive (see above)
+                                           * Lower 4 bits: Mask to enable change
+                                           *  detection IRQ for corresponding
+                                           *  GPIO_i
+                                           */
+    byte          DeltaIP_SyncIP;         /* Upper 4 bits show which bits
+                                           *  have changed (may set IRQ).
+                                           *  read automatically clears bit
+                                           * Lower 4 bits are actual status
+                                           */
+
+    uint16        intMask;                /* Same Bit defs for Mask and status */
+    uint16        intStatus;
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+    uint16        unused2;
+    uint16        Data;                   /* Write to TX, Read from RX */
+                                          /* bits 11:8 are BRK,PAR,FRM errors */
+
+    uint32        unused3;
+    uint32        unused4;
+} Uart;
+
+#define UART ((volatile Uart * const) UART_BASE)
+
+/*
+** Gpio Controller
+*/
+
+typedef struct GpioControl {
+    uint64      GPIODir;                    /* 0 */
+    uint64      GPIOio;                     /* 8 */
+    uint32      LEDCtrl;
+#define LED_ALL_STROBE          0x0f000000
+#define LED3_STROBE             0x08000000
+#define LED2_STROBE             0x04000000
+#define LED1_STROBE             0x02000000
+#define LED0_STROBE             0x01000000
+#define LED_TEST                0x00010000
+#define DISABLE_LINK_ACT_ALL    0x0000f000
+#define DISABLE_LINK_ACT_3      0x00008000
+#define DISABLE_LINK_ACT_2      0x00004000
+#define DISABLE_LINK_ACT_1      0x00002000
+#define DISABLE_LINK_ACT_0      0x00001000
+#define LED_INTERVAL_SET_MASK   0x00000f00
+#define LED_INTERVAL_SET_1280MS 0x00000700
+#define LED_INTERVAL_SET_640MS  0x00000600
+#define LED_INTERVAL_SET_320MS  0x00000500
+#define LED_INTERVAL_SET_160MS  0x00000400
+#define LED_INTERVAL_SET_80MS   0x00000300
+#define LED_INTERVAL_SET_40MS   0x00000200
+#define LED_INTERVAL_SET_20MS   0x00000100
+#define LED_ON_ALL              0x000000f0
+#define LED_ON_3                0x00000080
+#define LED_ON_2                0x00000040
+#define LED_ON_1                0x00000020
+#define LED_ON_0                0x00000010
+#define LED_ENABLE_ALL          0x0000000f
+#define LED_ENABLE_3            0x00000008
+#define LED_ENABLE_2            0x00000004
+#define LED_ENABLE_1            0x00000002
+#define LED_ENABLE_0            0x00000001
+    uint32      SpiSlaveCfg;                /* 14 */
+    uint32      GPIOMode;                   /* 18 */
+#define GPIO_MODE_SPI_SSN5          (1<<31)
+#define GPIO_MODE_SPI_SSN4          (1<<30)
+#define GPIO_MODE_SPI_SSN3          (1<<29)
+#define GPIO_MODE_SPI_SSN2          (1<<28)
+#define GPIO_MODE_EBI_CS3           (1<<27)
+#define GPIO_MODE_EBI_CS2           (1<<26)
+#define GPIO_MODE_PCMCIA_VS2        (1<<25)
+#define GPIO_MODE_PCMCIA_VS1        (1<<24)
+#define GPIO_MODE_PCMCIA_CD2        (1<<23)
+#define GPIO_MODE_PCMCIA_CD1        (1<<22)
+#define GPIO_MODE_PCI_GNT0          (1<<20)
+#define GPIO_MODE_PCI_REQ0          (1<<19)
+#define GPIO_MODE_PCI_INTB          (1<<18)
+#define GPIO_MODE_PCI_GNT1          (1<<17)
+#define GPIO_MODE_PCI_REQ1          (1<<16)
+#define GPIO_MODE_USBD_LED          (1<<14)
+#define GPIO_MODE_ROBOSW_LED1       (1<<13)
+#define GPIO_MODE_ROBOSW_LED0       (1<<12)
+#define GPIO_MODE_ROBOSW_LED_CLK    (1<<11)
+#define GPIO_MODE_ROBOSW_LED_DATA   (1<<10)
+#define GPIO_MODE_EPHY3_LED         (1<<9)
+#define GPIO_MODE_EPHY2_LED         (1<<8)
+#define GPIO_MODE_EPHY1_LED         (1<<7)
+#define GPIO_MODE_EPHY0_LED         (1<<6)
+#define GPIO_MODE_INET_LED          (1<<5)
+#define GPIO_MODE_SERIAL_LED_CLK    (1<<4)
+#define GPIO_MODE_SERIAL_LED_DATA   (1<<3)
+#define GPIO_MODE_SYS_IRQ           (1<<2)
+#define GPIO_MODE_ANALOG_AFE_1      (1<<1)
+#define GPIO_MODE_ANALOG_AFE_0      (1<<0)
+
+    uint32      VregConfig;                 /* 1C */
+#define VREG_VSEL1P2_SHIFT      8
+#define VREG_VSEL1P2_MASK       (0x0f<<8)
+#define VREG_VSEL1P2_MIDDLE     9
+
+    uint32      AuxLedInterval;             /* 20 */
+#define AUX_LED_IN_7            0x80000000
+#define AUX_LED_IN_6            0x40000000
+#define AUX_LED_IN_5            0x20000000
+#define AUX_LED_IN_4            0x10000000
+#define AUX_LED_IN_MASK         0xf0000000
+#define LED_IN_3                0x08000000
+#define LED_IN_2                0x04000000
+#define LED_IN_1                0x02000000
+#define LED_IN_0                0x01000000
+#define AUX_LED_TEST            0x00400000
+#define USE_NEW_INTV            0x00200000
+#define LED7_LNK_ORAND          0x00100000
+#define LED7_LNK_MASK           0x000f0000
+#define LED7_LNK_MASK_SHFT      16
+#define LED7_ACT_MASK           0x0000f000
+#define LED7_ACT_MASK_SHFT      12
+#define AUX_FLASH_INTV          0x00000fc0
+#define AUX_FLASH_INTV_SHFT     6
+#define AUX_BLINK_INTV          0x0000003f
+    uint32      AuxLedCtrl;                 /* 24 */
+#define AUX_HW_DISAB_7          0x80000000
+#define AUX_STROBE_7            0x40000000
+#define AUX_MODE_7              0x30000000
+#define AUX_MODE_SHFT_7         28
+#define AUX_HW_DISAB_6          0x08000000
+#define AUX_STROBE_6            0x04000000
+#define AUX_MODE_6              0x03000000
+#define AUX_MODE_SHFT_6         24
+#define AUX_HW_DISAB_5          0x00800000
+#define AUX_STROBE_5            0x00400000
+#define AUX_MODE_5              0x00300000
+#define AUX_MODE_SHFT_5         20
+#define AUX_HW_DISAB_4          0x00080000
+#define AUX_STROBE_4            0x00040000
+#define AUX_MODE_4              0x00030000
+#define AUX_MODE_SHFT_4         16
+#define AUX_HW_DISAB_3          0x00008000
+#define AUX_STROBE_3            0x00004000
+#define AUX_MODE_3              0x00003000
+#define AUX_MODE_SHFT_3         12
+#define AUX_HW_DISAB_2          0x00000800
+#define AUX_STROBE_2            0x00000400
+#define AUX_MODE_2              0x00000300
+#define AUX_MODE_SHFT_2         8
+#define AUX_HW_DISAB_1          0x00000080
+#define AUX_STROBE_1            0x00000040
+#define AUX_MODE_1              0x00000030
+#define AUX_MODE_SHFT_1         4
+#define AUX_HW_DISAB_0          0x00000008
+#define AUX_STROBE_0            0x00000004
+#define AUX_MODE_0              0x00000003
+#define AUX_MODE_SHFT_0         0
+
+#define LED_STEADY_OFF          0x0
+#define LED_FLASH               0x1
+#define LED_BLINK               0x2
+#define LED_STEADY_ON           0x3
+
+    uint32      TestControl;                /* 28 */
+
+    uint32      VDSLControl;                /* 2C */
+#define VDSL_CORE_RESET         (1<<2)
+#define VDSL_MIPS_RESET         (1<<1)
+#define VDSL_MIPS_POR_RESET     (1<<0)
+#define VDSL_CLK_RATIO_SHIFT    8
+#define VDSL_CLK_RATIO_MSK      (0x1F << VDSL_CLK_RATIO_SHIFT)
+    uint32      RoboSWLEDControl;           /* 30 */
+    uint32      RoboSWLEDLSR;               /* 34 */
+    uint32      GPIOBaseMode;               /* 38 */
+#define EN_PCI_CLK_66           (1<<20)
+#define EN_UTO_CLK_FAST         (1<<19)
+#define EN_UTO                  (1<<18)
+#define EN_GMII2                (1<<17)
+#define EN_GMII1                (1<<16)
+    uint32      RoboswEphyCtrl;             /* 3C */
+#define RSW_HW_FWDG_EN          (1<<19)
+#define RSW_MII_DUMB_FWDG_EN    (1<<16)
+#define EPHY_RST_4              (1<<9)
+#define EPHY_RST_3              (1<<8)
+#define EPHY_RST_2              (1<<7)
+#define EPHY_RST_1              (1<<6)
+#define EPHY_PWR_DOWN_4         (1<<5)
+#define EPHY_PWR_DOWN_3         (1<<4)
+#define EPHY_PWR_DOWN_2         (1<<3)
+#define EPHY_PWR_DOWN_1         (1<<2)
+#define EPHY_PWR_DOWN_DLL       (1<<1)
+#define EPHY_PWR_DOWN_BIAS      (1<<0)
+    uint32      StrapBus;                   /* 40 */
+#define UTOPIA_MASTER_ON        (1<<14)
+#define MISC_STRAP_BUS_BOOT_SEL_MASK     0x3
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT    0
+#define MISC_STRAP_BUS_BOOT_PARALLEL     0x03
+#define MISC_STRAP_BUS_BOOT_SERIAL       0x01
+#define MISC_STRAP_BUS_BOOT_NAND         0x00
+    uint32      StrapOverride;              /* 44 */
+
+    uint32      RingOscCtrl0;               /* 48 */
+#define RING_OSC_256_CYCLES         8
+#define RING_OSC_512_CYCLES         9
+#define RING_OSC_1024_CYCLES        10
+
+    uint32      RingOscCtrl1;               /* 4C */
+#define RING_OSC_ENABLE_MASK        (0x7f<<24)
+#define RING_OSC_ENABLE_SHIFT       24
+#define RING_OSC_MAX                7
+#define RING_OSC_COUNT_RESET        (0x1<<23)
+#define RING_OSC_SELECT_MASK        (0x7<<20)
+#define RING_OSC_SELECT_SHIFT       20
+#define RING_OSC_IRQ                (0x1<<18)
+#define RING_OSC_COUNTER_OVERFLOW   (0x1<<17)
+#define RING_OSC_COUNTER_BUSY       (0x1<<16)
+#define RING_OSC_COUNT_MASK         0x0000ffff
+
+    uint32      SerialLed;                  /* 50 */
+    uint32      SerialLedCtrl;              /* 54 */
+#define SER_LED_BUSY            (1<<3)
+#define SER_LED_POLARITY        (1<<2)
+#define SER_LED_DIV_1           0
+#define SER_LED_DIV_2           1
+#define SER_LED_DIV_4           2
+#define SER_LED_DIV_8           3
+#define SER_LED_DIV_MASK        0x3
+#define SER_LED_DIV_SHIFT       0
+    uint32    unused2[4];                   /* 58 */
+    uint32    DieRevID;                     /* 68 */
+    uint32    DiagMemStatus;                /* 6c */
+    uint32    DiagSelControl;               /* 70 */
+    uint32    DiagReadBack;                 /* 74 */
+    uint32    DiagReadBackHi;               /* 78 */
+    uint32    DiagMiscControl;              /* 7c */
+#define EPHY_SA_RESET_N           0x00000300
+#define EPHY_SA_TESTEN            0x00000500
+#define EPHY_SA_CLOCK_RESET       0x0000d900
+} GpioControl;
+
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/* Number to mask conversion macro used for GPIODir and GPIOio */
+#define GPIO_NUM_MAX                    40
+#define GPIO_NUM_TO_MASK(X)             ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) )
+
+/*
+** Spi Controller
+*/
+
+typedef struct SpiControl {
+  uint16        spiMsgCtl;              /* (0x0) control byte */
+#define FULL_DUPLEX_RW                  0
+#define HALF_DUPLEX_W                   1
+#define HALF_DUPLEX_R                   2
+#define SPI_MSG_TYPE_SHIFT              14
+#define SPI_BYTE_CNT_SHIFT              0
+  byte          spiMsgData[0x21e];      /* (0x02 - 0x21f) msg data */
+  byte          unused0[0x1e0];
+  byte          spiRxDataFifo[0x220];   /* (0x400 - 0x61f) rx data */
+  byte          unused1[0xe0];
+
+  uint16        spiCmd;                 /* (0x700): SPI command */
+#define SPI_CMD_NOOP                    0
+#define SPI_CMD_SOFT_RESET              1
+#define SPI_CMD_HARD_RESET              2
+#define SPI_CMD_START_IMMEDIATE         3
+
+#define SPI_CMD_COMMAND_SHIFT           0
+#define SPI_CMD_COMMAND_MASK            0x000f
+
+#define SPI_CMD_DEVICE_ID_SHIFT         4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
+#define SPI_CMD_ONE_BYTE_SHIFT          11
+#define SPI_CMD_ONE_WIRE_SHIFT          12
+#define SPI_DEV_ID_0                    0
+#define SPI_DEV_ID_1                    1
+#define SPI_DEV_ID_2                    2
+#define SPI_DEV_ID_3                    3
+
+  byte          spiIntStatus;           /* (0x702): SPI interrupt status */
+  byte          spiMaskIntStatus;       /* (0x703): SPI masked interrupt status */
+
+  byte          spiIntMask;             /* (0x704): SPI interrupt mask */
+#define SPI_INTR_CMD_DONE               0x01
+#define SPI_INTR_RX_OVERFLOW            0x02
+#define SPI_INTR_INTR_TX_UNDERFLOW      0x04
+#define SPI_INTR_TX_OVERFLOW            0x08
+#define SPI_INTR_RX_UNDERFLOW           0x10
+#define SPI_INTR_CLEAR_ALL              0x1f
+
+  byte          spiStatus;              /* (0x705): SPI status */
+#define SPI_RX_EMPTY                    0x02
+#define SPI_CMD_BUSY                    0x04
+#define SPI_SERIAL_BUSY                 0x08
+
+  byte          spiClkCfg;              /* (0x706): SPI clock configuration */
+#define SPI_CLK_0_391MHZ                1
+#define SPI_CLK_0_781MHZ                2 /* default */
+#define SPI_CLK_1_563MHZ                3
+#define SPI_CLK_3_125MHZ                4
+#define SPI_CLK_6_250MHZ                5
+#define SPI_CLK_12_50MHZ                6
+#define SPI_CLK_MASK                    0x07
+#define SPI_SSOFFTIME_MASK              0x38
+#define SPI_SSOFFTIME_SHIFT             3
+#define SPI_BYTE_SWAP                   0x80
+
+  byte          spiFillByte;            /* (0x707): SPI fill byte */
+  byte          unused2; 
+  byte          spiMsgTail;             /* (0x709): msgtail */
+  byte          unused3; 
+  byte          spiRxTail;              /* (0x70B): rxtail */
+} SpiControl;
+
+#define SPI ((volatile SpiControl * const) SPI_BASE)
+
+
+/*
+** Pcm Controller
+*/
+
+typedef struct PcmControlRegisters
+{
+    uint32 pcm_ctrl;                            // 00 offset from PCM_BASE
+#define  PCM_ENABLE              0x80000000     // PCM block master enable
+#define  PCM_ENABLE_SHIFT        31
+#define  PCM_SLAVE_SEL           0x40000000     // PCM TDM slave mode select (1 - TDM slave, 0 - TDM master)
+#define  PCM_SLAVE_SEL_SHIFT     30
+#define  PCM_CLOCK_INV           0x20000000     // PCM SCLK invert select (1 - invert, 0 - normal)
+#define  PCM_CLOCK_INV_SHIFT     29
+#define  PCM_FS_INVERT           0x10000000     // PCM FS invert select (1 - invert, 0 - normal)
+#define  PCM_FS_INVERT_SHIFT     28
+#define  PCM_FS_FREQ_16_8        0x08000000     // PCM FS 16/8 Khz select (1 - 16Khz, 0 - 8Khz)
+#define  PCM_FS_FREQ_16_8_SHIFT  27
+#define  PCM_FS_LONG             0x04000000     // PCM FS long/short select (1 - long FS, 0 - short FS)
+#define  PCM_FS_LONG_SHIFT       26
+#define  PCM_FS_TRIG             0x02000000     // PCM FS trigger (1 - falling edge, 0 - rising edge trigger)
+#define  PCM_FS_TRIG_SHIFT       25
+#define  PCM_DATA_OFF            0x01000000     // PCM data offset from FS (1 - one clock from FS, 0 - no offset)
+#define  PCM_DATA_OFF_SHIFT      24
+#define  PCM_DATA_16_8           0x00800000     // PCM data word length (1 - 16 bits, 0 - 8 bits)
+#define  PCM_DATA_16_8_SHIFT     23
+#define  PCM_CLOCK_SEL           0x00700000     // PCM SCLK freq select
+#define  PCM_CLOCK_SEL_SHIFT     20
+                                                  // 000 - 8192 Khz
+                                                  // 001 - 4096 Khz
+                                                  // 010 - 2048 Khz
+                                                  // 011 - 1024 Khz
+                                                  // 100 - 512 Khz
+                                                  // 101 - 256 Khz
+                                                  // 110 - 128 Khz
+                                                  // 111 - reserved
+#define  PCM_LSB_FIRST           0x00040000     // PCM shift direction (1 - LSBit first, 0 - MSBit first)
+#define  PCM_LSB_FIRST_SHIFT     18
+#define  PCM_LOOPBACK            0x00020000     // PCM diagnostic loobback enable
+#define  PCM_LOOPBACK_SHIFT      17
+#define  PCM_EXTCLK_SEL          0x00010000     // PCM external timing clock select -- Maybe removed in 6368
+#define  PCM_EXTCLK_SEL_SHIFT    16
+#define  PCM_NTR_ENABLE          0x00008000     // PCM NTR counter enable -- Nayve removed in 6368
+#define  PCM_NTR_ENABLE_SHIFT    15
+#define  PCM_BITS_PER_FRAME_1024 0x00000400     // 1024 - Max
+#define  PCM_BITS_PER_FRAME_256  0x00000100     // 256
+#define  PCM_BITS_PER_FRAME_8    0x00000008     // 8    - Min
+
+    uint32 pcm_chan_ctrl;                       // 04
+#define  PCM_TX0_EN              0x00000001     // PCM transmit channel 0 enable
+#define  PCM_TX1_EN              0x00000002     // PCM transmit channel 1 enable
+#define  PCM_TX2_EN              0x00000004     // PCM transmit channel 2 enable
+#define  PCM_TX3_EN              0x00000008     // PCM transmit channel 3 enable
+#define  PCM_TX4_EN              0x00000010     // PCM transmit channel 4 enable
+#define  PCM_TX5_EN              0x00000020     // PCM transmit channel 5 enable
+#define  PCM_TX6_EN              0x00000040     // PCM transmit channel 6 enable
+#define  PCM_TX7_EN              0x00000080     // PCM transmit channel 7 enable
+#define  PCM_RX0_EN              0x00000100     // PCM receive channel 0 enable
+#define  PCM_RX1_EN              0x00000200     // PCM receive channel 1 enable
+#define  PCM_RX2_EN              0x00000400     // PCM receive channel 2 enable
+#define  PCM_RX3_EN              0x00000800     // PCM receive channel 3 enable
+#define  PCM_RX4_EN              0x00001000     // PCM receive channel 4 enable
+#define  PCM_RX5_EN              0x00002000     // PCM receive channel 5 enable
+#define  PCM_RX6_EN              0x00004000     // PCM receive channel 6 enable
+#define  PCM_RX7_EN              0x00008000     // PCM receive channel 7 enable
+#define  PCM_RX_PACKET_SIZE      0x00ff0000     // PCM Rx DMA quasi-packet size
+#define  PCM_RX_PACKET_SIZE_SHIFT  16
+
+    uint32 pcm_int_pending;                     // 08
+    uint32 pcm_int_mask;                        // 0c
+#define  PCM_TX_UNDERFLOW        0x00000001     // PCM DMA receive overflow
+#define  PCM_RX_OVERFLOW         0x00000002     // PCM DMA transmit underflow
+#define  PCM_TDM_FRAME           0x00000004     // PCM frame boundary
+#define  PCM_RX_IRQ              0x00000008     // IUDMA interrupts
+#define  PCM_TX_IRQ              0x00000010
+
+    uint32 pcm_pll_ctrl1;                       // 10
+#define  PCM_PLL_PWRDN           0x80000000     // PLL PWRDN
+#define  PCM_PLL_PWRDN_CH1       0x40000000     // PLL CH PWRDN
+#define  PCM_PLL_REFCMP_PWRDN    0x20000000     // PLL REFCMP PWRDN
+#define  PCM_CLK16_RESET         0x10000000     // 16.382 MHz PCM interface circuitry reset. 
+#define  PCM_PLL_ARESET          0x08000000     // PLL Analog Reset
+#define  PCM_PLL_DRESET          0x04000000     // PLL Digital Reset
+
+    uint32 pcm_pll_ctrl2;                       // 14
+    uint32 pcm_pll_ctrl3;                       // 18
+    uint32 pcm_pll_ctrl4;                       // 1c
+
+    uint32 pcm_pll_stat;                        // 20
+#define  PCM_PLL_LOCK            0x00000001     // Asserted when PLL is locked to programmed frequency
+
+    uint32 pcm_ntr_counter;                     // 24
+
+    uint32 unused[6];
+
+#define  PCM_MAX_TIMESLOT_REGS   16             // Number of PCM time slot registers in the table.
+                                                // Each register provides the settings for 8 timeslots (4 bits per timeslot)
+    uint32 pcm_slot_alloc_tbl[PCM_MAX_TIMESLOT_REGS];
+#define  PCM_TS_VALID            0x8            // valid marker for TS alloc ram entry
+} PcmControlRegisters;
+
+#define PCM ((volatile PcmControlRegisters * const) PCM_BASE)
+
+typedef struct PcmIudmaRegisters
+{
+   uint16 reserved0;
+   uint16 ctrlConfig;
+#define BCM6368_IUDMA_REGS_CTRLCONFIG_MASTER_EN        0x0001
+#define BCM6368_IUDMA_REGS_CTRLCONFIG_FLOWC_CH1_EN     0x0002
+#define BCM6368_IUDMA_REGS_CTRLCONFIG_FLOWC_CH3_EN     0x0004
+#define BCM6368_IUDMA_REGS_CTRLCONFIG_FLOWC_CH5_EN     0x0008
+#define BCM6368_IUDMA_REGS_CTRLCONFIG_FLOWC_CH7_EN     0x0010
+
+    // Flow control Ch1
+    uint16 reserved1;
+    uint16 ch1_FC_Low_Thr;
+
+    uint16 reserved2;
+    uint16 ch1_FC_High_Thr;
+
+    uint16 reserved3;
+    uint16 ch1_Buff_Alloc;
+
+    // Flow control Ch3
+    uint16 reserved4;
+    uint16 ch3_FC_Low_Thr;
+
+    uint16 reserved5;
+    uint16 ch3_FC_High_Thr;
+
+    uint16 reserved6;
+    uint16 ch3_Buff_Alloc;
+
+    // Flow control Ch5
+    uint16 reserved7;
+    uint16 ch5_FC_Low_Thr;
+
+    uint16 reserved8;
+    uint16 ch5_FC_High_Thr;
+
+    uint16 reserved9;
+    uint16 ch5_Buff_Alloc;
+
+    // Flow control Ch7
+    uint16 reserved10;
+    uint16 ch7_FC_Low_Thr;
+
+    uint16 reserved11;
+    uint16 ch7_FC_High_Thr;
+
+    uint16 reserved12;
+    uint16 ch7_Buff_Alloc;
+
+    // Channel resets
+    uint16 reserved13;
+    uint16 channel_reset;
+    
+    uint16 reserved14;
+    uint16 channel_debug;
+    
+    // Spare register
+    uint32 dummy1;
+    
+    // Interrupt status registers
+    uint16 reserved15;
+    uint16 gbl_int_stat;
+    
+    // Interrupt mask registers
+    uint16 reserved16;
+    uint16 gbl_int_mask;        
+} PcmIudmaRegisters;
+
+typedef struct PcmIudmaChannelCtrl
+{
+    uint16 reserved1;
+    uint16 config;
+#define BCM6368_IUDMA_CONFIG_ENDMA       0x0001
+#define BCM6368_IUDMA_CONFIG_PKTHALT     0x0002
+#define BCM6368_IUDMA_CONFIG_BURSTHALT   0x0004
+
+    uint16 reserved2;
+    uint16 intStat;
+#define BCM6368_IUDMA_INTSTAT_BDONE   0x0001
+#define BCM6368_IUDMA_INTSTAT_PDONE   0x0002
+#define BCM6368_IUDMA_INTSTAT_NOTVLD  0x0004
+#define BCM6368_IUDMA_INTSTAT_MASK    0x0007
+#define BCM6368_IUDMA_INTSTAT_ALL     BCM6368_IUDMA_INTSTAT_MASK
+
+    uint16 reserved3;
+    uint16 intMask;
+#define BCM6368_IUDMA_INTMASK_BDONE   0x0001
+#define BCM6368_IUDMA_INTMASK_PDONE   0x0002
+#define BCM6368_IUDMA_INTMASK_NOTVLD  0x0004
+
+    uint32 maxBurst;
+#define BCM6368_IUDMA_MAXBURST_SIZE 16 /* 32-bit words */
+
+} PcmIudmaChannelCtrl;
+
+
+typedef struct PcmIudmaStateRam
+{
+   uint32 baseDescPointer;                /* pointer to first buffer descriptor */
+
+   uint32 stateBytesDoneRingOffset;       /* state info: how manu bytes done and the offset of the
+                                             current descritor in process */
+#define BCM6368_IUDMA_STRAM_DESC_RING_OFFSET 0x3fff
+
+
+   uint32 flagsLengthStatus;              /* Length and status field of the current descriptor */
+
+   uint32 currentBufferPointer;           /* pointer to the current descriptor */
+
+} PcmIudmaStateRam;
+
+#define BCM6368_MAX_PCM_DMA_CHANNELS 2
+
+typedef struct PcmIudma
+{
+   PcmIudmaRegisters regs;                                        // 
+   uint32 reserved1[110];                                         //            
+   PcmIudmaChannelCtrl ctrl[BCM6368_MAX_PCM_DMA_CHANNELS];        //
+   uint32 reserved2[120];                                         //
+   PcmIudmaStateRam stram[BCM6368_MAX_PCM_DMA_CHANNELS];          //
+
+} PcmIudma;
+
+#define PCM_IUDMA ((volatile PcmIudma * const) PCM_DMA_BASE)
+
+
+#define IUDMA_MAX_CHANNELS          32
+
+/*
+** DMA Channel Configuration (1 .. 32)
+*/
+typedef struct DmaChannelCfg {
+  uint32        cfg;                    /* (00) assorted configuration */
+#define         DMA_ENABLE      0x00000001  /* set to enable channel */
+#define         DMA_PKT_HALT    0x00000002  /* idle after an EOP flag is detected */
+#define         DMA_BURST_HALT  0x00000004  /* idle after finish current memory burst */
+  uint32        intStat;                /* (04) interrupts control and status */
+  uint32        intMask;                /* (08) interrupts mask */
+#define         DMA_BUFF_DONE   0x00000001  /* buffer done */
+#define         DMA_DONE        0x00000002  /* packet xfer complete */
+#define         DMA_NO_DESC     0x00000004  /* no valid descriptors */
+  uint32        maxBurst;               /* (0C) max burst length permitted */
+} DmaChannelCfg;
+
+/*
+** DMA State RAM (1 .. 16)
+*/
+typedef struct DmaStateRam {
+  uint32        baseDescPtr;            /* (00) descriptor ring start address */
+  uint32        state_data;             /* (04) state/bytes done/ring offset */
+  uint32        desc_len_status;        /* (08) buffer descriptor status and len */
+  uint32        desc_base_bufptr;       /* (0C) buffer descrpitor current processing */
+} DmaStateRam;
+
+
+/*
+** DMA Registers
+*/
+typedef struct DmaRegs {
+    uint32 controller_cfg;              /* (00) controller configuration */
+#define DMA_MASTER_EN           0x00000001
+#define DMA_FLOWC_CH1_EN        0x00000002
+#define DMA_FLOWC_CH3_EN        0x00000004
+
+    // Flow control Ch1
+    uint32 flowctl_ch1_thresh_lo;           /* 004 */
+    uint32 flowctl_ch1_thresh_hi;           /* 008 */
+    uint32 flowctl_ch1_alloc;               /* 00c */
+#define DMA_BUF_ALLOC_FORCE     0x80000000
+
+    // Flow control Ch3
+    uint32 flowctl_ch3_thresh_lo;           /* 010 */
+    uint32 flowctl_ch3_thresh_hi;           /* 014 */
+    uint32 flowctl_ch3_alloc;               /* 018 */
+
+    // Flow control Ch5
+    uint32 flowctl_ch5_thresh_lo;           /* 01C */
+    uint32 flowctl_ch5_thresh_hi;           /* 020 */
+    uint32 flowctl_ch5_alloc;               /* 024 */
+
+    // Flow control Ch7
+    uint32 flowctl_ch7_thresh_lo;           /* 028 */
+    uint32 flowctl_ch7_thresh_hi;           /* 02C */
+    uint32 flowctl_ch7_alloc;               /* 030 */
+
+    uint32 ctrl_channel_reset;              /* 034 */
+    uint32 ctrl_channel_debug;              /* 038 */
+    uint32 reserved1;                       /* 03C */
+    uint32 ctrl_global_interrupt_status;    /* 040 */
+    uint32 ctrl_global_interrupt_mask;      /* 044 */
+
+    // Unused words
+    uint8 reserved2[0x200-0x48];
+
+    // Per channel registers/state ram
+    DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */
+    union {
+        DmaStateRam     s[IUDMA_MAX_CHANNELS];
+        uint32          u32[4 * IUDMA_MAX_CHANNELS];
+    } stram;                                /* (400-5FF) state ram */
+} DmaRegs;
+
+/*
+** DMA Buffer 
+*/
+typedef struct DmaDesc {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM    0x8000
+#define          DMA_DESC_MULTICAST 0x4000
+#define          DMA_DESC_BUFLENGTH 0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                /* address of data */
+} DmaDesc;
+
+/*
+** External Bus Interface
+*/
+typedef struct EbiChipSelect {
+    uint32    base;                         /* base address in upper 24 bits */
+#define EBI_SIZE_8K         0
+#define EBI_SIZE_16K        1
+#define EBI_SIZE_32K        2
+#define EBI_SIZE_64K        3
+#define EBI_SIZE_128K       4
+#define EBI_SIZE_256K       5
+#define EBI_SIZE_512K       6
+#define EBI_SIZE_1M         7
+#define EBI_SIZE_2M         8
+#define EBI_SIZE_4M         9
+#define EBI_SIZE_8M         10
+#define EBI_SIZE_16M        11
+#define EBI_SIZE_32M        12
+#define EBI_SIZE_64M        13
+#define EBI_SIZE_128M       14
+#define EBI_SIZE_256M       15
+    uint32    config;
+#define EBI_ENABLE          0x00000001      /* .. enable this range */
+#define EBI_WAIT_STATES     0x0000000e      /* .. mask for wait states */
+#define EBI_WTST_SHIFT      1               /* .. for shifting wait states */
+#define EBI_WORD_WIDE       0x00000010      /* .. 16-bit peripheral, else 8 */
+#define EBI_WREN            0x00000020      /* enable posted writes */
+#define EBI_POLARITY        0x00000040      /* .. set to invert something, 
+                                        **    don't know what yet */
+#define EBI_TS_TA_MODE      0x00000080      /* .. use TS/TA mode */
+#define EBI_TS_SEL          0x00000100      /* .. drive tsize, not bs_b */
+#define EBI_FIFO            0x00000200      /* .. use fifo */
+#define EBI_RE              0x00000400      /* .. Reverse Endian */
+#define EBI_SETUP_SHIFT     16
+#define EBI_HOLD_SHIFT      20
+#define EBI_SETUP_STATES    0x0f0000
+#define EBI_HOLD_STATES     0xf00000
+} EbiChipSelect;
+
+typedef struct MpiRegisters {
+  EbiChipSelect cs[7];                  /* size chip select configuration */
+#define EBI_CS0_BASE            0
+#define EBI_CS1_BASE            1
+#define EBI_CS2_BASE            2
+#define EBI_CS3_BASE            3
+#define PCMCIA_COMMON_BASE      4
+#define PCMCIA_ATTRIBUTE_BASE   5
+#define PCMCIA_IO_BASE          6
+  uint32        unused0[2];             /* reserved */
+  uint32        ebi_control;            /* ebi control */
+  uint32        unused1[4];             /* reserved */
+#define EBI_ACCESS_TIMEOUT      0x000007FF
+  uint32        pcmcia_cntl1;           /* pcmcia control 1 */
+#define PCCARD_CARD_RESET       0x00040000
+#define CARDBUS_ENABLE          0x00008000
+#define PCMCIA_ENABLE           0x00004000
+#define PCMCIA_GPIO_ENABLE      0x00002000
+#define CARDBUS_IDSEL           0x00001F00
+#define VS2_OEN                 0x00000080
+#define VS1_OEN                 0x00000040
+#define VS2_OUT                 0x00000020
+#define VS1_OUT                 0x00000010
+#define VS2_IN                  0x00000008
+#define VS1_IN                  0x00000004
+#define CD2_IN                  0x00000002
+#define CD1_IN                  0x00000001
+#define VS_MASK                 0x0000000C
+#define CD_MASK                 0x00000003
+  uint32        unused2;                /* reserved */
+  uint32        pcmcia_cntl2;           /* pcmcia control 2 */
+#define PCMCIA_BYTESWAP_DIS     0x00000002
+#define PCMCIA_HALFWORD_EN      0x00000001
+#define RW_ACTIVE_CNT_BIT       2
+#define INACTIVE_CNT_BIT        8
+#define CE_SETUP_CNT_BIT        16
+#define CE_HOLD_CNT_BIT         24
+  uint32        unused3[40];            /* reserved */
+
+  uint32        sp0range;               /* PCI to internal system bus address space */
+#define ADDR_SPACE_MASK         0xFFFF0000
+  uint32        sp0remap;
+  uint32        sp0cfg;
+  uint32        sp1range;
+  uint32        sp1remap;
+  uint32        sp1cfg;
+
+  uint32        EndianCfg;
+
+  uint32        l2pcfgctl;              /* internal system bus to PCI IO/Cfg control */
+#define DIR_CFG_SEL             0x80000000 /* change from PCI I/O access to PCI config access */
+#define DIR_CFG_USEREG          0x40000000 /* use this register info for PCI configuration access */
+#define DEVICE_NUMBER           0x00007C00 /* device number for the PCI configuration access */
+#define FUNC_NUMBER             0x00000300 /* function number for the PCI configuration access */
+#define REG_NUMBER              0x000000FC /* register number for the PCI configuration access */
+#define CONFIG_TYPE             0x00000003 /* configuration type for the PCI configuration access */
+
+  uint32        l2pmrange1;             /* internal system bus to PCI memory space */
+#define PCI_SIZE_64K            0xFFFF0000
+#define PCI_SIZE_128K           0xFFFE0000
+#define PCI_SIZE_256K           0xFFFC0000
+#define PCI_SIZE_512K           0xFFF80000
+#define PCI_SIZE_1M             0xFFF00000
+#define PCI_SIZE_2M             0xFFE00000
+#define PCI_SIZE_4M             0xFFC00000
+#define PCI_SIZE_8M             0xFF800000
+#define PCI_SIZE_16M            0xFF000000
+#define PCI_SIZE_32M            0xFE000000
+  uint32        l2pmbase1;              /* kseg0 or kseg1 address & 0x1FFFFFFF */
+  uint32        l2pmremap1;
+#define CARDBUS_MEM             0x00000004
+#define MEM_WINDOW_EN           0x00000001
+  uint32        l2pmrange2;
+  uint32        l2pmbase2;
+  uint32        l2pmremap2;
+  uint32        l2piorange;             /* internal system bus to PCI I/O space */
+  uint32        l2piobase;
+  uint32        l2pioremap;
+
+  uint32        pcimodesel;
+#define PCI_INT_BUS_RD_PREFETCH 0x000001F0
+#define PCI_BAR2_NOSWAP         0x00000002 /* BAR at offset 0x20 */
+#define PCI_BAR1_NOSWAP         0x00000001 /* BAR at affset 0x1c */
+
+  uint32        pciintstat;             /* PCI interrupt mask/status */
+#define MAILBOX1_SENT           0x08
+#define MAILBOX0_SENT           0x04
+#define MAILBOX1_MSG_RCV        0x02
+#define MAILBOX0_MSG_RCV        0x01
+  uint32        locbuscntrl;            /* internal system bus control */
+#define DIR_U2P_NOSWAP          0x00000002
+#define EN_PCI_GPIO             0x00000001
+  uint32        locintstat;             /* internal system bus interrupt mask/status */
+#define CSERR                   0x0200
+#define SERR                    0x0100
+#define EXT_PCI_INT             0x0080
+#define DIR_FAILED              0x0040
+#define DIR_COMPLETE            0x0020
+#define PCI_CFG                 0x0010
+  uint32        unused4[7];
+
+  uint32        mailbox0;
+  uint32        mailbox1;
+
+  uint32        pcicfgcntrl;            /* internal system bus PCI configuration control */
+#define PCI_CFG_REG_WRITE_EN    0x00000080
+#define PCI_CFG_ADDR            0x0000003C
+  uint32        pcicfgdata;             /* internal system bus PCI configuration data */
+
+  uint32        locch2ctl;              /* PCI to interrnal system bus DMA (downstream) local control */
+#define MPI_DMA_HALT            0x00000008  /* idle after finish current memory burst */
+#define MPI_DMA_PKT_HALT        0x00000004  /* idle after an EOP flag is detected */
+#define MPI_DMA_STALL           0x00000002  /* idle after an EOP flag is detected */
+#define MPI_DMA_ENABLE          0x00000001  /* set to enable channel */
+  uint32        locch2intStat;
+#define MPI_DMA_NO_DESC         0x00000004  /* no valid descriptors */
+#define MPI_DMA_DONE            0x00000002  /* packet xfer complete */
+#define MPI_DMA_BUFF_DONE       0x00000001  /* buffer done */
+  uint32        locch2intMask;
+  uint32        unused5;
+  uint32        locch2descaddr;
+  uint32        locch2status1;
+#define LOCAL_DESC_STATE        0xE0000000
+#define PCI_DESC_STATE          0x1C000000
+#define BYTE_DONE               0x03FFC000
+#define RING_ADDR               0x00003FFF
+  uint32        locch2status2;
+#define BUFPTR_OFFSET           0x1FFF0000
+#define PCI_MASTER_STATE        0x000000C0
+#define LOC_MASTER_STATE        0x00000038
+#define CONTROL_STATE           0x00000007
+  uint32        unused6;
+
+  uint32        locch1Ctl;              /*internal system bus to PCI DMA (upstream) local control */
+#define DMA_U2P_LE              0x00000200  /* local bus is little endian */
+#define DMA_U2P_NOSWAP          0x00000100  /* lccal bus is little endian but no data swapped */
+  uint32        locch1intstat;
+  uint32        locch1intmask;
+  uint32        unused7;
+  uint32        locch1descaddr;
+  uint32        locch1status1;
+  uint32        locch1status2;
+  uint32        unused8;
+
+  uint32        pcich1ctl;              /* internal system bus to PCI DMA PCI control */
+  uint32        pcich1intstat;
+  uint32        pcich1intmask;
+  uint32        pcich1descaddr;
+  uint32        pcich1status1;
+  uint32        pcich1status2;
+
+  uint32        pcich2Ctl;              /* PCI to internal system bus DMA PCI control */
+  uint32        pcich2intstat;
+  uint32        pcich2intmask;
+  uint32        pcich2descaddr;
+  uint32        pcich2status1;
+  uint32        pcich2status2;
+
+  uint32        perm_id;                /* permanent device and vendor id */
+  uint32        perm_rev;               /* permanent revision id */
+} MpiRegisters;
+
+#define MPI ((volatile MpiRegisters * const) MPI_BASE)
+
+/* PCI configuration address space start offset 0x40 */
+#define BRCM_PCI_CONFIG_TIMER               0x40
+#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK    0x0000FF00
+#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK     0x000000FF
+/*
+** USB 2.0 Device Registers
+*/
+typedef struct UsbRegisters {
+#define USBD_CONTROL_APP_DONECSR                 0x0001
+#define USBD_CONTROL_APP_RESUME                  0x0002
+#define USBD_CONTROL_APP_RXFIFIO_INIT            0x0040
+#define USBD_CONTROL_APP_TXFIFIO_INIT            0x0080
+#define USBD_CONTROL_APP_FIFO_SEL_SHIFT          0x8
+#define USBD_CONTROL_APP_FIFO_INIT_SEL(x)        (((x)&0x0f)<<USBD_CONTROL_APP_FIFO_SEL_SHIFT)
+#define USBD_CONTROL_APP_AUTO_CSRS               0x2000
+#define USBD_CONTROL_APP_AUTO_INS_ZERO_LEN_PKT   0x4000
+#define EN_TXZLENINS  (1<<14)
+#define EN_RXZSCFG   (1<<12)
+#define APPSETUPERRLOCK  (1<<5)
+    uint32 usbd_control ;
+#define USBD_STRAPS_APP_SELF_PWR    0x0400
+#define USBD_STRAPS_APP_DEV_DISCON  0x0200
+#define USBD_STRAPS_APP_CSRPRG_SUP  0x0100
+#define USBD_STRAPS_APP_RAM_IF      0x0080
+#define USBD_STRAPS_APP_DEV_RMTWKUP 0x0040
+#define USBD_STRAPS_APP_PHYIF_8BIT  0x0004
+#define USBD_STRAPS_FULL_SPEED      0x0003
+#define USBD_STRAPS_LOW_SPEED       0x0002
+#define USBD_STRAPS_HIGH_SPEED      0x0000
+#define APPUTMIDIR(x)  ((x&1)<<3)
+#define UNIDIR   0
+    uint32 usbd_straps;
+#define USB_ENDPOINT_0  0x01
+    uint32 usbd_stall;
+#define USBD_ENUM_SPEED_SHIFT       12
+#define USBD_ENUM_SPEED             0x3000
+#define UDC20_ALTINTF(x) ((x>>8)&0xf)
+#define UDC20_INTF(x)  ((x>>4)&0xf)
+#define UDC20_CFG(x)  ((x>>0)&0xf)
+    uint32 usbd_status;
+#define USBD_LINK                   (0x1<<10)
+#define USBD_SET_CSRS               0x40
+#define USBD_SUSPEND                0x20
+#define USBD_EARLY_SUSPEND          0x10
+#define USBD_SOF                    0x08
+#define USBD_ENUMON                 0x04
+#define USBD_SETUP                  0x02
+#define USBD_USBRESET               0x01
+    uint32 usbd_events;
+    uint32 usbd_events_irq;
+#define UPPER(x)   (16+x)
+#define ENABLE(x)   (1<<x)
+#define SWP_TXBSY   (15)
+#define SWP_RXBSY   (14)
+#define SETUP_ERR   (13)
+#define APPUDCSTALLCHG  (12)
+#define BUS_ERR    (11)
+#define USB_LINK                                (10)
+#define HST_SETCFG   (9)
+#define HST_SETINTF   (8)
+#define ERRATIC_ERR   (7)
+#define SET_CSRS   (6)
+#define SUSPEND    (5)
+#define ERLY_SUSPEND  (4)
+#define SOF     (3)
+#define ENUM_ON    (2)
+#define SETUP    (1)
+#define USB_RESET   (0)
+#define RISING(x)   (0x0<<2*x)
+#define FALLING(x)   (0x1<<2*x)
+#define USBD_IRQCFG_ENUM_ON_FALLING_EDGE 0x00000010
+    uint32 usbd_irqcfg_hi ;
+    uint32 usbd_irqcfg_lo ;
+#define USBD_USB_RESET_IRQ          0x00000001
+#define USBD_USB_SETUP_IRQ          0x00000002 // non-standard setup cmd rcvd
+#define USBD_USB_ENUM_ON_IRQ        0x00000004
+#define USBD_USB_SOF_IRQ            0x00000008
+#define USBD_USB_EARLY_SUSPEND_IRQ  0x00000010
+#define USBD_USB_SUSPEND_IRQ        0x00000020 // non-standard setup cmd rcvd
+#define USBD_USB_SET_CSRS_IRQ       0x00000040
+#define USBD_USB_ERRATIC_ERR_IRQ    0x00000080
+#define USBD_USB_SETCFG_IRQ         0x00000200
+#define USBD_USB_LINK_IRQ                       0x00000400
+    uint32 usbd_events_irq_mask;
+    uint32 usbd_swcfg;
+    uint32 usbd_swtxctl;
+    uint32 usbd_swrxctl;
+    uint32 usbd_txfifo_rwptr;
+    uint32 usbd_rxfifo_rwptr;
+    uint32 usbd_txfifo_st_rwptr;
+    uint32 usbd_rxfifo_st_rwptr;
+    uint32 usbd_txfifo_config ;
+    uint32 usbd_rxfifo_config ;
+    uint32 usbd_txfifo_epsize ;
+    uint32 usbd_rxfifo_epsize ;
+#define USBD_EPNUM_CTRL             0x0
+#define USBD_EPNUM_ISO              0x1
+#define USBD_EPNUM_BULK             0x2
+#define USBD_EPNUM_IRQ              0x3
+#define USBD_EPNUM_EPTYPE(x)        (((x)&0x3)<<8)
+#define USBD_EPNUM_EPDMACHMAP(x)    (((x)&0xf)<<0)
+    uint32 usbd_epnum_typemap ;
+    uint32 usbd_reserved [0xB] ;
+    uint32 usbd_csr_setupaddr ;
+#define USBD_EPNUM_MASK             0xf
+#define USBD_EPNUM(x)               ((x&USBD_EPNUM_MASK)<<0)
+#define USBD_EPDIR_IN               (1<<4)
+#define USBD_EPDIR_OUT              (0<<4)
+#define USBD_EPTYP_CTRL             (USBD_EPNUM_CTRL<<5)
+#define USBD_EPTYP_ISO              (USBD_EPNUM_ISO<<5)
+#define USBD_EPTYP_BULK             (USBD_EPNUM_BULK<<5)
+#define USBD_EPTYP_IRQ              (USBD_EPNUM_IRQ<<5)
+#define USBD_EPCFG_MASK             0xf
+#define USBD_EPCFG(x)               ((x&USBD_EPCFG_MASK)<<7)
+#define USBD_EPINTF_MASK            0xf
+#define USBD_EPINTF(x)              ((x&USBD_EPINTF_MASK)<<11)
+#define USBD_EPAINTF_MASK           0xf
+#define USBD_EPAINTF(x)             ((x&USBD_EPAINTF_MASK)<<15)
+#define USBD_EPMAXPKT_MSK           0x7ff
+#define USBD_EPMAXPKT(x)            ((x&USBD_EPMAXPKT_MSK)<<19)
+#define USBD_EPISOPID_MASK          0x3
+#define USBD_EPISOPID(x)            ((x&USBD_ISOPID_MASK)<<30)
+    uint32 usbd_csr_ep [5] ;
+} UsbRegisters;
+
+#define USB ((volatile UsbRegisters * const) USB_CTL_BASE)
+
+typedef struct USBControl {
+    uint32 BrtControl1;
+    uint32 BrtControl2;
+    uint32 BrtStatus1;
+    uint32 BrtStatus2;
+    uint32 UTMIControl1;
+    uint32 TestPortControl;
+    uint32 PllControl1;
+    uint32 SwapControl;
+#define USB_DEVICE_SEL          (1<<6)
+#define EHCI_LOGICAL_ADDRESS_EN (1<<5)
+#define EHCI_ENDIAN_SWAP        (1<<4)
+#define EHCI_DATA_SWAP          (1<<3)
+#define OHCI_LOGICAL_ADDRESS_EN (1<<2)
+#define OHCI_ENDIAN_SWAP        (1<<1)
+#define OHCI_DATA_SWAP          (1<<0)
+    uint32 unused1;
+    uint32 FrameAdjustValue;
+    uint32 Setup;
+#define USBH_IOC                (1<<4)
+    uint32 MDIO;
+    uint32 MDIO32;
+    uint32 USBSimControl;
+} USBControl;
+
+#define USBH ((volatile USBControl * const) USBH_CFG_BASE)
+
+typedef struct EthSwRegs{
+    byte port_traffic_ctrl[9]; /* 0x00 - 0x08 */
+    byte reserved1[2]; /* 0x09 - 0x0a */
+    byte switch_mode; /* 0x0b */
+    unsigned short pause_quanta; /*0x0c */
+    byte imp_port_state; /*0x0e */
+    byte led_refresh; /* 0x0f */
+    unsigned short led_function[2]; /* 0x10 */
+    unsigned short led_function_map; /* 0x14 */
+    unsigned short led_enable_map; /* 0x16 */
+    unsigned short led_mode_map0; /* 0x18 */
+    unsigned short led_function_map1; /* 0x1a */
+    byte reserved2[5]; /* 0x1b - 0x20 */
+    byte port_forward_ctrl; /* 0x21 */ 
+    byte reserved3[2]; /* 0x22 - 0x23 */
+    unsigned short protected_port_selection; /* 0x24 */
+    unsigned short wan_port_select; /* 0x26 */
+    unsigned int pause_capability; /* 0x28 */
+    byte reserved4[3]; /* 0x2c - 0x2e */
+    byte reserved_multicast_control; /* 0x2f */
+    byte reserved5; /* 0x30 */
+    byte txq_flush_mode_control; /* 0x31 */
+    unsigned short ulf_forward_map; /* 0x32 */
+    unsigned short mlf_forward_map; /* 0x34 */
+    unsigned short mlf_impc_forward_map; /* 0x36 */
+    unsigned short pause_pass_through_for_rx; /* 0x38 */
+    unsigned short pause_pass_through_for_tx; /* 0x3a */
+    unsigned short disable_learning; /* 0x3c */
+    byte reserved6[26]; /* 0x3e - 0x57 */
+    byte port_state_override[8]; /* 0x58 - 0x5f */
+    byte reserved7[4]; /* 0x60 - 0x63 */
+    byte imp_rgmii_ctrl_p4; /* 0x64 */
+    byte imp_rgmii_ctrl_p5; /* 0x65 */
+    byte reserved8[6]; /* 0x66 - 0x6b */
+    byte rgmii_timing_delay_p4; /* 0x6c */
+    byte gmii_timing_delay_p5; /* 0x6d */
+    byte reserved9[11]; /* 0x6e - 0x78 */
+    byte software_reset; /* 0x79 */
+    byte reserved13[6]; /* 0x7a - 0x7f */
+    byte pause_frame_detection; /* 0x80 */
+    byte reserved10[7]; /* 0x81 - 0x87 */
+    byte fast_aging_ctrl; /* 0x88 */
+    byte fast_aging_port; /* 0x89 */
+    byte fast_aging_vid; /* 0x8a */
+    byte reserved11[21]; /* 0x8b - 0x9f */
+    unsigned int swpkt_ctrl_sar; /*0xa0 */
+    unsigned int swpkt_ctrl_usb; /*0xa4 */
+    unsigned int iudma_ctrl; /*0xa8 */
+    unsigned int rxfilt_ctrl; /*0xac */
+    unsigned int mdio_ctrl; /*0xb0 */
+    unsigned int mdio_data; /*0xb4 */
+    byte reserved12[42]; /* 0xb6 - 0xdf */
+    unsigned int sw_mem_test; /*0xe0 */
+} EthSwRegs;
+
+#define ETHSWREG ((volatile EthSwRegs * const) SWITCH_BASE)
+
+typedef struct EthSwMIBRegs {
+    unsigned int TxOctetsLo;
+    unsigned int TxOctetsHi;
+    unsigned int TxDropPkts;
+    unsigned int TxQoSPkts;
+    unsigned int TxBroadcastPkts;
+    unsigned int TxMulticastPkts;
+    unsigned int TxUnicastPkts;
+    unsigned int TxCol;
+    unsigned int TxSingleCol;
+    unsigned int TxMultipleCol;
+    unsigned int TxDeferredTx;
+    unsigned int TxLateCol;
+    unsigned int TxExcessiveCol;
+    unsigned int TxFrameInDisc;
+    unsigned int TxPausePkts;
+    unsigned int TxQoSOctetsLo;
+    unsigned int TxQoSOctetsHi;
+    unsigned int RxOctetsLo;
+    unsigned int RxOctetsHi;
+    unsigned int RxUndersizePkts;
+    unsigned int RxPausePkts;
+    unsigned int Pkts64Octets;
+    unsigned int Pkts65to127Octets;
+    unsigned int Pkts128to255Octets;
+    unsigned int Pkts256to511Octets;
+    unsigned int Pkts512to1023Octets;
+    unsigned int Pkts1024to1522Octets;
+    unsigned int RxOversizePkts;
+    unsigned int RxJabbers;
+    unsigned int RxAlignErrs;
+    unsigned int RxFCSErrs;
+    unsigned int RxGoodOctetsLo;
+    unsigned int RxGoodOctetsHi;
+    unsigned int RxDropPkts;
+    unsigned int RxUnicastPkts;
+    unsigned int RxMulticastPkts;
+    unsigned int RxBroadcastPkts;
+    unsigned int RxSAChanges;
+    unsigned int RxFragments;
+    unsigned int RxExcessSizeDisc;
+    unsigned int RxSymbolError;
+    unsigned int RxQoSPkts;
+    unsigned int RxQoSOctetsLo;
+    unsigned int RxQoSOctetsHi;
+    unsigned int Pkts1523to2047;
+    unsigned int Pkts2048to4095;
+    unsigned int Pkts4096to8191;
+    unsigned int Pkts8192to9728;
+} EthSwMIBRegs;
+
+#define ETHSWMIBREG ((volatile EthSwMIBRegs * const) (SWITCH_BASE + 0x2000))
+
+/*
+** NAND Interrupt Controller Registers
+*/
+typedef struct NandIntrCtrlRegs {
+    uint32 NandInterrupt;
+#define NINT_ENABLE_MASK    0xffff0000
+#define NINT_STS_MASK       0x00000fff
+#define NINT_ECC_ERROR_CORR 0x00000080
+#define NINT_ECC_ERROR_UNC  0x00000040
+#define NINT_DEV_RBPIN      0x00000020
+#define NINT_CTRL_READY     0x00000010
+#define NINT_PAGE_PGM       0x00000008
+#define NINT_COPY_BACK      0x00000004
+#define NINT_BLOCK_ERASE    0x00000002
+#define NINT_NP_READ        0x00000001
+
+    uint32 NandBaseAddr0;   /* Default address when booting from NAND flash */
+    uint32 reserved;
+    uint32 NandBaseAddr1;   /* Secondary base address for NAND flash */
+} NandIntrCtrlRegs;
+
+#define NAND_INTR ((volatile NandIntrCtrlRegs * const) NAND_INTR_BASE)
+
+/*
+** NAND Controller Registers
+*/
+typedef struct NandCtrlRegs {
+    uint32 NandRevision;            /* NAND Revision */
+    uint32 NandCmdStart;            /* Nand Flash Command Start */
+#define NCMD_MASK           0x0f000000
+#define NCMD_BLK_LOCK_STS   0x0d000000
+#define NCMD_BLK_UNLOCK     0x0c000000
+#define NCMD_BLK_LOCK_DOWN  0x0b000000
+#define NCMD_BLK_LOCK       0x0a000000
+#define NCMD_FLASH_RESET    0x09000000
+#define NCMD_BLOCK_ERASE    0x08000000
+#define NCMD_DEV_ID_READ    0x07000000
+#define NCMD_COPY_BACK      0x06000000
+#define NCMD_PROGRAM_SPARE  0x05000000
+#define NCMD_PROGRAM_PAGE   0x04000000
+#define NCMD_STS_READ       0x03000000
+#define NCMD_SPARE_READ     0x02000000
+#define NCMD_PAGE_READ      0x01000000
+
+    uint32 NandCmdExtAddr;          /* Nand Flash Command Extended Address */
+    uint32 NandCmdAddr;             /* Nand Flash Command Address */
+    uint32 NandCmdEndAddr;          /* Nand Flash Command End Address */
+    uint32 NandNandBootConfig;      /* Nand Flash Boot Config */
+#define NBC_CS_LOCK         0x80000000
+#define NBC_AUTO_DEV_ID_CFG 0x40000000
+#define NBC_WR_PROT_BLK0    0x10000000
+
+    uint32 NandCsNandXor;           /* Nand Flash EBI CS Address XOR with */
+                                    /*   1FC0 Control */
+    uint32 NandReserved;
+    uint32 NandSpareAreaReadOfs0;   /* Nand Flash Spare Area Read Bytes 0-3 */
+    uint32 NandSpareAreaReadOfs4;   /* Nand Flash Spare Area Read Bytes 4-7 */
+    uint32 NandSpareAreaReadOfs8;   /* Nand Flash Spare Area Read Bytes 8-11 */
+    uint32 NandSpareAreaReadOfsC;   /* Nand Flash Spare Area Read Bytes 12-15*/
+    uint32 NandSpareAreaWriteOfs0;  /* Nand Flash Spare Area Write Bytes 0-3 */
+    uint32 NandSpareAreaWriteOfs4;  /* Nand Flash Spare Area Write Bytes 4-7 */
+    uint32 NandSpareAreaWriteOfs8;  /* Nand Flash Spare Area Write Bytes 8-11*/
+    uint32 NandSpareAreaWriteOfsC;  /* Nand Flash Spare Area Write Bytes12-15*/
+    uint32 NandAccControl;          /* Nand Flash Access Control */
+    uint32 NandConfig;              /* Nand Flash Config */
+#define NC_CONFIG_LOCK      0x80000000
+#define NC_PG_SIZE_MASK     0x40000000
+#define NC_PG_SIZE_2K       0x40000000
+#define NC_PG_SIZE_512B     0x00000000
+#define NC_BLK_SIZE_MASK    0x30000000
+#define NC_BLK_SIZE_512K    0x30000000
+#define NC_BLK_SIZE_128K    0x10000000
+#define NC_BLK_SIZE_16K     0x00000000
+#define NC_BLK_SIZE_8K      0x20000000
+#define NC_DEV_SIZE_MASK    0x0f000000
+#define NC_DEV_SIZE_SHIFT   24
+#define NC_DEV_WIDTH_MASK   0x00800000
+#define NC_DEV_WIDTH_16     0x00800000
+#define NC_DEV_WIDTH_8      0x00000000
+#define NC_FUL_ADDR_MASK    0x00070000
+#define NC_FUL_ADDR_SHIFT   16
+#define NC_BLK_ADDR_MASK    0x00000700
+#define NC_BLK_ADDR_SHIFT   8
+
+    uint32 NandTiming1;             /* Nand Flash Timing Parameters 1 */
+    uint32 NandTiming2;             /* Nand Flash Timing Parameters 2 */
+    uint32 NandSemaphore;           /* Semaphore */
+    uint32 NandFlashDeviceId;       /* Nand Flash Device ID */
+    uint32 NandBlockLockStatus;     /* Nand Flash Block Lock Status */
+    uint32 NandIntfcStatus;         /* Nand Flash Interface Status */
+#define NIS_CTLR_READY      0x80000000
+#define NIS_FLASH_READY     0x40000000
+#define NIS_CACHE_VALID     0x20000000
+#define NIS_SPARE_VALID     0x10000000
+#define NIS_FLASH_STS_MASK  0x000000ff
+#define NIS_WRITE_PROTECT   0x00000080
+#define NIS_DEV_READY       0x00000040
+#define NIS_PGM_ERASE_ERROR 0x00000001
+
+    uint32 NandEccCorrExtAddr;      /* ECC Correctable Error Extended Address*/
+    uint32 NandEccCorrAddr;         /* ECC Correctable Error Address */
+    uint32 NandEccUncExtAddr;       /* ECC Uncorrectable Error Extended Addr */
+    uint32 NandEccUncAddr;          /* ECC Uncorrectable Error Address */
+    uint32 NandFlashReadExtAddr;    /* Flash Read Data Extended Address */
+    uint32 NandFlashReadAddr;       /* Flash Read Data Address */
+    uint32 NandProgramPageExtAddr;  /* Page Program Extended Address */
+    uint32 NandProgramPageAddr;     /* Page Program Address */
+    uint32 NandCopyBackExtAddr;     /* Copy Back Extended Address */
+    uint32 NandCopyBackAddr;        /* Copy Back Address */
+    uint32 NandBlockEraseExtAddr;   /* Block Erase Extended Address */
+    uint32 NandBlockEraseAddr;      /* Block Erase Address */
+    uint32 NandInvReadExtAddr;      /* Flash Invalid Data Extended Address */
+    uint32 NandInvReadAddr;         /* Flash Invalid Data Address */
+    uint32 NandBlkWrProtect;        /* Block Write Protect Enable and Size */
+                                    /*   for EBI_CS0b */
+} NandCtrlRegs;
+
+#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE)
+
+#define NAND_CACHE ((volatile uint8 * const) NAND_CACHE_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/shared/broadcom/include/bcm963xx/6816_common.h b/shared/broadcom/include/bcm963xx/6816_common.h
new file mode 100755
index 0000000..8c8c2ff
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/6816_common.h
@@ -0,0 +1,351 @@
+/*
+<:copyright-broadcom 
+ 
+ Copyright (c) 2007 Broadcom Corporation 
+ All Rights Reserved 
+ No portions of this material may be reproduced in any form without the 
+ written permission of: 
+          Broadcom Corporation 
+          16215 Alton Parkway 
+          Irvine, California 92619 
+ All information contained in this document is Broadcom Corporation 
+ company private, proprietary, and trade secret. 
+ 
+:>
+*/
+/***********************************************************************/
+/*                                                                     */
+/*   MODULE:  6816_common.h                                             */
+/*   DATE:    02/01/08                                                 */
+/*   PURPOSE: Define addresses of major hardware components of         */
+/*            BCM6816                                                  */
+/*                                                                     */
+/***********************************************************************/
+#ifndef __BCM6816_MAP_COMMON_H
+#define __BCM6816_MAP_COMMON_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PERF_BASE            0xb0000000  /* chip control registers */
+#define TIMR_BASE            0xb0000040  /* timer registers */
+#define NAND_INTR_BASE       0xb0000070
+#define GPIO_BASE            0xb0000080  /* gpio registers */
+#define UART_BASE            0xb0000100  /* uart registers */
+#define UART1_BASE           0xb0000120  /* uart registers */
+#define I2C_BASE             0xb0000180
+#define OTP_BASE             0xb0000400
+#define UBUS_STAT_BASE       0xb0000500
+#define SPI_BASE             0xb0000800  /* SPI master controller registers */
+#define HSSPIM_BASE          0xb0001000
+#define MISC_BASE            0xb0001800
+#define NAND_REG_BASE        0xb0002000  /* NAND control registers */
+#define MPI_BASE             0xb00020A0  /* MPI control registers */
+#define PCI_BASE             0xb0002100  /* PCI control registers */
+#define NAND_CACHE_BASE      0xb0002200
+#define USB_CTL_BASE         0xb0002400  /* USB 2.0 device control registers */
+#define USB_EHCI_BASE        0x10002500  /* USB host registers */
+#define USB_OHCI_BASE        0x10002600  /* USB host registers */
+#define USBH_CFG_BASE        0xb0002700
+#define IPSEC_BASE           0xb0002800
+#define DDR_BASE             0xb0003000  /* Memory control registers */
+#define GPON_BASE            0xb0004000
+#define APM_BASE             0xb0008000
+#define PCM_BASE             0xb0008200
+#define APM_HVG_BASE         0xb0008300
+#define APM_IUDMA_BASE       0xb0008800
+#define BMU_BASE             0xb0009000  /* fff9D000-fff9Dfff */
+#define USB_DMA_BASE         0xb000c000  /* USB 2.0 device DMA regiseters */
+#define GPON_DMA_BASE        0xb000c800
+#define IPSEC_DMA_BASE       0xb000d000
+#define SWITCH_DMA_BASE      0xb000d800
+#define SWITCH_DMA_CONFIG    0xb000da00
+#define SWITCH_DMA_STATE     0xb000dc00
+#define APM_MEM_BASE         0xb0010000
+#define MOCA_MEM_BASE        0xb0d00000
+#define MOCA_IO_BASE         0xb0d80000
+#define SWITCH_BASE          0xb0e00000
+#define PCIE_MEM65K_BASE     0xb0e40000
+#define PCIE_MEM1M_BASE      0xb0f00000
+
+/*
+#####################################################################
+# System PLL Control Register
+#####################################################################
+*/
+
+/*
+#####################################################################
+# GPIO Control Registers
+#####################################################################
+*/
+#define GPIO_SWREG_CONFIG       0x1c
+#define GPIO_LIN_VREG_ADJ_SHIFT 0x0
+#define GPIO_LIN_VREG_ADJ_MASK  (0xf<<GPIO_LIN_VREG_ADJ_SHIFT)
+#define GPIO_SW_VREG_SEL_SHIFT	0x8
+#define GPIO_SW_VREG_SEL_MASK	(0xf<<GPIO_SW_VREG_SEL_SHIFT)
+
+/*
+#####################################################################
+# Miscellaneous Registers
+#####################################################################
+*/
+#define MISC_MEMC_CONTROL		0x10
+#define MISC_STRAP_BUS			0x14
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT      27
+
+/*
+#####################################################################
+# Memory Control Registers
+#####################################################################
+*/
+#define DDR_CTL_CNFG                             0x000 
+#define DDR_CTL_CSST                             0x004 
+#define DDR_CTL_CSEND                            0x008 
+#define DDR_CTL_ROW00_0                          0x010 
+#define DDR_CTL_ROW00_1                          0x014 
+#define DDR_CTL_ROW01_0                          0x018 
+#define DDR_CTL_ROW01_1                          0x01c 
+#define DDR_CTL_ROW20_0                          0x030 
+#define DDR_CTL_ROW20_1                          0x034 
+#define DDR_CTL_ROW21_0                          0x038 
+#define DDR_CTL_ROW21_1                          0x03c 
+#define DDR_CTL_COL00_0                          0x050 
+#define DDR_CTL_COL00_1                          0x054 
+#define DDR_CTL_COL01_0                          0x058 
+#define DDR_CTL_COL01_1                          0x05c 
+#define DDR_CTL_COL20_0                          0x070 
+#define DDR_CTL_COL20_1                          0x074 
+#define DDR_CTL_COL21_0                          0x078 
+#define DDR_CTL_COL21_1                          0x07c 
+#define DDR_CTL_BNK10                            0x090 
+#define DDR_CTL_BNK32                            0x094 
+#define DDR_CTL_DCMD                             0x100 
+#define DDR_CTL_DMODE_0                          0x104 
+#define DDR_CTL_DMODE_1                          0x108 
+#define DDR_CTL_CLKS                             0x10c 
+#define DDR_CTL_ODT                              0x110 
+#define DDR_CTL_TIM1_0                           0x114 
+#define DDR_CTL_TIM1_1                           0x118 
+#define DDR_CTL_TIM2                             0x11c 
+#define DDR_CTL_CTL_CRC                          0x120 
+#define DDR_CTL_DOUT_CRC                         0x124 
+#define DDR_CTL_DIN_CRC                          0x128 
+#define PHY_CONTROL_REGS_REVISION                0x200 
+#define PHY_CONTROL_REGS_CLK_PM_CTRL             0x204 
+#define PHY_CONTROL_REGS_PLL_STATUS              0x210 
+#define PHY_CONTROL_REGS_PLL_CONFIG              0x214 
+#define PHY_CONTROL_REGS_PLL_PRE_DIVIDER         0x218 
+#define PHY_CONTROL_REGS_PLL_DIVIDER             0x21c 
+#define PHY_CONTROL_REGS_PLL_CONTROL1            0x220 
+#define PHY_CONTROL_REGS_PLL_CONTROL2            0x224 
+#define PHY_CONTROL_REGS_PLL_SS_EN               0x228 
+#define PHY_CONTROL_REGS_PLL_SS_CFG              0x22c 
+#define PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE     0x230 
+#define PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE    0x234 
+#define PHY_CONTROL_REGS_IDLE_PAD_CONTROL        0x238 
+#define PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL         0x23c 
+#define PHY_CONTROL_REGS_DRIVE_PAD_CTL           0x240 
+#define PHY_BYTE_LANE_0_REVISION                 0x300 
+#define PHY_BYTE_LANE_0_VDL_CALIBRATE            0x304 
+#define PHY_BYTE_LANE_0_VDL_STATUS               0x308 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_0           0x310 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_1           0x314 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_2           0x318 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_3           0x31c 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_4           0x320 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_5           0x324 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_6           0x328 
+#define PHY_BYTE_LANE_0_VDL_OVERRIDE_7           0x32c 
+#define PHY_BYTE_LANE_0_READ_CONTROL             0x330 
+#define PHY_BYTE_LANE_0_READ_FIFO_STATUS         0x334 
+#define PHY_BYTE_LANE_0_READ_FIFO_CLEAR          0x338 
+#define PHY_BYTE_LANE_0_IDLE_PAD_CONTROL         0x33c 
+#define PHY_BYTE_LANE_0_DRIVE_PAD_CTL            0x340 
+#define PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE        0x344 
+#define PHY_BYTE_LANE_0_WR_PREAMBLE_MODE         0x348 
+#define PHY_BYTE_LANE_1_REVISION                 0x400 
+#define PHY_BYTE_LANE_1_VDL_CALIBRATE            0x404 
+#define PHY_BYTE_LANE_1_VDL_STATUS               0x408 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_0           0x410 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_1           0x414 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_2           0x418 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_3           0x41c 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_4           0x420 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_5           0x424 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_6           0x428 
+#define PHY_BYTE_LANE_1_VDL_OVERRIDE_7           0x42c 
+#define PHY_BYTE_LANE_1_READ_CONTROL             0x430 
+#define PHY_BYTE_LANE_1_READ_FIFO_STATUS         0x434 
+#define PHY_BYTE_LANE_1_READ_FIFO_CLEAR          0x438 
+#define PHY_BYTE_LANE_1_IDLE_PAD_CONTROL         0x43c 
+#define PHY_BYTE_LANE_1_DRIVE_PAD_CTL            0x440 
+#define PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE        0x444 
+#define PHY_BYTE_LANE_1_WR_PREAMBLE_MODE         0x448 
+#define PHY_BYTE_LANE_2_REVISION                 0x500 
+#define PHY_BYTE_LANE_2_VDL_CALIBRATE            0x504 
+#define PHY_BYTE_LANE_2_VDL_STATUS               0x508 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_0           0x510 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_1           0x514 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_2           0x518 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_3           0x51c 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_4           0x520 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_5           0x524 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_6           0x528 
+#define PHY_BYTE_LANE_2_VDL_OVERRIDE_7           0x52c 
+#define PHY_BYTE_LANE_2_READ_CONTROL             0x530 
+#define PHY_BYTE_LANE_2_READ_FIFO_STATUS         0x534 
+#define PHY_BYTE_LANE_2_READ_FIFO_CLEAR          0x538 
+#define PHY_BYTE_LANE_2_IDLE_PAD_CONTROL         0x53c 
+#define PHY_BYTE_LANE_2_DRIVE_PAD_CTL            0x540 
+#define PHY_BYTE_LANE_2_CLOCK_PAD_DISABLE        0x544 
+#define PHY_BYTE_LANE_2_WR_PREAMBLE_MODE         0x548 
+#define PHY_BYTE_LANE_3_REVISION                 0x600 
+#define PHY_BYTE_LANE_3_VDL_CALIBRATE            0x604 
+#define PHY_BYTE_LANE_3_VDL_STATUS               0x608 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_0           0x610 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_1           0x614 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_2           0x618 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_3           0x61c 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_4           0x620 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_5           0x624 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_6           0x628 
+#define PHY_BYTE_LANE_3_VDL_OVERRIDE_7           0x62c 
+#define PHY_BYTE_LANE_3_READ_CONTROL             0x630 
+#define PHY_BYTE_LANE_3_READ_FIFO_STATUS         0x634 
+#define PHY_BYTE_LANE_3_READ_FIFO_CLEAR          0x638 
+#define PHY_BYTE_LANE_3_IDLE_PAD_CONTROL         0x63c 
+#define PHY_BYTE_LANE_3_DRIVE_PAD_CTL            0x640 
+#define PHY_BYTE_LANE_3_CLOCK_PAD_DISABLE        0x644 
+#define PHY_BYTE_LANE_3_WR_PREAMBLE_MODE         0x648 
+#define DDR_CTL_GCFG                             0x800 
+#define DDR_CTL_LBIST_CFG                        0x804 
+#define DDR_CTL_LBIST_SEED                       0x808 
+#define DDR_CTL_ARB                              0x80c 
+#define DDR_CTL_PI_GCF                           0x810 
+#define DDR_CTL_PI_UBUS_CTL                      0x814 
+#define DDR_CTL_PI_MIPS_CTL                      0x818 
+#define DDR_CTL_PI_DSL_MIPS_CTL                  0x81c 
+#define DDR_CTL_PI_DSL_PHY_CTL                   0x820 
+#define DDR_CTL_PI_UBUS_ST                       0x824 
+#define DDR_CTL_PI_MIPS_ST                       0x828 
+#define DDR_CTL_PI_DSL_MIPS_ST                   0x82c 
+#define DDR_CTL_PI_DSL_PHY_ST                    0x830 
+#define DDR_CTL_PI_UBUS_SMPL                     0x834 
+#define DDR_CTL_TESTMODE                         0x838 
+#define DDR_CTL_TEST_CFG1                        0x83c 
+#define DDR_CTL_TEST_PAT                         0x840 
+#define DDR_CTL_TEST_COUNT                       0x844 
+#define DDR_CTL_TEST_CURR_COUNT                  0x848 
+#define DDR_CTL_TEST_ADDR_UPDT                   0x84c 
+#define DDR_CTL_TEST_ADDR                        0x850 
+#define DDR_CTL_TEST_DATA0                       0x854 
+#define DDR_CTL_TEST_DATA1                       0x858 
+#define DDR_CTL_TEST_DATA2                       0x85c 
+#define DDR_CTL_TEST_DATA3                       0x860 
+
+/*
+#####################################################################
+# MPI Control Registers
+#####################################################################
+*/
+#define CS0BASE         0x00
+#define CS0CNTL         0x04
+
+/*
+# CSxBASE settings
+#   Size in low 4 bits
+#   Base Address for match in upper 24 bits
+#
+# TBD - Is it 8K to 256M or 4K to 128M?
+#
+*/
+#define EBI_SIZE_8K         0
+#define EBI_SIZE_16K        1
+#define EBI_SIZE_32K        2
+#define EBI_SIZE_64K        3
+#define EBI_SIZE_128K       4
+#define EBI_SIZE_256K       5
+#define EBI_SIZE_512K       6
+#define EBI_SIZE_1M         7
+#define EBI_SIZE_2M         8
+#define EBI_SIZE_4M         9
+#define EBI_SIZE_8M         10
+#define EBI_SIZE_16M        11
+#define EBI_SIZE_32M        12
+#define EBI_SIZE_64M        13
+#define EBI_SIZE_128M       14
+#define EBI_SIZE_256M       15
+
+/* CSxCNTL settings */
+/* TBD. Verify these definitions on BCM6816 */
+#define EBI_ENABLE          0x00000001  /* .. enable this range */
+#define EBI_WAIT_STATES     0x0000000e  /* .. mask for wait states */
+#define ZEROWT              0x00000000  /* ..  0 WS */
+#define ONEWT               0x00000002  /* ..  1 WS */
+#define TWOWT               0x00000004  /* ..  2 WS */
+#define THREEWT             0x00000006  /* ..  3 WS */
+#define FOURWT              0x00000008  /* ..  4 WS */
+#define FIVEWT              0x0000000a  /* ..  5 WS */
+#define SIXWT               0x0000000c  /* ..  6 WS */
+#define SEVENWT             0x0000000e  /* ..  7 WS */
+#define EBI_WORD_WIDE       0x00000010  /* .. 16-bit peripheral, else 8 */
+#define EBI_TS_TA_MODE      0x00000080  /* .. use TS/TA mode */
+#define EBI_TS_SEL          0x00000100  /* .. drive tsize, not bs_b */
+#define EBI_FIFO            0x00000200  /* .. enable fifo */
+#define EBI_RE              0x00000400  /* .. Reverse Endian */
+
+/*
+#####################################################################
+# UART Control Registers
+#####################################################################
+*/
+/* TBD. Verify these definitions on BCM6816 */
+#define UART0CONTROL     0x01
+#define UART0CONFIG      0x02
+#define UART0RXTIMEOUT   0x03
+#define UART0BAUD        0x04
+#define UART0FIFOCFG     0x0a
+#define UART0INTMASK     0x10
+#define UART0INTSTAT     0x12
+#define UART0DATA        0x17
+
+#define BRGEN            0x80   /* Control register bit defs */
+#define TXEN             0x40
+#define RXEN             0x20
+#define LOOPBK           0x10
+#define TXPARITYEN       0x08
+#define TXPARITYEVEN     0x04
+#define RXPARITYEN       0x02
+#define RXPARITYEVEN     0x01
+
+#define XMITBREAK        0x40   /* Config register */
+#define BITS5SYM         0x00
+#define BITS6SYM         0x10
+#define BITS7SYM         0x20
+#define BITS8SYM         0x30
+#define ONESTOP          0x07
+#define TWOSTOP          0x0f
+
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/shared/broadcom/include/bcm963xx/6816_map.h b/shared/broadcom/include/bcm963xx/6816_map.h
new file mode 100755
index 0000000..6b93307
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/6816_map.h
@@ -0,0 +1,2322 @@
+/*
+<:copyright-broadcom
+
+ Copyright (c) 2007 Broadcom Corporation
+ All Rights Reserved
+ No portions of this material may be reproduced in any form without the
+ written permission of:
+          Broadcom Corporation
+          16215 Alton Parkway
+          Irvine, California 92619
+ All information contained in this document is Broadcom Corporation
+ company private, proprietary, and trade secret.
+
+:>
+*/
+/***********************************************************************/
+/*                                                                     */
+/*   MODULE:  6816_map.h                                               */
+/*   DATE:    05/30/08                                                 */
+/*   PURPOSE: Define addresses of major hardware components of         */
+/*            BCM6816                                                  */
+/*                                                                     */
+/***********************************************************************/
+#ifndef __BCM6816_MAP_H
+#define __BCM6816_MAP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bcmtypes.h"
+#include "6816_common.h"
+#include "6816_intr.h"
+
+/* macro to convert logical data addresses to physical */
+/* DMA hardware must see physical address */
+#define LtoP( x )       ( (uint32)x & 0x1fffffff )
+#define PtoL( x )       ( LtoP(x) | 0xa0000000 )
+
+typedef struct DDRPhyControl {
+    uint32 REVISION;               /* 0x00 */
+    uint32 CLK_PM_CTRL;            /* 0x04 */
+    uint32 unused0[2];             /* 0x08-0x10 */
+    uint32 PLL_STATUS;             /* 0x10 */
+    uint32 PLL_CONFIG;             /* 0x14 */
+    uint32 PLL_PRE_DIVIDER;        /* 0x18 */
+    uint32 PLL_DIVIDER;            /* 0x1c */
+    uint32 PLL_CONTROL1;           /* 0x20 */
+    uint32 PLL_CONTROL2;           /* 0x24 */
+    uint32 PLL_SS_EN;              /* 0x28 */
+    uint32 PLL_SS_CFG;             /* 0x2c */
+    uint32 STATIC_VDL_OVERRIDE;    /* 0x30 */
+    uint32 DYNAMIC_VDL_OVERRIDE;   /* 0x34 */
+    uint32 IDLE_PAD_CONTROL;       /* 0x38 */
+    uint32 ZQ_PVT_COMP_CTL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;          /* 0x40 */
+    uint32 CLOCK_REG_CONTROL;      /* 0x44 */
+    uint32 unused1[46];
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+    uint32 REVISION;                /* 0x00 */
+    uint32 VDL_CALIBRATE;           /* 0x04 */
+    uint32 VDL_STATUS;              /* 0x08 */
+    uint32 unused;                  /* 0x0c */
+    uint32 VDL_OVERRIDE_0;          /* 0x10 */
+    uint32 VDL_OVERRIDE_1;          /* 0x14 */
+    uint32 VDL_OVERRIDE_2;          /* 0x18 */
+    uint32 VDL_OVERRIDE_3;          /* 0x1c */
+    uint32 VDL_OVERRIDE_4;          /* 0x20 */
+    uint32 VDL_OVERRIDE_5;          /* 0x24 */
+    uint32 VDL_OVERRIDE_6;          /* 0x28 */
+    uint32 VDL_OVERRIDE_7;          /* 0x2c */
+    uint32 READ_CONTROL;            /* 0x30 */
+    uint32 READ_FIFO_STATUS;        /* 0x34 */
+    uint32 READ_FIFO_CLEAR;         /* 0x38 */
+    uint32 IDLE_PAD_CONTROL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;           /* 0x40 */
+    uint32 CLOCK_PAD_DISABLE;       /* 0x44 */
+    uint32 WR_PREAMBLE_MODE;        /* 0x48 */
+    uint32 CLOCK_REG_CONTROL;       /* 0x4C */
+    uint32 unused0[44];
+} DDRPhyByteLaneControl;
+
+typedef struct DDRControl {
+    uint32 CNFG;                            /* 0x000 */
+    uint32 CSST;                            /* 0x004 */
+    uint32 CSEND;                           /* 0x008 */
+    uint32 unused;                          /* 0x00c */
+    uint32 ROW00_0;                         /* 0x010 */
+    uint32 ROW00_1;                         /* 0x014 */
+    uint32 ROW01_0;                         /* 0x018 */
+    uint32 ROW01_1;                         /* 0x01c */
+    uint32 unused0[4];
+    uint32 ROW20_0;                         /* 0x030 */
+    uint32 ROW20_1;                         /* 0x034 */
+    uint32 ROW21_0;                         /* 0x038 */
+    uint32 ROW21_1;                         /* 0x03c */
+    uint32 unused1[4];
+    uint32 COL00_0;                         /* 0x050 */
+    uint32 COL00_1;                         /* 0x054 */
+    uint32 COL01_0;                         /* 0x058 */
+    uint32 COL01_1;                         /* 0x05c */
+    uint32 unused2[4];
+    uint32 COL20_0;                         /* 0x070 */
+    uint32 COL20_1;                         /* 0x074 */
+    uint32 COL21_0;                         /* 0x078 */
+    uint32 COL21_1;                         /* 0x07c */
+    uint32 unused3[4];
+    uint32 BNK10;                           /* 0x090 */
+    uint32 BNK32;                           /* 0x094 */
+    uint32 unused4[26];
+    uint32 DCMD;                            /* 0x100 */
+#define DCMD_CS1          (1 << 5)
+#define DCMD_CS0          (1 << 4)
+#define DCMD_SET_SREF     4
+    uint32 DMODE_0;                         /* 0x104 */
+    uint32 DMODE_1;                         /* 0x108 */
+#define DMODE_1_DRAMSLEEP (1 << 11)
+    uint32 CLKS;                            /* 0x10c */
+    uint32 ODT;                             /* 0x110 */
+    uint32 TIM1_0;                          /* 0x114 */
+    uint32 TIM1_1;                          /* 0x118 */
+    uint32 TIM2;                            /* 0x11c */
+    uint32 CTL_CRC;                         /* 0x120 */
+    uint32 DOUT_CRC;                        /* 0x124 */
+    uint32 DIN_CRC;                         /* 0x128 */
+    uint32 unused5[53];
+
+    DDRPhyControl           PhyControl;             /* 0x200 */
+    DDRPhyByteLaneControl   PhyByteLane0Control;    /* 0x300 */
+    DDRPhyByteLaneControl   PhyByteLane1Control;    /* 0x400 */
+    DDRPhyByteLaneControl   PhyByteLane2Control;    /* 0x500 */
+    DDRPhyByteLaneControl   PhyByteLane3Control;    /* 0x600 */
+    uint32 unused6[64];
+
+    uint32 GCFG;                            /* 0x800 */
+    uint32 LBIST_CFG;                       /* 0x804 */
+    uint32 LBIST_SEED;                      /* 0x808 */
+    uint32 ARB;                             /* 0x80c */
+    uint32 PI_GCF;                          /* 0x810 */
+    uint32 PI_UBUS_CTL;                     /* 0x814 */
+    uint32 PI_MIPS_CTL;                     /* 0x818 */
+    uint32 PI_DSL_MIPS_CTL;                 /* 0x81c */
+    uint32 PI_DSL_PHY_CTL;                  /* 0x820 */
+    uint32 PI_UBUS_ST;                      /* 0x824 */
+    uint32 PI_MIPS_ST;                      /* 0x828 */
+    uint32 PI_DSL_MIPS_ST;                  /* 0x82c */
+    uint32 PI_DSL_PHY_ST;                   /* 0x830 */
+    uint32 PI_UBUS_SMPL;                    /* 0x834 */
+    uint32 TESTMODE;                        /* 0x838 */
+    uint32 TEST_CFG1;                       /* 0x83c */
+    uint32 TEST_PAT;                        /* 0x840 */
+    uint32 TEST_COUNT;                      /* 0x844 */
+    uint32 TEST_CURR_COUNT;                 /* 0x848 */
+    uint32 TEST_ADDR_UPDT;                  /* 0x84c */
+    uint32 TEST_ADDR;                       /* 0x850 */
+    uint32 TEST_DATA0;                      /* 0x854 */
+    uint32 TEST_DATA1;                      /* 0x858 */
+    uint32 TEST_DATA2;                      /* 0x85c */
+    uint32 TEST_DATA3;                      /* 0x860 */
+} DDRControl;
+
+#define DDR ((volatile DDRControl * const) DDR_BASE)
+
+/*
+** Peripheral Controller
+*/
+
+#define IRQ_BITS 64
+typedef struct  {
+    uint64		  IrqMask;
+    uint64		  IrqStatus;
+} IrqControl_t;
+
+typedef struct PerfControl {
+    uint32        RevID;             /* (00) word 0 */
+    uint32        blkEnables;        /* (04) word 1 */
+#define ACP_A_CLK_EN     (1 << 25)
+#define ACP_B_CLK_EN     (1 << 24)
+#define NTP_CLK_EN       (1 << 23)
+#define PCM_CLK_EN       (1 << 22)
+#define BMU_CLK_EN       (1 << 21)
+#define PCIE_CLK_EN      (1 << 20)
+#define GPON_SER_CLK_EN  (1 << 19)
+#define IPSEC_CLK_EN     (1 << 18)
+#define NAND_CLK_EN      (1 << 17)
+#define DISABLE_GLESS    (1 << 16)
+#define USBH_CLK_EN      (1 << 15)
+#define APM_CLK_EN       (1 << 14)
+#define ROBOSW_CLK_EN    (1 << 12)
+#define USBD_CLK_EN      (1 << 10)
+#define SPI_CLK_EN       (1 << 9)
+#define SWPKT_GPON_CLK_EN (1 << 8)
+#define SWPKT_USB_CLK_EN (1 << 7)
+#define GPON_CLK_EN      (1 << 6)
+
+    uint32        pll_control;       /* (08) word 2 */
+#define SOFT_RESET              0x00000001      // 0
+
+    uint32        deviceTimeoutEn;   /* (0c) word 3 */
+    uint32        softResetB;        /* (10) word 4 */
+#define SOFT_RST_SERDES_DIG     (1 << 23)
+#define SOFT_RST_SERDES         (1 << 22)
+#define SOFT_RST_SERDES_MDIO    (1 << 21)
+#define SOFT_RST_SERDES_PLL     (1 << 20)
+#define SOFT_RST_SERDES_HW      (1 << 19)
+#define SOFT_RST_GPON           (1 << 18)
+#define SOFT_RST_BMU            (1 << 17)
+#define SOFT_RST_HVG            (1 << 16)
+#define SOFT_RST_APM            (1 << 15)
+#define SOFT_RST_ACP            (1 << 14)
+#define SOFT_RST_PCM            (1 << 13)
+#define SOFT_RST_USBH           (1 << 12)
+#define SOFT_RST_USBD           (1 << 11)
+#define SOFT_RST_SWITCH         (1 << 10)
+#define SOFT_RST_MOCA_CPU       (1 << 9)
+#define SOFT_RST_MOCA_SYS       (1 << 8)
+#define SOFT_RST_MOCA           (1 << 7)
+#define SOFT_RST_EPHY           (1 << 6)
+#define SOFT_RST_PCIE           (1 << 5)
+#define SOFT_RST_IPSEC          (1 << 4)
+#define SOFT_RST_MPI            (1 << 3)
+#define SOFT_RST_PCIE_EXT       (1 << 2)
+#define SOFT_RST_PCIE_CORE      (1 << 1)
+#define SOFT_RST_SPI            (1 << 0)
+
+    uint32        diagControl;        /* (14) word 5 */
+    uint32        ExtIrqCfg;          /* (18) word 6*/
+    uint32        ExtIrqCfg1;         /* (1c) word 7 */
+#define EI_SENSE_SHFT   0
+#define EI_STATUS_SHFT  4
+#define EI_CLEAR_SHFT   8
+#define EI_MASK_SHFT    12
+#define EI_INSENS_SHFT  16
+#define EI_LEVEL_SHFT   20
+
+     IrqControl_t IrqControl[2];
+} PerfControl;
+
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+/*
+** Timer
+*/
+typedef struct Timer {
+    uint16        unused0;
+    byte          TimerMask;
+#define TIMER0EN        0x01
+#define TIMER1EN        0x02
+#define TIMER2EN        0x04
+    byte          TimerInts;
+#define TIMER0          0x01
+#define TIMER1          0x02
+#define TIMER2          0x04
+#define WATCHDOG        0x08
+    uint32        TimerCtl0;
+    uint32        TimerCtl1;
+    uint32        TimerCtl2;
+#define TIMERENABLE     0x80000000
+#define RSTCNTCLR       0x40000000
+    uint32        TimerCnt0;
+    uint32        TimerCnt1;
+    uint32        TimerCnt2;
+    uint32        WatchDogDefCount;
+
+    /* Write 0xff00 0x00ff to Start timer
+     * Write 0xee00 0x00ee to Stop and re-load default count
+     * Read from this register returns current watch dog count
+     */
+    uint32        WatchDogCtl;
+
+    /* Number of 50-MHz ticks for WD Reset pulse to last */
+    uint32        WDResetCount;
+} Timer;
+
+#define TIMER ((volatile Timer * const) TIMR_BASE)
+
+/*
+** UART
+*/
+typedef struct UartChannel {
+    byte          unused0;
+    byte          control;
+#define BRGEN           0x80    /* Control register bit defs */
+#define TXEN            0x40
+#define RXEN            0x20
+#define LOOPBK          0x10
+#define TXPARITYEN      0x08
+#define TXPARITYEVEN    0x04
+#define RXPARITYEN      0x02
+#define RXPARITYEVEN    0x01
+
+    byte          config;
+#define XMITBREAK       0x40
+#define BITS5SYM        0x00
+#define BITS6SYM        0x10
+#define BITS7SYM        0x20
+#define BITS8SYM        0x30
+#define ONESTOP         0x07
+#define TWOSTOP         0x0f
+    /* 4-LSBS represent STOP bits/char
+     * in 1/8 bit-time intervals.  Zero
+     * represents 1/8 stop bit interval.
+     * Fifteen represents 2 stop bits.
+     */
+    byte          fifoctl;
+#define RSTTXFIFOS      0x80
+#define RSTRXFIFOS      0x40
+    /* 5-bit TimeoutCnt is in low bits of this register.
+     *  This count represents the number of characters
+     *  idle times before setting receive Irq when below threshold
+     */
+    uint32        baudword;
+    /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
+     */
+
+    byte          txf_levl;       /* Read-only fifo depth */
+    byte          rxf_levl;       /* Read-only fifo depth */
+    byte          fifocfg;        /* Upper 4-bits are TxThresh, Lower are
+                                   *      RxThreshold.  Irq can be asserted
+                                   *      when rx fifo> thresh, txfifo<thresh
+                                   */
+    byte          prog_out;       /* Set value of DTR (Bit0), RTS (Bit1)
+                                   *  if these bits are also enabled to GPIO_o
+                                   */
+#define DTREN   0x01
+#define RTSEN   0x02
+
+    byte          unused1;
+    byte          DeltaIPEdgeNoSense;     /* Low 4-bits, set corr bit to 1 to
+                                           * detect irq on rising AND falling
+                                           * edges for corresponding GPIO_i
+                                           * if enabled (edge insensitive)
+                                           */
+    byte          DeltaIPConfig_Mask;     /* Upper 4 bits: 1 for posedge sense
+                                           *      0 for negedge sense if
+                                           *      not configured for edge
+                                           *      insensitive (see above)
+                                           * Lower 4 bits: Mask to enable change
+                                           *  detection IRQ for corresponding
+                                           *  GPIO_i
+                                           */
+    byte          DeltaIP_SyncIP;         /* Upper 4 bits show which bits
+                                           *  have changed (may set IRQ).
+                                           *  read automatically clears bit
+                                           * Lower 4 bits are actual status
+                                           */
+
+    uint16        intMask;                /* Same Bit defs for Mask and status */
+    uint16        intStatus;
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+    uint16        unused2;
+    uint16        Data;                   /* Write to TX, Read from RX */
+                                          /* bits 11:8 are BRK,PAR,FRM errors */
+
+    uint32        unused3;
+    uint32        unused4;
+} Uart;
+
+#define UART ((volatile Uart * const) UART_BASE)
+
+/*
+** Gpio Controller
+*/
+
+typedef struct GpioControl {
+    uint64      GPIODir;                    /* 0 */
+    uint64      GPIOio;                     /* 8 */
+#define GPIO_MoCA_OVERLAY_UART_WRITE  39
+#define GPIO_MoCA_OVERLAY_UART_READ   38
+    uint32      LEDCtrl;
+#define LED_ALL_STROBE          0x0f000000
+#define LED3_STROBE             0x08000000
+#define LED2_STROBE             0x04000000
+#define LED1_STROBE             0x02000000
+#define LED0_STROBE             0x01000000
+#define LED_TEST                0x00010000
+#define DISABLE_LINK_ACT_ALL    0x0000f000
+#define DISABLE_LINK_ACT_3      0x00008000
+#define DISABLE_LINK_ACT_2      0x00004000
+#define DISABLE_LINK_ACT_1      0x00002000
+#define DISABLE_LINK_ACT_0      0x00001000
+#define LED_INTERVAL_SET_MASK   0x00000f00
+#define LED_INTERVAL_SET_1280MS 0x00000700
+#define LED_INTERVAL_SET_640MS  0x00000600
+#define LED_INTERVAL_SET_320MS  0x00000500
+#define LED_INTERVAL_SET_160MS  0x00000400
+#define LED_INTERVAL_SET_80MS   0x00000300
+#define LED_INTERVAL_SET_40MS   0x00000200
+#define LED_INTERVAL_SET_20MS   0x00000100
+#define LED_ON_ALL              0x000000f0
+#define LED_ON_3                0x00000080
+#define LED_ON_2                0x00000040
+#define LED_ON_1                0x00000020
+#define LED_ON_0                0x00000010
+#define LED_ENABLE_ALL          0x0000000f
+#define LED_ENABLE_3            0x00000008
+#define LED_ENABLE_2            0x00000004
+#define LED_ENABLE_1            0x00000002
+#define LED_ENABLE_0            0x00000001
+    uint32      SpiSlaveCfg;                /* 14 */
+    uint32      GPIOMode;                   /* 18 */
+#define GPIO_MODE_SPI_SSN5          (1<<31)
+#define GPIO_MODE_SPI_SSN4          (1<<30)
+#define GPIO_MODE_SPI_SSN3          (1<<29)
+#define GPIO_MODE_SPI_SSN2          (1<<28)
+#define GPIO_MODE_EBI_CS3           (1<<27)
+#define GPIO_MODE_EBI_CS2           (1<<26)
+#define GPIO_MODE_APM_CLK           (1<<25)
+#define GPIO_MODE_APM_SDIN          (1<<24)
+#define GPIO_MODE_APM_SDOUT         (1<<23)
+#define GPIO_MODE_APM_FRAME_SYNC    (1<<22)
+#define GPIO_MODE_PCI_GNT0          (1<<20)
+#define GPIO_MODE_PCI_REQ0          (1<<19)
+#define GPIO_MODE_PCI_INTB          (1<<18)
+#define GPIO_MODE_PCI_GNT1          (1<<17)
+#define GPIO_MODE_PCI_REQ1          (1<<16)
+#define GPIO_MODE_NTR_PULSE         (1<<15)
+#define GPIO_MODE_USBD_LED          (1<<14)
+#define GPIO_MODE_ROBOSW_LED1       (1<<13)
+#define GPIO_MODE_ROBOSW_LED0       (1<<12)
+#define GPIO_MODE_ROBOSW_LED_CLK    (1<<11)
+#define GPIO_MODE_ROBOSW_LED_DATA   (1<<10)
+#define GPIO_MODE_GPON_LED          (1<<8)
+#define GPIO_MODE_GPHY1_LED         (1<<7)
+#define GPIO_MODE_GPHY0_LED         (1<<6)
+#define GPIO_MODE_MOCA_LED          (1<<5)
+#define GPIO_MODE_SERIAL_LED_CLK    (1<<4)
+#define GPIO_MODE_SERIAL_LED_DATA   (1<<3)
+#define GPIO_MODE_SYS_IRQ           (1<<2)
+#define GPIO_MODE_GPON_TX_APC_FAIL  (1<<1) /*Anticipating B0*/
+#define GPIO_MODE_GPON_TX_EN_L      (1<<0)
+
+    uint32      VregConfig;                 /* 1C */
+#define VREG_VSEL1P2_SHIFT      8
+#define VREG_VSEL1P2_MASK       (0x0f<<8)
+#define VREG_VSEL1P2_MIDDLE     9
+
+    uint32      AuxLedInterval;             /* 20 */
+#define AUX_LED_IN_7            0x80000000
+#define AUX_LED_IN_6            0x40000000
+#define AUX_LED_IN_5            0x20000000
+#define AUX_LED_IN_4            0x10000000
+#define AUX_LED_IN_MASK         0xf0000000
+#define LED_IN_3                0x08000000
+#define LED_IN_2                0x04000000
+#define LED_IN_1                0x02000000
+#define LED_IN_0                0x01000000
+#define AUX_LED_TEST            0x00400000
+#define USE_NEW_INTV            0x00200000
+#define LED7_LNK_ORAND          0x00100000
+#define LED7_LNK_MASK           0x000f0000
+#define LED7_LNK_MASK_SHFT      16
+#define LED7_ACT_MASK           0x0000f000
+#define LED7_ACT_MASK_SHFT      12
+#define AUX_FLASH_INTV          0x00000fc0
+#define AUX_FLASH_INTV_100MS    0x00000140
+#define AUX_FLASH_INTV_SHFT     6
+#define AUX_BLINK_INTV          0x0000003f
+#define AUX_BLINK_INTV_60MS     0x00000003
+    uint32      AuxLedCtrl;                 /* 24 */
+#define AUX_HW_DISAB_7          0x80000000
+#define AUX_STROBE_7            0x40000000
+#define AUX_MODE_7              0x30000000
+#define AUX_MODE_SHFT_7         28
+#define AUX_HW_DISAB_6          0x08000000
+#define AUX_STROBE_6            0x04000000
+#define AUX_MODE_6              0x03000000
+#define AUX_MODE_SHFT_6         24
+#define AUX_HW_DISAB_5          0x00800000
+#define AUX_STROBE_5            0x00400000
+#define AUX_MODE_5              0x00300000
+#define AUX_MODE_SHFT_5         20
+#define AUX_HW_DISAB_4          0x00080000
+#define AUX_STROBE_4            0x00040000
+#define AUX_MODE_4              0x00030000
+#define AUX_MODE_SHFT_4         16
+#define AUX_HW_DISAB_3          0x00008000
+#define AUX_STROBE_3            0x00004000
+#define AUX_MODE_3              0x00003000
+#define AUX_MODE_SHFT_3         12
+#define AUX_HW_DISAB_2          0x00000800
+#define AUX_STROBE_2            0x00000400
+#define AUX_MODE_2              0x00000300
+#define AUX_MODE_SHFT_2         8
+#define AUX_HW_DISAB_1          0x00000080
+#define AUX_STROBE_1            0x00000040
+#define AUX_MODE_1              0x00000030
+#define AUX_MODE_SHFT_1         4
+#define AUX_HW_DISAB_0          0x00000008
+#define AUX_STROBE_0            0x00000004
+#define AUX_MODE_0              0x00000003
+#define AUX_MODE_SHFT_0         0
+
+#define LED_STEADY_OFF          0x0
+#define LED_FLASH               0x1
+#define LED_BLINK               0x2
+#define LED_STEADY_ON           0x3
+
+    uint32      TestControl;                /* 28 */
+
+    uint32      OscControl;                 /* 2C */
+    uint32      RoboSWLEDControl;           /* 30 */
+    uint32      RoboSWLEDLSR;               /* 34 */
+    uint32      GPIOBaseMode;               /* 38 */
+#define EN_GMII2                (1<<17)
+#define EN_GMII1                (1<<16)
+    uint32      RoboswEphyCtrl;             /* 3C */
+#define RSW_HW_FWDG_EN          (1<<19)
+#define RSW_MII_DUMB_FWDG_EN    (1<<16)
+#define EPHY_RST_4              (1<<9)
+#define EPHY_RST_3              (1<<8)
+#define EPHY_RST_2              (1<<7)
+#define EPHY_RST_1              (1<<6)
+#define EPHY_PWR_DOWN_4         (1<<5)
+#define EPHY_PWR_DOWN_3         (1<<4)
+#define EPHY_PWR_DOWN_2         (1<<3)
+#define EPHY_PWR_DOWN_1         (1<<2)
+    uint32      unused1[2];                 /* 40 */
+
+    uint32      RingOscCtrl0;               /* 48 */
+#define RING_OSC_256_CYCLES        8
+#define RING_OSC_512_CYCLES        9
+#define RING_OSC_1024_CYCLES       10
+
+    uint32      RingOscCtrl1;               /* 4C */
+#define RING_OSC_ENABLE_MASK       (0x57<<24)
+#define RING_OSC_ENABLE_SHIFT      24
+#define RING_OSC_MAX               7
+#define RING_OSC_COUNT_RESET       (0x1<<23)
+#define RING_OSC_SELECT_MASK       (0x7<<20)
+#define RING_OSC_SELECT_SHIFT      20
+#define RING_OSC_IRQ               (0x1<<18)
+#define RING_OSC_COUNTER_OVERFLOW  (0x1<<17)
+#define RING_OSC_COUNTER_BUSY      (0x1<<16)
+#define RING_OSC_COUNT_MASK        0x0000ffff
+
+    uint32      SerialLed;                  /* 50 */
+    uint32      SerialLedCtrl;              /* 54 */
+#define SER_LED_BUSY            (1<<3)
+#define SER_LED_POLARITY        (1<<2)
+#define SER_LED_DIV_1           0
+#define SER_LED_DIV_2           1
+#define SER_LED_DIV_4           2
+#define SER_LED_DIV_8           3
+#define SER_LED_DIV_MASK        0x3
+#define SER_LED_DIV_SHIFT       0
+    uint32    SerialLedBlink;               /* 58 */
+    uint32    SerdesCtl;                    /* 5c */
+#define SERDES_PCIE_ENABLE  0x00000001
+#define SERDES_PCIE_EXD_ENABLE  (1<<15)
+    uint32    SerdesStatus;                 /* 60 */
+    uint32    unused2;                      /* 64 */
+    uint32    DieRevID;                     /* 68 */
+    uint32    DiagMemStatus;                /* 6c */
+    uint32    DiagSelControl;               /* 70 */
+    uint32    DiagReadBack;                 /* 74 */
+    uint32    DiagReadBackHi;               /* 78 */
+    uint32    DiagMiscControl;              /* 7c */
+#define EPHY_SA_RESET_N           0x00000300
+#define EPHY_SA_TESTEN            0x00000500
+#define EPHY_SA_CLOCK_RESET       0x0000d900
+} GpioControl;
+
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/* Number to mask conversion macro used for GPIODir and GPIOio */
+#define GPIO_NUM_MAX                    40
+#define GPIO_NUM_TO_MASK(X)             ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) )
+
+/*
+ * I2C Controller.
+ */
+
+typedef struct I2CControl {
+  uint32        ChipAddress;            /* 0x0 */
+#define I2C_CHIP_ADDRESS_MASK           0x000000f7
+#define I2C_CHIP_ADDRESS_SHIFT          0x1
+  uint32        DataIn0;                /* 0x4 */
+  uint32        DataIn1;                /* 0x8 */
+  uint32        DataIn2;                /* 0xc */
+  uint32        DataIn3;                /* 0x10 */
+  uint32        DataIn4;                /* 0x14 */
+  uint32        DataIn5;                /* 0x18 */
+  uint32        DataIn6;                /* 0x1c */
+  uint32        DataIn7;                /* 0x20 */
+  uint32        CntReg;                 /* 0x24 */
+#define I2C_CNT_REG1_SHIFT              0x0
+#define I2C_CNT_REG2_SHIFT              0x6
+  uint32        CtlReg;                 /* 0x28 */
+#define I2C_CTL_REG_DTF_MASK            0x00000003
+#define I2C_CTL_REG_DTF_WRITE           0x0
+#define I2C_CTL_REG_DTF_READ            0x1
+#define I2C_CTL_REG_DTF_READ_AND_WRITE  0x2
+#define I2C_CTL_REG_DTF_WRITE_AND_READ  0x3
+#define I2C_CTL_REG_DEGLITCH_DISABLE    0x00000004
+#define I2C_CTL_REG_DELAY_DISABLE       0x00000008
+#define I2C_CTL_REG_SCL_SEL_MASK        0x00000030
+#define I2C_CTL_REG_SCL_CLK_375KHZ      0x00000000
+#define I2C_CTL_REG_SCL_CLK_390KHZ      0x00000010
+#define I2C_CTL_REG_SCL_CLK_187_5KHZ    0x00000020
+#define I2C_CTL_REG_SCL_CLK_200KHZ      0x00000030
+#define I2C_CTL_REG_INT_ENABLE          0x00000040
+#define I2C_CTL_REG_DIV_CLK             0x00000080
+  uint32        IICEnable;              /* 0x2c */
+#define I2C_IIC_ENABLE                  0x00000001
+#define I2C_IIC_INTRP                   0x00000002
+#define I2C_IIC_NO_ACK                  0x00000004
+#define I2C_IIC_NO_STOP                 0x00000010
+#define I2C_IIC_NO_START                0x00000020
+  uint32        DataOut0;               /* 0x30 */
+  uint32        DataOut1;               /* 0x34 */
+  uint32        DataOut2;               /* 0x38 */
+  uint32        DataOut3;               /* 0x3c */
+  uint32        DataOut4;               /* 0x40 */
+  uint32        DataOut5;               /* 0x44 */
+  uint32        DataOut6;               /* 0x48 */
+  uint32        DataOut7;               /* 0x4c */
+  uint32        CtlHiReg;               /* 0x50 */
+#define I2C_CTLHI_REG_WAIT_DISABLE      0x00000001
+#define I2C_CTLHI_REG_IGNORE_ACK        0x00000002
+#define I2C_CTLHI_REG_DATA_REG_SIZE     0x00000040
+  uint32        SclParam;               /* 0x54 */
+} I2CControl;
+
+#define I2C ((volatile I2CControl * const) I2C_BASE)
+
+/*
+** Spi Controller
+*/
+
+typedef struct SpiControl {
+  uint16        spiMsgCtl;              /* (0x0) control byte */
+#define FULL_DUPLEX_RW                  0
+#define HALF_DUPLEX_W                   1
+#define HALF_DUPLEX_R                   2
+#define SPI_MSG_TYPE_SHIFT              14
+#define SPI_BYTE_CNT_SHIFT              0
+  byte          spiMsgData[0x21e];      /* (0x02 - 0x21f) msg data */
+  byte          unused0[0x1e0];
+  byte          spiRxDataFifo[0x220];   /* (0x400 - 0x61f) rx data */
+  byte          unused1[0xe0];
+
+  uint16        spiCmd;                 /* (0x700): SPI command */
+#define SPI_CMD_NOOP                    0
+#define SPI_CMD_SOFT_RESET              1
+#define SPI_CMD_HARD_RESET              2
+#define SPI_CMD_START_IMMEDIATE         3
+
+#define SPI_CMD_COMMAND_SHIFT           0
+#define SPI_CMD_COMMAND_MASK            0x000f
+
+#define SPI_CMD_DEVICE_ID_SHIFT         4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
+#define SPI_CMD_ONE_BYTE_SHIFT          11
+#define SPI_CMD_ONE_WIRE_SHIFT          12
+#define SPI_DEV_ID_0                    0
+#define SPI_DEV_ID_1                    1
+#define SPI_DEV_ID_2                    2
+#define SPI_DEV_ID_3                    3
+
+  byte          spiIntStatus;           /* (0x702): SPI interrupt status */
+  byte          spiMaskIntStatus;       /* (0x703): SPI masked interrupt status */
+
+  byte          spiIntMask;             /* (0x704): SPI interrupt mask */
+#define SPI_INTR_CMD_DONE               0x01
+#define SPI_INTR_RX_OVERFLOW            0x02
+#define SPI_INTR_INTR_TX_UNDERFLOW      0x04
+#define SPI_INTR_TX_OVERFLOW            0x08
+#define SPI_INTR_RX_UNDERFLOW           0x10
+#define SPI_INTR_CLEAR_ALL              0x1f
+
+  byte          spiStatus;              /* (0x705): SPI status */
+#define SPI_RX_EMPTY                    0x02
+#define SPI_CMD_BUSY                    0x04
+#define SPI_SERIAL_BUSY                 0x08
+
+  byte          spiClkCfg;              /* (0x706): SPI clock configuration */
+#define SPI_CLK_0_391MHZ                1
+#define SPI_CLK_0_781MHZ                2 /* default */
+#define SPI_CLK_1_563MHZ                3
+#define SPI_CLK_3_125MHZ                4
+#define SPI_CLK_6_250MHZ                5
+#define SPI_CLK_12_50MHZ                6
+#define SPI_CLK_MASK                    0x07
+#define SPI_SSOFFTIME_MASK              0x38
+#define SPI_SSOFFTIME_SHIFT             3
+#define SPI_BYTE_SWAP                   0x80
+
+  byte          spiFillByte;            /* (0x707): SPI fill byte */
+  byte          unused2;
+  byte          spiMsgTail;             /* (0x709): msgtail */
+  byte          unused3;
+  byte          spiRxTail;              /* (0x70B): rxtail */
+} SpiControl;
+
+
+#define SPI ((volatile SpiControl * const) SPI_BASE)
+
+
+/*
+** High-Speed SPI Controller
+*/
+
+#define	__mask(end, start)		(((1 << ((end - start) + 1)) - 1) << start)
+typedef struct HsSpiControl {
+
+  uint32	hs_spiGlobalCtrl;	// 0x0000
+#define	HS_SPI_MOSI_IDLE		(1 << 18)
+#define	HS_SPI_CLK_STATE_GATED		(1 << 17)
+#define	HS_SPI_CLK_GATE_SSOFF		(1 << 16)
+#define	HS_SPI_PLL_CLK_CTRL		(8)
+#define	HS_SPI_PLL_CLK_CTRL_MASK	__mask(15, HS_SPI_PLL_CLK_CTRL)
+#define	HS_SPI_SS_POLARITY		(0)
+#define	HS_SPI_SS_POLARITY_MASK		__mask(7, HS_SPI_SS_POLARITY)
+
+  uint32	hs_spiExtTrigCtrl;	// 0x0004
+#define	HS_SPI_TRIG_RAW_STATE		(24)
+#define	HS_SPI_TRIG_RAW_STATE_MASK	__mask(31, HS_SPI_TRIG_RAW_STATE)
+#define	HS_SPI_TRIG_LATCHED		(16)
+#define	HS_SPI_TRIG_LATCHED_MASK	__mask(23, HS_SPI_TRIG_LATCHED)
+#define	HS_SPI_TRIG_SENSE		(8)
+#define	HS_SPI_TRIG_SENSE_MASK		__mask(15, HS_SPI_TRIG_SENSE)
+#define	HS_SPI_TRIG_TYPE		(0)
+#define	HS_SPI_TRIG_TYPE_MASK		__mask(7, HS_SPI_TRIG_TYPE)
+#define	HS_SPI_TRIG_TYPE_EDGE		(0)
+#define	HS_SPI_TRIG_TYPE_LEVEL		(1)
+
+  uint32	hs_spiIntStatus;	// 0x0008
+#define	HS_SPI_IRQ_PING1_USER		(28)
+#define	HS_SPI_IRQ_PING1_USER_MASK	__mask(31, HS_SPI_IRQ_PING1_USER)
+#define	HS_SPI_IRQ_PING0_USER		(24)
+#define	HS_SPI_IRQ_PING0_USER_MASK	__mask(27, HS_SPI_IRQ_PING0_USER)
+
+#define	HS_SPI_IRQ_PING1_CTRL_INV	(1 << 12)
+#define	HS_SPI_IRQ_PING1_POLL_TOUT	(1 << 11)
+#define	HS_SPI_IRQ_PING1_TX_UNDER	(1 << 10)
+#define	HS_SPI_IRQ_PING1_RX_OVER	(1 << 9)
+#define	HS_SPI_IRQ_PING1_CMD_DONE	(1 << 8)
+
+#define	HS_SPI_IRQ_PING0_CTRL_INV	(1 << 4)
+#define	HS_SPI_IRQ_PING0_POLL_TOUT	(1 << 3)
+#define	HS_SPI_IRQ_PING0_TX_UNDER	(1 << 2)
+#define	HS_SPI_IRQ_PING0_RX_OVER	(1 << 1)
+#define	HS_SPI_IRQ_PING0_CMD_DONE	(1 << 0)
+
+  uint32	hs_spiIntStatusMasked;	// 0x000C
+#define	HS_SPI_IRQSM__PING1_USER	(28)
+#define	HS_SPI_IRQSM__PING1_USER_MASK	__mask(31, HS_SPI_IRQSM__PING1_USER)
+#define	HS_SPI_IRQSM__PING0_USER	(24)
+#define	HS_SPI_IRQSM__PING0_USER_MASK	__mask(27, HS_SPI_IRQSM__PING0_USER)
+
+#define	HS_SPI_IRQSM__PING1_CTRL_INV	(1 << 12)
+#define	HS_SPI_IRQSM__PING1_POLL_TOUT	(1 << 11)
+#define	HS_SPI_IRQSM__PING1_TX_UNDER	(1 << 10)
+#define	HS_SPI_IRQSM__PING1_RX_OVER	(1 << 9)
+#define	HS_SPI_IRQSM__PING1_CMD_DONE	(1 << 8)
+
+#define	HS_SPI_IRQSM__PING0_CTRL_INV	(1 << 4)
+#define	HS_SPI_IRQSM__PING0_POLL_TOUT	(1 << 3)
+#define	HS_SPI_IRQSM__PING0_TX_UNDER	(1 << 2)
+#define	HS_SPI_IRQSM__PING0_RX_OVER	(1 << 1)
+#define	HS_SPI_IRQSM__PING0_CMD_DONE	(1 << 0)
+
+  uint32	hs_spiIntMask;		// 0x0010
+#define	HS_SPI_IRQM_PING1_USER		(28)
+#define	HS_SPI_IRQM_PING1_USER_MASK	__mask(31, HS_SPI_IRQM_PING1_USER)
+#define	HS_SPI_IRQM_PING0_USER		(24)
+#define	HS_SPI_IRQM_PING0_USER_MASK	__mask(27, HS_SPI_IRQM_PING0_USER)
+
+#define	HS_SPI_IRQM_PING1_CTRL_INV	(1 << 12)
+#define	HS_SPI_IRQM_PING1_POLL_TOUT	(1 << 11)
+#define	HS_SPI_IRQM_PING1_TX_UNDER	(1 << 10)
+#define	HS_SPI_IRQM_PING1_RX_OVER	(1 << 9)
+#define	HS_SPI_IRQM_PING1_CMD_DONE	(1 << 8)
+
+#define	HS_SPI_IRQM_PING0_CTRL_INV	(1 << 4)
+#define	HS_SPI_IRQM_PING0_POLL_TOUT	(1 << 3)
+#define	HS_SPI_IRQM_PING0_TX_UNDER	(1 << 2)
+#define	HS_SPI_IRQM_PING0_RX_OVER	(1 << 1)
+#define	HS_SPI_IRQM_PING0_CMD_DONE	(1 << 0)
+
+#define HS_SPI_INTR_CLEAR_ALL       (0xFF001F1F)
+
+  uint32	hs_spiFlashCtrl;	// 0x0014
+#define	HS_SPI_FCTRL_MB_ENABLE		(1 << 23)
+#define	HS_SPI_FCTRL_SS_NUM		(20)
+#define	HS_SPI_FCTRL_SS_NUM_MASK	__mask(22, HS_SPI_FCTRL_SS_NUM)
+#define	HS_SPI_FCTRL_PROFILE_NUM	(16)
+#define	HS_SPI_FCTRL_PROFILE_NUM_MASK	__mask(18, HS_SPI_FCTRL_PROFILE_NUM)
+#define	HS_SPI_FCTRL_DUMMY_BYTES	(10)
+#define	HS_SPI_FCTRL_DUMMY_BYTES_MASK	__mask(11, HS_SPI_FCTRL_DUMMY_BYTES)
+#define	HS_SPI_FCTRL_ADDR_BYTES		(8)
+#define	HS_SPI_FCTRL_ADDR_BYTES_MASK	__mask(9, HS_SPI_FCTRL_ADDR_BYTES)
+#define	HS_SPI_FCTRL_ADDR_BYTES_2	(0)
+#define	HS_SPI_FCTRL_ADDR_BYTES_3	(1)
+#define	HS_SPI_FCTRL_ADDR_BYTES_4	(2)
+#define	HS_SPI_FCTRL_READ_OPCODE	(0)
+#define	HS_SPI_FCTRL_READ_OPCODE_MASK	__mask(7, HS_SPI_FCTRL_READ_OPCODE)
+
+  uint32	hs_spiFlashAddrBase;	// 0x0018
+
+  char		fill0[0x80 - 0x18];
+
+  uint32	hs_spiPP_0_Cmd;		// 0x0080
+#define	HS_SPI_PP_SS_NUM		(12)
+#define	HS_SPI_PP_SS_NUM_MASK		__mask(14, HS_SPI_PP_SS_NUM)
+#define	HS_SPI_PP_PROFILE_NUM		(8)
+#define	HS_SPI_PP_PROFILE_NUM_MASK	__mask(10, HS_SPI_PP_PROFILE_NUM)
+
+} HsSpiControl;
+
+typedef struct HsSpiPingPong {
+
+	uint32 command;
+#define HS_SPI_SS_NUM (12)
+#define HS_SPI_PROFILE_NUM (8)
+#define HS_SPI_TRIGGER_NUM (4)
+#define HS_SPI_COMMAND_VALUE (0)
+    #define HS_SPI_COMMAND_NOOP (0)
+    #define HS_SPI_COMMAND_START_NOW (1)
+    #define HS_SPI_COMMAND_START_TRIGGER (2)
+    #define HS_SPI_COMMAND_HALT (3)
+    #define HS_SPI_COMMAND_FLUSH (4)
+
+	uint32 status;
+#define HS_SPI_ERROR_BYTE_OFFSET (16)
+#define HS_SPI_WAIT_FOR_TRIGGER (2)
+#define HS_SPI_SOURCE_BUSY (1)
+#define HS_SPI_SOURCE_GNT (0)
+
+	uint32 fifo_status;
+	uint32 control;
+
+} HsSpiPingPong;
+
+typedef struct HsSpiProfile {
+
+	uint32 clk_ctrl;
+#define HS_SPI_ACCUM_RST_ON_LOOP (15)
+#define HS_SPI_SPI_CLK_2X_SEL (14)
+#define HS_SPI_FREQ_CTRL_WORD (0)
+	
+	uint32 signal_ctrl;
+#define	HS_SPI_LAUNCH_RISING   (1 << 13)
+#define	HS_SPI_LATCH_RISING    (1 << 12)
+
+	uint32 mode_ctrl;
+#define HS_SPI_PREPENDBYTE_CNT (24)
+#define HS_SPI_MODE_ONE_WIRE (20)
+#define HS_SPI_MULTIDATA_WR_SIZE (18)
+#define HS_SPI_MULTIDATA_RD_SIZE (16)
+#define HS_SPI_MULTIDATA_WR_STRT (12)
+#define HS_SPI_MULTIDATA_RD_STRT (8)
+#define HS_SPI_FILLBYTE (0)
+
+	uint32 polling_config;
+	uint32 polling_and_mask;
+	uint32 polling_compare;
+	uint32 polling_timeout;
+	uint32 reserved;
+
+} HsSpiProfile;
+
+#define HS_SPI_OP_CODE 13
+    #define HS_SPI_OP_SLEEP (0)
+    #define HS_SPI_OP_READ_WRITE (1)
+    #define HS_SPI_OP_WRITE (2)
+    #define HS_SPI_OP_READ (3)
+    #define HS_SPI_OP_SETIRQ (4)
+
+#define	HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE)
+#define	HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80))
+#define	HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0))
+#define	HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100))
+#define	HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200))
+#define	HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400))
+
+
+/*
+** Periph - Misc Register Set Definitions.
+*/
+
+typedef struct Misc {
+  uint32        miscMoCADiv ;              /* (0x0) MoCA Ref PLL Div */
+#define MISC_MOCA_DIV_REF_DIV_FB_MASK                              0xFF000000
+#define MISC_MOCA_DIV_REF_DIV_FB_SHIFT                             24
+#define MISC_MOCA_DIV_REF_OUTDIV_M1_MASK                           0x00FF0000
+#define MISC_MOCA_DIV_REF_OUTDIV_M1_SHIFT                          16
+#define MISC_MOCA_DIV_REF_OUTDIV_M4_MASK                           0x0000FF00
+#define MISC_MOCA_DIV_REF_OUTDIV_M4_SHIFT                          8
+#define MISC_MOCA_DIV_REF_OUTDIV_M5_MASK                           0x000000FF
+#define MISC_MOCA_DIV_REF_OUTDIV_M5_SHIFT                          0
+  uint32        miscMoCACtl ;              /* (0x4) MoCA Ref PLL Ctl */
+#define MISC_MOCA_CTL_REF_OUTCML_LOWCUR_MASK                       0x001FC000
+#define MISC_MOCA_CTL_REF_OUTCML_LOWCUR_SHIFT                      14
+#define MISC_MOCA_CTL_REF_CLFCNT_MASK                              0x00003000
+#define MISC_MOCA_CTL_REF_CLFCNT_SHIFT                             12
+#define MISC_MOCA_CTL_REF_QP_ICTRL_MASK                            0x00000E00
+#define MISC_MOCA_CTL_REF_QP_ICTRL_SHIFT                           9
+#define MISC_MOCA_CTL_REF_VCOBUF_LATCH_ON                          0x00000100
+#define MISC_MOCA_CTL_REF_LF_RCNTL_MASK                            0x000000E0
+#define MISC_MOCA_CTL_REF_LF_RCNTL_SHIFT                           5
+#define MISC_MOCA_CTL_REF_MUX_FBOFF                                0x00000010
+#define MISC_MOCA_CTL_REF_MUX_SEL_MASK                             0x0000000C
+#define MISC_MOCA_CTL_REF_MUX_SEL_SHIFT                            2
+#define MISC_MOCA_CTL_REF_REF_CMLBIAS_MASK                         0x00000003
+#define MISC_MOCA_CTL_REF_REF_CMLBIAS_SHIFT                        0
+  uint32        miscMoCAPwr ;              /* (0x8) MoCA Ref PLL Pwr */
+#define MISC_MOCA_PWR_REF_DEEP_PWRDN                               0x01000000
+#define MISC_MOCA_PWR_REF_OUTDIV_PWRDN_M_MASK                      0x00FE0000
+#define MISC_MOCA_PWR_REF_OUTDIV_PWRDN_M_SHIFT                     17
+#define MISC_MOCA_PWR_REF_OUTCML_PWRDN_M_MASK                      0x0001FC00
+#define MISC_MOCA_PWR_REF_OUTCML_PWRDN_M_SHIFT                     10
+#define MISC_MOCA_PWR_REF_OUTCMOS_PWRDN_M_MASK                     0x000003F8
+#define MISC_MOCA_PWR_REF_OUTCMOS_PWRDN_M_SHIFT                    3
+#define MISC_MOCA_PWR_REF_UGB_PWRDN                                0x00000004
+#define MISC_MOCA_PWR_REF_MUX_PWRDN                                0x00000002
+#define MISC_MOCA_PWR_REF_VCO_PWRDN                                0x00000001
+  uint32        miscMoCARst ;              /* (0xC) MoCA Ref PLL Rst */
+#define MISC_MOCA_RST_REF_OUTDIV_RESET_M_MASK                      0x00000FE0
+#define MISC_MOCA_RST_REF_OUTDIV_RESET_M_SHIFT                     5
+#define MISC_MOCA_RST_REF_DIV2RST                                  0x00000010
+#define MISC_MOCA_RST_REF_MDIV2RST                                 0x00000008
+#define MISC_MOCA_RST_REF_FBDIVRST                                 0x00000004
+#define MISC_MOCA_RST_REF_LD_RESET_STRT                            0x00000002
+#define MISC_MOCA_RST_REF_VCRST                                    0x00000001
+  uint32        miscMemcControl ;          /* (0x10) MEMC Control     */
+#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE                       0x00000008
+#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE                        0x00000004
+#define MISC_MEMC_CONTROL_DDR_TEST_DONE                            0x00000002
+#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE                         0x00000001
+  uint32        miscStrapBus ;             /* (0x14) Strap Register   */
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK                          0xF8000000
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT                         27
+#define MISC_STRAP_BUS_HRD_RST_DELAY                               0x04000000
+#define MISC_STRAP_BUS_ALT_BFC_EN                                  0x02000000
+#define MISC_STRAP_BUS_MOCA_STANDALONE_B                           0x01000000
+#define MISC_STRAP_BUS_MOCA_CONFIG_RATIO                           0x00800000
+#define MISC_STRAP_BUS_IXTAL_ADJ_MASK                              0x00600000
+#define MISC_STRAP_BUS_IXTAL_ADJ_SHIFT                             21
+#define MISC_STRAP_BUS_BYPASS_XTAL                                 0x00100000
+#define MISC_STRAP_BUS_TS                                          0x00080000
+#define MISC_STRAP_BUS_APM_PICO_BOOT_ROM                           0x00040000
+#define MISC_STRAP_BUS_TA                                          0x00020000
+#define MISC_STRAP_BUS_ROBOSW_2_MODE_MASK                          0x00018000
+#define MISC_STRAP_BUS_ROBOSW_2_MODE_SHIFT                         15
+#define MISC_STRAP_BUS_ROBOSW_1_MODE_MASK                          0x00006000
+#define MISC_STRAP_BUS_ROBOSW_1_MODE_SHIFT                         13
+#define MISC_STRAP_BUS_BIST_CLRMEM_N                               0x00001000
+#define MISC_STRAP_BUS_PLL_MIPS_WAIT_FAST_N                        0x00000200
+#define MISC_STRAP_BUS_PLL_USE_LOCK                                0x00000100
+#define MISC_STRAP_BUS_PCIE_ROOT_COMPLEX                           0x00000080
+#define MISC_STRAP_BUS_LS_SPIM_ENABLED                             0x00000040
+#define MISC_STRAP_BUS_USE_SPI_MASTER                              0x00000020
+#define MISC_STRAP_BUS_SPI_CLK_FAST                                0x00000010
+#define MISC_STRAP_BUS_SPI_BOOT_DELAY                              0x00000008
+#define MISC_STRAP_BUS_MIPS_BOOT16                                 0x00000004
+#define MISC_STRAP_BUS_BOOT_SEL_MASK                               0x00000003
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT                              0
+#define MISC_STRAP_BUS_BOOT_PARALLEL                               0x03
+#define MISC_STRAP_BUS_BOOT_SERIAL                                 0x01
+#define MISC_STRAP_BUS_BOOT_NAND                                   0x02
+  uint32        miscStrapOverride ;        /* (0x18) Strap Override Reg */
+#define MISC_STRAP_OVERRIDE_INT_MPI_ARB                            0x00000008
+#define MISC_STRAP_OVERRIDE_INT_MPI_CLK                            0x00000004
+#define MISC_STRAP_OVERRIDE_INT_HOST                               0x00000002
+#define MISC_STRAP_OVERRIDE_STRAP_OVERRIDE                         0x00000001
+  uint32        miscMoCAClkStrapBus ;      /* (0x1C) MoCA Clock Strap Reg */
+#define MISC_MOCA_CLK_STRAP_BUS_MDIV_10_OVERRIDE_MASK              0x0000FF00
+#define MISC_MOCA_CLK_STRAP_BUS_MDIV_10_OVERRIDE_SHIFT             8
+#define MISC_MOCA_CLK_STRAP_BUS_MDIV_9_OVERRIDE_MASK               0x000000FF
+#define MISC_MOCA_CLK_STRAP_BUS_MDIV_9_OVERRIDE_SHIFT              0
+  uint32        miscMoCAClkStrapOverride ; /* (0x20) MoCA Clock Strap Overdide Reg */
+#define MISC_MOCA_CLK_STRAP_OVERRIDE_MOCA_CLK_STRAP_OVERRIDE_CTL   0x00000001
+  uint32        miscMoCAGpioOverlayLo ;    /* (0x24) MoCA GPIO Overlay bus lo Reg */
+  uint32        miscMoCAGpioOverlayHi ;    /* (0x28) MoCA GPIO Overlay bus hi Reg */
+#define MISC_MOCA_GPIO_UART                 0x000000C0
+  uint32        miscDdrPllOutEnCh ;        /* (0x2C) DDR PLL Out En Ch Number */
+#define MISC_DDR_PLL_OUTEN_CH_DDR_PLL_OUTEN_CH_MASK                0x000001FF
+#define MISC_DDR_PLL_OUTEN_CH_DDR_PLL_OUTEN_CH_SHIFT               0
+#define MISC_DDR_PLL_OUTEN_CH_MOCA_CPU_CLK                 0x00000080
+#define MISC_DDR_PLL_OUTEN_CH_MOCA_PHY_CLK                 0x00000100
+  uint32        miscGpioDiagOverlay ;      /* (0x30) GPIO Diag Overlay Control Reg */
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_EN                     0x00000020
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_MASK                   0x0000001F
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_39_32             0x00000010
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_31_24             0x00000008
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_23_16             0x00000004
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_15_8              0x00000002
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_7_0               0x00000001
+  uint32        miscGpioModeCtrlHi ;       /* (0x34) GPIO Pin Mode Control Reg Hi */
+} Misc ;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+/*
+** Pcm Controller
+*/
+
+typedef struct PcmControlRegisters
+{
+    uint32 pcm_ctrl;                            // 00 offset from PCM_BASE
+#define  PCM_ENABLE              0x80000000     // PCM block master enable
+#define  PCM_ENABLE_SHIFT        31
+#define  PCM_SLAVE_SEL           0x40000000     // PCM TDM slave mode select (1 - TDM slave, 0 - TDM master)
+#define  PCM_SLAVE_SEL_SHIFT     30
+#define  PCM_CLOCK_INV           0x20000000     // PCM SCLK invert select (1 - invert, 0 - normal)
+#define  PCM_CLOCK_INV_SHIFT     29
+#define  PCM_FS_INVERT           0x10000000     // PCM FS invert select (1 - invert, 0 - normal)
+#define  PCM_FS_INVERT_SHIFT     28
+#define  PCM_FS_FREQ_16_8        0x08000000     // PCM FS 16/8 Khz select (1 - 16Khz, 0 - 8Khz)
+#define  PCM_FS_FREQ_16_8_SHIFT  27
+#define  PCM_FS_LONG             0x04000000     // PCM FS long/short select (1 - long FS, 0 - short FS)
+#define  PCM_FS_LONG_SHIFT       26
+#define  PCM_FS_TRIG             0x02000000     // PCM FS trigger (1 - falling edge, 0 - rising edge trigger)
+#define  PCM_FS_TRIG_SHIFT       25
+#define  PCM_DATA_OFF            0x01000000     // PCM data offset from FS (1 - one clock from FS, 0 - no offset)
+#define  PCM_DATA_OFF_SHIFT      24
+#define  PCM_DATA_16_8           0x00800000     // PCM data word length (1 - 16 bits, 0 - 8 bits)
+#define  PCM_DATA_16_8_SHIFT     23
+#define  PCM_CLOCK_SEL           0x00700000     // PCM SCLK freq select
+#define  PCM_CLOCK_SEL_SHIFT     20
+                                                  // 000 - 8192 Khz
+                                                  // 001 - 4096 Khz
+                                                  // 010 - 2048 Khz
+                                                  // 011 - 1024 Khz
+                                                  // 100 - 512 Khz
+                                                  // 101 - 256 Khz
+                                                  // 110 - 128 Khz
+                                                  // 111 - reserved
+#define  PCM_LSB_FIRST           0x00040000     // PCM shift direction (1 - LSBit first, 0 - MSBit first)
+#define  PCM_LSB_FIRST_SHIFT     18
+#define  PCM_LOOPBACK            0x00020000     // PCM diagnostic loobback enable
+#define  PCM_LOOPBACK_SHIFT      17
+#define  PCM_EXTCLK_SEL          0x00010000     // PCM external timing clock select -- Maybe removed in 6816
+#define  PCM_EXTCLK_SEL_SHIFT    16
+#define  PCM_NTR_ENABLE          0x00008000     // PCM NTR counter enable -- Nayve removed in 6816
+#define  PCM_NTR_ENABLE_SHIFT    15
+#define  PCM_BITS_PER_FRAME_1024 0x00000400     // 1024 - Max
+#define  PCM_BITS_PER_FRAME_256  0x00000100     // 256
+#define  PCM_BITS_PER_FRAME_8    0x00000008     // 8    - Min
+
+    uint32 pcm_chan_ctrl;                       // 04
+#define  PCM_TX0_EN              0x00000001     // PCM transmit channel 0 enable
+#define  PCM_TX1_EN              0x00000002     // PCM transmit channel 1 enable
+#define  PCM_TX2_EN              0x00000004     // PCM transmit channel 2 enable
+#define  PCM_TX3_EN              0x00000008     // PCM transmit channel 3 enable
+#define  PCM_TX4_EN              0x00000010     // PCM transmit channel 4 enable
+#define  PCM_TX5_EN              0x00000020     // PCM transmit channel 5 enable
+#define  PCM_TX6_EN              0x00000040     // PCM transmit channel 6 enable
+#define  PCM_TX7_EN              0x00000080     // PCM transmit channel 7 enable
+#define  PCM_RX0_EN              0x00000100     // PCM receive channel 0 enable
+#define  PCM_RX1_EN              0x00000200     // PCM receive channel 1 enable
+#define  PCM_RX2_EN              0x00000400     // PCM receive channel 2 enable
+#define  PCM_RX3_EN              0x00000800     // PCM receive channel 3 enable
+#define  PCM_RX4_EN              0x00001000     // PCM receive channel 4 enable
+#define  PCM_RX5_EN              0x00002000     // PCM receive channel 5 enable
+#define  PCM_RX6_EN              0x00004000     // PCM receive channel 6 enable
+#define  PCM_RX7_EN              0x00008000     // PCM receive channel 7 enable
+#define  PCM_RX_PACKET_SIZE      0x00ff0000     // PCM Rx DMA quasi-packet size
+#define  PCM_RX_PACKET_SIZE_SHIFT  16
+
+    uint32 pcm_int_pending;                     // 08
+    uint32 pcm_int_mask;                        // 0c
+#define  PCM_TX_UNDERFLOW        0x00000001     // PCM DMA receive overflow
+#define  PCM_RX_OVERFLOW         0x00000002     // PCM DMA transmit underflow
+#define  PCM_TDM_FRAME           0x00000004     // PCM frame boundary
+#define  PCM_RX_IRQ              0x00000008     // IUDMA interrupts
+#define  PCM_TX_IRQ              0x00000010
+
+// From apm_core.h in Irvine
+  uint32        reg_pcm_clk_cntl_0;                     // (0x210) PCM Clock Control 0 (NCO_FCW_MISC)
+  uint32        reg_pcm_clk_cntl_1;                     // (0x214) PCM Clock Control 1 (NCO_SCALE)
+  uint32        reg_pcm_clk_cntl_2;                     // (0x218) PCM Clock Control 2
+#define   PCM_NCO_SHIFT                    0x0000000f
+#define   PCM_NCO_MUX_CNTL                   0x00000030
+#define   PCM_NCO_LOAD_MISC               0x00000040
+#define   PCM_NCO_SOFT_INIT               0x00000080
+#if 0 // Incorrect for 6816
+    uint32 pcm_pll_ctrl1;                       // 10
+#define  PCM_PLL_PWRDN           0x80000000     // PLL PWRDN
+#define  PCM_PLL_PWRDN_CH1       0x40000000     // PLL CH PWRDN
+#define  PCM_PLL_REFCMP_PWRDN    0x20000000     // PLL REFCMP PWRDN
+#define  PCM_CLK16_RESET         0x10000000     // 16.382 MHz PCM interface circuitry reset.
+#define  PCM_PLL_ARESET          0x08000000     // PLL Analog Reset
+#define  PCM_PLL_DRESET          0x04000000     // PLL Digital Reset
+
+    uint32 pcm_pll_ctrl2;                       // 14
+    uint32 pcm_pll_ctrl3;                       // 18
+    uint32 pcm_pll_ctrl4;                       // 1c
+
+    uint32 pcm_pll_stat;                        // 20
+#define  PCM_PLL_LOCK            0x00000001     // Asserted when PLL is locked to programmed frequency
+
+    uint32 pcm_ntr_counter;                     // 24
+#endif
+
+    uint32 unused[9];
+#define  PCM_MAX_TIMESLOT_REGS   16             // Number of PCM time slot registers in the table.
+                                                // Each register provides the settings for 8 timeslots (4 bits per timeslot)
+    uint32 pcm_slot_alloc_tbl[PCM_MAX_TIMESLOT_REGS];
+#define  PCM_TS_VALID            0x8            // valid marker for TS alloc ram entry
+} PcmControlRegisters;
+
+#define PCM ((volatile PcmControlRegisters * const) PCM_BASE)
+
+typedef struct HvgControlRegisters
+{
+   uint16        reg_hvg_scale_vtip;
+   uint16        reg_hvg_scale_vhvg;
+
+   uint16        reg_hvg_scale_vloop;
+   uint16        reg_hvg_scale_vring;
+
+   uint16        reg_hvg_scale_vcal;
+   uint16        reg_hvg_scale_vinput;
+  
+   uint16        reg_hvg_offset_vtip;
+   uint16        reg_hvg_offset_vhvg;
+
+   uint16        reg_hvg_offset_vloop;
+   uint16        reg_hvg_offset_vring;
+
+   uint16        reg_hvg_offset_vcal;
+   uint16        reg_hvg_offset_vinput;
+  
+   uint32        reg_hvg_shift;
+#define   COND_SHIFT_V_HVG                0x0000000f
+#define   COND_SHIFT_V_TIP                0x000000f0
+#define   COND_SHIFT_V_RING               0x00000f00
+#define   COND_SHIFT_V_LOOP               0x0000f000
+#define   COND_SHIFT_V_INPUT              0x000f0000
+#define   COND_SHIFT_CAL                  0x00f00000
+#define   DIODE_DROP                      0x0f000000
+#define   HVG_IGNORE_RESET                0x10000000
+#define   BG_TRIM_SOURCE                  0x20000000
+#define   HVG_SOFT_INIT                   0x40000000
+
+   uint32        reg_hvg_turns_ratio;
+#define   TURNS_RATIO                     0x00000ffc
+#define   RING_RECT_LINE                  0xffff0000
+
+   uint32        reg_hvg_duty_cycle;
+#define   MAX_DUTY_CYCLE                  0x000000ff
+#define   MIN_DUTY_CYCLE                  0x0000ff00
+#define   MIN_ON_TIME                     0x00ff0000
+#define   SHORT_CIRCUIT_THSHLD            0xff000000
+
+   uint32        reg_hvg_ring;
+#define   RING_GAIN                       0x00000fff
+#define   RING_OVHD                       0x0fff0000
+#define   HVG_COMMON_RING_REF             0x80000000
+#define   RING_GAIN_SHIFT                          0
+#define   RING_OVHD_SHIFT                         16
+#define   HVG_COMMON_RING_REF_SHIFT               31
+
+   uint32        reg_hvg_off_hook;
+#define   OFF_HOOK_OVHD                   0x000001ff
+#define   OFF_HOOK_MIN                    0x0003fe00
+#define   PULSE_START_PHASE               0xff000000
+
+   uint32        reg_hvg_bg;
+#define   BG_CTAT                         0x0000003f
+#define   BG_PTAT                         0x00003f00
+#define   BG_PTAT_SHIFT                            8
+#define   RING_DELAY                      0x001f0000
+#define   HVG_SER_TST_INJECT              0x00200000
+
+   uint32        reg_hvg_reg_3;
+#define   SCALE_V_BAT                     0x00007fff
+#define   OFFSET_V_BAT                    0x0fff8000
+#define   SHIFT_V_BAT                     0xf0000000
+
+   uint32        reg_hvg_status1;
+#define   HVG_OOB_B                       0x40000000
+#define   HVG_INST_VALID_B                0x20000000
+#define   HVG_INST_B                      0x1fff0000
+#define   HVG_OOB_A                       0x00004000
+#define   HVG_INST_VALID_A                0x00002000
+#define   HVG_INST_A                      0x00001fff
+
+   uint32        reg_hvg_status2;
+#define   TIP_OOB_B                       0x40000000
+#define   TIP_INST_VALID_B                0x20000000
+#define   TIP_INST_B                      0x1fff0000
+#define   TIP_OOB_A                       0x00004000
+#define   TIP_INST_VALID_A                0x00002000
+#define   TIP_INST_A                      0x00001fff
+
+   uint32        reg_hvg_status3;
+#define   RING_OOB_B                      0x40000000
+#define   RING_INST_VALID_B               0x20000000
+#define   RING_INST_B                     0x1fff0000
+#define   RING_OOB_A                      0x00004000
+#define   RING_INST_VALID_A               0x00002000
+#define   RING_INST_A                     0x00001fff
+
+   uint32        reg_hvg_status4;               
+#define   LOOP_OOB_B                      0x40000000
+#define   LOOP_INST_VALID_B               0x20000000
+#define   LOOP_INST_B                     0x1fff0000
+#define   LOOP_OOB_A                      0x00004000
+#define   LOOP_INST_VALID_A               0x00002000
+#define   LOOP_INST_A                     0x00001fff
+
+   uint32        reg_hvg_status5;               
+#define   INPUT_OOB_B                     0x40000000
+#define   INPUT_INST_VALID_B              0x20000000
+#define   INPUT_INST_B                    0x1fff0000
+#define   INPUT_OOB_A                     0x00004000
+#define   INPUT_INST_VALID_A              0x00002000
+#define   INPUT_INST_A                    0x00001fff
+
+   uint32        reg_hvg_status6;               
+#define   CAL_OOB_B                       0x40000000
+#define   CAL_OOB_INST_VALID_B            0x20000000
+#define   CAL_INST_B                      0x1fff0000
+#define   CAL_OOB_A                       0x00004000
+#define   CAL_OOB_INST_VALID_A            0x00002000
+#define   CAL_INST_A                      0x00001fff
+
+   uint32        reg_hvg_status7;               
+#define   HVG_DUTY_CYCLE_B                0xff000000
+#define   HVG_DUTY_CYCLE_A                0x00ff0000
+#define   HVG_SHORT_FLAG_B                0x00000800
+#define   HVG_SHORT_FLAG_A                0x00000400
+#define   HVG_DUTY_CYCLE_LIMITED_B        0x00000200
+#define   HVG_DUTY_CYCLE_LIMITED_A        0x00000100
+#define   MAX_DIV_OOB_B                   0x00000080
+#define   MAX_DIV_OOB_A                   0x00000040
+#define   MAX_MULT_OOB_B                  0x00000020
+#define   MAX_MULT_OOB_A                  0x00000010
+#define   ARBITER_ERR_B                   0x00000008
+#define   ARBITER_ERR_A                   0x00000004
+#define   AVG_BLOCK_DONE_B                0x00000002
+#define   AVG_BLOCK_DONE_A                0x00000001
+
+   uint32        reg_hvg_status8;               
+#define   HVG_AVG_VALID                   0x20000000
+#define   HVG_SAT                         0x10000000
+#define   HVG_WINDOW_SLEW                 0x0f000000
+#define   HVG_MEAN                        0x001fffff
+
+   uint32        reg_hvg_status9;               
+   uint32        reg_hvg_status10;              
+#define   TIP_AVG_VALID                   0x20000000
+#define   TIP_SAT                         0x10000000
+#define   TIP_WINDOW_SLEW                 0x0f000000
+#define   TIP_MEAN                        0x001fffff
+
+   uint32        reg_hvg_status11;              
+   uint32        reg_hvg_status12;              
+#define   RING_AVG_VALID                  0x20000000
+#define   RING_SAT                        0x10000000
+#define   RING_WINDOW_SLEW                0x0f000000
+#define   RING_MEAN                       0x001fffff
+
+   uint32        reg_hvg_status13;              
+   uint32        reg_hvg_status14;              
+#define   TP_RG_AVG_VALID                 0x20000000
+#define   TP_RG_SAT                       0x10000000
+#define   TP_RG_WINDOW_SLEW               0x0f000000
+#define   TP_RG_MEAN                      0x001fffff
+
+   uint32        reg_hvg_status15;              
+   uint32        reg_hvg_status16;              
+#define   I_LOOP_AVG_VALID                0x20000000
+#define   I_LOOP_SAT                      0x10000000
+#define   I_LOOP_WINDOW_SLEW              0x0f000000
+#define   I_LOOP_MEAN                     0x001fffff
+
+   uint32        reg_hvg_status17;              
+   uint32        reg_hvg_status18;              
+#define   INPUT_AVG_VALID                 0x20000000
+#define   INPUT_SAT                       0x10000000
+#define   INPUT_WINDOW_SLEW               0x0f000000
+#define   INPUT_MEAN                      0x001fffff
+
+   uint32        reg_hvg_status19;              
+   uint32        reg_hvg_status20;              
+#define   CAL_AVG_VALID                   0x20000000
+#define   CAL_SAT                         0x10000000
+#define   CAL_WINDOW_SLEW                 0x0f000000
+#define   CAL_MEAN                        0x001fffff
+
+   uint32        reg_hvg_status21;              
+   uint32        reg_hvg_status22;              
+   uint32        reg_hvg_status23;              
+   uint32        reg_hvg_status24;              
+   uint32        reg_hvg_status25;              
+   uint32        reg_hvg_status26;              
+   uint32        reg_hvg_status27;              
+   uint32        reg_hvg_status28;              
+   uint32        reg_hvg_status29;              
+   uint32        reg_hvg_status30;              
+   uint32        reg_hvg_status31;              
+   uint32        reg_hvg_status32;              
+   uint32        reg_hvg_status33;              
+   uint32        reg_hvg_status34;              
+   uint32        reg_hvg_status35;              
+
+   uint32        hvg_spacer1[16];               
+
+   uint32        reg_hvg_cha_window_ctrl;       
+#define   HVG_WINDOW_SIZE                 0x0000000f
+#define   TIP_WINDOW_SIZE                 0x000000f0
+#define   RING_WINDOW_SIZE                0x00000f00
+#define   LOOP_WINDOW_SIZE                0x0000f000
+#define   INPUT_WINDOW_SIZE               0x000f0000
+#define   TP_RG_WINDOW_SIZE               0x00f00000
+#define   CAL_WINDOW_SIZE                 0x0f000000
+#define   SLEW_WINDOW_SIZES               0x10000000
+#define   NEW_BLK_RQST                    0x20000000
+  
+   uint16        reg_hvg_cha_max_hvg_slic;     
+   uint16        reg_hvg_cha_const_volt_goal;     
+
+   uint32        reg_hvg_cha_misc;              
+#define   K_PROP                          0x0000000f
+#define   K_INTEG                         0x000000f0
+#define   SER_TST_OUTPUT_SEL              0x00000700
+#define   CONT_OR_BLOCK                   0x00000800
+#define   HVG_MODE                        0x00003000
+#define   HVG_MODE_OFFHOOK_TRACKING       0x00001000
+#define   HVG_MODE_ONHOOK_FIXED           0x00002000
+#define   HVG_SOFT_INIT_0                 0x00004000
+#define   HVG_RR_SINGLE                   0x00008000
+
+   uint32        reg_hvg_cha_spare;             
+   uint32        hvg_spacer2[28];               
+
+   uint32        reg_hvg_chb_window_ctrl;       
+
+   uint16        reg_hvg_chb_max_hvg_slic;     
+   uint16        reg_hvg_chb_const_volt_goal;     
+
+   uint32        reg_hvg_chb_misc;              
+   uint32        reg_hvg_chb_spare;             
+
+} HvgControlRegisters;
+
+#define HVG ((volatile HvgControlRegisters * const) APM_HVG_BASE)
+
+/***** TBD. This is the BCM6368 definition.  Need BCM6816 definition. *****/
+typedef struct PcmIudmaRegisters
+{
+    uint16 reserved0;
+    uint16 ctrlConfig;
+#define BCM6816_IUDMA_REGS_CTRLCONFIG_MASTER_EN        0x0001
+#define BCM6816_IUDMA_REGS_CTRLCONFIG_FLOWC_CH1_EN     0x0002
+#define BCM6816_IUDMA_REGS_CTRLCONFIG_FLOWC_CH3_EN     0x0004
+#define BCM6816_IUDMA_REGS_CTRLCONFIG_FLOWC_CH5_EN     0x0008
+#define BCM6816_IUDMA_REGS_CTRLCONFIG_FLOWC_CH7_EN     0x0010
+
+    // Flow control Ch1
+    uint16 reserved1;
+    uint16 ch1_FC_Low_Thr;
+
+    uint16 reserved2;
+    uint16 ch1_FC_High_Thr;
+
+    uint16 reserved3;
+    uint16 ch1_Buff_Alloc;
+
+    // Flow control Ch3
+    uint16 reserved4;
+    uint16 ch3_FC_Low_Thr;
+
+    uint16 reserved5;
+    uint16 ch3_FC_High_Thr;
+
+    uint16 reserved6;
+    uint16 ch3_Buff_Alloc;
+
+    // Flow control Ch5
+    uint16 reserved7;
+    uint16 ch5_FC_Low_Thr;
+
+    uint16 reserved8;
+    uint16 ch5_FC_High_Thr;
+
+    uint16 reserved9;
+    uint16 ch5_Buff_Alloc;
+
+    // Flow control Ch7
+    uint16 reserved10;
+    uint16 ch7_FC_Low_Thr;
+
+    uint16 reserved11;
+    uint16 ch7_FC_High_Thr;
+
+    uint16 reserved12;
+    uint16 ch7_Buff_Alloc;
+
+    // Channel resets
+    uint16 reserved13;
+    uint16 channel_reset;
+
+    uint16 reserved14;
+    uint16 channel_debug;
+
+    // Spare register
+    uint32 dummy1;
+
+    // Interrupt status registers
+    uint16 reserved15;
+    uint16 gbl_int_stat;
+
+    // Interrupt mask registers
+    uint16 reserved16;
+    uint16 gbl_int_mask;
+} PcmIudmaRegisters;
+
+/***** TBD. This is the BCM6368 definition.  Need BCM6816 definition. *****/
+typedef struct PcmIudmaChannelCtrl
+{
+    uint16 reserved1;
+    uint16 config;
+#define BCM6816_IUDMA_CONFIG_ENDMA       0x0001
+#define BCM6816_IUDMA_CONFIG_PKTHALT     0x0002
+#define BCM6816_IUDMA_CONFIG_BURSTHALT   0x0004
+
+    uint16 reserved2;
+    uint16 intStat;
+#define BCM6816_IUDMA_INTSTAT_BDONE   0x0001
+#define BCM6816_IUDMA_INTSTAT_PDONE   0x0002
+#define BCM6816_IUDMA_INTSTAT_NOTVLD  0x0004
+#define BCM6816_IUDMA_INTSTAT_MASK    0x0007
+#define BCM6816_IUDMA_INTSTAT_ALL     BCM6816_IUDMA_INTSTAT_MASK
+
+    uint16 reserved3;
+    uint16 intMask;
+#define BCM6816_IUDMA_INTMASK_BDONE   0x0001
+#define BCM6816_IUDMA_INTMASK_PDONE   0x0002
+#define BCM6816_IUDMA_INTMASK_NOTVLD  0x0004
+
+    uint32 maxBurst;
+#define BCM6816_IUDMA_MAXBURST_SIZE 16 /* 32-bit words */
+
+} PcmIudmaChannelCtrl;
+
+
+typedef struct PcmIudmaStateRam
+{
+   uint32 baseDescPointer;                /* pointer to first buffer descriptor */
+
+   uint32 stateBytesDoneRingOffset;       /* state info: how manu bytes done and the offset of the
+                                             current descritor in process */
+#define BCM6816_IUDMA_STRAM_DESC_RING_OFFSET 0x3fff
+
+
+   uint32 flagsLengthStatus;              /* Length and status field of the current descriptor */
+
+   uint32 currentBufferPointer;           /* pointer to the current descriptor */
+
+} PcmIudmaStateRam;
+
+#define BCM6816_MAX_PCM_DMA_CHANNELS 2
+
+typedef struct PcmIudma
+{
+   PcmIudmaRegisters regs;                                        //
+   uint32 reserved1[110];                                         //
+   PcmIudmaChannelCtrl ctrl[BCM6816_MAX_PCM_DMA_CHANNELS];        //
+   uint32 reserved2[120];                                         //
+   PcmIudmaStateRam stram[BCM6816_MAX_PCM_DMA_CHANNELS];          //
+
+} PcmIudma;
+
+#define PCM_IUDMA ((volatile PcmIudma * const) PCM_DMA_BASE)
+
+
+#define IUDMA_MAX_CHANNELS          32
+
+/*
+** DMA Channel Configuration (1 .. 32)
+*/
+typedef struct DmaChannelCfg {
+  uint32        cfg;                    /* (00) assorted configuration */
+#define         DMA_ENABLE      0x00000001  /* set to enable channel */
+#define         DMA_PKT_HALT    0x00000002  /* idle after an EOP flag is detected */
+#define         DMA_BURST_HALT  0x00000004  /* idle after finish current memory burst */
+  uint32        intStat;                /* (04) interrupts control and status */
+  uint32        intMask;                /* (08) interrupts mask */
+#define         DMA_BUFF_DONE   0x00000001  /* buffer done */
+#define         DMA_DONE        0x00000002  /* packet xfer complete */
+#define         DMA_NO_DESC     0x00000004  /* no valid descriptors */
+  uint32        maxBurst;               /* (0C) max burst length permitted */
+#define         DMA_DESCSIZE_SEL 0x00040000  /* DMA Descriptor Size Selection */
+} DmaChannelCfg;
+
+/*
+** DMA State RAM (1 .. 16)
+*/
+typedef struct DmaStateRam {
+  uint32        baseDescPtr;            /* (00) descriptor ring start address */
+  uint32        state_data;             /* (04) state/bytes done/ring offset */
+  uint32        desc_len_status;        /* (08) buffer descriptor status and len */
+  uint32        desc_base_bufptr;       /* (0C) buffer descrpitor current processing */
+} DmaStateRam;
+
+
+/*
+** DMA Registers
+*/
+typedef struct DmaRegs {
+    uint32 controller_cfg;              /* (00) controller configuration */
+#define DMA_MASTER_EN           0x00000001
+#define DMA_FLOWC_CH1_EN        0x00000002
+#define DMA_FLOWC_CH3_EN        0x00000004
+
+    // Flow control Ch1
+    uint32 flowctl_ch1_thresh_lo;           /* 004 */
+    uint32 flowctl_ch1_thresh_hi;           /* 008 */
+    uint32 flowctl_ch1_alloc;               /* 00c */
+#define DMA_BUF_ALLOC_FORCE     0x80000000
+
+    // Flow control Ch3
+    uint32 flowctl_ch3_thresh_lo;           /* 010 */
+    uint32 flowctl_ch3_thresh_hi;           /* 014 */
+    uint32 flowctl_ch3_alloc;               /* 018 */
+
+    // Flow control Ch5
+    uint32 flowctl_ch5_thresh_lo;           /* 01C */
+    uint32 flowctl_ch5_thresh_hi;           /* 020 */
+    uint32 flowctl_ch5_alloc;               /* 024 */
+
+    // Flow control Ch7
+    uint32 flowctl_ch7_thresh_lo;           /* 028 */
+    uint32 flowctl_ch7_thresh_hi;           /* 02C */
+    uint32 flowctl_ch7_alloc;               /* 030 */
+
+    uint32 ctrl_channel_reset;              /* 034 */
+    uint32 ctrl_channel_debug;              /* 038 */
+    uint32 reserved1;                       /* 03C */
+    uint32 ctrl_global_interrupt_status;    /* 040 */
+    uint32 ctrl_global_interrupt_mask;      /* 044 */
+
+    // Unused words
+    uint8 reserved2[0x200-0x48];
+
+    // Per channel registers/state ram
+    DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */
+    union {
+        DmaStateRam     s[IUDMA_MAX_CHANNELS];
+        uint32          u32[4 * IUDMA_MAX_CHANNELS];
+    } stram;                                /* (400-5FF) state ram */
+} DmaRegs;
+
+#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE)
+
+/*
+** DMA Buffer
+*/
+typedef struct DmaDesc {
+  union {
+    struct {
+        uint16        length;                 /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM    0x8000
+#define          DMA_DESC_MULTICAST 0x4000
+#define          DMA_DESC_BUFLENGTH 0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                /* address of data */
+} DmaDesc;
+
+/*
+** 16 Byte DMA Buffer
+*/
+typedef struct {
+  union {
+    struct {
+        uint16        length;                 /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM        0x8000
+#define          DMA_DESC_MULTICAST     0x4000
+#define          DMA_DESC_BUFLENGTH     0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                 /* address of data */
+  uint32        control;
+#define         GEM_ID_MASK             0x001F
+  uint32        reserved;
+} DmaDesc16;
+
+/*
+** External Bus Interface
+*/
+typedef struct EbiChipSelect {
+    uint32    base;                         /* base address in upper 24 bits */
+#define EBI_SIZE_8K         0
+#define EBI_SIZE_16K        1
+#define EBI_SIZE_32K        2
+#define EBI_SIZE_64K        3
+#define EBI_SIZE_128K       4
+#define EBI_SIZE_256K       5
+#define EBI_SIZE_512K       6
+#define EBI_SIZE_1M         7
+#define EBI_SIZE_2M         8
+#define EBI_SIZE_4M         9
+#define EBI_SIZE_8M         10
+#define EBI_SIZE_16M        11
+#define EBI_SIZE_32M        12
+#define EBI_SIZE_64M        13
+#define EBI_SIZE_128M       14
+#define EBI_SIZE_256M       15
+    uint32    config;
+#define EBI_ENABLE          0x00000001      /* .. enable this range */
+#define EBI_WAIT_STATES     0x0000000e      /* .. mask for wait states */
+#define EBI_WTST_SHIFT      1               /* .. for shifting wait states */
+#define EBI_WORD_WIDE       0x00000010      /* .. 16-bit peripheral, else 8 */
+#define EBI_WREN            0x00000020      /* enable posted writes */
+#define EBI_POLARITY        0x00000040      /* .. set to invert something,
+                                        **    don't know what yet */
+#define EBI_TS_TA_MODE      0x00000080      /* .. use TS/TA mode */
+#define EBI_TS_SEL          0x00000100      /* .. drive tsize, not bs_b */
+#define EBI_FIFO            0x00000200      /* .. use fifo */
+#define EBI_RE              0x00000400      /* .. Reverse Endian */
+#define EBI_SETUP_SHIFT     16
+#define EBI_HOLD_SHIFT      20
+#define EBI_SETUP_STATES    0x0f0000
+#define EBI_HOLD_STATES     0xf00000
+} EbiChipSelect;
+
+typedef struct MpiRegisters {
+  EbiChipSelect cs[7];                  /* size chip select configuration */
+#define EBI_CS0_BASE            0
+#define EBI_CS1_BASE            1
+#define EBI_CS2_BASE            2
+#define EBI_CS3_BASE            3
+#define EBI_CS4_BASE            4
+#define EBI_CS5_BASE            5
+#define EBI_CS6_BASE            6
+  uint32        unused0[2];             /* reserved */
+  uint32        ebi_control;            /* ebi control */
+#define EBI_ACCESS_TIMEOUT      0x000007FF
+  uint32        unused1[7];             /* reserved */
+
+  uint32        sp0range;               /* PCI to internal system bus address space */
+#define ADDR_SPACE_MASK         0xFFFF0000
+  uint32        sp0remap;
+  uint32        sp0cfg;
+  uint32        sp1range;
+  uint32        sp1remap;
+  uint32        sp1cfg;
+
+  uint32        EndianCfg;
+
+  uint32        l2pcfgctl;              /* internal system bus to PCI IO/Cfg control */
+#define DIR_CFG_SEL             0x80000000 /* change from PCI I/O access to PCI config access */
+#define DIR_CFG_USEREG          0x40000000 /* use this register info for PCI configuration access */
+#define DEVICE_NUMBER           0x00007C00 /* device number for the PCI configuration access */
+#define FUNC_NUMBER             0x00000300 /* function number for the PCI configuration access */
+#define REG_NUMBER              0x000000FC /* register number for the PCI configuration access */
+#define CONFIG_TYPE             0x00000003 /* configuration type for the PCI configuration access */
+
+  uint32        l2pmrange1;             /* internal system bus to PCI memory space */
+#define PCI_SIZE_64K            0xFFFF0000
+#define PCI_SIZE_128K           0xFFFE0000
+#define PCI_SIZE_256K           0xFFFC0000
+#define PCI_SIZE_512K           0xFFF80000
+#define PCI_SIZE_1M             0xFFF00000
+#define PCI_SIZE_2M             0xFFE00000
+#define PCI_SIZE_4M             0xFFC00000
+#define PCI_SIZE_8M             0xFF800000
+#define PCI_SIZE_16M            0xFF000000
+#define PCI_SIZE_32M            0xFE000000
+  uint32        l2pmbase1;              /* kseg0 or kseg1 address & 0x1FFFFFFF */
+  uint32        l2pmremap1;
+#define CARDBUS_MEM             0x00000004
+#define MEM_WINDOW_EN           0x00000001
+  uint32        l2pmrange2;
+  uint32        l2pmbase2;
+  uint32        l2pmremap2;
+  uint32        l2piorange;             /* internal system bus to PCI I/O space */
+  uint32        l2piobase;
+  uint32        l2pioremap;
+
+  uint32        pcimodesel;
+#define PCI_INT_BUS_RD_PREFETCH 0x000001F0
+#define PCI_BAR2_NOSWAP         0x00000002 /* BAR at offset 0x20 */
+#define PCI_BAR1_NOSWAP         0x00000001 /* BAR at affset 0x1c */
+
+  uint32        pciintstat;             /* PCI interrupt mask/status */
+#define MAILBOX1_SENT           0x08
+#define MAILBOX0_SENT           0x04
+#define MAILBOX1_MSG_RCV        0x02
+#define MAILBOX0_MSG_RCV        0x01
+  uint32        locbuscntrl;            /* internal system bus control */
+#define DIR_U2P_NOSWAP          0x00000002
+#define EN_PCI_GPIO             0x00000001
+  uint32        locintstat;             /* internal system bus interrupt mask/status */
+#define CSERR                   0x0200
+#define SERR                    0x0100
+#define EXT_PCI_INT             0x0080
+#define DIR_FAILED              0x0040
+#define DIR_COMPLETE            0x0020
+#define PCI_CFG                 0x0010
+  uint32        unused4[7];
+
+  uint32        mailbox0;
+  uint32        mailbox1;
+
+  uint32        pcicfgcntrl;            /* internal system bus PCI configuration control */
+#define PCI_CFG_REG_WRITE_EN    0x00000080
+#define PCI_CFG_ADDR            0x0000003C
+  uint32        pcicfgdata;             /* internal system bus PCI configuration data */
+
+  uint32        locch2ctl;              /* PCI to interrnal system bus DMA (downstream) local control */
+#define MPI_DMA_HALT            0x00000008  /* idle after finish current memory burst */
+#define MPI_DMA_PKT_HALT        0x00000004  /* idle after an EOP flag is detected */
+#define MPI_DMA_STALL           0x00000002  /* idle after an EOP flag is detected */
+#define MPI_DMA_ENABLE          0x00000001  /* set to enable channel */
+  uint32        locch2intStat;
+#define MPI_DMA_NO_DESC         0x00000004  /* no valid descriptors */
+#define MPI_DMA_DONE            0x00000002  /* packet xfer complete */
+#define MPI_DMA_BUFF_DONE       0x00000001  /* buffer done */
+  uint32        locch2intMask;
+  uint32        unused5;
+  uint32        locch2descaddr;
+  uint32        locch2status1;
+#define LOCAL_DESC_STATE        0xE0000000
+#define PCI_DESC_STATE          0x1C000000
+#define BYTE_DONE               0x03FFC000
+#define RING_ADDR               0x00003FFF
+  uint32        locch2status2;
+#define BUFPTR_OFFSET           0x1FFF0000
+#define PCI_MASTER_STATE        0x000000C0
+#define LOC_MASTER_STATE        0x00000038
+#define CONTROL_STATE           0x00000007
+  uint32        unused6;
+
+  uint32        locch1Ctl;              /*internal system bus to PCI DMA (upstream) local control */
+#define DMA_U2P_LE              0x00000200  /* local bus is little endian */
+#define DMA_U2P_NOSWAP          0x00000100  /* lccal bus is little endian but no data swapped */
+  uint32        locch1intstat;
+  uint32        locch1intmask;
+  uint32        unused7;
+  uint32        locch1descaddr;
+  uint32        locch1status1;
+  uint32        locch1status2;
+  uint32        unused8;
+
+  uint32        pcich1ctl;              /* internal system bus to PCI DMA PCI control */
+  uint32        pcich1intstat;
+  uint32        pcich1intmask;
+  uint32        pcich1descaddr;
+  uint32        pcich1status1;
+  uint32        pcich1status2;
+
+  uint32        pcich2Ctl;              /* PCI to internal system bus DMA PCI control */
+  uint32        pcich2intstat;
+  uint32        pcich2intmask;
+  uint32        pcich2descaddr;
+  uint32        pcich2status1;
+  uint32        pcich2status2;
+
+  uint32        perm_id;                /* permanent device and vendor id */
+  uint32        perm_rev;               /* permanent revision id */
+} MpiRegisters;
+
+#define MPI ((volatile MpiRegisters * const) MPI_BASE)
+
+/* PCI configuration address space start offset 0x40 */
+#define BRCM_PCI_CONFIG_TIMER               0x40
+#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK    0x0000FF00
+#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK     0x000000FF
+
+/*
+** USB 2.0 Device Registers
+*/
+typedef struct UsbRegisters {
+#define USBD_CONTROL_APP_DONECSR                 0x0001
+#define USBD_CONTROL_APP_RESUME                  0x0002
+#define USBD_CONTROL_APP_RXFIFIO_INIT            0x0040
+#define USBD_CONTROL_APP_TXFIFIO_INIT            0x0080
+#define USBD_CONTROL_APP_FIFO_SEL_SHIFT          0x8
+#define USBD_CONTROL_APP_FIFO_INIT_SEL(x)        (((x)&0x0f)<<USBD_CONTROL_APP_FIFO_SEL_SHIFT)
+#define USBD_CONTROL_APP_AUTO_CSRS               0x2000
+#define USBD_CONTROL_APP_AUTO_INS_ZERO_LEN_PKT   0x4000
+#define EN_TXZLENINS  (1<<14)
+#define EN_RXZSCFG   (1<<12)
+#define APPSETUPERRLOCK  (1<<5)
+    uint32 usbd_control ;
+#define USBD_STRAPS_APP_SELF_PWR    0x0400
+#define USBD_STRAPS_APP_DEV_DISCON  0x0200
+#define USBD_STRAPS_APP_CSRPRG_SUP  0x0100
+#define USBD_STRAPS_APP_RAM_IF      0x0080
+#define USBD_STRAPS_APP_DEV_RMTWKUP 0x0040
+#define USBD_STRAPS_APP_PHYIF_8BIT  0x0004
+#define USBD_STRAPS_FULL_SPEED      0x0003
+#define USBD_STRAPS_LOW_SPEED       0x0002
+#define USBD_STRAPS_HIGH_SPEED      0x0000
+#define APPUTMIDIR(x)  ((x&1)<<3)
+#define UNIDIR   0
+    uint32 usbd_straps;
+#define USB_ENDPOINT_0  0x01
+    uint32 usbd_stall;
+#define USBD_ENUM_SPEED_SHIFT       12
+#define USBD_ENUM_SPEED             0x3000
+#define UDC20_ALTINTF(x) ((x>>8)&0xf)
+#define UDC20_INTF(x)  ((x>>4)&0xf)
+#define UDC20_CFG(x)  ((x>>0)&0xf)
+    uint32 usbd_status;
+#define USBD_LINK                   (0x1<<10)
+#define USBD_SET_CSRS               0x40
+#define USBD_SUSPEND                0x20
+#define USBD_EARLY_SUSPEND          0x10
+#define USBD_SOF                    0x08
+#define USBD_ENUMON                 0x04
+#define USBD_SETUP                  0x02
+#define USBD_USBRESET               0x01
+    uint32 usbd_events;
+    uint32 usbd_events_irq;
+#define UPPER(x)   (16+x)
+#define ENABLE(x)   (1<<x)
+#define SWP_TXBSY   (15)
+#define SWP_RXBSY   (14)
+#define SETUP_ERR   (13)
+#define APPUDCSTALLCHG  (12)
+#define BUS_ERR    (11)
+#define USB_LINK                                (10)
+#define HST_SETCFG   (9)
+#define HST_SETINTF   (8)
+#define ERRATIC_ERR   (7)
+#define SET_CSRS   (6)
+#define SUSPEND    (5)
+#define ERLY_SUSPEND  (4)
+#define SOF     (3)
+#define ENUM_ON    (2)
+#define SETUP    (1)
+#define USB_RESET   (0)
+#define RISING(x)   (0x0<<2*x)
+#define FALLING(x)   (0x1<<2*x)
+#define USBD_IRQCFG_ENUM_ON_FALLING_EDGE 0x00000010
+    uint32 usbd_irqcfg_hi ;
+    uint32 usbd_irqcfg_lo ;
+#define USBD_USB_RESET_IRQ          0x00000001
+#define USBD_USB_SETUP_IRQ          0x00000002 // non-standard setup cmd rcvd
+#define USBD_USB_ENUM_ON_IRQ        0x00000004
+#define USBD_USB_SOF_IRQ            0x00000008
+#define USBD_USB_EARLY_SUSPEND_IRQ  0x00000010
+#define USBD_USB_SUSPEND_IRQ        0x00000020 // non-standard setup cmd rcvd
+#define USBD_USB_SET_CSRS_IRQ       0x00000040
+#define USBD_USB_ERRATIC_ERR_IRQ    0x00000080
+#define USBD_USB_SETCFG_IRQ         0x00000200
+#define USBD_USB_LINK_IRQ                       0x00000400
+    uint32 usbd_events_irq_mask;
+    uint32 usbd_swcfg;
+    uint32 usbd_swtxctl;
+    uint32 usbd_swrxctl;
+    uint32 usbd_txfifo_rwptr;
+    uint32 usbd_rxfifo_rwptr;
+    uint32 usbd_txfifo_st_rwptr;
+    uint32 usbd_rxfifo_st_rwptr;
+    uint32 usbd_txfifo_config ;
+    uint32 usbd_rxfifo_config ;
+    uint32 usbd_txfifo_epsize ;
+    uint32 usbd_rxfifo_epsize ;
+#define USBD_EPNUM_CTRL             0x0
+#define USBD_EPNUM_ISO              0x1
+#define USBD_EPNUM_BULK             0x2
+#define USBD_EPNUM_IRQ              0x3
+#define USBD_EPNUM_EPTYPE(x)        (((x)&0x3)<<8)
+#define USBD_EPNUM_EPDMACHMAP(x)    (((x)&0xf)<<0)
+    uint32 usbd_epnum_typemap ;
+    uint32 usbd_reserved [0xB] ;
+    uint32 usbd_csr_setupaddr ;
+#define USBD_EPNUM_MASK             0xf
+#define USBD_EPNUM(x)               ((x&USBD_EPNUM_MASK)<<0)
+#define USBD_EPDIR_IN               (1<<4)
+#define USBD_EPDIR_OUT              (0<<4)
+#define USBD_EPTYP_CTRL             (USBD_EPNUM_CTRL<<5)
+#define USBD_EPTYP_ISO              (USBD_EPNUM_ISO<<5)
+#define USBD_EPTYP_BULK             (USBD_EPNUM_BULK<<5)
+#define USBD_EPTYP_IRQ              (USBD_EPNUM_IRQ<<5)
+#define USBD_EPCFG_MASK             0xf
+#define USBD_EPCFG(x)               ((x&USBD_EPCFG_MASK)<<7)
+#define USBD_EPINTF_MASK            0xf
+#define USBD_EPINTF(x)              ((x&USBD_EPINTF_MASK)<<11)
+#define USBD_EPAINTF_MASK           0xf
+#define USBD_EPAINTF(x)             ((x&USBD_EPAINTF_MASK)<<15)
+#define USBD_EPMAXPKT_MSK           0x7ff
+#define USBD_EPMAXPKT(x)            ((x&USBD_EPMAXPKT_MSK)<<19)
+#define USBD_EPISOPID_MASK          0x3
+#define USBD_EPISOPID(x)            ((x&USBD_ISOPID_MASK)<<30)
+    uint32 usbd_csr_ep [5] ;
+} UsbRegisters;
+
+#define USB ((volatile UsbRegisters * const) USB_CTL_BASE)
+
+typedef struct USBControl {
+    uint32 BrtControl1;
+    uint32 BrtControl2;
+    uint32 BrtStatus1;
+    uint32 BrtStatus2;
+    uint32 UTMIControl1;
+    uint32 TestPortControl;
+    uint32 PllControl1;
+    uint32 SwapControl;
+#define USB_DEVICE_SEL          (1<<6)
+#define EHCI_LOGICAL_ADDRESS_EN (1<<5)
+#define EHCI_ENDIAN_SWAP        (1<<4)
+#define EHCI_DATA_SWAP          (1<<3)
+#define OHCI_LOGICAL_ADDRESS_EN (1<<2)
+#define OHCI_ENDIAN_SWAP        (1<<1)
+#define OHCI_DATA_SWAP          (1<<0)
+    uint32 unused1;
+    uint32 FrameAdjustValue;
+    uint32 Setup;
+#define USBH_IOC                (1<<4)
+    uint32 MDIO;
+    uint32 MDIO32;
+    uint32 USBSimControl;
+} USBControl;
+
+#define USBH ((volatile USBControl * const) USBH_CFG_BASE)
+
+/*
+** GPON SERDES Registers
+*/
+typedef struct GponSerdesRegs {
+  uint32 topCfg;
+  uint32 swReset;
+  uint32 aeCfg;
+  uint32 aeStatus;
+  uint32 phyCfg;
+  uint32 phyStatus;
+  uint32 mdioWr;
+  uint32 mdioRd;
+  uint32 reserved[2];
+  uint32 fifoCfg;
+  uint32 fifoStatus;
+  uint32 patternCfg[4];
+  uint32 patternStatus[2];
+  uint32 laserCfg;
+#define GPON_SERDES_LASERMODE_MASK (3<<30)
+#define GPON_SERDES_LASERMODE_NORMAL (0<<30)
+#define GPON_SERDES_LASERMODE_FORCE_OFF (1<<30)
+#define GPON_SERDES_LASERMODE_FORCE_ON (2<<30)
+  uint32 laserStatus;
+  uint32 miscCfg;
+  uint32 miscStatus;
+  uint32 phDet[5];
+} GponSerdesRegs;
+
+#define GPON_SERDES ((volatile GponSerdesRegs * const) GPON_SERDES_BASE)
+
+
+/*
+** PCI-E
+*/
+typedef struct PcieRegs{
+  uint32 devVenID;
+  uint16 command;
+  uint16 status;
+  uint32 revIdClassCode;
+  uint32 headerTypeLatCacheLineSize;
+  uint32 bar1;
+  uint32 bar2;
+  uint32 priSecBusNo;
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK              0x00ff0000
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT             16
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK              0x0000ff00
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT             8
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK              0x000000ff
+} PcieRegs;
+
+typedef struct PcieBlk404Regs{
+  uint32 unused;          /* 0x404 */
+  uint32 config2;         /* 0x408 */
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK         0x0000000f
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE           0
+  uint32 config3;         /* 0x40c */
+  uint32 pmDataA;         /* 0x410 */
+  uint32 pmDataB;         /* 0x414 */
+} PcieBlk404Regs;
+
+typedef struct PcieBlk428Regs{
+   uint32 vpdIntf;        /* 0x428 */
+   uint16 unused_g;       /* 0x42c */
+   uint16 vpdAddrFlag;    /* 0x42e */
+   uint32 vpdData;        /* 0x430 */
+   uint32 idVal1;         /* 0x434 */
+   uint32 idVal2;         /* 0x438 */
+   uint32 idVal3;         /* 0x43c */
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK                    0xff000000
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT                   24
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK                     0x00ffffff
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT                    16
+#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT                 8
+}PcieBlk428Regs;
+
+typedef struct PcieBridgeRegs{
+   uint32 bar1Remap;       /* 0x0818*/
+   uint32 bar2Remap;       /* 0x081c*/
+   uint32 bridgeOptReg1;   /* 0x0820*/
+#define PCIE_BRIDGE_OPT_REG1_EN_RD_BE                  (1 << 4)
+#define PCIE_BRIDGE_OPT_REG1_EN_RD_BE_NOSWAP           (1 << 5)
+   uint32 bridgeOptReg2;    /* 0x0824*/
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK    0xe0000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT   29
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK     0x1f000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT    24
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK     0x00ff0000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT    16
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK     0x00000080
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT    7
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK     0x00000040
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT    6
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK       0x00000020
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT      5
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK    0x00000010
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT   4
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK   0x00000004
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT  2
+#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK         0x0000ff0b
+}PcieBridgeRegs;
+
+typedef struct PcieBlk1000Regs{
+   uint32 undisclosed[18]; /*0x1000 - 0x1044*/
+   uint32 dlStatus;        /* 0x1048 */
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK                   0x00002000
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT                  13
+}PcieBlk1000Regs;
+
+typedef struct PcieBlk1800Regs{
+#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS         4
+  uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS];
+#define REG_POWERDOWN_P1PLL_ENA                      (1<<12)
+  uint32 phyErrorAttnVec;
+  uint32 phyErrorAttnMask;
+#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS   3
+  uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS];
+#define NUM_PCIE_BLK_1800_PHY_DBG_REGS          11
+  uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS];
+} PcieBlk1800Regs;
+
+#define PCIEH_DEV_OFFSET              0x8000
+#define PCIEH                         ((volatile uint32 * const) PCIE_BASE)
+#define PCIEH_REGS                    ((volatile PcieCfeType1Regs * const) PCIE_BASE)
+#define PCIEH_BLK_404_REGS            ((volatile PcieBlk404Regs * const)(PCIE_BASE+0x404))
+#define PCIEH_BLK_428_REGS            ((volatile PcieBlk428Regs * const)(PCIE_BASE+0x428))
+#define PCIEH_BRIDGE_REGS             ((volatile PcieBridgeRegs * const) (PCIE_BASE+0x818))
+#define PCIEH_BLK_1000_REGS           ((volatile PcieBlk1000Regs * const) (PCIE_BASE+0x1000))
+#define PCIEH_BLK_1800_REGS           ((volatile PcieBlk1800Regs * const) (PCIE_BASE+0x1800))
+
+typedef struct EthSwRegs{
+    byte port_traffic_ctrl[9]; /* 0x00 - 0x08 */
+    byte reserved1[2]; /* 0x09 - 0x0a */
+    byte switch_mode; /* 0x0b */
+    unsigned short pause_quanta; /*0x0c */
+    byte imp_port_state; /*0x0e */
+    byte led_refresh; /* 0x0f */
+    unsigned short led_function[2]; /* 0x10 */
+    unsigned short led_function_map; /* 0x14 */
+    unsigned short led_enable_map; /* 0x16 */
+    unsigned short led_mode_map0; /* 0x18 */
+    unsigned short led_function_map1; /* 0x1a */
+    byte reserved2[5]; /* 0x1b - 0x20 */
+    byte port_forward_ctrl; /* 0x21 */
+    byte reserved3[2]; /* 0x22 - 0x23 */
+    unsigned short protected_port_selection; /* 0x24 */
+    unsigned short wan_port_select; /* 0x26 */
+    unsigned int pause_capability; /* 0x28 */
+    byte reserved4[3]; /* 0x2c - 0x2e */
+    byte reserved_multicast_control; /* 0x2f */
+    byte reserved5; /* 0x30 */
+    byte txq_flush_mode_control; /* 0x31 */
+    unsigned short ulf_forward_map; /* 0x32 */
+    unsigned short mlf_forward_map; /* 0x34 */
+    unsigned short mlf_impc_forward_map; /* 0x36 */
+    unsigned short pause_pass_through_for_rx; /* 0x38 */
+    unsigned short pause_pass_through_for_tx; /* 0x3a */
+    unsigned short disable_learning; /* 0x3c */
+    byte reserved6[26]; /* 0x3e - 0x57 */
+    byte port_state_override[8]; /* 0x58 - 0x5f */
+    byte reserved7[4]; /* 0x60 - 0x63 */
+    byte imp_rgmii_ctrl_p4; /* 0x64 */
+    byte imp_rgmii_ctrl_p5; /* 0x65 */
+    byte reserved8[6]; /* 0x66 - 0x6b */
+    byte rgmii_timing_delay_p4; /* 0x6c */
+    byte gmii_timing_delay_p5; /* 0x6d */
+    byte reserved9[11]; /* 0x6e - 0x78 */
+    byte software_reset; /* 0x79 */
+    byte reserved13[6]; /* 0x7a - 0x7f */
+    byte pause_frame_detection; /* 0x80 */
+    byte reserved10[7]; /* 0x81 - 0x87 */
+    byte fast_aging_ctrl; /* 0x88 */
+    byte fast_aging_port; /* 0x89 */
+    byte fast_aging_vid; /* 0x8a */
+    byte reserved11[21]; /* 0x8b - 0x9f */
+    unsigned int swpkt_ctrl_sar; /*0xa0 */
+    unsigned int swpkt_ctrl_usb; /*0xa4 */
+    unsigned int iudma_ctrl; /*0xa8 */
+    unsigned int rxfilt_ctrl; /*0xac */
+    unsigned int mdio_ctrl; /*0xb0 */
+    unsigned int mdio_data; /*0xb4 */
+    byte reserved12[42]; /* 0xb6 - 0xdf */
+    unsigned int sw_mem_test; /*0xe0 */
+} EthSwRegs;
+
+#define ETHSWREG ((volatile EthSwRegs * const) SWITCH_BASE)
+
+typedef struct EthSwMIBRegs {
+    unsigned int TxOctetsLo;
+    unsigned int TxOctetsHi;
+    unsigned int TxDropPkts;
+    unsigned int TxQoSPkts;
+    unsigned int TxBroadcastPkts;
+    unsigned int TxMulticastPkts;
+    unsigned int TxUnicastPkts;
+    unsigned int TxCol;
+    unsigned int TxSingleCol;
+    unsigned int TxMultipleCol;
+    unsigned int TxDeferredTx;
+    unsigned int TxLateCol;
+    unsigned int TxExcessiveCol;
+    unsigned int TxFrameInDisc;
+    unsigned int TxPausePkts;
+    unsigned int TxQoSOctetsLo;
+    unsigned int TxQoSOctetsHi;
+    unsigned int RxOctetsLo;
+    unsigned int RxOctetsHi;
+    unsigned int RxUndersizePkts;
+    unsigned int RxPausePkts;
+    unsigned int Pkts64Octets;
+    unsigned int Pkts65to127Octets;
+    unsigned int Pkts128to255Octets;
+    unsigned int Pkts256to511Octets;
+    unsigned int Pkts512to1023Octets;
+    unsigned int Pkts1024to1522Octets;
+    unsigned int RxOversizePkts;
+    unsigned int RxJabbers;
+    unsigned int RxAlignErrs;
+    unsigned int RxFCSErrs;
+    unsigned int RxGoodOctetsLo;
+    unsigned int RxGoodOctetsHi;
+    unsigned int RxDropPkts;
+    unsigned int RxUnicastPkts;
+    unsigned int RxMulticastPkts;
+    unsigned int RxBroadcastPkts;
+    unsigned int RxSAChanges;
+    unsigned int RxFragments;
+    unsigned int RxExcessSizeDisc;
+    unsigned int RxSymbolError;
+    unsigned int RxQoSPkts;
+    unsigned int RxQoSOctetsLo;
+    unsigned int RxQoSOctetsHi;
+    unsigned int Pkts1523to2047;
+    unsigned int Pkts2048to4095;
+    unsigned int Pkts4096to8191;
+    unsigned int Pkts8192to9728;
+} EthSwMIBRegs;
+
+#define ETHSWMIBREG ((volatile EthSwMIBRegs * const) (SWITCH_BASE + 0x2000))
+
+/*
+** NAND Interrupt Controller Registers
+*/
+typedef struct NandIntrCtrlRegs {
+    uint32 NandInterrupt;
+#define NINT_ENABLE_MASK    0xffff0000
+#define NINT_STS_MASK       0x00000fff
+#define NINT_ECC_ERROR_CORR 0x00000080
+#define NINT_ECC_ERROR_UNC  0x00000040
+#define NINT_DEV_RBPIN      0x00000020
+#define NINT_CTRL_READY     0x00000010
+#define NINT_PAGE_PGM       0x00000008
+#define NINT_COPY_BACK      0x00000004
+#define NINT_BLOCK_ERASE    0x00000002
+#define NINT_NP_READ        0x00000001
+
+    uint32 NandBaseAddr0;   /* Default address when booting from NAND flash */
+    uint32 reserved;
+    uint32 NandBaseAddr1;   /* Secondary base address for NAND flash */
+} NandIntrCtrlRegs;
+
+#define NAND_INTR ((volatile NandIntrCtrlRegs * const) NAND_INTR_BASE)
+
+/*
+** NAND Controller Registers
+*/
+typedef struct NandCtrlRegs {
+    uint32 NandRevision;            /* NAND Revision */
+    uint32 NandCmdStart;            /* Nand Flash Command Start */
+#define NCMD_MASK           0x0f000000
+#define NCMD_BLK_LOCK_STS   0x0d000000
+#define NCMD_BLK_UNLOCK     0x0c000000
+#define NCMD_BLK_LOCK_DOWN  0x0b000000
+#define NCMD_BLK_LOCK       0x0a000000
+#define NCMD_FLASH_RESET    0x09000000
+#define NCMD_BLOCK_ERASE    0x08000000
+#define NCMD_DEV_ID_READ    0x07000000
+#define NCMD_COPY_BACK      0x06000000
+#define NCMD_PROGRAM_SPARE  0x05000000
+#define NCMD_PROGRAM_PAGE   0x04000000
+#define NCMD_STS_READ       0x03000000
+#define NCMD_SPARE_READ     0x02000000
+#define NCMD_PAGE_READ      0x01000000
+
+    uint32 NandCmdExtAddr;          /* Nand Flash Command Extended Address */
+    uint32 NandCmdAddr;             /* Nand Flash Command Address */
+    uint32 NandCmdEndAddr;          /* Nand Flash Command End Address */
+    uint32 NandNandBootConfig;      /* Nand Flash Boot Config */
+#define NBC_CS_LOCK         0x80000000
+#define NBC_AUTO_DEV_ID_CFG 0x40000000
+#define NBC_WR_PROT_BLK0    0x10000000
+
+    uint32 NandCsNandXor;           /* Nand Flash EBI CS Address XOR with */
+                                    /*   1FC0 Control */
+    uint32 NandReserved;
+    uint32 NandSpareAreaReadOfs0;   /* Nand Flash Spare Area Read Bytes 0-3 */
+    uint32 NandSpareAreaReadOfs4;   /* Nand Flash Spare Area Read Bytes 4-7 */
+    uint32 NandSpareAreaReadOfs8;   /* Nand Flash Spare Area Read Bytes 8-11 */
+    uint32 NandSpareAreaReadOfsC;   /* Nand Flash Spare Area Read Bytes 12-15*/
+    uint32 NandSpareAreaWriteOfs0;  /* Nand Flash Spare Area Write Bytes 0-3 */
+    uint32 NandSpareAreaWriteOfs4;  /* Nand Flash Spare Area Write Bytes 4-7 */
+    uint32 NandSpareAreaWriteOfs8;  /* Nand Flash Spare Area Write Bytes 8-11*/
+    uint32 NandSpareAreaWriteOfsC;  /* Nand Flash Spare Area Write Bytes12-15*/
+    uint32 NandAccControl;          /* Nand Flash Access Control */
+    uint32 NandConfig;              /* Nand Flash Config */
+#define NC_CONFIG_LOCK      0x80000000
+#define NC_PG_SIZE_MASK     0x40000000
+#define NC_PG_SIZE_2K       0x40000000
+#define NC_PG_SIZE_512B     0x00000000
+#define NC_BLK_SIZE_MASK    0x30000000
+#define NC_BLK_SIZE_512K    0x30000000
+#define NC_BLK_SIZE_128K    0x10000000
+#define NC_BLK_SIZE_16K     0x00000000
+#define NC_BLK_SIZE_8K      0x20000000
+#define NC_DEV_SIZE_MASK    0x0f000000
+#define NC_DEV_SIZE_SHIFT   24
+#define NC_DEV_WIDTH_MASK   0x00800000
+#define NC_DEV_WIDTH_16     0x00800000
+#define NC_DEV_WIDTH_8      0x00000000
+#define NC_FUL_ADDR_MASK    0x00070000
+#define NC_FUL_ADDR_SHIFT   16
+#define NC_BLK_ADDR_MASK    0x00000700
+#define NC_BLK_ADDR_SHIFT   8
+
+    uint32 NandTiming1;             /* Nand Flash Timing Parameters 1 */
+    uint32 NandTiming2;             /* Nand Flash Timing Parameters 2 */
+    uint32 NandSemaphore;           /* Semaphore */
+    uint32 NandFlashDeviceId;       /* Nand Flash Device ID */
+    uint32 NandBlockLockStatus;     /* Nand Flash Block Lock Status */
+    uint32 NandIntfcStatus;         /* Nand Flash Interface Status */
+#define NIS_CTLR_READY      0x80000000
+#define NIS_FLASH_READY     0x40000000
+#define NIS_CACHE_VALID     0x20000000
+#define NIS_SPARE_VALID     0x10000000
+#define NIS_FLASH_STS_MASK  0x000000ff
+#define NIS_WRITE_PROTECT   0x00000080
+#define NIS_DEV_READY       0x00000040
+#define NIS_PGM_ERASE_ERROR 0x00000001
+
+    uint32 NandEccCorrExtAddr;      /* ECC Correctable Error Extended Address*/
+    uint32 NandEccCorrAddr;         /* ECC Correctable Error Address */
+    uint32 NandEccUncExtAddr;       /* ECC Uncorrectable Error Extended Addr */
+    uint32 NandEccUncAddr;          /* ECC Uncorrectable Error Address */
+    uint32 NandFlashReadExtAddr;    /* Flash Read Data Extended Address */
+    uint32 NandFlashReadAddr;       /* Flash Read Data Address */
+    uint32 NandProgramPageExtAddr;  /* Page Program Extended Address */
+    uint32 NandProgramPageAddr;     /* Page Program Address */
+    uint32 NandCopyBackExtAddr;     /* Copy Back Extended Address */
+    uint32 NandCopyBackAddr;        /* Copy Back Address */
+    uint32 NandBlockEraseExtAddr;   /* Block Erase Extended Address */
+    uint32 NandBlockEraseAddr;      /* Block Erase Address */
+    uint32 NandInvReadExtAddr;      /* Flash Invalid Data Extended Address */
+    uint32 NandInvReadAddr;         /* Flash Invalid Data Address */
+    uint32 NandBlkWrProtect;        /* Block Write Protect Enable and Size */
+                                    /*   for EBI_CS0b */
+} NandCtrlRegs;
+
+#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE)
+
+#define NAND_CACHE ((volatile uint8 * const) NAND_CACHE_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/shared/broadcom/include/bcm963xx/mocablock.h b/shared/broadcom/include/bcm963xx/mocablock.h
new file mode 100755
index 0000000..bccb24b
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/mocablock.h
@@ -0,0 +1,144 @@
+/*
+<:copyright-broadcom 
+ 
+ Copyright (c) 2007 Broadcom Corporation 
+ All Rights Reserved 
+ No portions of this material may be reproduced in any form without the 
+ written permission of: 
+          Broadcom Corporation 
+          5300 California Avenue
+          Irvine, California 92617 
+ All information contained in this document is Broadcom Corporation 
+ company private, proprietary, and trade secret. 
+ 
+:>
+*/
+/***************************************************************************
+ * File Name  : MoCABlock.h
+ *
+ * Description: This file contains definitions for the MoCA Block for the
+ *              BCM6816 and the BCM3450 chipset(s).
+ ***************************************************************************/
+
+#if !defined(_MoCABLOCK_H_)
+#define _MoCABLOCK_H_
+
+/* BCM 96816 related definitions . */
+#define MoCA_INTERRUPT_DISABLE               0x0
+#define MoCA_INTERRUPT_ENABLE                0x1
+
+/* Definitions for coreInterrupts from host */
+#define MoCA_HOST_RESP_TO_CORE               0x1
+#define MoCA_HOST_REQ_TO_CORE                0x2
+
+/* Definitions for hostInterrupts from core */
+#define MoCA_CORE_RESP_TO_HOST               0x1
+#define MoCA_CORE_REQ_TO_HOST                0x2
+#define MoCA_CORE_ASSERT_TO_HOST             0x4
+#define MoCA_CORE_UNUSED                     0xFC
+#define MoCA_CORE_DDR_START                  0x100
+#define MoCA_CORE_DDR_END                    0x200
+
+#define MoCA_LED_LINK_ON_ACTIVE_OFF          0x0
+#define MoCA_LED_LINK_OFF_ACTIVE_OFF         0x1
+#define MoCA_LED_LINK_ON_ACTIVE_ON           0x2
+#define MoCA_LED_LINK_OFF_ACTIVE_ON          0x3 /* NW Search and New Node Admission */
+typedef struct _MoCAExtras {
+   UINT32 host2MoCAIntEn ;
+   UINT32 host2MoCAIntTrig ;
+   UINT32 host2MoCAIntStatus ;
+   UINT32 MoCA2HostIntEn ;
+   UINT32 MoCA2HostIntTrig ;
+   UINT32 MoCA2HostIntStatus ;
+   UINT32 genPurpose0 ;
+   UINT32 genPurpose1 ;
+   UINT32 sideBandGmiiFC ;
+   UINT32 leds ;
+   UINT32 MoCAStatus ;
+   UINT32 testMuxSel ;
+   UINT32 mdCtrl ;
+   UINT32 mdcDivider ;
+   UINT32 outRefIntR01 ;
+   UINT32 outRefIntR02 ;
+   UINT32 outRefIntR03 ;
+   UINT32 outRefIntR04 ;
+   UINT32 outRefIntR05 ;
+   UINT32 outRefIntSel ;
+} MoCAExtras ;
+
+
+typedef struct _MoCAMACRegs {
+   UINT32 macCtrl ;           // 0x00
+#define MoCA_MAC_REGS_MAC_CTRL_MAC_ENABLE    0x00000001
+   UINT32 resv1 [7] ;
+   UINT32 frmHdr  ;           // 0x20
+   UINT32 msduHdr ;           // 0x24
+   UINT32 resv2 [2] ;
+   UINT32 macStatus ;         // 0x30
+   UINT32 macStatusEn ;       // 0x34
+   UINT32 resv3 [2] ;
+   UINT32 netTimer ;          // 0x40
+   UINT32 maxNetTimerCorr ;   // 0x44
+   UINT32 timerCorrCtrl ;     // 0x48
+   UINT32 bitParams ;         // 0x4c
+   UINT32 fineCorr ;          // 0x50
+   UINT32 coarseCorr ;        // 0x54
+   UINT32 loadTimer1 ;        // 0x58
+   UINT32 loadTimer2 ;        // 0x5c
+   UINT32 mpiConfigCtrl ;     // 0x60
+#define MoCA_MAC_REGS_MPI_CONFIG_CTRL_READ 			0x00000001
+#define MoCA_MAC_REGS_MPI_CONFIG_CTRL_WRITE			0x00000002
+   UINT32 mpiConfigAddr ;     // 0x64
+   UINT32 mpiConfigDataW ;    // 0x68
+   UINT32 mpiConfigDataR ;    // 0x6c
+} MoCA_MAC_REGST, *PMoCA_MAC_REGST ;
+
+#define MoCA_BLOCK_BASE                                          MOCA_MEM_BASE
+typedef struct MoCABlockT {
+
+   UINT8       dataMem [0x3FFFC] ;
+   UINT8       resvd [0x61403] ;
+   MoCAExtras  extras ;                                           // 0xb0da1400.
+   //MoCAHostM2M follows.
+   //MoCAMoCAM2M follows.
+} MoCA_BLOCKT, *PMoCA_BLOCKT ;
+
+#define MoCA_PHYS_IO_BASE								NONCACHE_TO_PHYS(MOCA_IO_BASE)
+#define MoCA_BLOCK_MAC_REGS_START					(MOCA_IO_BASE+0x400)
+#define MoCA_BLOCK_PHY_START                    MoCA_PHYS_IO_BASE+0x8000
+#define MoCA_BLOCK_PHY_END                      MoCA_PHYS_IO_BASE+0xA3FF
+#define MoCA_BLOCK ((volatile PMoCA_BLOCKT const) MoCA_BLOCK_BASE)
+#define MoCA_MAC_REGS ((volatile PMoCA_MAC_REGST const) MoCA_BLOCK_MAC_REGS_START)
+#define MoCA_CORE_MEM_BASE                      MoCA_BLOCK->dataMem
+#define MoCA_MAIL_BOX_ADDR_REG                  MoCA_BLOCK->extras.genPurpose0
+#define MoCA_IQ_SNR_ADDR_REG                    MoCA_BLOCK->extras.genPurpose1
+
+/* BCM 93450 related definitions . */
+
+#define BCM3450_I2C_CHIP_ADDRESS    0x70
+typedef struct _Bcm3450Reg {
+   UINT32   ChipId;           /* 0x0 */
+   UINT32   ChipRev;          /* 0x4 */
+   UINT32   Test;             /* 0x8 */
+   UINT32   SerialCtl;        /* 0xc */
+   UINT32   StatusRead;       /* 0x10 */
+   UINT32   LnaCntl;          /* 0x14 */
+   UINT32   PaCntl;           /* 0x18 */
+#define BCM3450_PACNTL_PA_RDEG_SHIFT           11
+#define BCM3450_PACNTL_PA_RDEG_MASK            0x00007800
+#define BCM3450_PACNTL_PA_CURR_CONT_SHIFT      5
+#define BCM3450_PACNTL_PA_CURR_CONT_MASK       0x000007E0
+#define BCM3450_PACNTL_PA_CURR_FOLLOWER_SHIFT  2
+#define BCM3450_PACNTL_PA_CURR_FOLLOWER_MASK   0x0000001C
+#define BCM3450_PACNTL_PA_PWRDWN_SHIFT         0
+#define BCM3450_PACNTL_PA_PWRDWN_MASK          0x00000001
+#define BCM3450_PACNTL_OFFSET          		  0x18
+   UINT32   Misc;             /* 0x1c */
+#define BCM3452_MISC_BG_PWRDWN_SHIFT 15
+#define BCM3452_MISC_BG_PWRDWN_MASK  0x00008000
+#define BCM3450_MISC_IIC_RESET       0x1
+#define BCM3450_MISC_SERIAL_RESET    0x2
+#define BCM3450_MISC_OFFSET          0x1c
+} Bcm3450Reg ;
+
+#endif /* _MoCABLOCK_H_ */
diff --git a/shared/broadcom/include/bcm963xx/robosw_reg.h b/shared/broadcom/include/bcm963xx/robosw_reg.h
new file mode 100755
index 0000000..4fcc0ac
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/robosw_reg.h
@@ -0,0 +1,169 @@
+/*
+<:copyright-broadcom
+
+ Copyright (c) 2007 Broadcom Corporation
+ All Rights Reserved
+ No portions of this material may be reproduced in any form without the
+ written permission of:
+          Broadcom Corporation
+          16215 Alton Parkway
+          Irvine, California 92619
+ All information contained in this document is Broadcom Corporation
+ company private, proprietary, and trade secret.
+
+:>
+*/
+
+#ifndef __ROBOSW_REG_H
+#define __ROBOSW_REG_H
+
+void robosw_init(void);
+void robosw_configure_ports(void);
+void robosw_check_ports(void);
+
+// These macros make offset validation vs. data sheet easier.
+
+#define group(type, name, start_offset, next) type name[(next - start_offset) / sizeof(type)]
+#define entry(type, name, start_offset, next) type name
+
+typedef struct RoboSwitch {
+  group(byte,     PortCtrl,     0x0000, 0x0009);
+  group(byte,     Reserved0009, 0x0009, 0x000b);
+  entry(byte,     SwitchMode,   0x000b, 0x000c);
+  entry(uint16,   PauseQuanta,  0x000c, 0x000e);
+  entry(byte,     ImpOverride,  0x000e, 0x000f);
+  entry(byte,     LedRefresh,   0x000f, 0x0010);
+  entry(uint16,   LedFunc0,     0x0010, 0x0012);
+  entry(uint16,   LedFunc1,     0x0012, 0x0014);
+  entry(uint16,   LedFuncMap,   0x0014, 0x0016);
+  entry(uint16,   LedEnableMap, 0x0016, 0x0018);
+  entry(uint16,   LedMap0,      0x0018, 0x001a);
+  entry(uint16,   LedMap1,      0x001a, 0x001c);
+  group(byte,     Reserved001c, 0x001c, 0x0020);
+  group(byte,     Reserved0020, 0x0020, 0x0021);
+  entry(byte,     ForwardCtrl,  0x0021, 0x0022);
+  group(byte,     Reserved0022, 0x0022, 0x0024);
+  entry(uint16,   ProtSelect,   0x0024, 0x0026);
+  entry(uint16,   WanSelect,    0x0026, 0x0028);
+  entry(uint32,   PauseCap,     0x0028, 0x002c);
+  group(byte,     Reserved002c, 0x002c, 0x002f);
+  entry(byte,     MultiCtrl,    0x002f, 0x0030);
+  group(byte,     Reserved0030, 0x0030, 0x0031);
+  entry(byte,     TxqFlush,     0x0031, 0x0032);
+  entry(uint16,   UniFail,      0x0032, 0x0034);
+  entry(uint16,   MultiFail,    0x0034, 0x0036);
+  entry(uint16,   MlfIpmc,      0x0036, 0x0038);
+  entry(uint16,   PausePassRx,  0x0038, 0x003a);
+  entry(uint16,   PausePassTx,  0x003a, 0x003c);
+  entry(uint16,   DisableLearn, 0x003c, 0x003e);
+  group(byte,     Reserved003e, 0x003e, 0x004a);
+  entry(uint16,   PllTest,      0x004a, 0x004c);
+  group(byte,     Reserved004c, 0x004c, 0x0058);
+  group(byte,     PortOverride, 0x0058, 0x0060);
+  group(byte,	  Reserved0061, 0x0060, 0x0064);
+  entry(byte,     ImpRgmiiCtrlP4, 0x0064, 0x0065);
+  entry(byte,	  ImpRgmiiCtrlP5, 0x0065, 0x0066);
+  group(byte,     Reserved0066, 0x0066, 0x006c);
+  entry(byte,     ImpRgmiiTimingDelayP4, 0x006c, 0x006d);
+  entry(byte,	  ImpRgmiiTimingDelayP5, 0x006d, 0x006e);
+  group(byte,     Reserved006e, 0x006e, 0x0079);
+  entry(byte,     SWResetCtrl,  0x0079, 0x007a);
+  group(byte,     Reserved007a, 0x007a, 0x0090);
+  entry(uint32,   Rxfilt_Ctl,   0x0090, 0x0094);
+  entry(uint32,   Cmf_En_Ctl,   0x0094, 0x0098);
+  group(byte,     Reserved0098, 0x0098, 0x00a0);
+  entry(uint32,   SwpktCtrl0,   0x00a0, 0x00a4);
+  entry(uint32,   SwpktCtrl1,   0x00a4, 0x00a8);
+  group(byte,     Reserved00a8, 0x00a8, 0x00b0);
+  entry(uint32,   MdioCtrl,     0x00b0, 0x00b4);
+  entry(uint16,   MdioData,     0x00b4, 0x00b6);
+  group(byte,     Reserved00b4, 0x00b6, 0x0200);
+  entry(byte,     GlbMgmt,      0x0200, 0x0201);
+  entry(byte,     ChpBoxID,     0x0201, 0x0202);
+  entry(byte,     MngPID,       0x0202, 0x0203);
+  group(byte,     Reserved0203, 0x0203, 0x1100);
+  entry(uint16,   MIICtrl0,     0x1100, 0x1101);
+
+} RoboSwitch;
+
+#define SWITCH ((volatile RoboSwitch * const)SWITCH_BASE)
+#define PBVLAN_OFFSET 0x3100
+#define PBMAP_MIPS 0x100
+#define SWITCH_PBVLAN ((volatile uint16 * const)(SWITCH_BASE + PBVLAN_OFFSET))
+
+#define PortCtrl_Forwarding   0xa0
+#define PortCtrl_Learning     0x80
+#define PortCtrl_Listening    0x60
+#define PortCtrl_Blocking     0x40
+#define PortCtrl_Disable      0x20
+#define PortCtrl_RxUcstEn     0x10
+#define PortCtrl_RxMcstEn     0x08
+#define PortCtrl_RxBcstEn     0x04
+#define PortCtrl_DisableTx    0x02
+#define PortCtrl_DisableRx    0x01
+
+#define SwitchMode_FwdgEn     0x02
+#define SwitchMode_ManageMode 0x01
+
+#define ImpOverride_Force     0x80
+#define ImpOverride_TxFlow    0x20
+#define ImpOverrode_RxFlow    0x10
+#define ImpOverride_1000Mbs   0x08
+#define ImpOverride_100Mbs    0x04
+#define ImpOverride_10Mbs     0x00
+#define ImpOverride_Fdx       0x02
+#define ImpOverride_Linkup    0x01
+
+#define PortOverride_Enable   0x40
+#define PortOverride_TxFlow   0x20
+#define PortOverride_RxFlow   0x10
+#define PortOverride_1000Mbs  0x08
+#define PortOverride_100Mbs   0x04
+#define PortOverride_10Mbs    0x00
+#define PortOverride_Fdx      0x02
+#define PortOverride_Linkup   0x01
+
+#define GlbMgmt_EnableImp     0x80
+#define GlbMgmt_IgmpSnooping  0x08
+#define GlbMgmt_ReceiveBpdu   0x02
+#define GlbMgmt_ResetMib      0x01
+
+#define MdioCtrl_Write        (1 << 31)
+#define MdioCtrl_Read         (1 << 30)
+#define MdioCtrl_Ext          (1 << 16)
+#define MdioCtrl_ID_Shift     25
+#define MdioCtrl_ID_Mask      (0x1f << MdioCtrl_ID_Shift)
+#define MdioCtrl_Addr_Shift   20
+#define MdioCtrl_Addr_Mask    (0x1f << MdioCtrl_Addr_Shift)
+
+#define ImpRgmiiCtrl_GMII_En        0x80
+#define ImpRgmiiCtrl_DLL_IQQD       0x04
+#define ImpRgmiiCtrl_DLL_RXC_Bypass 0x02
+#define ImpRgmiiCtrl_Timing_Sel     0x01
+
+#define ImpRgmiiTimingDelayDefault  0xF9
+
+#if defined (_BCM96328_)
+#define EPHY_PORTS      5
+#define PORT_6_PORT_ID  6
+#define PORT_7_PORT_ID  7
+#endif
+#if defined (_BCM96362_)
+#define EPHY_PORTS      6
+#define PORT_6_PORT_ID  6
+#define PORT_7_PORT_ID  7
+#endif
+#if defined (_BCM96368_)
+#define EPHY_PORTS      6
+#define USB_PORT_ID     6
+#define SAR_PORT_ID     7
+#endif
+#if defined (_BCM96816_)
+#define EPHY_PORTS      4
+#define SERDES_PORT_ID  4
+#define MOCA_PORT_ID    5
+#define USB_PORT_ID     6
+#define GPON_PORT_ID    7
+#endif
+
+#endif
diff --git a/shared/broadcom/include/bcm963xx/xtmprocregs.h b/shared/broadcom/include/bcm963xx/xtmprocregs.h
new file mode 100755
index 0000000..307ed79
--- /dev/null
+++ b/shared/broadcom/include/bcm963xx/xtmprocregs.h
@@ -0,0 +1,602 @@
+/*
+<:copyright-broadcom 
+ 
+ Copyright (c) 2007 Broadcom Corporation 
+ All Rights Reserved 
+ No portions of this material may be reproduced in any form without the 
+ written permission of: 
+          Broadcom Corporation 
+          5300 California Avenue
+          Irvine, California 92617 
+ All information contained in this document is Broadcom Corporation 
+ company private, proprietary, and trade secret. 
+ 
+:>
+*/
+/***************************************************************************
+ * File Name  : XtmProcRegs.h
+ *
+ * Description: This file contains definitions for the ATM/PTM processor
+ *              registers.
+ ***************************************************************************/
+
+#if !defined(_XTMPROCREGS_H_)
+#define _XTMPROCREGS_H_
+
+/* Miscellaneous values. */
+#define XP_MAX_PORTS                        4
+#define XP_MAX_CONNS                        16
+#define XP_MAX_RX_QUEUES                    4
+#define XP_MAX_TX_HDRS                      8
+#define XP_TX_HDR_WORDS                     (16 / sizeof(UINT32))
+#define XP_RX_MIB_MATCH_ENTRIES             128
+
+/* Circuit types. */
+#define XCT_TRANSPARENT                     0x00000001
+#define XCT_AAL0_PKT                        0x00000002
+#define XCT_AAL0_CELL                       0x00000003
+#define XCT_OAM_F5_SEG                      0x00000004
+#define XCT_OAM_F5_E2E                      0x00000005
+#define XCT_RM                              0x00000006
+#define XCT_AAL5                            0x00000007
+#define XCT_ASM_P0                          0x00000008
+#define XCT_ASM_P1                          0x00000009
+#define XCT_ASM_P2                          0x0000000a
+#define XCT_ASM_P3                          0x0000000b
+#define XCT_OAM_F4_SEG                      0x0000000c
+#define XCT_OAM_F4_E2E                      0x0000000d
+#define XCT_TEQ                             0x0000000e
+#define XCT_PTM                             0x0000000f
+
+/* Definitions for ATM ulTxChannelCfg. */
+#define TXCHA_VCID_MASK                     0x0000000f
+#define TXCHA_VCID_SHIFT                    0
+#define TXCHA_CT_MASK                       0x000000f0
+#define TXCHA_CT_SHIFT                      4
+#define TXCHA_CT_TRANSPARENT                (XCT_TRANSPARENT << TXCHA_CT_SHIFT)
+#define TXCHA_CT_AAL0_PKT                   (XCT_AAL0_PKT    << TXCHA_CT_SHIFT)
+#define TXCHA_CT_AAL0_CELL                  (XCT_AAL0_CELL   << TXCHA_CT_SHIFT)
+#define TXCHA_CT_OAM_F5_SEG                 (XCT_OAM_F5_SEG  << TXCHA_CT_SHIFT)
+#define TXCHA_CT_OAM_F5_E2E                 (XCT_OAM_F5_E2E  << TXCHA_CT_SHIFT)
+#define TXCHA_CT_RM                         (XCT_RM          << TXCHA_CT_SHIFT)
+#define TXCHA_CT_AAL5                       (XCT_AAL5        << TXCHA_CT_SHIFT)
+#define TXCHA_CT_ASM_P0                     (XCT_ASM_P0      << TXCHA_CT_SHIFT)
+#define TXCHA_CT_ASM_P1                     (XCT_ASM_P1      << TXCHA_CT_SHIFT)
+#define TXCHA_CT_ASM_P2                     (XCT_ASM_P2      << TXCHA_CT_SHIFT)
+#define TXCHA_CT_ASM_P3                     (XCT_ASM_P3      << TXCHA_CT_SHIFT)
+#define TXCHA_CT_OAM_F4_SEG                 (XCT_OAM_F4_SEG  << TXCHA_CT_SHIFT)
+#define TXCHA_CT_OAM_F4_E2E                 (XCT_OAM_F4_E2E  << TXCHA_CT_SHIFT)
+#define TXCHA_CT_TEQ                        (XCT_TEQ         << TXCHA_CT_SHIFT)
+#define TXCHA_CT_PTM                        (XCT_PTM         << TXCHA_CT_SHIFT)
+#define TXCHA_CI                            0x00000100
+#define TXCHA_CLP                           0x00000200
+#define TXCHA_USE_ALT_GFC                   0x00000400
+#define TXCHA_ALT_GFC_MASK                  0x00007800
+#define TXCHA_ALT_GFC_SHIFT                 11
+#define TXCHA_HDR_EN                        0x00008000
+#define TXCHA_HDR_IDX_MASK                  0x00070000
+#define TXCHA_HDR_IDX_SHIFT                 16
+#define TXCHA_FCS_STRIP                     0x00080000
+
+/* Definitions for PTM ulTxChannelCfg. */
+#define TXCHP_FCS_EN                        0x00000001
+#define TXCHP_CRC_EN                        0x00000002
+#define TXCHP_HDR_EN                        0x00008000
+#define TXCHP_HDR_IDX_MASK                  0x00070000
+#define TXCHP_HDR_IDX_SHIFT                 16
+
+/* Definitions for ulSwitchPktCfg. */
+#define SWP_MAX_PKT_COUNT_MASK              0x00000003
+#define SWP_MAX_PKT_COUNT_SHIFT             0
+#define SWP_MAX_PKT_SIZE_MASK               0x0000007c
+#define SWP_MAX_PKT_SIZE_SHIFT              2
+#define SWP_SRC_ID_MASK                     0x00000380
+#define SWP_SRC_ID_SHIFT                    7
+#define SWP_RX_CHAN_MASK                    0x00000c00
+#define SWP_RX_CHAN_SHIFT                   10
+#define SWP_TX_CHAN_MASK                    0x0000f000
+#define SWP_TX_CHAN_SHIFT                   12
+#define SWP_TX_EN                           0x00010000
+#define SWP_RX_EN                           0x00020000
+
+/* Definitions for ulSwitchPktTxCtrl. */
+#define SWP_VCID_VALUE_MASK                 0x0000000f
+#define SWP_VCID_VALUE_SHIFT                0
+#define SWP_CT_VALUE_MASK                   0x000000f0
+#define SWP_CT_VALUE_SHIFT                  4
+#define SWP_FSTAT_CFG_VALUE_MASK            0x00000700
+#define SWP_FSTAT_CFG_VALUE_SHIFT           8
+#define SWP_MUX_MODE_VALUE                  0x00000800
+#define SWP_VCID_MASK_MASK                  0x000f0000
+#define SWP_VCID_MASK_SHIFT                 16
+#define SWP_CT_MASK_MASK                    0x00f00000
+#define SWP_CT_MASK_SHIFT                   20
+#define SWP_FSTAT_CFG_MASK_MASK             0x07000000
+#define SWP_FSTAT_CFG_MASK_SHIFT            24
+#define SWP_MUX_MODE_MASK                   0x08000000
+
+/* Definitions for ulSwitchPktRxCtrl. */
+#define SWP_MATCH_MASK                      0x0000007f
+#define SWP_MASK_SHIFT                      0
+#define SWP_CRC32                           0x00000080
+#define SWP_DEST_PORT_MASK                  0x0000ff00
+#define SWP_DEST_PORT_SHIFT                 8
+#define SWP_MUX_MATCH_MASK                  0x007f0000
+#define SWP_MUX_MATCH_SHIFT                 16
+#define SWP_MUX_CRC32                       0x00800000
+#define SWP_MUX_DESTPORT_MASK               0xff000000
+#define SWP_MUX_DESTPORT_SHIFT              24
+
+/* Definitions for ulPktModCtrl. */
+#define PKTM_RXQ_EN_MASK                    0x0000000f
+#define PKTM_RXQ_EN_SHIFT                   0
+#define PKTM_EN                             0x80000000
+
+/* Definitions for ulIrqStatus and ulIrqMask. */
+#define INTR_RX_BUF_EMPTY                   0x00000001
+#define INTR_TX_BUF_EMPTY                   0x00000002
+#define INTR_RX_DMA_NO_DESC_MASK            0x0000003c
+#define INTR_RX_DMA_NO_DESC_SHIFT           2
+#define INTR_PTM_FRAG_ERROR                 0x00000040
+#define INTR_PKT_BUF_UNDERFLOW              0x00000080
+#define INTR_TX_DMA_UNDERFLOW               0x00000100
+#define INTR_TX_ATM_DC                      0x00000200
+#define INTR_BOND_BUF_FULL                  0x00000400
+#define INTR_RX_ATM_DC                      0x00000800
+#define INTR_MULT_MATCH_ERROR               0x00001000
+#define INTR_PKT_BUF_IRQ_MASK               0x0000e000
+#define INTR_PKT_BUF_IRQ_SHIFT              13
+
+/* Definitions for ulTxSarCfg. */
+#define TXSAR_MODE_ATM                      0x00000000
+#define TXSAR_MODE_PTM                      0x00000001
+#define TXSARA_BOND_EN                      0x00000002
+#define TXSARA_SID12_EN                     0x00000004
+#define TXSARA_CRC10_INIT                   0x00000008
+#define TXSARA_CRC10_EN_MASK                0x000000f0
+#define TXSARA_CRC10_EN_SHIFT               4
+#define TXSARA_BOND_DUAL_LATENCY            0x00000100
+#define TXSAR_USE_ALT_FSTAT                 0x00000200
+#define TXSARP_ENET_FCS_INSERT              0x00000400
+#define TXSARP_CRC16_EN                     0x00000800
+#define TXSARP_SOF_WHILE_TX                 0x00001000
+#define TXSARP_PREEMPT                      0x00002000
+#define TXSAR_HDR_INS_OFFSET_MASK           0x0007c000
+#define TXSAR_HDR_INS_OFFSET_SHIFT          14
+#define TXSARP_NUM_Z_BYTES_MASK             0x00780000
+#define TXSARP_NUM_Z_BYTES_SHIFT            19
+#define TXSAR_SW_EN                         0x00800000
+#define TXSAR_USE_THRESH                    0x01000000
+#define TXSAR_PKT_THRESH_MASK               0x06000000
+#define TXSAR_PKT_THRESH_SHIFT              25
+#define TXSARA_BOND_PORT_DIS_MASK           0x78000000
+#define TXSARA_BOND_PORT_DIS_SHIFT          27
+#define TXSARA_ASM_CRC_DIS                  0x80000000
+
+/* Definitions for ulTxSchedCfg. */
+#define TXSCH_PORT_EN_MASK                  0x0000000f
+#define TXSCH_PORT_EN_SHIFT                 0
+#define TXSCHA_ALT_SHAPER_MODE              0x00000010
+#define TXSCHP_FAST_SCHED                   0x00000020
+#define TXSCH_SHAPER_RESET                  0x00000040
+#define TXSCH_SIT_COUNT_EN                  0x00000080
+#define TXSCH_SIT_COUNT_VALUE_MASK          0x00ffff00
+#define TXSCH_SIT_COUNT_VALUE_SHIFT         8
+#define TXSCH_SIT_MAX_VALUE                 (TXSCH_SIT_COUNT_VALUE_MASK >> \
+                                             TXSCH_SIT_COUNT_VALUE_SHIFT)
+#define TXSCH_SOFWT_PRIORITY_EN             0x01000000
+#define TXSCH_BASE_COUNT_EN                 0x02000000
+#define TXSCH_BASE_COUNT_VALUE_MASK         0x3c000000
+#define TXSCH_BASE_COUNT_VALUE_SHIFT        26
+#define TXSCHP_USE_BIT4_SOF                 0x40000000
+#define TXSCH_ALT_MCR_MODE                  0x80000000
+
+/* Definitions for ulTxOamCfg. */
+#define TXOAM_F4_SEG_VPI_MASK               0x000000ff
+#define TXOAM_F4_SEG_VPI_SHIFT              0
+#define TXOAM_F4_E2E_VPI_MASK               0x0000ff00
+#define TXOAM_F4_E2E_VPI_SHIFT              8
+#define TXASM_VCI_MASK                      0xffff0000
+#define TXASM_VCI_SHIFT                     16
+
+/* Definitions for ulTxMpAalCfg. */
+#define TXMP_NUM_GROUPS                     4
+#define TXMP_GROUP_SIZE                     5
+#define TXMP_GROUP_EN                       0x00000001
+#define TXMP_GROUP_SHAPER_MASK              0x0000001e
+#define TXMP_GROUP_SHAPER_SHIFT             1
+#define TXSOPWT_COUNT_EN                    0x00100000
+#define TXSOPWT_COUNT_VALUE_MASK            0x07e00000
+#define TXSOPWT_COUNT_VALUE_SHIFT           21
+
+/* Definitions for ulTxUtopiaCfg. */
+#define TXUTO_PORT_EN_MASK                  0x0000000f
+#define TXUTO_PORT_EN_SHIFT                 0
+#define TXUTO_MODE_INT_EXT_MASK             0x00000030
+#define TXUTO_MODE_ALL_INT                  0x00000000
+#define TXUTO_MODE_ALL_EXT                  0x00000010
+#define TXUTO_MODE_INT_EXT                  0x00000020
+#define TXUTO_CELL_FIFO_DEPTH_2             0x00000000
+#define TXUTO_CELL_FIFO_DEPTH_1             0x00000040
+#define TXUTO_NEG_EDGE                      0x00000080
+#define TXUTO_LEVEL_1                       0x00000100
+
+/* Definitions for ulTxLineRateTimer. */
+#define TXLRT_EN                            0x00000001
+#define TXLRT_COUNT_VALUE_MASK              0x0001fffe
+#define TXLRT_COUNT_VALUE_SHIFT             1
+#define TXLRT_MAX_VALUE                     (TXLRT_COUNT_VALUE_MASK >> \
+                                             TXLRT_COUNT_VALUE_SHIFT)
+#define TXLRT_IDLE_CELL_INS_MASK            0xf0000000
+#define TXLRT_IDLE_CELL_INS_SHIFT           28
+
+/* Definitions for ulRxAtmCfg. */
+#define RX_PORT_EN                          0x00000001
+#define RX_DOE_MASK                         0x000001fe
+#define RX_DOE_SHIFT                        1
+#define RX_DOE_GFC_ERROR                    0x00000002
+#define RX_DOE_CRC_ERROR                    0x00000004
+#define RX_DOE_CT_ERROR                     0x00000008
+#define RX_DOE_CAM_LOOKUP_ERROR             0x00000010
+#define RX_DOE_IDLE_CELL                    0x00000020
+#define RX_DOE_PTI_ERROR                    0x00000040
+#define RX_DOE_HEC_ERROR                    0x00000080
+#define RX_DOE_PORT_NOT_ENABLED_ERROR       0x00000100
+#define RXA_HEC_CRC_IGNORE                  0x00000200
+#define RXA_GFC_ERROR_IGNORE                0x00000400
+#define RX_PORT_MASK                        0x00001800
+#define RX_PORT_MASK_SHIFT                  11
+#define RXP_RX_FLOW_DISABLED                0x00004000
+#define RXA_VCI_MASK                        0x00008000
+#define RXA_VC_BIT_MASK                     0xffff0000
+#define RXA_BONDING_VP_MASK					  0x00ff0000
+
+/* Definitions for ulRxSarCfg. */
+#define RXSAR_MODE_ATM                      0x00000000
+#define RXSAR_MODE_PTM                      0x00000001
+#define RXSAR_MODE_MASK                     0x00000001
+#define RXSARA_BOND_EN                      0x00000002
+#define RXSARA_SID12_EN                     0x00000004
+#define RXSARA_CRC10_INIT                   0x00000008
+#define RXSARA_CRC10_EN_MASK                0x000000f0
+#define RXSARA_CRC10_EN_SHIFT               4
+#define RXSARA_BOND_DUAL_LATENCY            0x00000100
+#define RXSARA_BOND_CELL_COUNT_MASK         0x07ff0000
+#define RXSARA_BOND_CELL_COUNT_SHIFT        16
+#define RXSARA_BOND_TIMER_MODE              0x08000000
+#define RXSARA_BOND_BUF_MODE_MASK           0x70000000
+#define RXSARA_BOND_BUF_MODE_SHIFT          29
+#define RXSARA_BOND_BUF_MODE_MASK           0x70000000
+#define RXSARA_ASM_CRC_DIS                  0x80000000
+
+/* Definitions for ulRxOamCfg. */
+#define RXOAM_F4_SEG_VPI_MASK               0x000000ff
+#define RXOAM_F4_SEG_VPI_SHIFT              0
+#define RXOAM_F4_E2E_VPI_MASK               0x0000ff00
+#define RXOAM_F4_E2E_VPI_SHIFT              8
+#define RXASM_VCI_MASK                      0xffff0000
+#define RXASM_VCI_SHIFT                     16
+
+/* Definitions for ulRxUtopiaCfg. */
+#define RXUTO_PORT_EN_MASK                  0x0000000f
+#define RXUTO_PORT_EN_SHIFT                 0
+#define RXUTO_TEQ_PORT_MASK                 0x00000070
+#define RXUTO_TEQ_PORT_SHIFT                4
+#define RXUTO_NEG_EDGE                      0x00000080
+#define RXUTO_LEVEL_1                       0x00000100
+#define RXUTO_INTERNAL_BUF0_EN              0x00000200
+#define RXUTO_EXTERNAL_BUF1_EN              0x00000400
+
+/* Definitions for ulRxAalCfg. */
+#define RXAALA_AAL5_SW_TRAILER_EN           0x00000001
+#define RXAALA_AAL0_CRC_CHECK               0x00000002
+#define RXAALP_CRC32_EN                     0x00000004
+#define RXAALP_CELL_LENGTH_MASK             0x000000f0
+#define RXAALP_CELL_LENGTH_SHIFT            4
+
+/* Definitions for ulLedCtrl. */
+#define SAR_LED_EN                          0x00000001
+#define SAR_LED_MODE_MASK                   0x00000006
+#define SAR_LED_MODE_SHIFT                  1
+#define SAR_LED_MODE_LINK_ONLY              0x00000000
+#define SAR_LED_MODE_CELL_ACTIVITY          0x00000002
+#define SAR_LED_MODE_MELODY_LINK            0x00000004
+#define SAR_LED_MODE_LINK_CELL_ACTIVITY     0x00000006
+#define SAR_LED_LINK                        0x00000010
+#define SAR_LED_SPEED_MASK                  0x00000060
+#define SAR_LED_SPEED_SHIFT                 5
+#define SAR_LED_SPEED_30MS                  0x00000000
+#define SAR_LED_SPEED_50MS                  0x00000020
+#define SAR_LED_SPEED_125MS                 0x00000040
+#define SAR_LED_SPEED_250MS                 0x00000060
+#define SAR_LED_INTERNAL                    0x00000080
+
+/* Definitions for ulTxVpiVciTable. */
+#define TXTBL_VCI_MASK                      0x0000ffff
+#define TXTBL_VCI_SHIFT                     0
+#define TXTBL_VPI_MASK                      0x00ff0000
+#define TXTBL_VPI_SHIFT                     16
+
+/* Definitions for ulRxVpiVciCam - CAM side. */
+#define RXCAM_PORT_MASK                     0x00000003
+#define RXCAM_PORT_SHIFT                    0
+#define RXCAMP_PTM_PRI_LOW                  0x00000000
+#define RXCAMP_PTM_PRI_HIGH                 0x00000004
+#define RXCAM_TEQ_CELL                      0x00000008
+#define RXCAMA_VCI_MASK                     0x000ffff0
+#define RXCAMA_VCI_SHIFT                    4
+#define RXCAMA_VPI_MASK                     0x0ff00000
+#define RXCAMA_VPI_SHIFT                    20
+#define RXCAM_VALID                         0x10000000
+
+/* Definitions for ulRxVpiVciCam - RAM side. */
+#define RXCAM_CT_MASK                       0x0000000f
+#define RXCAM_CT_SHIFT                      0
+#define RXCAM_CT_TRANSPARENT                (XCT_TRANSPARENT << RXCAM_CT_SHIFT)
+#define RXCAM_CT_AAL0_PKT                   (XCT_AAL0_PKT    << RXCAM_CT_SHIFT)
+#define RXCAM_CT_AAL0_CELL                  (XCT_AAL0_CELL   << RXCAM_CT_SHIFT)
+#define RXCAM_CT_AAL5                       (XCT_AAL5        << RXCAM_CT_SHIFT)
+#define RXCAM_CT_TEQ                        (XCT_TEQ         << RXCAM_CT_SHIFT)
+#define RXCAM_CT_PTM                        (XCT_PTM         << RXCAM_CT_SHIFT)
+#define RXCAM_VCID_MASK                     0x000001f0
+#define RXCAM_VCID_SHIFT                    4
+#define RXCAM_STRIP_BYTE_MASK               0x00003e00
+#define RXCAM_STRIP_BYTE_SHIFT              9
+#define RXCAM_STRIP_EN                      0x00004000
+#define RXCAMA_ASM_CELL                     0x00080000
+#define RXCAMA_CRC10_EN                     0x00100000
+
+/* Definitions for ulSstCtrl. */
+#define SST_EN                              0x00000001
+#define SST_MP_GROUP_MASK                   0x00000006
+#define SST_MP_GROUP_SHIFT                  1
+#define SST_PTM_PREEMPT                     0x00000010
+#define SST_PORT_MASK                       0x00000060
+#define SST_PORT_SHIFT                      5
+#define SST_ALG_MASK                        0x00000380
+#define SST_ALG_SHIFT                       7
+#define SST_ALG_UBR_NO_PCR                  0x00000000
+#define SST_ALG_UBR_PCR                     0x00000080
+#define SST_ALG_MBR                         0x00000100
+#define SST_ALG_VBR_1                       0x00000180
+#define SST_ALG_CBR                         0x00000200
+#define SST_SUB_PRIORITY_MASK               0x00001c00
+#define SST_SUB_PRIORITY_SHIFT              10
+#define SST_SUPER_PRIORITY                  0x00002000
+#define SST_MP_EN                           0x00004000
+#define SST_MCR_EN                          0x00008000
+#define SST_RATE_MCR_MASK                   0xffff0000
+#define SST_RATE_MCR_SHIFT                  16
+
+/* Definitions for ulSstPcrScr. */
+#define SST_RATE_PCR_MASK                   0x0000ffff
+#define SST_RATE_PCR_SHIFT                  0
+#define SST_RATE_SCR_MASK                   0xffff0000
+#define SST_RATE_SCR_SHIFT                  16
+
+/* Definitions for ulSstBt. */
+#define SST_RATE_BT_MASK                    0x00ffffff
+#define SST_RATE_BT_SHIFT                   0
+#define SST_ALG_WEIGHT_MASK                 0x03000000
+#define SST_ALG_WEIGHT_SHIFT                24
+#define SST_ALG_DISABLED                    0x00000000
+#define SST_ALG_CWRR                        0x01000000
+#define SST_ALG_PWRR                        0x02000000
+#define SST_ALG_WFQ                         0x03000000
+#define SST_WEIGHT_VALUE_MASK               0xfc000000
+#define SST_WEIGHT_VALUE_SHIFT              26
+
+/* Definitions for ulSstBucketCnt. */
+#define SST_BP_PCR_MASK                     0x0000ffff
+#define SST_BP_PCR_SHIFT                    0
+#define SST_BM_MCR_MASK                     0xffff0000
+#define SST_BM_MCR_SHIFT                    16
+
+/* Definitions for ulRxPktBufCfg. */
+#define PBCFG_LENGTH_MASK                   0x0000ffff
+#define PBCFG_LENGTH_SHIFT                  0
+#define PBCFG_FPM_EMPTY                     0x02000000
+#define PBCFG_LD_PTRS                       0x04000000
+#define PBCFG_ALLOCATE_LAST                 0x08000000
+#define PBCFG_KEEP_ERROR_PKTS               0x10000000
+#define PBCFG_FPM_ENABLE                    0x20000000
+#define PBCFG_INIT_REQ                      0x40000000
+#define PBCFG_S_RESET                       0x80000000
+
+/* Definitions for ulRxPktBufThreshold. */
+#define PBTHRESH_MAX_COUNT_MASK             0x000000ff
+#define PBTHRESH_MAX_COUNT_SHIFT            0
+#define PBTHRESH_NO_BUF_DELAY_MASK          0xffff0000
+#define PBTHRESH_NO_BUF_DELAY_SHIFT         16
+
+/* Definitions for ulRxPktBufVcid. */
+#define PBVCID_WAIT_EN_MASK                 0x0000ffff
+#define PBVCID_WAIT_EN_SHIFT                0
+
+/* Definitions for ulRxPktBufMem. */
+#define PBMEM_ADDR_MASK                     0x0000ffff
+#define PBMEM_ADDR_SHIFT                    0
+#define PBMEM_BS_B_MASK                     0x00ff0000
+#define PBMEM_BS_B_SHIFT                    16
+#define PBMEM_READ_WRITE_B                  0x40000000
+#define PBMEM_GO_BUSY                       0x80000000
+
+/* Definitions for ulRxPktBufPtr. */
+#define PBPTR_BUF_STOP_MASK                 0x0000ffff
+#define PBPTR_BUF_STOP_SHIFT                0
+#define PBPTR_BUF_START_MASK                0xffff0000
+#define PBPTR_BUF_START_SHIFT               16
+
+/* Definitions for ulRxPktBufSize. */
+#define PBSIZE_THRESHOLD_MASK               0x0000ffff
+#define PBSIZE_THRESHOLD_SHIFT              0
+#define PBSIZE_MASK                         0xffff0000
+#define PBSIZE_SHIFT                        16
+
+/* Definitions for ulRxPktBufFifoStart[2]. */
+#define PBSTART_0_MASK                      0x0000ffff
+#define PBSTART_0_SHIFT                     0
+#define PBSTART_1_MASK                      0xffff0000
+#define PBSTART_1_SHIFT                     16
+
+/* Definitions for ulRxPktBufFifoStop[2]. */
+#define PBSTOP_0_MASK                       0x0000ffff
+#define PBSTOP_0_SHIFT                      0
+#define PBSTOP_1_MASK                       0xffff0000
+#define PBSTOP_1_SHIFT                      16
+
+/* Definitions for ulRxPktBufFifoDelay[2]. */
+#define PBDELAY_0_MASK                      0x0000ffff
+#define PBDELAY_0_SHIFT                     0
+#define PBDELAY_1_MASK                      0xffff0000
+#define PBDELAY_1_SHIFT                     16
+
+/* Definitions for ulRxPktBufQueueStatus. */
+#define PBQS_NUM_NO_BUFS_MASK               0x0000ffff
+#define PBQS_NUM_NO_BUFS_SHIFT              0
+#define PBQS_NUM_QUEUE_FULL_MASK            0xffff0000
+#define PBQS_NUM_QUEUE_FULL_SHIFT           16
+
+/* Definitions for ulRxPktBufErrorStatus. */
+#define PBERR_NUM_ERROR_FRAGS_MASK          0x0000ffff
+#define PBERR_NUM_ERROR_FRAGS_SHIFT         0
+#define PBERR_NUM_ERROR_PKTS_MASK           0xffff0000
+#define PBERR_NUM_ERROR_PKTS_SHIFT          16
+
+/* Definitions for ulRxPktBufTR. */
+#define PBTR_LD_T_PTR_MASK                  0x0000ffff
+#define PBTR_LD_T_PTR_SHIFT                 0
+#define PBTR_LD_H_PTR_MASK                  0xffff0000
+#define PBTR_LD_H_PTR_SHIFT                 16
+
+/* Definitions for ulRxPktBufFPM. */
+#define PBFPM_FRAME_BUF_MASK                0x0000ffff
+#define PBFPM_FRAME_BUF_SHIFT               0
+#define PBFPM_LOAD_COUNT_MASK               0xffff0000
+#define PBFPM_LOAD_COUNT_SHIFT              16
+
+/* Definitions for ulRxPktBufMibCtrl. */
+#define PBMIB_TOGGLE                        0x40000000
+#define PBMIB_CLEAR                         0x80000000
+
+/* Definitions for ulRxPktBufMibMatch. */
+#define PBMIB_MATCH_MASK                    0x0000007f
+
+/* Definitions for ulTxHdrInsert. */
+#define TXHDR_COUNT_MASK                    0x0000001f
+#define TXHDR_COUNT_SHIFT                   0
+#define TXHDR_OFFSET_MASK                   0x00ff0000
+#define TXHDR_OFFSET_SHIFT                  16
+
+/* Definitions for ulTxRxPortOamCellCnt. */
+#define OAM_TX_CELL_COUNT_MASK              0x0000ffff
+#define OAM_TX_CELL_COUNT_SHIFT             0
+#define OAM_RX_CELL_COUNT_MASK              0xffff0000
+#define OAM_RX_CELL_COUNT_SHIFT             16
+
+/* Definitions for ulTxRxPortAsmCellCnt. */
+#define ASM_TX_CELL_COUNT_MASK              0x0000ffff
+#define ASM_TX_CELL_COUNT_SHIFT             0
+#define ASM_RX_CELL_COUNT_MASK              0xffff0000
+#define ASM_RX_CELL_COUNT_SHIFT             16
+
+/* Definitions for ulRxPortErrorPktCellCnt. */
+#define ERROR_RX_CELL_COUNT_MASK            0x0000ffff
+#define ERROR_RX_CELL_COUNT_SHIFT           0
+#define ERROR_RX_PKT_COUNT_MASK             0xffff0000
+#define ERROR_RX_PKT_COUNT_SHIFT            16
+
+
+#if defined(CONFIG_BCM96368)
+#define XTM_PROCESSOR_BASE                                       0xb0001800
+#elif defined(CONFIG_BCM96328) || defined(CONFIG_BCM96362)
+#define XTM_PROCESSOR_BASE                                       0xb0007800
+#endif
+typedef struct XtmProcessorRegisters
+{
+    UINT32 ulTxChannelCfg[XP_MAX_CONNS];                            /* 0000 */
+    UINT32 ulSwitchPktCfg;                                          /* 0040 */
+    UINT32 ulSwitchPktTxCtrl;                                       /* 0044 */
+    UINT32 ulSwitchPktRxCtrl;                                       /* 0048 */
+    UINT32 ulPktModCtrl;                                            /* 004c */
+    UINT32 ulIrqStatus;                                             /* 0050 */
+    UINT32 ulIrqMask;                                               /* 0054 */
+    UINT32 ulReserved1[2];                                          /* 0058 */
+    UINT32 ulTxSarCfg;                                              /* 0060 */
+    UINT32 ulTxSchedCfg;                                            /* 0064 */
+    UINT32 ulTxOamCfg;                                              /* 0068 */
+    UINT32 ulTxAtmStatus;                                           /* 006c */
+    UINT32 ulTxAalStatus;                                           /* 0070 */
+    UINT32 ulTxMpAalCfg;                                            /* 0074 */
+    UINT32 ulTxUtopiaCfg;                                           /* 0078 */
+    UINT32 ulTxLineRateTimer;                                       /* 007c */
+    UINT32 ulRxAtmCfg[XP_MAX_PORTS];                                /* 0080 */
+    UINT32 ulRxSarCfg;                                              /* 0090 */
+    UINT32 ulRxOamCfg;                                              /* 0094 */
+    UINT32 ulRxAtmStatus;                                           /* 0098 */
+    UINT32 ulRxUtopiaCfg;                                           /* 009c */
+    UINT32 ulRxAalCfg;                                              /* 00a0 */
+    UINT32 ulRxAalMaxSdu;                                           /* 00a4 */
+    UINT32 ulRxAalStatus;                                           /* 00a8 */
+    UINT32 ulLedCtrl;                                               /* 00ac */
+    UINT32 ulReserved2[20];                                         /* 00b0 */
+    UINT32 ulTxVpiVciTable[XP_MAX_CONNS];                           /* 0100 */
+    UINT32 ulRxVpiVciCam[XP_MAX_CONNS * 2];                         /* 0140 */
+    UINT32 ulReserved3[16];                                         /* 01c0 */
+    UINT32 ulSstCtrl[XP_MAX_CONNS];                                 /* 0200 */
+    UINT32 ulSstPcrScr[XP_MAX_CONNS];                               /* 0240 */
+    UINT32 ulSstBt[XP_MAX_CONNS];                                   /* 0280 */
+    UINT32 ulSstBucketCnt[XP_MAX_CONNS];                            /* 02c0 */
+    UINT32 ulRxPktBufCfg;                                           /* 0300 */
+    UINT32 ulRxPktBufThreshold;                                     /* 0304 */
+    UINT32 ulRxPktBufVcid;                                          /* 0308 */
+    UINT32 ulRxPktBufMem;                                           /* 030c */
+    UINT32 ulRxPktBufData[2];                                       /* 0310 */
+    UINT32 ulRxPktBufPtr;                                           /* 0318 */
+    UINT32 ulRxPktBufSize;                                          /* 031c */
+    UINT32 ulRxPktBufFifoStart[2];                                  /* 0320 */
+    UINT32 ulRxPktBufFifoStop[2];                                   /* 0328 */
+    UINT32 ulRxPktBufFifoDelay[2];                                  /* 0330 */
+    UINT32 ulRxPktBufQueueStatus;                                   /* 0338 */
+    UINT32 ulRxPktBufErrorStatus;                                   /* 033c */
+    UINT32 ulRxPktBufTR;                                            /* 0340 */
+    UINT32 ulRxPktBufFPM;                                           /* 0344 */
+    UINT32 ulRxPktBufMibCtrl;                                       /* 0348 */
+    UINT32 ulRxPktBufMibMatch;                                      /* 034c */
+    UINT32 ulRxPktBufMibRxOctet;                                    /* 0350 */
+    UINT32 ulRxPktBufMibRxPkt;                                      /* 0354 */
+    UINT32 ulReserved4[106];                                        /* 0358 */
+    UINT32 ulTxHdrInsert[XP_MAX_TX_HDRS];                           /* 0500 */
+    UINT32 ulReserved5[24];                                         /* 0520 */
+    UINT32 ulTxHdrValues[XP_MAX_TX_HDRS][XP_TX_HDR_WORDS];          /* 0580 */
+    UINT32 ulTxPortPktOctCnt[XP_MAX_PORTS];                         /* 0600 */
+    UINT32 ulRxPortPktOctCnt[XP_MAX_PORTS];                         /* 0610 */
+    UINT32 ulTxPortPktCnt[XP_MAX_PORTS];                            /* 0620 */
+    UINT32 ulRxPortPktCnt[XP_MAX_PORTS];                            /* 0630 */
+    UINT32 ulTxRxPortOamCellCnt[XP_MAX_PORTS];                      /* 0640 */
+    UINT32 ulTxRxPortAsmCellCnt[XP_MAX_PORTS];                      /* 0650 */
+    UINT32 ulRxPortErrorPktCellCnt[XP_MAX_PORTS];                   /* 0660 */
+    UINT32 ulBondInputCellCnt;                                      /* 0670 */
+    UINT32 ulBondOutputCellCnt;                                     /* 0674 */
+    UINT32 ulReserved6[1];                                          /* 0678 */
+    UINT32 ulMibCtrl;                                               /* 067c */
+    UINT32 ulTxVcPktOctCnt[XP_MAX_CONNS];                           /* 0680 */
+} XTM_PROCESSOR_REGISTERS, *PXTM_PROCESSOR_REGISTERS;
+
+#define XP_REGS ((volatile PXTM_PROCESSOR_REGISTERS const) XTM_PROCESSOR_BASE)
+
+/* Definitions from pktCmfHw.h.  TBD. Use commoon header file. */
+#ifndef PKTCMF_OFFSET_ENGINE_SAR
+#define PKTCMF_OFFSET_ENGINE_SAR        0xB0002000
+#endif
+#define PKTCMF_OFFSET_RXFILT            0x00001B00
+#define RXFILT_REG_MATCH0_DEF_ID        0x0000000C /* 7b/VCID 03..00 */
+#define RXFILT_REG_MATCH1_DEF_ID        0x00000010 /* 7b/VCID 07..04 */
+#define RXFILT_REG_MATCH2_DEF_ID        0x00000014 /* 7b/VCID 11..08 */
+#define RXFILT_REG_MATCH3_DEF_ID        0x00000018 /* 7b/VCID 15..12 */
+
+#define RXFILT_REG_VCID0_QID            0x00000004 /* 2b/VCID 15..00 */
+#define RXFILT_REG_VCID1_QID            0x00000008 /* 2b VCID=    16 */
+
+#endif /* _XTMPROCREGS_H_ */
+