From 1a2238d1bddc823df06f67312d96ccf9de2893cc Mon Sep 17 00:00:00 2001 From: root Date: Sat, 19 Dec 2015 13:13:57 +0000 Subject: CFE from danitool [without hostTools dir]: https://mega.nz/#!mwZyFK7a!CPT3BKC8dEw29kubtdYxhB91G9vIIismTkgzQ3iUy3k --- shared/broadcom/include/bcm963xx/6328_common.h | 299 +++ shared/broadcom/include/bcm963xx/6328_map.h | 1886 +++++++++++++++++++ shared/broadcom/include/bcm963xx/6362_common.h | 326 ++++ shared/broadcom/include/bcm963xx/6362_map.h | 2251 +++++++++++++++++++++++ shared/broadcom/include/bcm963xx/6368_common.h | 270 +++ shared/broadcom/include/bcm963xx/6368_map.h | 1592 ++++++++++++++++ shared/broadcom/include/bcm963xx/6816_common.h | 351 ++++ shared/broadcom/include/bcm963xx/6816_map.h | 2322 ++++++++++++++++++++++++ shared/broadcom/include/bcm963xx/mocablock.h | 144 ++ shared/broadcom/include/bcm963xx/robosw_reg.h | 169 ++ shared/broadcom/include/bcm963xx/xtmprocregs.h | 602 ++++++ 11 files changed, 10212 insertions(+) create mode 100755 shared/broadcom/include/bcm963xx/6328_common.h create mode 100755 shared/broadcom/include/bcm963xx/6328_map.h create mode 100755 shared/broadcom/include/bcm963xx/6362_common.h create mode 100755 shared/broadcom/include/bcm963xx/6362_map.h create mode 100755 shared/broadcom/include/bcm963xx/6368_common.h create mode 100755 shared/broadcom/include/bcm963xx/6368_map.h create mode 100755 shared/broadcom/include/bcm963xx/6816_common.h create mode 100755 shared/broadcom/include/bcm963xx/6816_map.h create mode 100755 shared/broadcom/include/bcm963xx/mocablock.h create mode 100755 shared/broadcom/include/bcm963xx/robosw_reg.h create mode 100755 shared/broadcom/include/bcm963xx/xtmprocregs.h (limited to 'shared/broadcom') diff --git a/shared/broadcom/include/bcm963xx/6328_common.h b/shared/broadcom/include/bcm963xx/6328_common.h new file mode 100755 index 0000000..4d36942 --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6328_common.h @@ -0,0 +1,299 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6328_common.h */ +/* DATE: 02/01/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6328 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6328_MAP_COMMON_H +#define __BCM6328_MAP_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define NAND_INTR_BASE 0xb0000070 /* nand interrupt control registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 +#define NAND_CACHE_BASE 0xb0000400 +#define OTP_BASE 0xb0000600 +#define LED_BASE 0xb0000800 /* LED control registers */ +#define HSSPIM_BASE 0xb0001000 /* High-Speed SPI registers */ +#define MISC_BASE 0xb0001800 /* Miscellaneous Registers */ +#define ADSL_CTRL_BASE 0xb0001900 +#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10002500 /* USB host registers */ +#define USB_OHCI_BASE 0x10002600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0002700 +#define DDR_BASE 0xb0003000 /* Memory control registers */ +#define PCM_BASE 0xb000a000 +#define PCM_DMA_BASE 0xb000a800 /* PCM UIDMA register base */ +#define SAR_DMA_BASE 0xb000b800 /* ATM SAR DMA control registers */ +#define USB_DMA_BASE 0xb000c000 /* USB 2.0 device DMA regiseters */ +#define SWITCH_DMA_BASE 0xb000d800 +#define SWITCH_BASE 0xb0e00000 +#define PCIE_BASE 0xb0e40000 + + +/* +##################################################################### +# System PLL Control Register +##################################################################### +*/ + +/* +##################################################################### +# GPIO Control Registers +##################################################################### +*/ + +/* +##################################################################### +# Miscellaneous Registers +##################################################################### +*/ +#define MISC_MEMC_CONTROL 0x0c +#define MISC_STRAP_BUS 0x240 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 7 + +/* +##################################################################### +# OTP Registers +##################################################################### +*/ +#define OTP_USER_BITS 0x20 +#define OTP_TP1_DISABLE_BIT 9 + +/* +##################################################################### +# Memory Control Registers +##################################################################### +*/ +#define DDR_CTL_CNFG 0x000 +#define DDR_CTL_CSST 0x004 +#define DDR_CTL_CSEND 0x008 +#define DDR_CTL_ROW00_0 0x010 +#define DDR_CTL_ROW00_1 0x014 +#define DDR_CTL_ROW01_0 0x018 +#define DDR_CTL_ROW01_1 0x01c +#define DDR_CTL_ROW20_0 0x030 +#define DDR_CTL_ROW20_1 0x034 +#define DDR_CTL_ROW21_0 0x038 +#define DDR_CTL_ROW21_1 0x03c +#define DDR_CTL_COL00_0 0x050 +#define DDR_CTL_COL00_1 0x054 +#define DDR_CTL_COL01_0 0x058 +#define DDR_CTL_COL01_1 0x05c +#define DDR_CTL_COL20_0 0x070 +#define DDR_CTL_COL20_1 0x074 +#define DDR_CTL_COL21_0 0x078 +#define DDR_CTL_COL21_1 0x07c +#define DDR_CTL_BNK10 0x090 +#define DDR_CTL_BNK32 0x094 +#define DDR_CTL_DCMD 0x100 +#define DDR_CTL_DMODE_0 0x104 +#define DDR_CTL_DMODE_1 0x108 +#define DDR_CTL_CLKS 0x10c +#define DDR_CTL_ODT 0x110 +#define DDR_CTL_TIM1_0 0x114 +#define DDR_CTL_TIM1_1 0x118 +#define DDR_CTL_TIM2 0x11c +#define DDR_CTL_CTL_CRC 0x120 +#define DDR_CTL_DOUT_CRC 0x124 +#define DDR_CTL_DIN_CRC 0x128 +#define PHY_CONTROL_REGS_REVISION 0x200 +#define PHY_CONTROL_REGS_CLK_PM_CTRL 0x204 +#define PHY_CONTROL_REGS_PLL_STATUS 0x210 +#define PHY_CONTROL_REGS_PLL_CONFIG 0x214 +#define PHY_CONTROL_REGS_PLL_PRE_DIVIDER 0x218 +#define PHY_CONTROL_REGS_PLL_DIVIDER 0x21c +#define PHY_CONTROL_REGS_PLL_CONTROL1 0x220 +#define PHY_CONTROL_REGS_PLL_CONTROL2 0x224 +#define PHY_CONTROL_REGS_PLL_SS_EN 0x228 +#define PHY_CONTROL_REGS_PLL_SS_CFG 0x22c +#define PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE 0x230 +#define PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE 0x234 +#define PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x238 +#define PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL 0x23c +#define PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x240 +#define PHY_CONTROL_REGS_CLOCK_REG_CONTROL 0x244 + +#define PHY_BYTE_LANE_0_REVISION 0x300 +#define PHY_BYTE_LANE_0_VDL_CALIBRATE 0x304 +#define PHY_BYTE_LANE_0_VDL_STATUS 0x308 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_0 0x310 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_1 0x314 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_2 0x318 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_3 0x31c +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_4 0x320 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_5 0x324 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_6 0x328 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_7 0x32c +#define PHY_BYTE_LANE_0_READ_CONTROL 0x330 +#define PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x334 +#define PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x338 +#define PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x33c +#define PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x340 +#define PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE 0x344 +#define PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x348 +#define PHY_BYTE_LANE_0_CLOCK_REG_CONTROL 0x34c + +#define PHY_BYTE_LANE_1_REVISION 0x400 +#define PHY_BYTE_LANE_1_VDL_CALIBRATE 0x404 +#define PHY_BYTE_LANE_1_VDL_STATUS 0x408 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_0 0x410 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_1 0x414 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_2 0x418 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_3 0x41c +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_4 0x420 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_5 0x424 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_6 0x428 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_7 0x42c +#define PHY_BYTE_LANE_1_READ_CONTROL 0x430 +#define PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x434 +#define PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x438 +#define PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x43c +#define PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x440 +#define PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE 0x444 +#define PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x448 +#define PHY_BYTE_LANE_1_CLOCK_REG_CONTROL 0x44c + +#define PHY_BYTE_LANE_2_REVISION 0x500 +#define PHY_BYTE_LANE_2_VDL_CALIBRATE 0x504 +#define PHY_BYTE_LANE_2_VDL_STATUS 0x508 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_0 0x510 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_1 0x514 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_2 0x518 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_3 0x51c +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_4 0x520 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_5 0x524 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_6 0x528 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_7 0x52c +#define PHY_BYTE_LANE_2_READ_CONTROL 0x530 +#define PHY_BYTE_LANE_2_READ_FIFO_STATUS 0x534 +#define PHY_BYTE_LANE_2_READ_FIFO_CLEAR 0x538 +#define PHY_BYTE_LANE_2_IDLE_PAD_CONTROL 0x53c +#define PHY_BYTE_LANE_2_DRIVE_PAD_CTL 0x540 +#define PHY_BYTE_LANE_2_CLOCK_PAD_DISABLE 0x544 +#define PHY_BYTE_LANE_2_WR_PREAMBLE_MODE 0x548 +#define PHY_BYTE_LANE_2_CLOCK_REG_CONTROL 0x54c + +#define PHY_BYTE_LANE_3_REVISION 0x600 +#define PHY_BYTE_LANE_3_VDL_CALIBRATE 0x604 +#define PHY_BYTE_LANE_3_VDL_STATUS 0x608 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_0 0x610 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_1 0x614 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_2 0x618 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_3 0x61c +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_4 0x620 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_5 0x624 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_6 0x628 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_7 0x62c +#define PHY_BYTE_LANE_3_READ_CONTROL 0x630 +#define PHY_BYTE_LANE_3_READ_FIFO_STATUS 0x634 +#define PHY_BYTE_LANE_3_READ_FIFO_CLEAR 0x638 +#define PHY_BYTE_LANE_3_IDLE_PAD_CONTROL 0x63c +#define PHY_BYTE_LANE_3_DRIVE_PAD_CTL 0x640 +#define PHY_BYTE_LANE_3_CLOCK_PAD_DISABLE 0x644 +#define PHY_BYTE_LANE_3_WR_PREAMBLE_MODE 0x648 +#define PHY_BYTE_LANE_3_CLOCK_REG_CONTROL 0x64c + +#define DDR_CTL_GCFG 0x800 +#define DDR_CTL_LBIST_CFG 0x804 +#define DDR_CTL_LBIST_SEED 0x808 +#define DDR_CTL_ARB 0x80c +#define DDR_CTL_PI_GCF 0x810 +#define DDR_CTL_PI_UBUS_CTL 0x814 +#define DDR_CTL_PI_MIPS_CTL 0x818 +#define DDR_CTL_PI_DSL_MIPS_CTL 0x81c +#define DDR_CTL_PI_DSL_PHY_CTL 0x820 +#define DDR_CTL_PI_UBUS_ST 0x824 +#define DDR_CTL_PI_MIPS_ST 0x828 +#define DDR_CTL_PI_DSL_MIPS_ST 0x82c +#define DDR_CTL_PI_DSL_PHY_ST 0x830 +#define DDR_CTL_PI_UBUS_SMPL 0x834 +#define DDR_CTL_TESTMODE 0x838 +#define DDR_CTL_TEST_CFG1 0x83c +#define DDR_CTL_TEST_PAT 0x840 +#define DDR_CTL_TEST_COUNT 0x844 +#define DDR_CTL_TEST_CURR_COUNT 0x848 +#define DDR_CTL_TEST_ADDR_UPDT 0x84c +#define DDR_CTL_TEST_ADDR 0x850 +#define DDR_CTL_TEST_DATA0 0x854 +#define DDR_CTL_TEST_DATA1 0x858 +#define DDR_CTL_TEST_DATA2 0x85c +#define DDR_CTL_TEST_DATA3 0x860 + + +/* +##################################################################### +# UART Control Registers +##################################################################### +*/ +#define UART0CONTROL 0x01 +#define UART0CONFIG 0x02 +#define UART0RXTIMEOUT 0x03 +#define UART0BAUD 0x04 +#define UART0FIFOCFG 0x0a +#define UART0INTMASK 0x10 +#define UART0INTSTAT 0x12 +#define UART0DATA 0x17 + +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + +#define XMITBREAK 0x40 /* Config register */ +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/broadcom/include/bcm963xx/6328_map.h b/shared/broadcom/include/bcm963xx/6328_map.h new file mode 100755 index 0000000..246d211 --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6328_map.h @@ -0,0 +1,1886 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6328_map.h */ +/* DATE: 05/30/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6328 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6328_MAP_H +#define __BCM6328_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" +#include "6328_common.h" +#include "6328_intr.h" + +/* macro to convert logical data addresses to physical */ +/* DMA hardware must see physical address */ +#define LtoP( x ) ( (uint32)x & 0x1fffffff ) +#define PtoL( x ) ( LtoP(x) | 0xa0000000 ) + +typedef struct DDRPhyControl { + uint32 REVISION; /* 0x00 */ + uint32 CLK_PM_CTRL; /* 0x04 */ + uint32 unused0[2]; /* 0x08-0x10 */ + uint32 PLL_STATUS; /* 0x10 */ + uint32 PLL_CONFIG; /* 0x14 */ + uint32 PLL_PRE_DIVIDER; /* 0x18 */ + uint32 PLL_DIVIDER; /* 0x1c */ + uint32 PLL_CONTROL1; /* 0x20 */ + uint32 PLL_CONTROL2; /* 0x24 */ + uint32 PLL_SS_EN; /* 0x28 */ + uint32 PLL_SS_CFG; /* 0x2c */ + uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ + uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ + uint32 IDLE_PAD_CONTROL; /* 0x38 */ + uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_REG_CONTROL; /* 0x44 */ + uint32 unused1[46]; +} DDRPhyControl; + +typedef struct DDRPhyByteLaneControl { + uint32 REVISION; /* 0x00 */ + uint32 VDL_CALIBRATE; /* 0x04 */ + uint32 VDL_STATUS; /* 0x08 */ + uint32 unused; /* 0x0c */ + uint32 VDL_OVERRIDE_0; /* 0x10 */ + uint32 VDL_OVERRIDE_1; /* 0x14 */ + uint32 VDL_OVERRIDE_2; /* 0x18 */ + uint32 VDL_OVERRIDE_3; /* 0x1c */ + uint32 VDL_OVERRIDE_4; /* 0x20 */ + uint32 VDL_OVERRIDE_5; /* 0x24 */ + uint32 VDL_OVERRIDE_6; /* 0x28 */ + uint32 VDL_OVERRIDE_7; /* 0x2c */ + uint32 READ_CONTROL; /* 0x30 */ + uint32 READ_FIFO_STATUS; /* 0x34 */ + uint32 READ_FIFO_CLEAR; /* 0x38 */ + uint32 IDLE_PAD_CONTROL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_PAD_DISABLE; /* 0x44 */ + uint32 WR_PREAMBLE_MODE; /* 0x48 */ + uint32 CLOCK_REG_CONTROL; /* 0x4C */ + uint32 unused0[44]; +} DDRPhyByteLaneControl; + +typedef struct DDRControl { + uint32 CNFG; /* 0x000 */ + uint32 CSST; /* 0x004 */ + uint32 CSEND; /* 0x008 */ + uint32 unused; /* 0x00c */ + uint32 ROW00_0; /* 0x010 */ + uint32 ROW00_1; /* 0x014 */ + uint32 ROW01_0; /* 0x018 */ + uint32 ROW01_1; /* 0x01c */ + uint32 unused0[4]; + uint32 ROW20_0; /* 0x030 */ + uint32 ROW20_1; /* 0x034 */ + uint32 ROW21_0; /* 0x038 */ + uint32 ROW21_1; /* 0x03c */ + uint32 unused1[4]; + uint32 COL00_0; /* 0x050 */ + uint32 COL00_1; /* 0x054 */ + uint32 COL01_0; /* 0x058 */ + uint32 COL01_1; /* 0x05c */ + uint32 unused2[4]; + uint32 COL20_0; /* 0x070 */ + uint32 COL20_1; /* 0x074 */ + uint32 COL21_0; /* 0x078 */ + uint32 COL21_1; /* 0x07c */ + uint32 unused3[4]; + uint32 BNK10; /* 0x090 */ + uint32 BNK32; /* 0x094 */ + uint32 unused4[26]; + uint32 DCMD; /* 0x100 */ +#define DCMD_CS1 (1 << 5) +#define DCMD_CS0 (1 << 4) +#define DCMD_SET_SREF 4 + uint32 DMODE_0; /* 0x104 */ + uint32 DMODE_1; /* 0x108 */ +#define DMODE_1_DRAMSLEEP (1 << 11) + uint32 CLKS; /* 0x10c */ + uint32 ODT; /* 0x110 */ + uint32 TIM1_0; /* 0x114 */ + uint32 TIM1_1; /* 0x118 */ + uint32 TIM2; /* 0x11c */ + uint32 CTL_CRC; /* 0x120 */ + uint32 DOUT_CRC; /* 0x124 */ + uint32 DIN_CRC; /* 0x128 */ + uint32 unused5[53]; + + DDRPhyControl PhyControl; /* 0x200 */ + DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ + DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ + DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ + DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ + uint32 unused6[64]; + + uint32 GCFG; /* 0x800 */ + uint32 LBIST_CFG; /* 0x804 */ + uint32 LBIST_SEED; /* 0x808 */ + uint32 ARB; /* 0x80c */ + uint32 PI_GCF; /* 0x810 */ + uint32 PI_UBUS_CTL; /* 0x814 */ + uint32 PI_MIPS_CTL; /* 0x818 */ + uint32 PI_DSL_MIPS_CTL; /* 0x81c */ + uint32 PI_DSL_PHY_CTL; /* 0x820 */ + uint32 PI_UBUS_ST; /* 0x824 */ + uint32 PI_MIPS_ST; /* 0x828 */ + uint32 PI_DSL_MIPS_ST; /* 0x82c */ + uint32 PI_DSL_PHY_ST; /* 0x830 */ + uint32 PI_UBUS_SMPL; /* 0x834 */ + uint32 TESTMODE; /* 0x838 */ + uint32 TEST_CFG1; /* 0x83c */ + uint32 TEST_PAT; /* 0x840 */ + uint32 TEST_COUNT; /* 0x844 */ + uint32 TEST_CURR_COUNT; /* 0x848 */ + uint32 TEST_ADDR_UPDT; /* 0x84c */ + uint32 TEST_ADDR; /* 0x850 */ + uint32 TEST_DATA0; /* 0x854 */ + uint32 TEST_DATA1; /* 0x858 */ + uint32 TEST_DATA2; /* 0x85c */ + uint32 TEST_DATA3; /* 0x860 */ +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define ROBOSW_CLK_EN (1 << 11) +#define PCIE_CLK_EN (1 << 10) +#define HS_SPI_CLK_EN (1 << 9) +#define USBH_CLK_EN (1 << 8) +#define USBD_CLK_EN (1 << 7) +#define PCM_CLK_EN (1 << 6) +#define SAR_CLK_EN (1 << 5) +#define MIPS_CLK_EN (1 << 4) +#define ADSL_CLK_EN (1 << 3) +#define ADSL_AFE_EN (1 << 2) +#define ADSL_QPROC_EN (1 << 1) +#define PHYMIPS_CLK_EN (1 << 0) + + uint32 unused0; /* (08) word 2 */ + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_PCIE_HARD (1 << 10) +#define SOFT_RST_PCIE_EXT (1 << 9) +#define SOFT_RST_PCIE (1 << 8) +#define SOFT_RST_PCIE_CORE (1 << 7) +#define SOFT_RST_PCM (1 << 6) +#define SOFT_RST_USBH (1 << 5) +#define SOFT_RST_USBD (1 << 4) +#define SOFT_RST_SWITCH (1 << 3) +#define SOFT_RST_SAR (1 << 2) +#define SOFT_RST_EPHY (1 << 1) +#define SOFT_RST_SPI (1 << 0) + + uint32 diagControl; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 unused1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 // 0 +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo>8)&0xf) +#define UDC20_INTF(x) ((x>>4)&0xf) +#define UDC20_CFG(x) ((x>>0)&0xf) + uint32 usbd_status; +#define USBD_LINK (0x1<<10) +#define USBD_SET_CSRS 0x40 +#define USBD_SUSPEND 0x20 +#define USBD_EARLY_SUSPEND 0x10 +#define USBD_SOF 0x08 +#define USBD_ENUMON 0x04 +#define USBD_SETUP 0x02 +#define USBD_USBRESET 0x01 + uint32 usbd_events; + uint32 usbd_events_irq; +#define UPPER(x) (16+x) +#define ENABLE(x) (1< +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6362_common.h */ +/* DATE: 02/01/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6362 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6362_MAP_COMMON_H +#define __BCM6362_MAP_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define NAND_INTR_BASE 0xb0000070 /* nand interrupt control registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 +#define OTP_BASE 0xb0000400 +#define UBUS_STAT_BASE 0xb0000500 +#define NAND_CACHE_BASE 0xb0000600 +#define SPI_BASE 0xb0000800 /* SPI master controller registers */ +#define HSSPIM_BASE 0xb0001000 /* High-Speed SPI registers */ +#define ADSL_CTRL_BASE 0xb0001800 +#define MISC_BASE 0xb0001800 /* Miscellaneous Registers */ +#define LED_BASE 0xb0001900 /* LED control registers */ +#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10002500 /* USB host registers */ +#define USB_OHCI_BASE 0x10002600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0002700 +#define IPSEC_BASE 0xb0002800 +#define DDR_BASE 0xb0003000 /* Memory control registers */ +#define WLAN_CHIPC_BASE 0x10004000 /* WLAN ChipCommon registers, use 1xxx for ioremap */ +#define WLAN_MAC_BASE 0x10005000 /* WLAN d11mac registers */ +#define WLAN_SHIM_BASE 0xb0007000 /* shim interface to WLAN */ +#define PCM_BASE 0xb000a000 +#define PCM_DMA_BASE 0xb000a800 /* PCM UIDMA register base */ +#define SAR_DMA_BASE 0xb000b800 /* ATM SAR DMA control registers */ +#define USB_DMA_BASE 0xb000c000 /* USB 2.0 device DMA regiseters */ +#define IPSEC_DMA_BASE 0xb000d000 +#define SWITCH_DMA_BASE 0xb000d800 +#define SWITCH_BASE 0xb0e00000 +#define PCIE_BASE 0xb0e40000 +#define DECT_SHIM_CTRL_BASE 0xb000b000 +#define DECT_SHIM_DMA_CTRL_BASE 0xb000b050 +#define DECT_SHIM_TEST_BASE 0xb000b0f0 +#define DECT_APB_REG_BASE 0xb000e000 +#define DECT_AHB_SHARED_RAM_BASE 0xb0e50000 +#define DECT_AHB_REG_BASE 0xb0e57f80 + + +/* +##################################################################### +# System PLL Control Register +##################################################################### +*/ + +/* +##################################################################### +# GPIO Control Registers +##################################################################### +*/ +/* +##################################################################### +# Miscellaneous Registers +##################################################################### +*/ +#define MISC_MEMC_CONTROL 0x10 +#define MISC_STRAP_BUS 0x14 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 1 + +#define MISC_VREG_CONTROL0 0x1C +#define MISC_VREG_CONTROL0_VREG_ADJ_SHIFT 8 +#define MISC_VREG_CONTROL0_VREG_OSC1P2_SHIFT 20 +#define MISC_VREG_CONTROL0_VREG_OSC1P8_SHIFT 22 +#define MISC_VREG_CONTROL0_VREG_RAMP1P2_SHIFT 26 +#define MISC_VREG_CONTROL0_VREG_RAMP1P8_SHIFT 29 + +#define MISC_VREG_CONTROL1 0x20 +#define MISC_VREG_CONTROL1_VREG_ISEL2P5_SHIFT 13 +#define MISC_VREG_CONTROL1_VREG_ISEL2P5_MASK 0x0001e000 +#define MISC_VREG_LDO_2P61 1 + +#define MISC_VREG_CONTROL2 0x24 + +/* +##################################################################### +# Memory Control Registers +##################################################################### +*/ +#define DDR_CTL_CNFG 0x000 +#define DDR_CTL_CSST 0x004 +#define DDR_CTL_CSEND 0x008 +#define DDR_CTL_ROW00_0 0x010 +#define DDR_CTL_ROW00_1 0x014 +#define DDR_CTL_ROW01_0 0x018 +#define DDR_CTL_ROW01_1 0x01c +#define DDR_CTL_ROW20_0 0x030 +#define DDR_CTL_ROW20_1 0x034 +#define DDR_CTL_ROW21_0 0x038 +#define DDR_CTL_ROW21_1 0x03c +#define DDR_CTL_COL00_0 0x050 +#define DDR_CTL_COL00_1 0x054 +#define DDR_CTL_COL01_0 0x058 +#define DDR_CTL_COL01_1 0x05c +#define DDR_CTL_COL20_0 0x070 +#define DDR_CTL_COL20_1 0x074 +#define DDR_CTL_COL21_0 0x078 +#define DDR_CTL_COL21_1 0x07c +#define DDR_CTL_BNK10 0x090 +#define DDR_CTL_BNK32 0x094 +#define DDR_CTL_DCMD 0x100 +#define DDR_CTL_DMODE_0 0x104 +#define DDR_CTL_DMODE_1 0x108 +#define DDR_CTL_CLKS 0x10c +#define DDR_CTL_ODT 0x110 +#define DDR_CTL_TIM1_0 0x114 +#define DDR_CTL_TIM1_1 0x118 +#define DDR_CTL_TIM2 0x11c +#define DDR_CTL_CTL_CRC 0x120 +#define DDR_CTL_DOUT_CRC 0x124 +#define DDR_CTL_DIN_CRC 0x128 +#define PHY_CONTROL_REGS_REVISION 0x200 +#define PHY_CONTROL_REGS_CLK_PM_CTRL 0x204 +#define PHY_CONTROL_REGS_PLL_STATUS 0x210 +#define PHY_CONTROL_REGS_PLL_CONFIG 0x214 +#define PHY_CONTROL_REGS_PLL_PRE_DIVIDER 0x218 +#define PHY_CONTROL_REGS_PLL_DIVIDER 0x21c +#define PHY_CONTROL_REGS_PLL_CONTROL1 0x220 +#define PHY_CONTROL_REGS_PLL_CONTROL2 0x224 +#define PHY_CONTROL_REGS_PLL_SS_EN 0x228 +#define PHY_CONTROL_REGS_PLL_SS_CFG 0x22c +#define PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE 0x230 +#define PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE 0x234 +#define PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x238 +#define PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL 0x23c +#define PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x240 +#define PHY_BYTE_LANE_0_REVISION 0x300 +#define PHY_BYTE_LANE_0_VDL_CALIBRATE 0x304 +#define PHY_BYTE_LANE_0_VDL_STATUS 0x308 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_0 0x310 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_1 0x314 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_2 0x318 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_3 0x31c +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_4 0x320 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_5 0x324 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_6 0x328 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_7 0x32c +#define PHY_BYTE_LANE_0_READ_CONTROL 0x330 +#define PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x334 +#define PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x338 +#define PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x33c +#define PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x340 +#define PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE 0x344 +#define PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x348 +#define PHY_BYTE_LANE_1_REVISION 0x400 +#define PHY_BYTE_LANE_1_VDL_CALIBRATE 0x404 +#define PHY_BYTE_LANE_1_VDL_STATUS 0x408 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_0 0x410 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_1 0x414 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_2 0x418 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_3 0x41c +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_4 0x420 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_5 0x424 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_6 0x428 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_7 0x42c +#define PHY_BYTE_LANE_1_READ_CONTROL 0x430 +#define PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x434 +#define PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x438 +#define PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x43c +#define PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x440 +#define PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE 0x444 +#define PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x448 +#define PHY_BYTE_LANE_2_REVISION 0x500 +#define PHY_BYTE_LANE_2_VDL_CALIBRATE 0x504 +#define PHY_BYTE_LANE_2_VDL_STATUS 0x508 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_0 0x510 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_1 0x514 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_2 0x518 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_3 0x51c +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_4 0x520 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_5 0x524 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_6 0x528 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_7 0x52c +#define PHY_BYTE_LANE_2_READ_CONTROL 0x530 +#define PHY_BYTE_LANE_2_READ_FIFO_STATUS 0x534 +#define PHY_BYTE_LANE_2_READ_FIFO_CLEAR 0x538 +#define PHY_BYTE_LANE_2_IDLE_PAD_CONTROL 0x53c +#define PHY_BYTE_LANE_2_DRIVE_PAD_CTL 0x540 +#define PHY_BYTE_LANE_2_CLOCK_PAD_DISABLE 0x544 +#define PHY_BYTE_LANE_2_WR_PREAMBLE_MODE 0x548 +#define PHY_BYTE_LANE_3_REVISION 0x600 +#define PHY_BYTE_LANE_3_VDL_CALIBRATE 0x604 +#define PHY_BYTE_LANE_3_VDL_STATUS 0x608 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_0 0x610 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_1 0x614 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_2 0x618 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_3 0x61c +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_4 0x620 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_5 0x624 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_6 0x628 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_7 0x62c +#define PHY_BYTE_LANE_3_READ_CONTROL 0x630 +#define PHY_BYTE_LANE_3_READ_FIFO_STATUS 0x634 +#define PHY_BYTE_LANE_3_READ_FIFO_CLEAR 0x638 +#define PHY_BYTE_LANE_3_IDLE_PAD_CONTROL 0x63c +#define PHY_BYTE_LANE_3_DRIVE_PAD_CTL 0x640 +#define PHY_BYTE_LANE_3_CLOCK_PAD_DISABLE 0x644 +#define PHY_BYTE_LANE_3_WR_PREAMBLE_MODE 0x648 +#define DDR_CTL_GCFG 0x800 +#define DDR_CTL_LBIST_CFG 0x804 +#define DDR_CTL_LBIST_SEED 0x808 +#define DDR_CTL_ARB 0x80c +#define DDR_CTL_PI_GCF 0x810 +#define DDR_CTL_PI_UBUS_CTL 0x814 +#define DDR_CTL_PI_MIPS_CTL 0x818 +#define DDR_CTL_PI_DSL_MIPS_CTL 0x81c +#define DDR_CTL_PI_DSL_PHY_CTL 0x820 +#define DDR_CTL_PI_UBUS_ST 0x824 +#define DDR_CTL_PI_MIPS_ST 0x828 +#define DDR_CTL_PI_DSL_MIPS_ST 0x82c +#define DDR_CTL_PI_DSL_PHY_ST 0x830 +#define DDR_CTL_PI_UBUS_SMPL 0x834 +#define DDR_CTL_TESTMODE 0x838 +#define DDR_CTL_TEST_CFG1 0x83c +#define DDR_CTL_TEST_PAT 0x840 +#define DDR_CTL_TEST_COUNT 0x844 +#define DDR_CTL_TEST_CURR_COUNT 0x848 +#define DDR_CTL_TEST_ADDR_UPDT 0x84c +#define DDR_CTL_TEST_ADDR 0x850 +#define DDR_CTL_TEST_DATA0 0x854 +#define DDR_CTL_TEST_DATA1 0x858 +#define DDR_CTL_TEST_DATA2 0x85c +#define DDR_CTL_TEST_DATA3 0x860 + + +/* +##################################################################### +# UART Control Registers +##################################################################### +*/ +#define UART0CONTROL 0x01 +#define UART0CONFIG 0x02 +#define UART0RXTIMEOUT 0x03 +#define UART0BAUD 0x04 +#define UART0FIFOCFG 0x0a +#define UART0INTMASK 0x10 +#define UART0INTSTAT 0x12 +#define UART0DATA 0x17 + +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + +#define XMITBREAK 0x40 /* Config register */ +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + + +/* +##################################################################### +# DECT IP Control Registers +##################################################################### +*/ +#define DECT_STARTCTL 0xb0e50818 +#define PCM_BUFF_CTL3 0xb0e5082c +#define PCM_BUFF_CTL7 0xb0e5083c +#define DECT_AHB_CHAN0_RX 0xb0e50a20 +#define DECT_AHB_CHAN1_RX 0xb0e50de0 +#define DECT_AHB_CHAN2_RX 0xb0e511a0 +#define DECT_AHB_CHAN3_RX 0xb0e51560 +#define DECT_AHB_CHAN0_TX 0xb0e50840 +#define DECT_AHB_CHAN1_TX 0xb0e50c00 +#define DECT_AHB_CHAN2_TX 0xb0e50fc0 +#define DECT_AHB_CHAN3_TX 0xb0e51380 +#define DECT_CLKEN 0x00000040 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/broadcom/include/bcm963xx/6362_map.h b/shared/broadcom/include/bcm963xx/6362_map.h new file mode 100755 index 0000000..d0fa38f --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6362_map.h @@ -0,0 +1,2251 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6362_map.h */ +/* DATE: 05/30/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6362 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6362_MAP_H +#define __BCM6362_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "bcmtypes.h" +#include "6362_common.h" +#include "6362_intr.h" + +/* macro to convert logical data addresses to physical */ +/* DMA hardware must see physical address */ +#define LtoP( x ) ( (uint32)x & 0x1fffffff ) +#define PtoL( x ) ( LtoP(x) | 0xa0000000 ) + +typedef struct DDRPhyControl { + uint32 REVISION; /* 0x00 */ + uint32 CLK_PM_CTRL; /* 0x04 */ + uint32 unused0[2]; /* 0x08-0x10 */ + uint32 PLL_STATUS; /* 0x10 */ + uint32 PLL_CONFIG; /* 0x14 */ + uint32 PLL_PRE_DIVIDER; /* 0x18 */ + uint32 PLL_DIVIDER; /* 0x1c */ + uint32 PLL_CONTROL1; /* 0x20 */ + uint32 PLL_CONTROL2; /* 0x24 */ + uint32 PLL_SS_EN; /* 0x28 */ + uint32 PLL_SS_CFG; /* 0x2c */ + uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ + uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ + uint32 IDLE_PAD_CONTROL; /* 0x38 */ + uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_REG_CONTROL; /* 0x44 */ + uint32 unused1[46]; +} DDRPhyControl; + +typedef struct DDRPhyByteLaneControl { + uint32 REVISION; /* 0x00 */ + uint32 VDL_CALIBRATE; /* 0x04 */ + uint32 VDL_STATUS; /* 0x08 */ + uint32 unused; /* 0x0c */ + uint32 VDL_OVERRIDE_0; /* 0x10 */ + uint32 VDL_OVERRIDE_1; /* 0x14 */ + uint32 VDL_OVERRIDE_2; /* 0x18 */ + uint32 VDL_OVERRIDE_3; /* 0x1c */ + uint32 VDL_OVERRIDE_4; /* 0x20 */ + uint32 VDL_OVERRIDE_5; /* 0x24 */ + uint32 VDL_OVERRIDE_6; /* 0x28 */ + uint32 VDL_OVERRIDE_7; /* 0x2c */ + uint32 READ_CONTROL; /* 0x30 */ + uint32 READ_FIFO_STATUS; /* 0x34 */ + uint32 READ_FIFO_CLEAR; /* 0x38 */ + uint32 IDLE_PAD_CONTROL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_PAD_DISABLE; /* 0x44 */ + uint32 WR_PREAMBLE_MODE; /* 0x48 */ + uint32 CLOCK_REG_CONTROL; /* 0x4C */ + uint32 unused0[44]; +} DDRPhyByteLaneControl; + +typedef struct DDRControl { + uint32 CNFG; /* 0x000 */ + uint32 CSST; /* 0x004 */ + uint32 CSEND; /* 0x008 */ + uint32 unused; /* 0x00c */ + uint32 ROW00_0; /* 0x010 */ + uint32 ROW00_1; /* 0x014 */ + uint32 ROW01_0; /* 0x018 */ + uint32 ROW01_1; /* 0x01c */ + uint32 unused0[4]; + uint32 ROW20_0; /* 0x030 */ + uint32 ROW20_1; /* 0x034 */ + uint32 ROW21_0; /* 0x038 */ + uint32 ROW21_1; /* 0x03c */ + uint32 unused1[4]; + uint32 COL00_0; /* 0x050 */ + uint32 COL00_1; /* 0x054 */ + uint32 COL01_0; /* 0x058 */ + uint32 COL01_1; /* 0x05c */ + uint32 unused2[4]; + uint32 COL20_0; /* 0x070 */ + uint32 COL20_1; /* 0x074 */ + uint32 COL21_0; /* 0x078 */ + uint32 COL21_1; /* 0x07c */ + uint32 unused3[4]; + uint32 BNK10; /* 0x090 */ + uint32 BNK32; /* 0x094 */ + uint32 unused4[26]; + uint32 DCMD; /* 0x100 */ +#define DCMD_CS1 (1 << 5) +#define DCMD_CS0 (1 << 4) +#define DCMD_SET_SREF 4 + uint32 DMODE_0; /* 0x104 */ + uint32 DMODE_1; /* 0x108 */ +#define DMODE_1_DRAMSLEEP (1 << 11) + uint32 CLKS; /* 0x10c */ + uint32 ODT; /* 0x110 */ + uint32 TIM1_0; /* 0x114 */ + uint32 TIM1_1; /* 0x118 */ + uint32 TIM2; /* 0x11c */ + uint32 CTL_CRC; /* 0x120 */ + uint32 DOUT_CRC; /* 0x124 */ + uint32 DIN_CRC; /* 0x128 */ + uint32 unused5[53]; + + DDRPhyControl PhyControl; /* 0x200 */ + DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ + DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ + DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ + DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ + uint32 unused6[64]; + + uint32 GCFG; /* 0x800 */ + uint32 LBIST_CFG; /* 0x804 */ + uint32 LBIST_SEED; /* 0x808 */ + uint32 ARB; /* 0x80c */ + uint32 PI_GCF; /* 0x810 */ + uint32 PI_UBUS_CTL; /* 0x814 */ + uint32 PI_MIPS_CTL; /* 0x818 */ + uint32 PI_DSL_MIPS_CTL; /* 0x81c */ + uint32 PI_DSL_PHY_CTL; /* 0x820 */ + uint32 PI_UBUS_ST; /* 0x824 */ + uint32 PI_MIPS_ST; /* 0x828 */ + uint32 PI_DSL_MIPS_ST; /* 0x82c */ + uint32 PI_DSL_PHY_ST; /* 0x830 */ + uint32 PI_UBUS_SMPL; /* 0x834 */ + uint32 TESTMODE; /* 0x838 */ + uint32 TEST_CFG1; /* 0x83c */ + uint32 TEST_PAT; /* 0x840 */ + uint32 TEST_COUNT; /* 0x844 */ + uint32 TEST_CURR_COUNT; /* 0x848 */ + uint32 TEST_ADDR_UPDT; /* 0x84c */ + uint32 TEST_ADDR; /* 0x850 */ + uint32 TEST_DATA0; /* 0x854 */ + uint32 TEST_DATA1; /* 0x858 */ + uint32 TEST_DATA2; /* 0x85c */ + uint32 TEST_DATA3; /* 0x860 */ +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define NAND_CLK_EN (1 << 20) +#define PHYMIPS_CLK_EN (1 << 19) +#define FAP_CLK_EN (1 << 18) +#define PCIE_CLK_EN (1 << 17) +#define HS_SPI_CLK_EN (1 << 16) +#define SPI_CLK_EN (1 << 15) +#define IPSEC_CLK_EN (1 << 14) +#define USBH_CLK_EN (1 << 13) +#define USBD_CLK_EN (1 << 12) +#define PCM_CLK_EN (1 << 11) +#define ROBOSW_CLK_EN (1 << 10) +#define SAR_CLK_EN (1 << 9) +#define SWPKT_SAR_CLK_EN (1 << 8) +#define SWPKT_USB_CLK_EN (1 << 7) +#define WLAN_OCP_CLK_EN (1 << 5) +#define MIPS_CLK_EN (1 << 4) +#define ADSL_CLK_EN (1 << 3) +#define ADSL_AFE_EN (1 << 2) +#define ADSL_QPROC_EN (1 << 1) +#define DISABLE_GLESS (1 << 0) + + uint32 pll_control; /* (08) word 2 */ +#define SOFT_RESET 0x00000001 // 0 + + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_WLAN_SHIM_UBUS (1 << 14) +#define SOFT_RST_FAP (1 << 13) +#define SOFT_RST_DDR_PHY (1 << 12) +#define SOFT_RST_WLAN_SHIM (1 << 11) +#define SOFT_RST_PCIE_EXT (1 << 10) +#define SOFT_RST_PCIE (1 << 9) +#define SOFT_RST_PCIE_CORE (1 << 8) +#define SOFT_RST_PCM (1 << 7) +#define SOFT_RST_USBH (1 << 6) +#define SOFT_RST_USBD (1 << 5) +#define SOFT_RST_SWITCH (1 << 4) +#define SOFT_RST_SAR (1 << 3) +#define SOFT_RST_EPHY (1 << 2) +#define SOFT_RST_IPSEC (1 << 1) +#define SOFT_RST_SPI (1 << 0) + + uint32 diagControl; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 unused1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifoUserBits[((sizeof(OTP->UserBits)/4) - (x)/32 - 1)] >> ((x) % 32)) & 1) + +/* +** Spi Controller +*/ + +typedef struct SpiControl { + uint16 spiMsgCtl; /* (0x0) control byte */ +#define FULL_DUPLEX_RW 0 +#define HALF_DUPLEX_W 1 +#define HALF_DUPLEX_R 2 +#define SPI_MSG_TYPE_SHIFT 14 +#define SPI_BYTE_CNT_SHIFT 0 + byte spiMsgData[0x21e]; /* (0x02 - 0x21f) msg data */ + byte unused0[0x1e0]; + byte spiRxDataFifo[0x220]; /* (0x400 - 0x61f) rx data */ + byte unused1[0xe0]; + + uint16 spiCmd; /* (0x700): SPI command */ +#define SPI_CMD_NOOP 0 +#define SPI_CMD_SOFT_RESET 1 +#define SPI_CMD_HARD_RESET 2 +#define SPI_CMD_START_IMMEDIATE 3 + +#define SPI_CMD_COMMAND_SHIFT 0 +#define SPI_CMD_COMMAND_MASK 0x000f + +#define SPI_CMD_DEVICE_ID_SHIFT 4 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 +#define SPI_CMD_ONE_BYTE_SHIFT 11 +#define SPI_CMD_ONE_WIRE_SHIFT 12 +#define SPI_DEV_ID_0 0 +#define SPI_DEV_ID_1 1 +#define SPI_DEV_ID_2 2 +#define SPI_DEV_ID_3 3 + + byte spiIntStatus; /* (0x702): SPI interrupt status */ + byte spiMaskIntStatus; /* (0x703): SPI masked interrupt status */ + + byte spiIntMask; /* (0x704): SPI interrupt mask */ +#define SPI_INTR_CMD_DONE 0x01 +#define SPI_INTR_RX_OVERFLOW 0x02 +#define SPI_INTR_INTR_TX_UNDERFLOW 0x04 +#define SPI_INTR_TX_OVERFLOW 0x08 +#define SPI_INTR_RX_UNDERFLOW 0x10 +#define SPI_INTR_CLEAR_ALL 0x1f + + byte spiStatus; /* (0x705): SPI status */ +#define SPI_RX_EMPTY 0x02 +#define SPI_CMD_BUSY 0x04 +#define SPI_SERIAL_BUSY 0x08 + + byte spiClkCfg; /* (0x706): SPI clock configuration */ +#define SPI_CLK_0_391MHZ 1 +#define SPI_CLK_0_781MHZ 2 /* default */ +#define SPI_CLK_1_563MHZ 3 +#define SPI_CLK_3_125MHZ 4 +#define SPI_CLK_6_250MHZ 5 +#define SPI_CLK_12_50MHZ 6 +#define SPI_CLK_MASK 0x07 +#define SPI_SSOFFTIME_MASK 0x38 +#define SPI_SSOFFTIME_SHIFT 3 +#define SPI_BYTE_SWAP 0x80 + + byte spiFillByte; /* (0x707): SPI fill byte */ + byte unused2; + byte spiMsgTail; /* (0x709): msgtail */ + byte unused3; + byte spiRxTail; /* (0x70B): rxtail */ +} SpiControl; + +#define SPI ((volatile SpiControl * const) SPI_BASE) + + +/* +** High-Speed SPI Controller +*/ + +#define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start) +typedef struct HsSpiControl { + + uint32 hs_spiGlobalCtrl; // 0x0000 +#define HS_SPI_MOSI_IDLE (1 << 18) +#define HS_SPI_CLK_POLARITY (1 << 17) +#define HS_SPI_CLK_GATE_SSOFF (1 << 16) +#define HS_SPI_PLL_CLK_CTRL (8) +#define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL) +#define HS_SPI_SS_POLARITY (0) +#define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY) + + uint32 hs_spiExtTrigCtrl; // 0x0004 +#define HS_SPI_TRIG_RAW_STATE (24) +#define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE) +#define HS_SPI_TRIG_LATCHED (16) +#define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED) +#define HS_SPI_TRIG_SENSE (8) +#define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE) +#define HS_SPI_TRIG_TYPE (0) +#define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE) +#define HS_SPI_TRIG_TYPE_EDGE (0) +#define HS_SPI_TRIG_TYPE_LEVEL (1) + + uint32 hs_spiIntStatus; // 0x0008 +#define HS_SPI_IRQ_PING1_USER (28) +#define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER) +#define HS_SPI_IRQ_PING0_USER (24) +#define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER) + +#define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQ_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQ_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntStatusMasked; // 0x000C +#define HS_SPI_IRQSM__PING1_USER (28) +#define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER) +#define HS_SPI_IRQSM__PING0_USER (24) +#define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER) + +#define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntMask; // 0x0010 +#define HS_SPI_IRQM_PING1_USER (28) +#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER) +#define HS_SPI_IRQM_PING0_USER (24) +#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER) + +#define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQM_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQM_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0) + +#define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F) + + uint32 hs_spiFlashCtrl; // 0x0014 +#define HS_SPI_FCTRL_MB_ENABLE (1 << 23) +#define HS_SPI_FCTRL_SS_NUM (20) +#define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM) +#define HS_SPI_FCTRL_PROFILE_NUM (16) +#define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM) +#define HS_SPI_FCTRL_DUMMY_BYTES (10) +#define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES (8) +#define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES_2 (0) +#define HS_SPI_FCTRL_ADDR_BYTES_3 (1) +#define HS_SPI_FCTRL_ADDR_BYTES_4 (2) +#define HS_SPI_FCTRL_READ_OPCODE (0) +#define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE) + + uint32 hs_spiFlashAddrBase; // 0x0018 + + char fill0[0x80 - 0x18]; + + uint32 hs_spiPP_0_Cmd; // 0x0080 +#define HS_SPI_PP_SS_NUM (12) +#define HS_SPI_PP_SS_NUM_MASK __mask(14, HS_SPI_PP_SS_NUM) +#define HS_SPI_PP_PROFILE_NUM (8) +#define HS_SPI_PP_PROFILE_NUM_MASK __mask(10, HS_SPI_PP_PROFILE_NUM) + +} HsSpiControl; + +typedef struct HsSpiPingPong { + + uint32 command; +#define HS_SPI_SS_NUM (12) +#define HS_SPI_PROFILE_NUM (8) +#define HS_SPI_TRIGGER_NUM (4) +#define HS_SPI_COMMAND_VALUE (0) + #define HS_SPI_COMMAND_NOOP (0) + #define HS_SPI_COMMAND_START_NOW (1) + #define HS_SPI_COMMAND_START_TRIGGER (2) + #define HS_SPI_COMMAND_HALT (3) + #define HS_SPI_COMMAND_FLUSH (4) + + uint32 status; +#define HS_SPI_ERROR_BYTE_OFFSET (16) +#define HS_SPI_WAIT_FOR_TRIGGER (2) +#define HS_SPI_SOURCE_BUSY (1) +#define HS_SPI_SOURCE_GNT (0) + + uint32 fifo_status; + uint32 control; + +} HsSpiPingPong; + +typedef struct HsSpiProfile { + + uint32 clk_ctrl; +#define HS_SPI_ACCUM_RST_ON_LOOP (15) +#define HS_SPI_SPI_CLK_2X_SEL (14) +#define HS_SPI_FREQ_CTRL_WORD (0) + + uint32 signal_ctrl; +#define HS_SPI_ASYNC_INPUT_PATH (1 << 16) +#define HS_SPI_LAUNCH_RISING (1 << 13) +#define HS_SPI_LATCH_RISING (1 << 12) + + uint32 mode_ctrl; +#define HS_SPI_PREPENDBYTE_CNT (24) +#define HS_SPI_MODE_ONE_WIRE (20) +#define HS_SPI_MULTIDATA_WR_SIZE (18) +#define HS_SPI_MULTIDATA_RD_SIZE (16) +#define HS_SPI_MULTIDATA_WR_STRT (12) +#define HS_SPI_MULTIDATA_RD_STRT (8) +#define HS_SPI_FILLBYTE (0) + + uint32 polling_config; + uint32 polling_and_mask; + uint32 polling_compare; + uint32 polling_timeout; + uint32 reserved; + +} HsSpiProfile; + +#define HS_SPI_OP_CODE 13 + #define HS_SPI_OP_SLEEP (0) + #define HS_SPI_OP_READ_WRITE (1) + #define HS_SPI_OP_WRITE (2) + #define HS_SPI_OP_READ (3) + #define HS_SPI_OP_SETIRQ (4) + +#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE) +#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80)) +#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0)) +#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100)) +#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200)) +#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400)) + + +/* +** Misc Register Set Definitions. +*/ + +typedef struct Misc { + uint32 unused1; /* 0x00 */ + uint32 miscSerdesCtrl; /* 0x04 */ +#define SERDES_PCIE_ENABLE 0x00000001 +#define SERDES_PCIE_EXD_ENABLE (1<<15) + + uint32 miscSerdesSts; /* 0x08 */ + uint32 miscIrqOutMask; /* 0x0C */ +#define MISC_PCIE_EP_IRQ_MASK0 (1<<0) +#define MISC_PCIE_EP_IRQ_MASK1 (1<<1) + + uint32 miscMemcControl; /* 0x10 */ +#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE (1<<3) +#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE (1<<2) +#define MISC_MEMC_CONTROL_DDR_TEST_DONE (1<<1) +#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE (1<<0) + + uint32 miscStrapBus; /* 0x14 */ +#define MISC_STRAP_BUS_RESET_CFG_DELAY (1<<18) +#define MISC_STRAP_BUS_RESET_OUT_SHIFT 16 +#define MISC_STRAP_BUS_RESET_OUT_MASK (3<>8)&0xf) +#define UDC20_INTF(x) ((x>>4)&0xf) +#define UDC20_CFG(x) ((x>>0)&0xf) + uint32 usbd_status; +#define USBD_LINK (0x1<<10) +#define USBD_SET_CSRS 0x40 +#define USBD_SUSPEND 0x20 +#define USBD_EARLY_SUSPEND 0x10 +#define USBD_SOF 0x08 +#define USBD_ENUMON 0x04 +#define USBD_SETUP 0x02 +#define USBD_USBRESET 0x01 + uint32 usbd_events; + uint32 usbd_events_irq; +#define UPPER(x) (16+x) +#define ENABLE(x) (1< +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6368_common.h */ +/* DATE: 02/06/07 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6368 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6368_MAP_COMMON_H +#define __BCM6368_MAP_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define NAND_INTR_BASE 0xb0000070 /* nand interrupt control registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 +#define NAND_SEC_BASE 0xb0000300 +#define OTP_BASE 0xb0000400 +#define UBUS_STAT_BASE 0xb0000500 +#define NAND_CACHE_BASE 0xb0000600 +#define SPI_BASE 0xb0000800 /* SPI master controller registers */ +#define MPI_BASE 0xb0001000 /* MPI control registers */ +#define MEMC_BASE 0xb0001200 /* Memory control registers */ +#define DDR_BASE 0xb0001280 /* DDR IO Buf Control registers */ +#define USB_CTL_BASE 0xb0001400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10001500 /* USB host registers */ +#define USB_OHCI_BASE 0x10001600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0001700 +#define SAR_BASE 0xb0001800 /* ATM SAR control registers */ +#define SAR_CMF_BASE 0xb0002000 /* ATM SAR CMF control registers */ +#define PCM_BASE 0xb0004000 /* PCM control registers */ +#define IPSEC_BASE 0xb0004100 +#define USB_DMA_BASE 0xb0004800 /* USB 2.0 device DMA regiseters */ +#define SAR_DMA_BASE 0xb0005000 /* ATM SAR DMA control registers */ +#define PCM_DMA_BASE 0xb0005800 /* PCM UIDMA register base */ +#define IPSEC_DMA_BASE 0xb0006000 +#define SWITCH_DMA_BASE 0xb0006800 +#define SWITCH_BASE 0xb0f00000 +#define SWITCH_CMF_BASE 0xb0f0a000 /* Switch CMF register base */ + +#define ADSL_PHY_BASE 0xb0f40000 +#define ADSL_ENUM_BASE 0xb0f56000 +#define ADSL_LMEM_BASE 0xb0f80000 + +/* +##################################################################### +# System PLL Control Register +##################################################################### +*/ + + +/* +##################################################################### +# GPIO Control Registers +##################################################################### +*/ + + +/* +##################################################################### +# Memory Control Registers +##################################################################### +*/ +#define MEMC_CONTROL 0x0 +#define MEMC_CONFIG 0x4 +#define MEMC_REF_PD_CONTROL 0x8 +#define MEMC_BIST_STATUS 0xc +#define MEMC_M_EM_BUF 0x10 +#define MEMC_BANK_CLS_TIM 0x14 +#define MEMC_PRIOR_INV_TIM 0x18 +#define MEMC_DRAM_TIM 0x1c +#define MEMC_INT_STATUS 0x20 +#define MEMC_INT_MASK 0x24 +#define MEMC_INT_INFO 0x28 +#define MEMC_BARRIER 0x50 +#define MEMC_CORE_ID 0x54 + +#define DDR_REV_ID 0x0 +#define DDR_PAD_SSTL_MODE 0x4 +#define DDR_CMD_PAD_CNTL 0x8 +#define DDR_DQ_PAD_CNTL 0xc +#define DDR_DQS_PAD_CNTL 0x10 +#define DDR_CLK_PAD_CNTL 0x14 +#define DDR_PLL_CNTL0 0x18 +#define DDR_PLL_CNTL1 0x1c +#define DDR_MIPSDDR_PLL_CONFIG 0x20 +#define DDR_MIPSDDR_PLL_MDIV 0x24 +#define DDR_DSL_PHY_PHASE_CNTL 0x28 +#define DDR_DSL_CPU_PHASE_CNTL 0x2c +#define DDR_MIPS_PHASE_CNTL 0x30 +#define DDR_DDR1_2_PHASE_CNTL 0x34 +#define DDR_DDR3_4_PHASE_CNTL 0x38 +#define DDR_VCDL_PHASE_CNTL0 0x3c +#define DDR_VCDL_PHASE_CNTL1 0x40 +#define DDR_BSLICE_CNTL 0x44 +#define DDR_DESKEW_DLL_CNTL 0x48 +#define DDR_DESKEW_DLL_RESET 0x4c +#define DDR_DESKEW_DLL_PHASE 0x50 +#define DDR_ANALOG_TEST_CNTL 0x54 +#define DDR_RD_DQS_GATE_CNTL 0x58 +#define DDR_MISC 0x5c +#define DDR_SPARE0 0x60 +#define DDR_SPARE1 0x64 +#define DDR_SPARE2 0x68 +#define DDR_CLBIST 0x6c +#define DDR_LBIST_CRC 0x70 +#define DDR_UBUS_PHASE_CNTR 0x74 +#define DDR_UBUS_PI_DSK0 0x78 +#define DDR_UBUS_PI_DSK1 0x7c + +// Some bit/field definitions for the MEMC_CONFIG register. +#define MEMC_EARLY_HDR_CNT_SHFT 25 +#define MEMC_EARLY_HDR_CNT_MASK (0x7< +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6368_map.h */ +/* DATE: 02/06/07 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6368 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6368_MAP_H +#define __BCM6368_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" +#include "6368_common.h" +#include "6368_intr.h" + +/* macro to convert logical data addresses to physical */ +/* DMA hardware must see physical address */ +#define LtoP( x ) ( (uint32)x & 0x1fffffff ) +#define PtoL( x ) ( LtoP(x) | 0xa0000000 ) + +typedef struct MemoryControl +{ + uint32 Control; /* (00) */ +#define MEMC_SELF_REFRESH (1<<6) // enable self refresh mode +#define MEMC_MRS (1<<4) // generate a mode register select cycle +#define MEMC_PRECHARGE (1<<3) // generate a precharge cycle +#define MEMC_REFRESH (1<<2) // generate an auto refresh cycle +#define MEMC_SEQUENCE_ENABLE (1<<1) // enable memory controller sequencer +#define MEMC_MASTER_ENABLE (1<<0) // enable accesses to external sdram + + uint32 Config; /* (04) */ +#define MEMC_EARLY_HDR_CNT_SHFT 25 +#define MEMC_EARLY_HDR_CNT_MASK (0x7< thresh, txfifo>8)&0xf) +#define UDC20_INTF(x) ((x>>4)&0xf) +#define UDC20_CFG(x) ((x>>0)&0xf) + uint32 usbd_status; +#define USBD_LINK (0x1<<10) +#define USBD_SET_CSRS 0x40 +#define USBD_SUSPEND 0x20 +#define USBD_EARLY_SUSPEND 0x10 +#define USBD_SOF 0x08 +#define USBD_ENUMON 0x04 +#define USBD_SETUP 0x02 +#define USBD_USBRESET 0x01 + uint32 usbd_events; + uint32 usbd_events_irq; +#define UPPER(x) (16+x) +#define ENABLE(x) (1< +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6816_common.h */ +/* DATE: 02/01/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6816 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6816_MAP_COMMON_H +#define __BCM6816_MAP_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define NAND_INTR_BASE 0xb0000070 +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define I2C_BASE 0xb0000180 +#define OTP_BASE 0xb0000400 +#define UBUS_STAT_BASE 0xb0000500 +#define SPI_BASE 0xb0000800 /* SPI master controller registers */ +#define HSSPIM_BASE 0xb0001000 +#define MISC_BASE 0xb0001800 +#define NAND_REG_BASE 0xb0002000 /* NAND control registers */ +#define MPI_BASE 0xb00020A0 /* MPI control registers */ +#define PCI_BASE 0xb0002100 /* PCI control registers */ +#define NAND_CACHE_BASE 0xb0002200 +#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10002500 /* USB host registers */ +#define USB_OHCI_BASE 0x10002600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0002700 +#define IPSEC_BASE 0xb0002800 +#define DDR_BASE 0xb0003000 /* Memory control registers */ +#define GPON_BASE 0xb0004000 +#define APM_BASE 0xb0008000 +#define PCM_BASE 0xb0008200 +#define APM_HVG_BASE 0xb0008300 +#define APM_IUDMA_BASE 0xb0008800 +#define BMU_BASE 0xb0009000 /* fff9D000-fff9Dfff */ +#define USB_DMA_BASE 0xb000c000 /* USB 2.0 device DMA regiseters */ +#define GPON_DMA_BASE 0xb000c800 +#define IPSEC_DMA_BASE 0xb000d000 +#define SWITCH_DMA_BASE 0xb000d800 +#define SWITCH_DMA_CONFIG 0xb000da00 +#define SWITCH_DMA_STATE 0xb000dc00 +#define APM_MEM_BASE 0xb0010000 +#define MOCA_MEM_BASE 0xb0d00000 +#define MOCA_IO_BASE 0xb0d80000 +#define SWITCH_BASE 0xb0e00000 +#define PCIE_MEM65K_BASE 0xb0e40000 +#define PCIE_MEM1M_BASE 0xb0f00000 + +/* +##################################################################### +# System PLL Control Register +##################################################################### +*/ + +/* +##################################################################### +# GPIO Control Registers +##################################################################### +*/ +#define GPIO_SWREG_CONFIG 0x1c +#define GPIO_LIN_VREG_ADJ_SHIFT 0x0 +#define GPIO_LIN_VREG_ADJ_MASK (0xf< +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6816_map.h */ +/* DATE: 05/30/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6816 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6816_MAP_H +#define __BCM6816_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" +#include "6816_common.h" +#include "6816_intr.h" + +/* macro to convert logical data addresses to physical */ +/* DMA hardware must see physical address */ +#define LtoP( x ) ( (uint32)x & 0x1fffffff ) +#define PtoL( x ) ( LtoP(x) | 0xa0000000 ) + +typedef struct DDRPhyControl { + uint32 REVISION; /* 0x00 */ + uint32 CLK_PM_CTRL; /* 0x04 */ + uint32 unused0[2]; /* 0x08-0x10 */ + uint32 PLL_STATUS; /* 0x10 */ + uint32 PLL_CONFIG; /* 0x14 */ + uint32 PLL_PRE_DIVIDER; /* 0x18 */ + uint32 PLL_DIVIDER; /* 0x1c */ + uint32 PLL_CONTROL1; /* 0x20 */ + uint32 PLL_CONTROL2; /* 0x24 */ + uint32 PLL_SS_EN; /* 0x28 */ + uint32 PLL_SS_CFG; /* 0x2c */ + uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ + uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ + uint32 IDLE_PAD_CONTROL; /* 0x38 */ + uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_REG_CONTROL; /* 0x44 */ + uint32 unused1[46]; +} DDRPhyControl; + +typedef struct DDRPhyByteLaneControl { + uint32 REVISION; /* 0x00 */ + uint32 VDL_CALIBRATE; /* 0x04 */ + uint32 VDL_STATUS; /* 0x08 */ + uint32 unused; /* 0x0c */ + uint32 VDL_OVERRIDE_0; /* 0x10 */ + uint32 VDL_OVERRIDE_1; /* 0x14 */ + uint32 VDL_OVERRIDE_2; /* 0x18 */ + uint32 VDL_OVERRIDE_3; /* 0x1c */ + uint32 VDL_OVERRIDE_4; /* 0x20 */ + uint32 VDL_OVERRIDE_5; /* 0x24 */ + uint32 VDL_OVERRIDE_6; /* 0x28 */ + uint32 VDL_OVERRIDE_7; /* 0x2c */ + uint32 READ_CONTROL; /* 0x30 */ + uint32 READ_FIFO_STATUS; /* 0x34 */ + uint32 READ_FIFO_CLEAR; /* 0x38 */ + uint32 IDLE_PAD_CONTROL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_PAD_DISABLE; /* 0x44 */ + uint32 WR_PREAMBLE_MODE; /* 0x48 */ + uint32 CLOCK_REG_CONTROL; /* 0x4C */ + uint32 unused0[44]; +} DDRPhyByteLaneControl; + +typedef struct DDRControl { + uint32 CNFG; /* 0x000 */ + uint32 CSST; /* 0x004 */ + uint32 CSEND; /* 0x008 */ + uint32 unused; /* 0x00c */ + uint32 ROW00_0; /* 0x010 */ + uint32 ROW00_1; /* 0x014 */ + uint32 ROW01_0; /* 0x018 */ + uint32 ROW01_1; /* 0x01c */ + uint32 unused0[4]; + uint32 ROW20_0; /* 0x030 */ + uint32 ROW20_1; /* 0x034 */ + uint32 ROW21_0; /* 0x038 */ + uint32 ROW21_1; /* 0x03c */ + uint32 unused1[4]; + uint32 COL00_0; /* 0x050 */ + uint32 COL00_1; /* 0x054 */ + uint32 COL01_0; /* 0x058 */ + uint32 COL01_1; /* 0x05c */ + uint32 unused2[4]; + uint32 COL20_0; /* 0x070 */ + uint32 COL20_1; /* 0x074 */ + uint32 COL21_0; /* 0x078 */ + uint32 COL21_1; /* 0x07c */ + uint32 unused3[4]; + uint32 BNK10; /* 0x090 */ + uint32 BNK32; /* 0x094 */ + uint32 unused4[26]; + uint32 DCMD; /* 0x100 */ +#define DCMD_CS1 (1 << 5) +#define DCMD_CS0 (1 << 4) +#define DCMD_SET_SREF 4 + uint32 DMODE_0; /* 0x104 */ + uint32 DMODE_1; /* 0x108 */ +#define DMODE_1_DRAMSLEEP (1 << 11) + uint32 CLKS; /* 0x10c */ + uint32 ODT; /* 0x110 */ + uint32 TIM1_0; /* 0x114 */ + uint32 TIM1_1; /* 0x118 */ + uint32 TIM2; /* 0x11c */ + uint32 CTL_CRC; /* 0x120 */ + uint32 DOUT_CRC; /* 0x124 */ + uint32 DIN_CRC; /* 0x128 */ + uint32 unused5[53]; + + DDRPhyControl PhyControl; /* 0x200 */ + DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ + DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ + DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ + DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ + uint32 unused6[64]; + + uint32 GCFG; /* 0x800 */ + uint32 LBIST_CFG; /* 0x804 */ + uint32 LBIST_SEED; /* 0x808 */ + uint32 ARB; /* 0x80c */ + uint32 PI_GCF; /* 0x810 */ + uint32 PI_UBUS_CTL; /* 0x814 */ + uint32 PI_MIPS_CTL; /* 0x818 */ + uint32 PI_DSL_MIPS_CTL; /* 0x81c */ + uint32 PI_DSL_PHY_CTL; /* 0x820 */ + uint32 PI_UBUS_ST; /* 0x824 */ + uint32 PI_MIPS_ST; /* 0x828 */ + uint32 PI_DSL_MIPS_ST; /* 0x82c */ + uint32 PI_DSL_PHY_ST; /* 0x830 */ + uint32 PI_UBUS_SMPL; /* 0x834 */ + uint32 TESTMODE; /* 0x838 */ + uint32 TEST_CFG1; /* 0x83c */ + uint32 TEST_PAT; /* 0x840 */ + uint32 TEST_COUNT; /* 0x844 */ + uint32 TEST_CURR_COUNT; /* 0x848 */ + uint32 TEST_ADDR_UPDT; /* 0x84c */ + uint32 TEST_ADDR; /* 0x850 */ + uint32 TEST_DATA0; /* 0x854 */ + uint32 TEST_DATA1; /* 0x858 */ + uint32 TEST_DATA2; /* 0x85c */ + uint32 TEST_DATA3; /* 0x860 */ +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define ACP_A_CLK_EN (1 << 25) +#define ACP_B_CLK_EN (1 << 24) +#define NTP_CLK_EN (1 << 23) +#define PCM_CLK_EN (1 << 22) +#define BMU_CLK_EN (1 << 21) +#define PCIE_CLK_EN (1 << 20) +#define GPON_SER_CLK_EN (1 << 19) +#define IPSEC_CLK_EN (1 << 18) +#define NAND_CLK_EN (1 << 17) +#define DISABLE_GLESS (1 << 16) +#define USBH_CLK_EN (1 << 15) +#define APM_CLK_EN (1 << 14) +#define ROBOSW_CLK_EN (1 << 12) +#define USBD_CLK_EN (1 << 10) +#define SPI_CLK_EN (1 << 9) +#define SWPKT_GPON_CLK_EN (1 << 8) +#define SWPKT_USB_CLK_EN (1 << 7) +#define GPON_CLK_EN (1 << 6) + + uint32 pll_control; /* (08) word 2 */ +#define SOFT_RESET 0x00000001 // 0 + + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_SERDES_DIG (1 << 23) +#define SOFT_RST_SERDES (1 << 22) +#define SOFT_RST_SERDES_MDIO (1 << 21) +#define SOFT_RST_SERDES_PLL (1 << 20) +#define SOFT_RST_SERDES_HW (1 << 19) +#define SOFT_RST_GPON (1 << 18) +#define SOFT_RST_BMU (1 << 17) +#define SOFT_RST_HVG (1 << 16) +#define SOFT_RST_APM (1 << 15) +#define SOFT_RST_ACP (1 << 14) +#define SOFT_RST_PCM (1 << 13) +#define SOFT_RST_USBH (1 << 12) +#define SOFT_RST_USBD (1 << 11) +#define SOFT_RST_SWITCH (1 << 10) +#define SOFT_RST_MOCA_CPU (1 << 9) +#define SOFT_RST_MOCA_SYS (1 << 8) +#define SOFT_RST_MOCA (1 << 7) +#define SOFT_RST_EPHY (1 << 6) +#define SOFT_RST_PCIE (1 << 5) +#define SOFT_RST_IPSEC (1 << 4) +#define SOFT_RST_MPI (1 << 3) +#define SOFT_RST_PCIE_EXT (1 << 2) +#define SOFT_RST_PCIE_CORE (1 << 1) +#define SOFT_RST_SPI (1 << 0) + + uint32 diagControl; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 ExtIrqCfg1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo>8)&0xf) +#define UDC20_INTF(x) ((x>>4)&0xf) +#define UDC20_CFG(x) ((x>>0)&0xf) + uint32 usbd_status; +#define USBD_LINK (0x1<<10) +#define USBD_SET_CSRS 0x40 +#define USBD_SUSPEND 0x20 +#define USBD_EARLY_SUSPEND 0x10 +#define USBD_SOF 0x08 +#define USBD_ENUMON 0x04 +#define USBD_SETUP 0x02 +#define USBD_USBRESET 0x01 + uint32 usbd_events; + uint32 usbd_events_irq; +#define UPPER(x) (16+x) +#define ENABLE(x) (1< +*/ +/*************************************************************************** + * File Name : MoCABlock.h + * + * Description: This file contains definitions for the MoCA Block for the + * BCM6816 and the BCM3450 chipset(s). + ***************************************************************************/ + +#if !defined(_MoCABLOCK_H_) +#define _MoCABLOCK_H_ + +/* BCM 96816 related definitions . */ +#define MoCA_INTERRUPT_DISABLE 0x0 +#define MoCA_INTERRUPT_ENABLE 0x1 + +/* Definitions for coreInterrupts from host */ +#define MoCA_HOST_RESP_TO_CORE 0x1 +#define MoCA_HOST_REQ_TO_CORE 0x2 + +/* Definitions for hostInterrupts from core */ +#define MoCA_CORE_RESP_TO_HOST 0x1 +#define MoCA_CORE_REQ_TO_HOST 0x2 +#define MoCA_CORE_ASSERT_TO_HOST 0x4 +#define MoCA_CORE_UNUSED 0xFC +#define MoCA_CORE_DDR_START 0x100 +#define MoCA_CORE_DDR_END 0x200 + +#define MoCA_LED_LINK_ON_ACTIVE_OFF 0x0 +#define MoCA_LED_LINK_OFF_ACTIVE_OFF 0x1 +#define MoCA_LED_LINK_ON_ACTIVE_ON 0x2 +#define MoCA_LED_LINK_OFF_ACTIVE_ON 0x3 /* NW Search and New Node Admission */ +typedef struct _MoCAExtras { + UINT32 host2MoCAIntEn ; + UINT32 host2MoCAIntTrig ; + UINT32 host2MoCAIntStatus ; + UINT32 MoCA2HostIntEn ; + UINT32 MoCA2HostIntTrig ; + UINT32 MoCA2HostIntStatus ; + UINT32 genPurpose0 ; + UINT32 genPurpose1 ; + UINT32 sideBandGmiiFC ; + UINT32 leds ; + UINT32 MoCAStatus ; + UINT32 testMuxSel ; + UINT32 mdCtrl ; + UINT32 mdcDivider ; + UINT32 outRefIntR01 ; + UINT32 outRefIntR02 ; + UINT32 outRefIntR03 ; + UINT32 outRefIntR04 ; + UINT32 outRefIntR05 ; + UINT32 outRefIntSel ; +} MoCAExtras ; + + +typedef struct _MoCAMACRegs { + UINT32 macCtrl ; // 0x00 +#define MoCA_MAC_REGS_MAC_CTRL_MAC_ENABLE 0x00000001 + UINT32 resv1 [7] ; + UINT32 frmHdr ; // 0x20 + UINT32 msduHdr ; // 0x24 + UINT32 resv2 [2] ; + UINT32 macStatus ; // 0x30 + UINT32 macStatusEn ; // 0x34 + UINT32 resv3 [2] ; + UINT32 netTimer ; // 0x40 + UINT32 maxNetTimerCorr ; // 0x44 + UINT32 timerCorrCtrl ; // 0x48 + UINT32 bitParams ; // 0x4c + UINT32 fineCorr ; // 0x50 + UINT32 coarseCorr ; // 0x54 + UINT32 loadTimer1 ; // 0x58 + UINT32 loadTimer2 ; // 0x5c + UINT32 mpiConfigCtrl ; // 0x60 +#define MoCA_MAC_REGS_MPI_CONFIG_CTRL_READ 0x00000001 +#define MoCA_MAC_REGS_MPI_CONFIG_CTRL_WRITE 0x00000002 + UINT32 mpiConfigAddr ; // 0x64 + UINT32 mpiConfigDataW ; // 0x68 + UINT32 mpiConfigDataR ; // 0x6c +} MoCA_MAC_REGST, *PMoCA_MAC_REGST ; + +#define MoCA_BLOCK_BASE MOCA_MEM_BASE +typedef struct MoCABlockT { + + UINT8 dataMem [0x3FFFC] ; + UINT8 resvd [0x61403] ; + MoCAExtras extras ; // 0xb0da1400. + //MoCAHostM2M follows. + //MoCAMoCAM2M follows. +} MoCA_BLOCKT, *PMoCA_BLOCKT ; + +#define MoCA_PHYS_IO_BASE NONCACHE_TO_PHYS(MOCA_IO_BASE) +#define MoCA_BLOCK_MAC_REGS_START (MOCA_IO_BASE+0x400) +#define MoCA_BLOCK_PHY_START MoCA_PHYS_IO_BASE+0x8000 +#define MoCA_BLOCK_PHY_END MoCA_PHYS_IO_BASE+0xA3FF +#define MoCA_BLOCK ((volatile PMoCA_BLOCKT const) MoCA_BLOCK_BASE) +#define MoCA_MAC_REGS ((volatile PMoCA_MAC_REGST const) MoCA_BLOCK_MAC_REGS_START) +#define MoCA_CORE_MEM_BASE MoCA_BLOCK->dataMem +#define MoCA_MAIL_BOX_ADDR_REG MoCA_BLOCK->extras.genPurpose0 +#define MoCA_IQ_SNR_ADDR_REG MoCA_BLOCK->extras.genPurpose1 + +/* BCM 93450 related definitions . */ + +#define BCM3450_I2C_CHIP_ADDRESS 0x70 +typedef struct _Bcm3450Reg { + UINT32 ChipId; /* 0x0 */ + UINT32 ChipRev; /* 0x4 */ + UINT32 Test; /* 0x8 */ + UINT32 SerialCtl; /* 0xc */ + UINT32 StatusRead; /* 0x10 */ + UINT32 LnaCntl; /* 0x14 */ + UINT32 PaCntl; /* 0x18 */ +#define BCM3450_PACNTL_PA_RDEG_SHIFT 11 +#define BCM3450_PACNTL_PA_RDEG_MASK 0x00007800 +#define BCM3450_PACNTL_PA_CURR_CONT_SHIFT 5 +#define BCM3450_PACNTL_PA_CURR_CONT_MASK 0x000007E0 +#define BCM3450_PACNTL_PA_CURR_FOLLOWER_SHIFT 2 +#define BCM3450_PACNTL_PA_CURR_FOLLOWER_MASK 0x0000001C +#define BCM3450_PACNTL_PA_PWRDWN_SHIFT 0 +#define BCM3450_PACNTL_PA_PWRDWN_MASK 0x00000001 +#define BCM3450_PACNTL_OFFSET 0x18 + UINT32 Misc; /* 0x1c */ +#define BCM3452_MISC_BG_PWRDWN_SHIFT 15 +#define BCM3452_MISC_BG_PWRDWN_MASK 0x00008000 +#define BCM3450_MISC_IIC_RESET 0x1 +#define BCM3450_MISC_SERIAL_RESET 0x2 +#define BCM3450_MISC_OFFSET 0x1c +} Bcm3450Reg ; + +#endif /* _MoCABLOCK_H_ */ diff --git a/shared/broadcom/include/bcm963xx/robosw_reg.h b/shared/broadcom/include/bcm963xx/robosw_reg.h new file mode 100755 index 0000000..4fcc0ac --- /dev/null +++ b/shared/broadcom/include/bcm963xx/robosw_reg.h @@ -0,0 +1,169 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ + +#ifndef __ROBOSW_REG_H +#define __ROBOSW_REG_H + +void robosw_init(void); +void robosw_configure_ports(void); +void robosw_check_ports(void); + +// These macros make offset validation vs. data sheet easier. + +#define group(type, name, start_offset, next) type name[(next - start_offset) / sizeof(type)] +#define entry(type, name, start_offset, next) type name + +typedef struct RoboSwitch { + group(byte, PortCtrl, 0x0000, 0x0009); + group(byte, Reserved0009, 0x0009, 0x000b); + entry(byte, SwitchMode, 0x000b, 0x000c); + entry(uint16, PauseQuanta, 0x000c, 0x000e); + entry(byte, ImpOverride, 0x000e, 0x000f); + entry(byte, LedRefresh, 0x000f, 0x0010); + entry(uint16, LedFunc0, 0x0010, 0x0012); + entry(uint16, LedFunc1, 0x0012, 0x0014); + entry(uint16, LedFuncMap, 0x0014, 0x0016); + entry(uint16, LedEnableMap, 0x0016, 0x0018); + entry(uint16, LedMap0, 0x0018, 0x001a); + entry(uint16, LedMap1, 0x001a, 0x001c); + group(byte, Reserved001c, 0x001c, 0x0020); + group(byte, Reserved0020, 0x0020, 0x0021); + entry(byte, ForwardCtrl, 0x0021, 0x0022); + group(byte, Reserved0022, 0x0022, 0x0024); + entry(uint16, ProtSelect, 0x0024, 0x0026); + entry(uint16, WanSelect, 0x0026, 0x0028); + entry(uint32, PauseCap, 0x0028, 0x002c); + group(byte, Reserved002c, 0x002c, 0x002f); + entry(byte, MultiCtrl, 0x002f, 0x0030); + group(byte, Reserved0030, 0x0030, 0x0031); + entry(byte, TxqFlush, 0x0031, 0x0032); + entry(uint16, UniFail, 0x0032, 0x0034); + entry(uint16, MultiFail, 0x0034, 0x0036); + entry(uint16, MlfIpmc, 0x0036, 0x0038); + entry(uint16, PausePassRx, 0x0038, 0x003a); + entry(uint16, PausePassTx, 0x003a, 0x003c); + entry(uint16, DisableLearn, 0x003c, 0x003e); + group(byte, Reserved003e, 0x003e, 0x004a); + entry(uint16, PllTest, 0x004a, 0x004c); + group(byte, Reserved004c, 0x004c, 0x0058); + group(byte, PortOverride, 0x0058, 0x0060); + group(byte, Reserved0061, 0x0060, 0x0064); + entry(byte, ImpRgmiiCtrlP4, 0x0064, 0x0065); + entry(byte, ImpRgmiiCtrlP5, 0x0065, 0x0066); + group(byte, Reserved0066, 0x0066, 0x006c); + entry(byte, ImpRgmiiTimingDelayP4, 0x006c, 0x006d); + entry(byte, ImpRgmiiTimingDelayP5, 0x006d, 0x006e); + group(byte, Reserved006e, 0x006e, 0x0079); + entry(byte, SWResetCtrl, 0x0079, 0x007a); + group(byte, Reserved007a, 0x007a, 0x0090); + entry(uint32, Rxfilt_Ctl, 0x0090, 0x0094); + entry(uint32, Cmf_En_Ctl, 0x0094, 0x0098); + group(byte, Reserved0098, 0x0098, 0x00a0); + entry(uint32, SwpktCtrl0, 0x00a0, 0x00a4); + entry(uint32, SwpktCtrl1, 0x00a4, 0x00a8); + group(byte, Reserved00a8, 0x00a8, 0x00b0); + entry(uint32, MdioCtrl, 0x00b0, 0x00b4); + entry(uint16, MdioData, 0x00b4, 0x00b6); + group(byte, Reserved00b4, 0x00b6, 0x0200); + entry(byte, GlbMgmt, 0x0200, 0x0201); + entry(byte, ChpBoxID, 0x0201, 0x0202); + entry(byte, MngPID, 0x0202, 0x0203); + group(byte, Reserved0203, 0x0203, 0x1100); + entry(uint16, MIICtrl0, 0x1100, 0x1101); + +} RoboSwitch; + +#define SWITCH ((volatile RoboSwitch * const)SWITCH_BASE) +#define PBVLAN_OFFSET 0x3100 +#define PBMAP_MIPS 0x100 +#define SWITCH_PBVLAN ((volatile uint16 * const)(SWITCH_BASE + PBVLAN_OFFSET)) + +#define PortCtrl_Forwarding 0xa0 +#define PortCtrl_Learning 0x80 +#define PortCtrl_Listening 0x60 +#define PortCtrl_Blocking 0x40 +#define PortCtrl_Disable 0x20 +#define PortCtrl_RxUcstEn 0x10 +#define PortCtrl_RxMcstEn 0x08 +#define PortCtrl_RxBcstEn 0x04 +#define PortCtrl_DisableTx 0x02 +#define PortCtrl_DisableRx 0x01 + +#define SwitchMode_FwdgEn 0x02 +#define SwitchMode_ManageMode 0x01 + +#define ImpOverride_Force 0x80 +#define ImpOverride_TxFlow 0x20 +#define ImpOverrode_RxFlow 0x10 +#define ImpOverride_1000Mbs 0x08 +#define ImpOverride_100Mbs 0x04 +#define ImpOverride_10Mbs 0x00 +#define ImpOverride_Fdx 0x02 +#define ImpOverride_Linkup 0x01 + +#define PortOverride_Enable 0x40 +#define PortOverride_TxFlow 0x20 +#define PortOverride_RxFlow 0x10 +#define PortOverride_1000Mbs 0x08 +#define PortOverride_100Mbs 0x04 +#define PortOverride_10Mbs 0x00 +#define PortOverride_Fdx 0x02 +#define PortOverride_Linkup 0x01 + +#define GlbMgmt_EnableImp 0x80 +#define GlbMgmt_IgmpSnooping 0x08 +#define GlbMgmt_ReceiveBpdu 0x02 +#define GlbMgmt_ResetMib 0x01 + +#define MdioCtrl_Write (1 << 31) +#define MdioCtrl_Read (1 << 30) +#define MdioCtrl_Ext (1 << 16) +#define MdioCtrl_ID_Shift 25 +#define MdioCtrl_ID_Mask (0x1f << MdioCtrl_ID_Shift) +#define MdioCtrl_Addr_Shift 20 +#define MdioCtrl_Addr_Mask (0x1f << MdioCtrl_Addr_Shift) + +#define ImpRgmiiCtrl_GMII_En 0x80 +#define ImpRgmiiCtrl_DLL_IQQD 0x04 +#define ImpRgmiiCtrl_DLL_RXC_Bypass 0x02 +#define ImpRgmiiCtrl_Timing_Sel 0x01 + +#define ImpRgmiiTimingDelayDefault 0xF9 + +#if defined (_BCM96328_) +#define EPHY_PORTS 5 +#define PORT_6_PORT_ID 6 +#define PORT_7_PORT_ID 7 +#endif +#if defined (_BCM96362_) +#define EPHY_PORTS 6 +#define PORT_6_PORT_ID 6 +#define PORT_7_PORT_ID 7 +#endif +#if defined (_BCM96368_) +#define EPHY_PORTS 6 +#define USB_PORT_ID 6 +#define SAR_PORT_ID 7 +#endif +#if defined (_BCM96816_) +#define EPHY_PORTS 4 +#define SERDES_PORT_ID 4 +#define MOCA_PORT_ID 5 +#define USB_PORT_ID 6 +#define GPON_PORT_ID 7 +#endif + +#endif diff --git a/shared/broadcom/include/bcm963xx/xtmprocregs.h b/shared/broadcom/include/bcm963xx/xtmprocregs.h new file mode 100755 index 0000000..307ed79 --- /dev/null +++ b/shared/broadcom/include/bcm963xx/xtmprocregs.h @@ -0,0 +1,602 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 5300 California Avenue + Irvine, California 92617 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/*************************************************************************** + * File Name : XtmProcRegs.h + * + * Description: This file contains definitions for the ATM/PTM processor + * registers. + ***************************************************************************/ + +#if !defined(_XTMPROCREGS_H_) +#define _XTMPROCREGS_H_ + +/* Miscellaneous values. */ +#define XP_MAX_PORTS 4 +#define XP_MAX_CONNS 16 +#define XP_MAX_RX_QUEUES 4 +#define XP_MAX_TX_HDRS 8 +#define XP_TX_HDR_WORDS (16 / sizeof(UINT32)) +#define XP_RX_MIB_MATCH_ENTRIES 128 + +/* Circuit types. */ +#define XCT_TRANSPARENT 0x00000001 +#define XCT_AAL0_PKT 0x00000002 +#define XCT_AAL0_CELL 0x00000003 +#define XCT_OAM_F5_SEG 0x00000004 +#define XCT_OAM_F5_E2E 0x00000005 +#define XCT_RM 0x00000006 +#define XCT_AAL5 0x00000007 +#define XCT_ASM_P0 0x00000008 +#define XCT_ASM_P1 0x00000009 +#define XCT_ASM_P2 0x0000000a +#define XCT_ASM_P3 0x0000000b +#define XCT_OAM_F4_SEG 0x0000000c +#define XCT_OAM_F4_E2E 0x0000000d +#define XCT_TEQ 0x0000000e +#define XCT_PTM 0x0000000f + +/* Definitions for ATM ulTxChannelCfg. */ +#define TXCHA_VCID_MASK 0x0000000f +#define TXCHA_VCID_SHIFT 0 +#define TXCHA_CT_MASK 0x000000f0 +#define TXCHA_CT_SHIFT 4 +#define TXCHA_CT_TRANSPARENT (XCT_TRANSPARENT << TXCHA_CT_SHIFT) +#define TXCHA_CT_AAL0_PKT (XCT_AAL0_PKT << TXCHA_CT_SHIFT) +#define TXCHA_CT_AAL0_CELL (XCT_AAL0_CELL << TXCHA_CT_SHIFT) +#define TXCHA_CT_OAM_F5_SEG (XCT_OAM_F5_SEG << TXCHA_CT_SHIFT) +#define TXCHA_CT_OAM_F5_E2E (XCT_OAM_F5_E2E << TXCHA_CT_SHIFT) +#define TXCHA_CT_RM (XCT_RM << TXCHA_CT_SHIFT) +#define TXCHA_CT_AAL5 (XCT_AAL5 << TXCHA_CT_SHIFT) +#define TXCHA_CT_ASM_P0 (XCT_ASM_P0 << TXCHA_CT_SHIFT) +#define TXCHA_CT_ASM_P1 (XCT_ASM_P1 << TXCHA_CT_SHIFT) +#define TXCHA_CT_ASM_P2 (XCT_ASM_P2 << TXCHA_CT_SHIFT) +#define TXCHA_CT_ASM_P3 (XCT_ASM_P3 << TXCHA_CT_SHIFT) +#define TXCHA_CT_OAM_F4_SEG (XCT_OAM_F4_SEG << TXCHA_CT_SHIFT) +#define TXCHA_CT_OAM_F4_E2E (XCT_OAM_F4_E2E << TXCHA_CT_SHIFT) +#define TXCHA_CT_TEQ (XCT_TEQ << TXCHA_CT_SHIFT) +#define TXCHA_CT_PTM (XCT_PTM << TXCHA_CT_SHIFT) +#define TXCHA_CI 0x00000100 +#define TXCHA_CLP 0x00000200 +#define TXCHA_USE_ALT_GFC 0x00000400 +#define TXCHA_ALT_GFC_MASK 0x00007800 +#define TXCHA_ALT_GFC_SHIFT 11 +#define TXCHA_HDR_EN 0x00008000 +#define TXCHA_HDR_IDX_MASK 0x00070000 +#define TXCHA_HDR_IDX_SHIFT 16 +#define TXCHA_FCS_STRIP 0x00080000 + +/* Definitions for PTM ulTxChannelCfg. */ +#define TXCHP_FCS_EN 0x00000001 +#define TXCHP_CRC_EN 0x00000002 +#define TXCHP_HDR_EN 0x00008000 +#define TXCHP_HDR_IDX_MASK 0x00070000 +#define TXCHP_HDR_IDX_SHIFT 16 + +/* Definitions for ulSwitchPktCfg. */ +#define SWP_MAX_PKT_COUNT_MASK 0x00000003 +#define SWP_MAX_PKT_COUNT_SHIFT 0 +#define SWP_MAX_PKT_SIZE_MASK 0x0000007c +#define SWP_MAX_PKT_SIZE_SHIFT 2 +#define SWP_SRC_ID_MASK 0x00000380 +#define SWP_SRC_ID_SHIFT 7 +#define SWP_RX_CHAN_MASK 0x00000c00 +#define SWP_RX_CHAN_SHIFT 10 +#define SWP_TX_CHAN_MASK 0x0000f000 +#define SWP_TX_CHAN_SHIFT 12 +#define SWP_TX_EN 0x00010000 +#define SWP_RX_EN 0x00020000 + +/* Definitions for ulSwitchPktTxCtrl. */ +#define SWP_VCID_VALUE_MASK 0x0000000f +#define SWP_VCID_VALUE_SHIFT 0 +#define SWP_CT_VALUE_MASK 0x000000f0 +#define SWP_CT_VALUE_SHIFT 4 +#define SWP_FSTAT_CFG_VALUE_MASK 0x00000700 +#define SWP_FSTAT_CFG_VALUE_SHIFT 8 +#define SWP_MUX_MODE_VALUE 0x00000800 +#define SWP_VCID_MASK_MASK 0x000f0000 +#define SWP_VCID_MASK_SHIFT 16 +#define SWP_CT_MASK_MASK 0x00f00000 +#define SWP_CT_MASK_SHIFT 20 +#define SWP_FSTAT_CFG_MASK_MASK 0x07000000 +#define SWP_FSTAT_CFG_MASK_SHIFT 24 +#define SWP_MUX_MODE_MASK 0x08000000 + +/* Definitions for ulSwitchPktRxCtrl. */ +#define SWP_MATCH_MASK 0x0000007f +#define SWP_MASK_SHIFT 0 +#define SWP_CRC32 0x00000080 +#define SWP_DEST_PORT_MASK 0x0000ff00 +#define SWP_DEST_PORT_SHIFT 8 +#define SWP_MUX_MATCH_MASK 0x007f0000 +#define SWP_MUX_MATCH_SHIFT 16 +#define SWP_MUX_CRC32 0x00800000 +#define SWP_MUX_DESTPORT_MASK 0xff000000 +#define SWP_MUX_DESTPORT_SHIFT 24 + +/* Definitions for ulPktModCtrl. */ +#define PKTM_RXQ_EN_MASK 0x0000000f +#define PKTM_RXQ_EN_SHIFT 0 +#define PKTM_EN 0x80000000 + +/* Definitions for ulIrqStatus and ulIrqMask. */ +#define INTR_RX_BUF_EMPTY 0x00000001 +#define INTR_TX_BUF_EMPTY 0x00000002 +#define INTR_RX_DMA_NO_DESC_MASK 0x0000003c +#define INTR_RX_DMA_NO_DESC_SHIFT 2 +#define INTR_PTM_FRAG_ERROR 0x00000040 +#define INTR_PKT_BUF_UNDERFLOW 0x00000080 +#define INTR_TX_DMA_UNDERFLOW 0x00000100 +#define INTR_TX_ATM_DC 0x00000200 +#define INTR_BOND_BUF_FULL 0x00000400 +#define INTR_RX_ATM_DC 0x00000800 +#define INTR_MULT_MATCH_ERROR 0x00001000 +#define INTR_PKT_BUF_IRQ_MASK 0x0000e000 +#define INTR_PKT_BUF_IRQ_SHIFT 13 + +/* Definitions for ulTxSarCfg. */ +#define TXSAR_MODE_ATM 0x00000000 +#define TXSAR_MODE_PTM 0x00000001 +#define TXSARA_BOND_EN 0x00000002 +#define TXSARA_SID12_EN 0x00000004 +#define TXSARA_CRC10_INIT 0x00000008 +#define TXSARA_CRC10_EN_MASK 0x000000f0 +#define TXSARA_CRC10_EN_SHIFT 4 +#define TXSARA_BOND_DUAL_LATENCY 0x00000100 +#define TXSAR_USE_ALT_FSTAT 0x00000200 +#define TXSARP_ENET_FCS_INSERT 0x00000400 +#define TXSARP_CRC16_EN 0x00000800 +#define TXSARP_SOF_WHILE_TX 0x00001000 +#define TXSARP_PREEMPT 0x00002000 +#define TXSAR_HDR_INS_OFFSET_MASK 0x0007c000 +#define TXSAR_HDR_INS_OFFSET_SHIFT 14 +#define TXSARP_NUM_Z_BYTES_MASK 0x00780000 +#define TXSARP_NUM_Z_BYTES_SHIFT 19 +#define TXSAR_SW_EN 0x00800000 +#define TXSAR_USE_THRESH 0x01000000 +#define TXSAR_PKT_THRESH_MASK 0x06000000 +#define TXSAR_PKT_THRESH_SHIFT 25 +#define TXSARA_BOND_PORT_DIS_MASK 0x78000000 +#define TXSARA_BOND_PORT_DIS_SHIFT 27 +#define TXSARA_ASM_CRC_DIS 0x80000000 + +/* Definitions for ulTxSchedCfg. */ +#define TXSCH_PORT_EN_MASK 0x0000000f +#define TXSCH_PORT_EN_SHIFT 0 +#define TXSCHA_ALT_SHAPER_MODE 0x00000010 +#define TXSCHP_FAST_SCHED 0x00000020 +#define TXSCH_SHAPER_RESET 0x00000040 +#define TXSCH_SIT_COUNT_EN 0x00000080 +#define TXSCH_SIT_COUNT_VALUE_MASK 0x00ffff00 +#define TXSCH_SIT_COUNT_VALUE_SHIFT 8 +#define TXSCH_SIT_MAX_VALUE (TXSCH_SIT_COUNT_VALUE_MASK >> \ + TXSCH_SIT_COUNT_VALUE_SHIFT) +#define TXSCH_SOFWT_PRIORITY_EN 0x01000000 +#define TXSCH_BASE_COUNT_EN 0x02000000 +#define TXSCH_BASE_COUNT_VALUE_MASK 0x3c000000 +#define TXSCH_BASE_COUNT_VALUE_SHIFT 26 +#define TXSCHP_USE_BIT4_SOF 0x40000000 +#define TXSCH_ALT_MCR_MODE 0x80000000 + +/* Definitions for ulTxOamCfg. */ +#define TXOAM_F4_SEG_VPI_MASK 0x000000ff +#define TXOAM_F4_SEG_VPI_SHIFT 0 +#define TXOAM_F4_E2E_VPI_MASK 0x0000ff00 +#define TXOAM_F4_E2E_VPI_SHIFT 8 +#define TXASM_VCI_MASK 0xffff0000 +#define TXASM_VCI_SHIFT 16 + +/* Definitions for ulTxMpAalCfg. */ +#define TXMP_NUM_GROUPS 4 +#define TXMP_GROUP_SIZE 5 +#define TXMP_GROUP_EN 0x00000001 +#define TXMP_GROUP_SHAPER_MASK 0x0000001e +#define TXMP_GROUP_SHAPER_SHIFT 1 +#define TXSOPWT_COUNT_EN 0x00100000 +#define TXSOPWT_COUNT_VALUE_MASK 0x07e00000 +#define TXSOPWT_COUNT_VALUE_SHIFT 21 + +/* Definitions for ulTxUtopiaCfg. */ +#define TXUTO_PORT_EN_MASK 0x0000000f +#define TXUTO_PORT_EN_SHIFT 0 +#define TXUTO_MODE_INT_EXT_MASK 0x00000030 +#define TXUTO_MODE_ALL_INT 0x00000000 +#define TXUTO_MODE_ALL_EXT 0x00000010 +#define TXUTO_MODE_INT_EXT 0x00000020 +#define TXUTO_CELL_FIFO_DEPTH_2 0x00000000 +#define TXUTO_CELL_FIFO_DEPTH_1 0x00000040 +#define TXUTO_NEG_EDGE 0x00000080 +#define TXUTO_LEVEL_1 0x00000100 + +/* Definitions for ulTxLineRateTimer. */ +#define TXLRT_EN 0x00000001 +#define TXLRT_COUNT_VALUE_MASK 0x0001fffe +#define TXLRT_COUNT_VALUE_SHIFT 1 +#define TXLRT_MAX_VALUE (TXLRT_COUNT_VALUE_MASK >> \ + TXLRT_COUNT_VALUE_SHIFT) +#define TXLRT_IDLE_CELL_INS_MASK 0xf0000000 +#define TXLRT_IDLE_CELL_INS_SHIFT 28 + +/* Definitions for ulRxAtmCfg. */ +#define RX_PORT_EN 0x00000001 +#define RX_DOE_MASK 0x000001fe +#define RX_DOE_SHIFT 1 +#define RX_DOE_GFC_ERROR 0x00000002 +#define RX_DOE_CRC_ERROR 0x00000004 +#define RX_DOE_CT_ERROR 0x00000008 +#define RX_DOE_CAM_LOOKUP_ERROR 0x00000010 +#define RX_DOE_IDLE_CELL 0x00000020 +#define RX_DOE_PTI_ERROR 0x00000040 +#define RX_DOE_HEC_ERROR 0x00000080 +#define RX_DOE_PORT_NOT_ENABLED_ERROR 0x00000100 +#define RXA_HEC_CRC_IGNORE 0x00000200 +#define RXA_GFC_ERROR_IGNORE 0x00000400 +#define RX_PORT_MASK 0x00001800 +#define RX_PORT_MASK_SHIFT 11 +#define RXP_RX_FLOW_DISABLED 0x00004000 +#define RXA_VCI_MASK 0x00008000 +#define RXA_VC_BIT_MASK 0xffff0000 +#define RXA_BONDING_VP_MASK 0x00ff0000 + +/* Definitions for ulRxSarCfg. */ +#define RXSAR_MODE_ATM 0x00000000 +#define RXSAR_MODE_PTM 0x00000001 +#define RXSAR_MODE_MASK 0x00000001 +#define RXSARA_BOND_EN 0x00000002 +#define RXSARA_SID12_EN 0x00000004 +#define RXSARA_CRC10_INIT 0x00000008 +#define RXSARA_CRC10_EN_MASK 0x000000f0 +#define RXSARA_CRC10_EN_SHIFT 4 +#define RXSARA_BOND_DUAL_LATENCY 0x00000100 +#define RXSARA_BOND_CELL_COUNT_MASK 0x07ff0000 +#define RXSARA_BOND_CELL_COUNT_SHIFT 16 +#define RXSARA_BOND_TIMER_MODE 0x08000000 +#define RXSARA_BOND_BUF_MODE_MASK 0x70000000 +#define RXSARA_BOND_BUF_MODE_SHIFT 29 +#define RXSARA_BOND_BUF_MODE_MASK 0x70000000 +#define RXSARA_ASM_CRC_DIS 0x80000000 + +/* Definitions for ulRxOamCfg. */ +#define RXOAM_F4_SEG_VPI_MASK 0x000000ff +#define RXOAM_F4_SEG_VPI_SHIFT 0 +#define RXOAM_F4_E2E_VPI_MASK 0x0000ff00 +#define RXOAM_F4_E2E_VPI_SHIFT 8 +#define RXASM_VCI_MASK 0xffff0000 +#define RXASM_VCI_SHIFT 16 + +/* Definitions for ulRxUtopiaCfg. */ +#define RXUTO_PORT_EN_MASK 0x0000000f +#define RXUTO_PORT_EN_SHIFT 0 +#define RXUTO_TEQ_PORT_MASK 0x00000070 +#define RXUTO_TEQ_PORT_SHIFT 4 +#define RXUTO_NEG_EDGE 0x00000080 +#define RXUTO_LEVEL_1 0x00000100 +#define RXUTO_INTERNAL_BUF0_EN 0x00000200 +#define RXUTO_EXTERNAL_BUF1_EN 0x00000400 + +/* Definitions for ulRxAalCfg. */ +#define RXAALA_AAL5_SW_TRAILER_EN 0x00000001 +#define RXAALA_AAL0_CRC_CHECK 0x00000002 +#define RXAALP_CRC32_EN 0x00000004 +#define RXAALP_CELL_LENGTH_MASK 0x000000f0 +#define RXAALP_CELL_LENGTH_SHIFT 4 + +/* Definitions for ulLedCtrl. */ +#define SAR_LED_EN 0x00000001 +#define SAR_LED_MODE_MASK 0x00000006 +#define SAR_LED_MODE_SHIFT 1 +#define SAR_LED_MODE_LINK_ONLY 0x00000000 +#define SAR_LED_MODE_CELL_ACTIVITY 0x00000002 +#define SAR_LED_MODE_MELODY_LINK 0x00000004 +#define SAR_LED_MODE_LINK_CELL_ACTIVITY 0x00000006 +#define SAR_LED_LINK 0x00000010 +#define SAR_LED_SPEED_MASK 0x00000060 +#define SAR_LED_SPEED_SHIFT 5 +#define SAR_LED_SPEED_30MS 0x00000000 +#define SAR_LED_SPEED_50MS 0x00000020 +#define SAR_LED_SPEED_125MS 0x00000040 +#define SAR_LED_SPEED_250MS 0x00000060 +#define SAR_LED_INTERNAL 0x00000080 + +/* Definitions for ulTxVpiVciTable. */ +#define TXTBL_VCI_MASK 0x0000ffff +#define TXTBL_VCI_SHIFT 0 +#define TXTBL_VPI_MASK 0x00ff0000 +#define TXTBL_VPI_SHIFT 16 + +/* Definitions for ulRxVpiVciCam - CAM side. */ +#define RXCAM_PORT_MASK 0x00000003 +#define RXCAM_PORT_SHIFT 0 +#define RXCAMP_PTM_PRI_LOW 0x00000000 +#define RXCAMP_PTM_PRI_HIGH 0x00000004 +#define RXCAM_TEQ_CELL 0x00000008 +#define RXCAMA_VCI_MASK 0x000ffff0 +#define RXCAMA_VCI_SHIFT 4 +#define RXCAMA_VPI_MASK 0x0ff00000 +#define RXCAMA_VPI_SHIFT 20 +#define RXCAM_VALID 0x10000000 + +/* Definitions for ulRxVpiVciCam - RAM side. */ +#define RXCAM_CT_MASK 0x0000000f +#define RXCAM_CT_SHIFT 0 +#define RXCAM_CT_TRANSPARENT (XCT_TRANSPARENT << RXCAM_CT_SHIFT) +#define RXCAM_CT_AAL0_PKT (XCT_AAL0_PKT << RXCAM_CT_SHIFT) +#define RXCAM_CT_AAL0_CELL (XCT_AAL0_CELL << RXCAM_CT_SHIFT) +#define RXCAM_CT_AAL5 (XCT_AAL5 << RXCAM_CT_SHIFT) +#define RXCAM_CT_TEQ (XCT_TEQ << RXCAM_CT_SHIFT) +#define RXCAM_CT_PTM (XCT_PTM << RXCAM_CT_SHIFT) +#define RXCAM_VCID_MASK 0x000001f0 +#define RXCAM_VCID_SHIFT 4 +#define RXCAM_STRIP_BYTE_MASK 0x00003e00 +#define RXCAM_STRIP_BYTE_SHIFT 9 +#define RXCAM_STRIP_EN 0x00004000 +#define RXCAMA_ASM_CELL 0x00080000 +#define RXCAMA_CRC10_EN 0x00100000 + +/* Definitions for ulSstCtrl. */ +#define SST_EN 0x00000001 +#define SST_MP_GROUP_MASK 0x00000006 +#define SST_MP_GROUP_SHIFT 1 +#define SST_PTM_PREEMPT 0x00000010 +#define SST_PORT_MASK 0x00000060 +#define SST_PORT_SHIFT 5 +#define SST_ALG_MASK 0x00000380 +#define SST_ALG_SHIFT 7 +#define SST_ALG_UBR_NO_PCR 0x00000000 +#define SST_ALG_UBR_PCR 0x00000080 +#define SST_ALG_MBR 0x00000100 +#define SST_ALG_VBR_1 0x00000180 +#define SST_ALG_CBR 0x00000200 +#define SST_SUB_PRIORITY_MASK 0x00001c00 +#define SST_SUB_PRIORITY_SHIFT 10 +#define SST_SUPER_PRIORITY 0x00002000 +#define SST_MP_EN 0x00004000 +#define SST_MCR_EN 0x00008000 +#define SST_RATE_MCR_MASK 0xffff0000 +#define SST_RATE_MCR_SHIFT 16 + +/* Definitions for ulSstPcrScr. */ +#define SST_RATE_PCR_MASK 0x0000ffff +#define SST_RATE_PCR_SHIFT 0 +#define SST_RATE_SCR_MASK 0xffff0000 +#define SST_RATE_SCR_SHIFT 16 + +/* Definitions for ulSstBt. */ +#define SST_RATE_BT_MASK 0x00ffffff +#define SST_RATE_BT_SHIFT 0 +#define SST_ALG_WEIGHT_MASK 0x03000000 +#define SST_ALG_WEIGHT_SHIFT 24 +#define SST_ALG_DISABLED 0x00000000 +#define SST_ALG_CWRR 0x01000000 +#define SST_ALG_PWRR 0x02000000 +#define SST_ALG_WFQ 0x03000000 +#define SST_WEIGHT_VALUE_MASK 0xfc000000 +#define SST_WEIGHT_VALUE_SHIFT 26 + +/* Definitions for ulSstBucketCnt. */ +#define SST_BP_PCR_MASK 0x0000ffff +#define SST_BP_PCR_SHIFT 0 +#define SST_BM_MCR_MASK 0xffff0000 +#define SST_BM_MCR_SHIFT 16 + +/* Definitions for ulRxPktBufCfg. */ +#define PBCFG_LENGTH_MASK 0x0000ffff +#define PBCFG_LENGTH_SHIFT 0 +#define PBCFG_FPM_EMPTY 0x02000000 +#define PBCFG_LD_PTRS 0x04000000 +#define PBCFG_ALLOCATE_LAST 0x08000000 +#define PBCFG_KEEP_ERROR_PKTS 0x10000000 +#define PBCFG_FPM_ENABLE 0x20000000 +#define PBCFG_INIT_REQ 0x40000000 +#define PBCFG_S_RESET 0x80000000 + +/* Definitions for ulRxPktBufThreshold. */ +#define PBTHRESH_MAX_COUNT_MASK 0x000000ff +#define PBTHRESH_MAX_COUNT_SHIFT 0 +#define PBTHRESH_NO_BUF_DELAY_MASK 0xffff0000 +#define PBTHRESH_NO_BUF_DELAY_SHIFT 16 + +/* Definitions for ulRxPktBufVcid. */ +#define PBVCID_WAIT_EN_MASK 0x0000ffff +#define PBVCID_WAIT_EN_SHIFT 0 + +/* Definitions for ulRxPktBufMem. */ +#define PBMEM_ADDR_MASK 0x0000ffff +#define PBMEM_ADDR_SHIFT 0 +#define PBMEM_BS_B_MASK 0x00ff0000 +#define PBMEM_BS_B_SHIFT 16 +#define PBMEM_READ_WRITE_B 0x40000000 +#define PBMEM_GO_BUSY 0x80000000 + +/* Definitions for ulRxPktBufPtr. */ +#define PBPTR_BUF_STOP_MASK 0x0000ffff +#define PBPTR_BUF_STOP_SHIFT 0 +#define PBPTR_BUF_START_MASK 0xffff0000 +#define PBPTR_BUF_START_SHIFT 16 + +/* Definitions for ulRxPktBufSize. */ +#define PBSIZE_THRESHOLD_MASK 0x0000ffff +#define PBSIZE_THRESHOLD_SHIFT 0 +#define PBSIZE_MASK 0xffff0000 +#define PBSIZE_SHIFT 16 + +/* Definitions for ulRxPktBufFifoStart[2]. */ +#define PBSTART_0_MASK 0x0000ffff +#define PBSTART_0_SHIFT 0 +#define PBSTART_1_MASK 0xffff0000 +#define PBSTART_1_SHIFT 16 + +/* Definitions for ulRxPktBufFifoStop[2]. */ +#define PBSTOP_0_MASK 0x0000ffff +#define PBSTOP_0_SHIFT 0 +#define PBSTOP_1_MASK 0xffff0000 +#define PBSTOP_1_SHIFT 16 + +/* Definitions for ulRxPktBufFifoDelay[2]. */ +#define PBDELAY_0_MASK 0x0000ffff +#define PBDELAY_0_SHIFT 0 +#define PBDELAY_1_MASK 0xffff0000 +#define PBDELAY_1_SHIFT 16 + +/* Definitions for ulRxPktBufQueueStatus. */ +#define PBQS_NUM_NO_BUFS_MASK 0x0000ffff +#define PBQS_NUM_NO_BUFS_SHIFT 0 +#define PBQS_NUM_QUEUE_FULL_MASK 0xffff0000 +#define PBQS_NUM_QUEUE_FULL_SHIFT 16 + +/* Definitions for ulRxPktBufErrorStatus. */ +#define PBERR_NUM_ERROR_FRAGS_MASK 0x0000ffff +#define PBERR_NUM_ERROR_FRAGS_SHIFT 0 +#define PBERR_NUM_ERROR_PKTS_MASK 0xffff0000 +#define PBERR_NUM_ERROR_PKTS_SHIFT 16 + +/* Definitions for ulRxPktBufTR. */ +#define PBTR_LD_T_PTR_MASK 0x0000ffff +#define PBTR_LD_T_PTR_SHIFT 0 +#define PBTR_LD_H_PTR_MASK 0xffff0000 +#define PBTR_LD_H_PTR_SHIFT 16 + +/* Definitions for ulRxPktBufFPM. */ +#define PBFPM_FRAME_BUF_MASK 0x0000ffff +#define PBFPM_FRAME_BUF_SHIFT 0 +#define PBFPM_LOAD_COUNT_MASK 0xffff0000 +#define PBFPM_LOAD_COUNT_SHIFT 16 + +/* Definitions for ulRxPktBufMibCtrl. */ +#define PBMIB_TOGGLE 0x40000000 +#define PBMIB_CLEAR 0x80000000 + +/* Definitions for ulRxPktBufMibMatch. */ +#define PBMIB_MATCH_MASK 0x0000007f + +/* Definitions for ulTxHdrInsert. */ +#define TXHDR_COUNT_MASK 0x0000001f +#define TXHDR_COUNT_SHIFT 0 +#define TXHDR_OFFSET_MASK 0x00ff0000 +#define TXHDR_OFFSET_SHIFT 16 + +/* Definitions for ulTxRxPortOamCellCnt. */ +#define OAM_TX_CELL_COUNT_MASK 0x0000ffff +#define OAM_TX_CELL_COUNT_SHIFT 0 +#define OAM_RX_CELL_COUNT_MASK 0xffff0000 +#define OAM_RX_CELL_COUNT_SHIFT 16 + +/* Definitions for ulTxRxPortAsmCellCnt. */ +#define ASM_TX_CELL_COUNT_MASK 0x0000ffff +#define ASM_TX_CELL_COUNT_SHIFT 0 +#define ASM_RX_CELL_COUNT_MASK 0xffff0000 +#define ASM_RX_CELL_COUNT_SHIFT 16 + +/* Definitions for ulRxPortErrorPktCellCnt. */ +#define ERROR_RX_CELL_COUNT_MASK 0x0000ffff +#define ERROR_RX_CELL_COUNT_SHIFT 0 +#define ERROR_RX_PKT_COUNT_MASK 0xffff0000 +#define ERROR_RX_PKT_COUNT_SHIFT 16 + + +#if defined(CONFIG_BCM96368) +#define XTM_PROCESSOR_BASE 0xb0001800 +#elif defined(CONFIG_BCM96328) || defined(CONFIG_BCM96362) +#define XTM_PROCESSOR_BASE 0xb0007800 +#endif +typedef struct XtmProcessorRegisters +{ + UINT32 ulTxChannelCfg[XP_MAX_CONNS]; /* 0000 */ + UINT32 ulSwitchPktCfg; /* 0040 */ + UINT32 ulSwitchPktTxCtrl; /* 0044 */ + UINT32 ulSwitchPktRxCtrl; /* 0048 */ + UINT32 ulPktModCtrl; /* 004c */ + UINT32 ulIrqStatus; /* 0050 */ + UINT32 ulIrqMask; /* 0054 */ + UINT32 ulReserved1[2]; /* 0058 */ + UINT32 ulTxSarCfg; /* 0060 */ + UINT32 ulTxSchedCfg; /* 0064 */ + UINT32 ulTxOamCfg; /* 0068 */ + UINT32 ulTxAtmStatus; /* 006c */ + UINT32 ulTxAalStatus; /* 0070 */ + UINT32 ulTxMpAalCfg; /* 0074 */ + UINT32 ulTxUtopiaCfg; /* 0078 */ + UINT32 ulTxLineRateTimer; /* 007c */ + UINT32 ulRxAtmCfg[XP_MAX_PORTS]; /* 0080 */ + UINT32 ulRxSarCfg; /* 0090 */ + UINT32 ulRxOamCfg; /* 0094 */ + UINT32 ulRxAtmStatus; /* 0098 */ + UINT32 ulRxUtopiaCfg; /* 009c */ + UINT32 ulRxAalCfg; /* 00a0 */ + UINT32 ulRxAalMaxSdu; /* 00a4 */ + UINT32 ulRxAalStatus; /* 00a8 */ + UINT32 ulLedCtrl; /* 00ac */ + UINT32 ulReserved2[20]; /* 00b0 */ + UINT32 ulTxVpiVciTable[XP_MAX_CONNS]; /* 0100 */ + UINT32 ulRxVpiVciCam[XP_MAX_CONNS * 2]; /* 0140 */ + UINT32 ulReserved3[16]; /* 01c0 */ + UINT32 ulSstCtrl[XP_MAX_CONNS]; /* 0200 */ + UINT32 ulSstPcrScr[XP_MAX_CONNS]; /* 0240 */ + UINT32 ulSstBt[XP_MAX_CONNS]; /* 0280 */ + UINT32 ulSstBucketCnt[XP_MAX_CONNS]; /* 02c0 */ + UINT32 ulRxPktBufCfg; /* 0300 */ + UINT32 ulRxPktBufThreshold; /* 0304 */ + UINT32 ulRxPktBufVcid; /* 0308 */ + UINT32 ulRxPktBufMem; /* 030c */ + UINT32 ulRxPktBufData[2]; /* 0310 */ + UINT32 ulRxPktBufPtr; /* 0318 */ + UINT32 ulRxPktBufSize; /* 031c */ + UINT32 ulRxPktBufFifoStart[2]; /* 0320 */ + UINT32 ulRxPktBufFifoStop[2]; /* 0328 */ + UINT32 ulRxPktBufFifoDelay[2]; /* 0330 */ + UINT32 ulRxPktBufQueueStatus; /* 0338 */ + UINT32 ulRxPktBufErrorStatus; /* 033c */ + UINT32 ulRxPktBufTR; /* 0340 */ + UINT32 ulRxPktBufFPM; /* 0344 */ + UINT32 ulRxPktBufMibCtrl; /* 0348 */ + UINT32 ulRxPktBufMibMatch; /* 034c */ + UINT32 ulRxPktBufMibRxOctet; /* 0350 */ + UINT32 ulRxPktBufMibRxPkt; /* 0354 */ + UINT32 ulReserved4[106]; /* 0358 */ + UINT32 ulTxHdrInsert[XP_MAX_TX_HDRS]; /* 0500 */ + UINT32 ulReserved5[24]; /* 0520 */ + UINT32 ulTxHdrValues[XP_MAX_TX_HDRS][XP_TX_HDR_WORDS]; /* 0580 */ + UINT32 ulTxPortPktOctCnt[XP_MAX_PORTS]; /* 0600 */ + UINT32 ulRxPortPktOctCnt[XP_MAX_PORTS]; /* 0610 */ + UINT32 ulTxPortPktCnt[XP_MAX_PORTS]; /* 0620 */ + UINT32 ulRxPortPktCnt[XP_MAX_PORTS]; /* 0630 */ + UINT32 ulTxRxPortOamCellCnt[XP_MAX_PORTS]; /* 0640 */ + UINT32 ulTxRxPortAsmCellCnt[XP_MAX_PORTS]; /* 0650 */ + UINT32 ulRxPortErrorPktCellCnt[XP_MAX_PORTS]; /* 0660 */ + UINT32 ulBondInputCellCnt; /* 0670 */ + UINT32 ulBondOutputCellCnt; /* 0674 */ + UINT32 ulReserved6[1]; /* 0678 */ + UINT32 ulMibCtrl; /* 067c */ + UINT32 ulTxVcPktOctCnt[XP_MAX_CONNS]; /* 0680 */ +} XTM_PROCESSOR_REGISTERS, *PXTM_PROCESSOR_REGISTERS; + +#define XP_REGS ((volatile PXTM_PROCESSOR_REGISTERS const) XTM_PROCESSOR_BASE) + +/* Definitions from pktCmfHw.h. TBD. Use commoon header file. */ +#ifndef PKTCMF_OFFSET_ENGINE_SAR +#define PKTCMF_OFFSET_ENGINE_SAR 0xB0002000 +#endif +#define PKTCMF_OFFSET_RXFILT 0x00001B00 +#define RXFILT_REG_MATCH0_DEF_ID 0x0000000C /* 7b/VCID 03..00 */ +#define RXFILT_REG_MATCH1_DEF_ID 0x00000010 /* 7b/VCID 07..04 */ +#define RXFILT_REG_MATCH2_DEF_ID 0x00000014 /* 7b/VCID 11..08 */ +#define RXFILT_REG_MATCH3_DEF_ID 0x00000018 /* 7b/VCID 15..12 */ + +#define RXFILT_REG_VCID0_QID 0x00000004 /* 2b/VCID 15..00 */ +#define RXFILT_REG_VCID1_QID 0x00000008 /* 2b VCID= 16 */ + +#endif /* _XTMPROCREGS_H_ */ + -- cgit v1.2.3