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| author | root <root@lamia.panaceas.james.local> | 2015-12-19 13:13:57 +0000 |
|---|---|---|
| committer | root <root@lamia.panaceas.james.local> | 2015-12-19 14:18:03 +0000 |
| commit | 1a2238d1bddc823df06f67312d96ccf9de2893cc (patch) | |
| tree | c58a3944d674a667f133ea5a730f5037e57d3d2e /shared | |
| download | bootloader-1a2238d1bddc823df06f67312d96ccf9de2893cc.tar.gz bootloader-1a2238d1bddc823df06f67312d96ccf9de2893cc.tar.bz2 bootloader-1a2238d1bddc823df06f67312d96ccf9de2893cc.zip | |
CFE from danitool [without hostTools dir]: https://mega.nz/#!mwZyFK7a!CPT3BKC8dEw29kubtdYxhB91G9vIIismTkgzQ3iUy3k
Diffstat (limited to 'shared')
49 files changed, 37449 insertions, 0 deletions
diff --git a/shared/broadcom/include/bcm963xx/6328_common.h b/shared/broadcom/include/bcm963xx/6328_common.h new file mode 100755 index 0000000..4d36942 --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6328_common.h @@ -0,0 +1,299 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6328_common.h */ +/* DATE: 02/01/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6328 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6328_MAP_COMMON_H +#define __BCM6328_MAP_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define NAND_INTR_BASE 0xb0000070 /* nand interrupt control registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 +#define NAND_CACHE_BASE 0xb0000400 +#define OTP_BASE 0xb0000600 +#define LED_BASE 0xb0000800 /* LED control registers */ +#define HSSPIM_BASE 0xb0001000 /* High-Speed SPI registers */ +#define MISC_BASE 0xb0001800 /* Miscellaneous Registers */ +#define ADSL_CTRL_BASE 0xb0001900 +#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10002500 /* USB host registers */ +#define USB_OHCI_BASE 0x10002600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0002700 +#define DDR_BASE 0xb0003000 /* Memory control registers */ +#define PCM_BASE 0xb000a000 +#define PCM_DMA_BASE 0xb000a800 /* PCM UIDMA register base */ +#define SAR_DMA_BASE 0xb000b800 /* ATM SAR DMA control registers */ +#define USB_DMA_BASE 0xb000c000 /* USB 2.0 device DMA regiseters */ +#define SWITCH_DMA_BASE 0xb000d800 +#define SWITCH_BASE 0xb0e00000 +#define PCIE_BASE 0xb0e40000 + + +/* +##################################################################### +# System PLL Control Register +##################################################################### +*/ + +/* +##################################################################### +# GPIO Control Registers +##################################################################### +*/ + +/* +##################################################################### +# Miscellaneous Registers +##################################################################### +*/ +#define MISC_MEMC_CONTROL 0x0c +#define MISC_STRAP_BUS 0x240 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 7 + +/* +##################################################################### +# OTP Registers +##################################################################### +*/ +#define OTP_USER_BITS 0x20 +#define OTP_TP1_DISABLE_BIT 9 + +/* +##################################################################### +# Memory Control Registers +##################################################################### +*/ +#define DDR_CTL_CNFG 0x000 +#define DDR_CTL_CSST 0x004 +#define DDR_CTL_CSEND 0x008 +#define DDR_CTL_ROW00_0 0x010 +#define DDR_CTL_ROW00_1 0x014 +#define DDR_CTL_ROW01_0 0x018 +#define DDR_CTL_ROW01_1 0x01c +#define DDR_CTL_ROW20_0 0x030 +#define DDR_CTL_ROW20_1 0x034 +#define DDR_CTL_ROW21_0 0x038 +#define DDR_CTL_ROW21_1 0x03c +#define DDR_CTL_COL00_0 0x050 +#define DDR_CTL_COL00_1 0x054 +#define DDR_CTL_COL01_0 0x058 +#define DDR_CTL_COL01_1 0x05c +#define DDR_CTL_COL20_0 0x070 +#define DDR_CTL_COL20_1 0x074 +#define DDR_CTL_COL21_0 0x078 +#define DDR_CTL_COL21_1 0x07c +#define DDR_CTL_BNK10 0x090 +#define DDR_CTL_BNK32 0x094 +#define DDR_CTL_DCMD 0x100 +#define DDR_CTL_DMODE_0 0x104 +#define DDR_CTL_DMODE_1 0x108 +#define DDR_CTL_CLKS 0x10c +#define DDR_CTL_ODT 0x110 +#define DDR_CTL_TIM1_0 0x114 +#define DDR_CTL_TIM1_1 0x118 +#define DDR_CTL_TIM2 0x11c +#define DDR_CTL_CTL_CRC 0x120 +#define DDR_CTL_DOUT_CRC 0x124 +#define DDR_CTL_DIN_CRC 0x128 +#define PHY_CONTROL_REGS_REVISION 0x200 +#define PHY_CONTROL_REGS_CLK_PM_CTRL 0x204 +#define PHY_CONTROL_REGS_PLL_STATUS 0x210 +#define PHY_CONTROL_REGS_PLL_CONFIG 0x214 +#define PHY_CONTROL_REGS_PLL_PRE_DIVIDER 0x218 +#define PHY_CONTROL_REGS_PLL_DIVIDER 0x21c +#define PHY_CONTROL_REGS_PLL_CONTROL1 0x220 +#define PHY_CONTROL_REGS_PLL_CONTROL2 0x224 +#define PHY_CONTROL_REGS_PLL_SS_EN 0x228 +#define PHY_CONTROL_REGS_PLL_SS_CFG 0x22c +#define PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE 0x230 +#define PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE 0x234 +#define PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x238 +#define PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL 0x23c +#define PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x240 +#define PHY_CONTROL_REGS_CLOCK_REG_CONTROL 0x244 + +#define PHY_BYTE_LANE_0_REVISION 0x300 +#define PHY_BYTE_LANE_0_VDL_CALIBRATE 0x304 +#define PHY_BYTE_LANE_0_VDL_STATUS 0x308 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_0 0x310 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_1 0x314 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_2 0x318 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_3 0x31c +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_4 0x320 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_5 0x324 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_6 0x328 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_7 0x32c +#define PHY_BYTE_LANE_0_READ_CONTROL 0x330 +#define PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x334 +#define PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x338 +#define PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x33c +#define PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x340 +#define PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE 0x344 +#define PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x348 +#define PHY_BYTE_LANE_0_CLOCK_REG_CONTROL 0x34c + +#define PHY_BYTE_LANE_1_REVISION 0x400 +#define PHY_BYTE_LANE_1_VDL_CALIBRATE 0x404 +#define PHY_BYTE_LANE_1_VDL_STATUS 0x408 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_0 0x410 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_1 0x414 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_2 0x418 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_3 0x41c +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_4 0x420 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_5 0x424 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_6 0x428 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_7 0x42c +#define PHY_BYTE_LANE_1_READ_CONTROL 0x430 +#define PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x434 +#define PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x438 +#define PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x43c +#define PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x440 +#define PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE 0x444 +#define PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x448 +#define PHY_BYTE_LANE_1_CLOCK_REG_CONTROL 0x44c + +#define PHY_BYTE_LANE_2_REVISION 0x500 +#define PHY_BYTE_LANE_2_VDL_CALIBRATE 0x504 +#define PHY_BYTE_LANE_2_VDL_STATUS 0x508 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_0 0x510 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_1 0x514 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_2 0x518 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_3 0x51c +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_4 0x520 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_5 0x524 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_6 0x528 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_7 0x52c +#define PHY_BYTE_LANE_2_READ_CONTROL 0x530 +#define PHY_BYTE_LANE_2_READ_FIFO_STATUS 0x534 +#define PHY_BYTE_LANE_2_READ_FIFO_CLEAR 0x538 +#define PHY_BYTE_LANE_2_IDLE_PAD_CONTROL 0x53c +#define PHY_BYTE_LANE_2_DRIVE_PAD_CTL 0x540 +#define PHY_BYTE_LANE_2_CLOCK_PAD_DISABLE 0x544 +#define PHY_BYTE_LANE_2_WR_PREAMBLE_MODE 0x548 +#define PHY_BYTE_LANE_2_CLOCK_REG_CONTROL 0x54c + +#define PHY_BYTE_LANE_3_REVISION 0x600 +#define PHY_BYTE_LANE_3_VDL_CALIBRATE 0x604 +#define PHY_BYTE_LANE_3_VDL_STATUS 0x608 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_0 0x610 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_1 0x614 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_2 0x618 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_3 0x61c +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_4 0x620 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_5 0x624 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_6 0x628 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_7 0x62c +#define PHY_BYTE_LANE_3_READ_CONTROL 0x630 +#define PHY_BYTE_LANE_3_READ_FIFO_STATUS 0x634 +#define PHY_BYTE_LANE_3_READ_FIFO_CLEAR 0x638 +#define PHY_BYTE_LANE_3_IDLE_PAD_CONTROL 0x63c +#define PHY_BYTE_LANE_3_DRIVE_PAD_CTL 0x640 +#define PHY_BYTE_LANE_3_CLOCK_PAD_DISABLE 0x644 +#define PHY_BYTE_LANE_3_WR_PREAMBLE_MODE 0x648 +#define PHY_BYTE_LANE_3_CLOCK_REG_CONTROL 0x64c + +#define DDR_CTL_GCFG 0x800 +#define DDR_CTL_LBIST_CFG 0x804 +#define DDR_CTL_LBIST_SEED 0x808 +#define DDR_CTL_ARB 0x80c +#define DDR_CTL_PI_GCF 0x810 +#define DDR_CTL_PI_UBUS_CTL 0x814 +#define DDR_CTL_PI_MIPS_CTL 0x818 +#define DDR_CTL_PI_DSL_MIPS_CTL 0x81c +#define DDR_CTL_PI_DSL_PHY_CTL 0x820 +#define DDR_CTL_PI_UBUS_ST 0x824 +#define DDR_CTL_PI_MIPS_ST 0x828 +#define DDR_CTL_PI_DSL_MIPS_ST 0x82c +#define DDR_CTL_PI_DSL_PHY_ST 0x830 +#define DDR_CTL_PI_UBUS_SMPL 0x834 +#define DDR_CTL_TESTMODE 0x838 +#define DDR_CTL_TEST_CFG1 0x83c +#define DDR_CTL_TEST_PAT 0x840 +#define DDR_CTL_TEST_COUNT 0x844 +#define DDR_CTL_TEST_CURR_COUNT 0x848 +#define DDR_CTL_TEST_ADDR_UPDT 0x84c +#define DDR_CTL_TEST_ADDR 0x850 +#define DDR_CTL_TEST_DATA0 0x854 +#define DDR_CTL_TEST_DATA1 0x858 +#define DDR_CTL_TEST_DATA2 0x85c +#define DDR_CTL_TEST_DATA3 0x860 + + +/* +##################################################################### +# UART Control Registers +##################################################################### +*/ +#define UART0CONTROL 0x01 +#define UART0CONFIG 0x02 +#define UART0RXTIMEOUT 0x03 +#define UART0BAUD 0x04 +#define UART0FIFOCFG 0x0a +#define UART0INTMASK 0x10 +#define UART0INTSTAT 0x12 +#define UART0DATA 0x17 + +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + +#define XMITBREAK 0x40 /* Config register */ +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/broadcom/include/bcm963xx/6328_map.h b/shared/broadcom/include/bcm963xx/6328_map.h new file mode 100755 index 0000000..246d211 --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6328_map.h @@ -0,0 +1,1886 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6328_map.h */ +/* DATE: 05/30/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6328 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6328_MAP_H +#define __BCM6328_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" +#include "6328_common.h" +#include "6328_intr.h" + +/* macro to convert logical data addresses to physical */ +/* DMA hardware must see physical address */ +#define LtoP( x ) ( (uint32)x & 0x1fffffff ) +#define PtoL( x ) ( LtoP(x) | 0xa0000000 ) + +typedef struct DDRPhyControl { + uint32 REVISION; /* 0x00 */ + uint32 CLK_PM_CTRL; /* 0x04 */ + uint32 unused0[2]; /* 0x08-0x10 */ + uint32 PLL_STATUS; /* 0x10 */ + uint32 PLL_CONFIG; /* 0x14 */ + uint32 PLL_PRE_DIVIDER; /* 0x18 */ + uint32 PLL_DIVIDER; /* 0x1c */ + uint32 PLL_CONTROL1; /* 0x20 */ + uint32 PLL_CONTROL2; /* 0x24 */ + uint32 PLL_SS_EN; /* 0x28 */ + uint32 PLL_SS_CFG; /* 0x2c */ + uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ + uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ + uint32 IDLE_PAD_CONTROL; /* 0x38 */ + uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_REG_CONTROL; /* 0x44 */ + uint32 unused1[46]; +} DDRPhyControl; + +typedef struct DDRPhyByteLaneControl { + uint32 REVISION; /* 0x00 */ + uint32 VDL_CALIBRATE; /* 0x04 */ + uint32 VDL_STATUS; /* 0x08 */ + uint32 unused; /* 0x0c */ + uint32 VDL_OVERRIDE_0; /* 0x10 */ + uint32 VDL_OVERRIDE_1; /* 0x14 */ + uint32 VDL_OVERRIDE_2; /* 0x18 */ + uint32 VDL_OVERRIDE_3; /* 0x1c */ + uint32 VDL_OVERRIDE_4; /* 0x20 */ + uint32 VDL_OVERRIDE_5; /* 0x24 */ + uint32 VDL_OVERRIDE_6; /* 0x28 */ + uint32 VDL_OVERRIDE_7; /* 0x2c */ + uint32 READ_CONTROL; /* 0x30 */ + uint32 READ_FIFO_STATUS; /* 0x34 */ + uint32 READ_FIFO_CLEAR; /* 0x38 */ + uint32 IDLE_PAD_CONTROL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_PAD_DISABLE; /* 0x44 */ + uint32 WR_PREAMBLE_MODE; /* 0x48 */ + uint32 CLOCK_REG_CONTROL; /* 0x4C */ + uint32 unused0[44]; +} DDRPhyByteLaneControl; + +typedef struct DDRControl { + uint32 CNFG; /* 0x000 */ + uint32 CSST; /* 0x004 */ + uint32 CSEND; /* 0x008 */ + uint32 unused; /* 0x00c */ + uint32 ROW00_0; /* 0x010 */ + uint32 ROW00_1; /* 0x014 */ + uint32 ROW01_0; /* 0x018 */ + uint32 ROW01_1; /* 0x01c */ + uint32 unused0[4]; + uint32 ROW20_0; /* 0x030 */ + uint32 ROW20_1; /* 0x034 */ + uint32 ROW21_0; /* 0x038 */ + uint32 ROW21_1; /* 0x03c */ + uint32 unused1[4]; + uint32 COL00_0; /* 0x050 */ + uint32 COL00_1; /* 0x054 */ + uint32 COL01_0; /* 0x058 */ + uint32 COL01_1; /* 0x05c */ + uint32 unused2[4]; + uint32 COL20_0; /* 0x070 */ + uint32 COL20_1; /* 0x074 */ + uint32 COL21_0; /* 0x078 */ + uint32 COL21_1; /* 0x07c */ + uint32 unused3[4]; + uint32 BNK10; /* 0x090 */ + uint32 BNK32; /* 0x094 */ + uint32 unused4[26]; + uint32 DCMD; /* 0x100 */ +#define DCMD_CS1 (1 << 5) +#define DCMD_CS0 (1 << 4) +#define DCMD_SET_SREF 4 + uint32 DMODE_0; /* 0x104 */ + uint32 DMODE_1; /* 0x108 */ +#define DMODE_1_DRAMSLEEP (1 << 11) + uint32 CLKS; /* 0x10c */ + uint32 ODT; /* 0x110 */ + uint32 TIM1_0; /* 0x114 */ + uint32 TIM1_1; /* 0x118 */ + uint32 TIM2; /* 0x11c */ + uint32 CTL_CRC; /* 0x120 */ + uint32 DOUT_CRC; /* 0x124 */ + uint32 DIN_CRC; /* 0x128 */ + uint32 unused5[53]; + + DDRPhyControl PhyControl; /* 0x200 */ + DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ + DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ + DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ + DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ + uint32 unused6[64]; + + uint32 GCFG; /* 0x800 */ + uint32 LBIST_CFG; /* 0x804 */ + uint32 LBIST_SEED; /* 0x808 */ + uint32 ARB; /* 0x80c */ + uint32 PI_GCF; /* 0x810 */ + uint32 PI_UBUS_CTL; /* 0x814 */ + uint32 PI_MIPS_CTL; /* 0x818 */ + uint32 PI_DSL_MIPS_CTL; /* 0x81c */ + uint32 PI_DSL_PHY_CTL; /* 0x820 */ + uint32 PI_UBUS_ST; /* 0x824 */ + uint32 PI_MIPS_ST; /* 0x828 */ + uint32 PI_DSL_MIPS_ST; /* 0x82c */ + uint32 PI_DSL_PHY_ST; /* 0x830 */ + uint32 PI_UBUS_SMPL; /* 0x834 */ + uint32 TESTMODE; /* 0x838 */ + uint32 TEST_CFG1; /* 0x83c */ + uint32 TEST_PAT; /* 0x840 */ + uint32 TEST_COUNT; /* 0x844 */ + uint32 TEST_CURR_COUNT; /* 0x848 */ + uint32 TEST_ADDR_UPDT; /* 0x84c */ + uint32 TEST_ADDR; /* 0x850 */ + uint32 TEST_DATA0; /* 0x854 */ + uint32 TEST_DATA1; /* 0x858 */ + uint32 TEST_DATA2; /* 0x85c */ + uint32 TEST_DATA3; /* 0x860 */ +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define ROBOSW_CLK_EN (1 << 11) +#define PCIE_CLK_EN (1 << 10) +#define HS_SPI_CLK_EN (1 << 9) +#define USBH_CLK_EN (1 << 8) +#define USBD_CLK_EN (1 << 7) +#define PCM_CLK_EN (1 << 6) +#define SAR_CLK_EN (1 << 5) +#define MIPS_CLK_EN (1 << 4) +#define ADSL_CLK_EN (1 << 3) +#define ADSL_AFE_EN (1 << 2) +#define ADSL_QPROC_EN (1 << 1) +#define PHYMIPS_CLK_EN (1 << 0) + + uint32 unused0; /* (08) word 2 */ + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_PCIE_HARD (1 << 10) +#define SOFT_RST_PCIE_EXT (1 << 9) +#define SOFT_RST_PCIE (1 << 8) +#define SOFT_RST_PCIE_CORE (1 << 7) +#define SOFT_RST_PCM (1 << 6) +#define SOFT_RST_USBH (1 << 5) +#define SOFT_RST_USBD (1 << 4) +#define SOFT_RST_SWITCH (1 << 3) +#define SOFT_RST_SAR (1 << 2) +#define SOFT_RST_EPHY (1 << 1) +#define SOFT_RST_SPI (1 << 0) + + uint32 diagControl; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 unused1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 // 0 +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo<thresh + */ + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1) + * if these bits are also enabled to GPIO_o + */ +#define DTREN 0x01 +#define RTSEN 0x02 + + byte unused1; + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to + * detect irq on rising AND falling + * edges for corresponding GPIO_i + * if enabled (edge insensitive) + */ + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense + * 0 for negedge sense if + * not configured for edge + * insensitive (see above) + * Lower 4 bits: Mask to enable change + * detection IRQ for corresponding + * GPIO_i + */ + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits + * have changed (may set IRQ). + * read automatically clears bit + * Lower 4 bits are actual status + */ + + uint16 intMask; /* Same Bit defs for Mask and status */ + uint16 intStatus; +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + + uint16 unused2; + uint16 Data; /* Write to TX, Read from RX */ + /* bits 11:8 are BRK,PAR,FRM errors */ + + uint32 unused3; + uint32 unused4; +} Uart; + +#define UART ((volatile Uart * const) UART_BASE) + +/* +** Gpio Controller +*/ + +#pragma pack(push, 4) +typedef struct GpioControl { + uint32 GPIODirHi; /* 0 */ + uint32 GPIODir; /* 4 */ + uint32 GPIOioHi; /* 8 */ + uint32 GPIOio; /* C */ + uint32 unused0; /* 10 */ + uint32 SpiSlaveCfg; /* 14 */ + uint32 GPIOMode; /* 18 */ + uint64 PinMuxSel; /* 1C */ +#define SERIAL_LED_DATA 6 +#define SERIAL_LED_CLK 7 +#define INET_ACT_LED 11 +#define EPHY0_SPD_LED 17 +#define EPHY1_SPD_LED 18 +#define EPHY2_SPD_LED 19 +#define EPHY3_SPD_LED 20 +#define EPHY0_ACT_LED 25 +#define EPHY1_ACT_LED 26 +#define EPHY2_ACT_LED 27 +#define EPHY3_ACT_LED 28 + +#define PINMUX_SERIAL_LED_DATA ((uint64)2 << (SERIAL_LED_DATA << 1)) +#define PINMUX_SERIAL_LED_CLK ((uint64)2 << (SERIAL_LED_CLK << 1)) +#define PINMUX_INET_ACT_LED ((uint64)1 << (INET_ACT_LED << 1)) +#define PINMUX_EPHY0_ACT_LED ((uint64)1 << (EPHY0_ACT_LED << 1)) +#define PINMUX_EPHY1_ACT_LED ((uint64)1 << (EPHY1_ACT_LED << 1)) +#define PINMUX_EPHY2_ACT_LED ((uint64)1 << (EPHY2_ACT_LED << 1)) +#define PINMUX_EPHY3_ACT_LED ((uint64)1 << (EPHY3_ACT_LED << 1)) + + uint32 PinMuxSelOther; /* 24 */ +#define SEL_USB 12 +#define PINMUX_SEL_USB_MASK (3 << SEL_USB) +#define PINMUX_SEL_USB_HOST (1 << SEL_USB) +#define PINMUX_SEL_USB_DEV (2 << SEL_USB) + + uint32 TestControl; /* 28 */ + uint32 unused2; /* 2C */ + uint32 RoboSWLEDControl; /* 30 */ + uint32 RoboSWLEDLSR; /* 34 */ + uint32 unused3; /* 38 */ + uint32 RoboswEphyCtrl; /* 3C */ +#define EPHY_AUTO_PWR_DOWN_EN (1<<29) +#define EPHY_IDDQ_FROM_PHY (1<<28) +#define EPHY_PLL_LOCK (1<<27) +#define EPHY_ATEST_25MHZ_EN (1<<26) +#define EPHY_PWR_DOWN_DLL (1<<25) +#define EPHY_PWR_DOWN_BIAS (1<<24) +#define EPHY_PWR_DOWN_TX_4 (1<<23) +#define EPHY_PWR_DOWN_TX_3 (1<<22) +#define EPHY_PWR_DOWN_TX_2 (1<<21) +#define EPHY_PWR_DOWN_TX_1 (1<<20) +#define EPHY_PWR_DOWN_RX_4 (1<<19) +#define EPHY_PWR_DOWN_RX_3 (1<<18) +#define EPHY_PWR_DOWN_RX_2 (1<<17) +#define EPHY_PWR_DOWN_RX_1 (1<<16) +#define EPHY_PWR_DOWN_SD_4 (1<<15) +#define EPHY_PWR_DOWN_SD_3 (1<<14) +#define EPHY_PWR_DOWN_SD_2 (1<<13) +#define EPHY_PWR_DOWN_SD_1 (1<<12) +#define EPHY_PWR_DOWN_RD_4 (1<<11) +#define EPHY_PWR_DOWN_RD_3 (1<<10) +#define EPHY_PWR_DOWN_RD_2 (1<<9) +#define EPHY_PWR_DOWN_RD_1 (1<<8) +#define EPHY_PWR_DOWN_4 (1<<7) +#define EPHY_PWR_DOWN_3 (1<<6) +#define EPHY_PWR_DOWN_2 (1<<5) +#define EPHY_PWR_DOWN_1 (1<<4) +#define EPHY_RST_4 (1<<3) +#define EPHY_RST_3 (1<<2) +#define EPHY_RST_2 (1<<1) +#define EPHY_RST_1 (1<<0) + uint32 RoboswSwitchCtrl; /* 40 */ +#define RSW_SPI_MODE (1<<11) +#define RSW_BC_SUPP_EN (1<<10) +#define RSW_CLK_FREQ_MASK (3<<8) +#define RSW_ENF_DFX_FLOW (1<<7) +#define RSW_ENH_DFX_FLOW (1<<6) +#define RSW_GRX_0_SETUP (1<<5) +#define RSW_GTX_0_SETUP (1<<4) +#define RSW_HW_FWDG_EN (1<<3) +#define RSW_QOS_EN (1<<2) +#define RSW_WD_CLR_EN (1<<1) +#define RSW_MII_DUMB_FWDG_EN (1<<0) + + uint32 RegFileTmCtl; /* 44 */ + + uint32 RingOscCtrl0; /* 48 */ +#define RING_OSC_256_CYCLES 8 +#define RING_OSC_512_CYCLES 9 +#define RING_OSC_1024_CYCLES 10 + + uint32 RingOscCtrl1; /* 4C */ +#define RING_OSC_ENABLE_MASK (0x0f<<24) +#define RING_OSC_ENABLE_SHIFT 24 +#define RING_OSC_MAX 4 +#define RING_OSC_COUNT_RESET (0x1<<23) +#define RING_OSC_SELECT_MASK (0x7<<20) +#define RING_OSC_SELECT_SHIFT 20 +#define RING_OSC_IRQ (0x1<<18) +#define RING_OSC_COUNTER_OVERFLOW (0x1<<17) +#define RING_OSC_COUNTER_BUSY (0x1<<16) +#define RING_OSC_COUNT_MASK 0x0000ffff + + uint32 unused4[6]; /* 50 - 64 */ + uint32 DieRevID; /* 68 */ + uint32 unused5; /* 6c */ + uint32 DiagSelControl; /* 70 */ + uint32 DiagReadBack; /* 74 */ + uint32 DiagReadBackHi; /* 78 */ + uint32 DiagMiscControl; /* 7c */ +} GpioControl; +#pragma pack(pop) + +#define GPIO ((volatile GpioControl * const) GPIO_BASE) + +/* Number to mask conversion macro used for GPIODir and GPIOio */ +#define GPIO_NUM_MAX 32 +#define GPIO_NUM_TO_MASK(X) ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (1 << ((X) & BP_GPIO_NUM_MASK)) : (0) ) + +/* +** High-Speed SPI Controller +*/ + +#define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start) +typedef struct HsSpiControl { + + uint32 hs_spiGlobalCtrl; // 0x0000 +#define HS_SPI_MOSI_IDLE (1 << 18) +#define HS_SPI_CLK_POLARITY (1 << 17) +#define HS_SPI_CLK_GATE_SSOFF (1 << 16) +#define HS_SPI_PLL_CLK_CTRL (8) +#define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL) +#define HS_SPI_SS_POLARITY (0) +#define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY) + + uint32 hs_spiExtTrigCtrl; // 0x0004 +#define HS_SPI_TRIG_RAW_STATE (24) +#define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE) +#define HS_SPI_TRIG_LATCHED (16) +#define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED) +#define HS_SPI_TRIG_SENSE (8) +#define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE) +#define HS_SPI_TRIG_TYPE (0) +#define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE) +#define HS_SPI_TRIG_TYPE_EDGE (0) +#define HS_SPI_TRIG_TYPE_LEVEL (1) + + uint32 hs_spiIntStatus; // 0x0008 +#define HS_SPI_IRQ_PING1_USER (28) +#define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER) +#define HS_SPI_IRQ_PING0_USER (24) +#define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER) + +#define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQ_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQ_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntStatusMasked; // 0x000C +#define HS_SPI_IRQSM__PING1_USER (28) +#define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER) +#define HS_SPI_IRQSM__PING0_USER (24) +#define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER) + +#define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntMask; // 0x0010 +#define HS_SPI_IRQM_PING1_USER (28) +#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER) +#define HS_SPI_IRQM_PING0_USER (24) +#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER) + +#define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQM_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQM_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0) + +#define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F) + + uint32 hs_spiFlashCtrl; // 0x0014 +#define HS_SPI_FCTRL_MB_ENABLE (1 << 23) +#define HS_SPI_FCTRL_SS_NUM (20) +#define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM) +#define HS_SPI_FCTRL_PROFILE_NUM (16) +#define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM) +#define HS_SPI_FCTRL_DUMMY_BYTES (10) +#define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES (8) +#define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES_2 (0) +#define HS_SPI_FCTRL_ADDR_BYTES_3 (1) +#define HS_SPI_FCTRL_ADDR_BYTES_4 (2) +#define HS_SPI_FCTRL_READ_OPCODE (0) +#define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE) + + uint32 hs_spiFlashAddrBase; // 0x0018 + + char fill0[0x80 - 0x18]; + + uint32 hs_spiPP_0_Cmd; // 0x0080 +#define HS_SPI_PP_SS_NUM (12) +#define HS_SPI_PP_SS_NUM_MASK __mask(14, HS_SPI_PP_SS_NUM) +#define HS_SPI_PP_PROFILE_NUM (8) +#define HS_SPI_PP_PROFILE_NUM_MASK __mask(10, HS_SPI_PP_PROFILE_NUM) + +} HsSpiControl; + +typedef struct HsSpiPingPong { + + uint32 command; +#define HS_SPI_SS_NUM (12) +#define HS_SPI_PROFILE_NUM (8) +#define HS_SPI_TRIGGER_NUM (4) +#define HS_SPI_COMMAND_VALUE (0) + #define HS_SPI_COMMAND_NOOP (0) + #define HS_SPI_COMMAND_START_NOW (1) + #define HS_SPI_COMMAND_START_TRIGGER (2) + #define HS_SPI_COMMAND_HALT (3) + #define HS_SPI_COMMAND_FLUSH (4) + + uint32 status; +#define HS_SPI_ERROR_BYTE_OFFSET (16) +#define HS_SPI_WAIT_FOR_TRIGGER (2) +#define HS_SPI_SOURCE_BUSY (1) +#define HS_SPI_SOURCE_GNT (0) + + uint32 fifo_status; + uint32 control; + +} HsSpiPingPong; + +typedef struct HsSpiProfile { + + uint32 clk_ctrl; +#define HS_SPI_ACCUM_RST_ON_LOOP (15) +#define HS_SPI_SPI_CLK_2X_SEL (14) +#define HS_SPI_FREQ_CTRL_WORD (0) + + uint32 signal_ctrl; +#define HS_SPI_ASYNC_INPUT_PATH (1 << 16) +#define HS_SPI_LAUNCH_RISING (1 << 13) +#define HS_SPI_LATCH_RISING (1 << 12) + + uint32 mode_ctrl; +#define HS_SPI_PREPENDBYTE_CNT (24) +#define HS_SPI_MODE_ONE_WIRE (20) +#define HS_SPI_MULTIDATA_WR_SIZE (18) +#define HS_SPI_MULTIDATA_RD_SIZE (16) +#define HS_SPI_MULTIDATA_WR_STRT (12) +#define HS_SPI_MULTIDATA_RD_STRT (8) +#define HS_SPI_FILLBYTE (0) + + uint32 polling_config; + uint32 polling_and_mask; + uint32 polling_compare; + uint32 polling_timeout; + uint32 reserved; + +} HsSpiProfile; + +#define HS_SPI_OP_CODE 13 + #define HS_SPI_OP_SLEEP (0) + #define HS_SPI_OP_READ_WRITE (1) + #define HS_SPI_OP_WRITE (2) + #define HS_SPI_OP_READ (3) + #define HS_SPI_OP_SETIRQ (4) + +#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE) +#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80)) +#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0)) +#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100)) +#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200)) +#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400)) + + +/* +** Misc Register Set Definitions. +*/ + +typedef struct Misc { + uint32 miscSerdesCtrl; /* 0x0000 */ +#define SERDES_PCIE_ENABLE 0x00000001 +#define SERDES_PCIE_EXD_ENABLE (1<<15) + + uint32 miscSerdesSts; /* 0x0004 */ + uint32 miscIrqOutMask; /* 0x0008 */ +#define MISC_PCIE_EP_IRQ_MASK0 (1<<0) +#define MISC_PCIE_EP_IRQ_MASK1 (1<<1) + + uint32 miscMemcControl; /* 0x000c */ +#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE (1<<3) +#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE (1<<2) +#define MISC_MEMC_CONTROL_DDR_TEST_DONE (1<<1) +#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE (1<<0) + + uint32 unused0[2]; /* 0x0010 */ + + uint32 miscVregCtrl0; /* 0x0018 */ +#define VREG_VSEL1P2_SHIFT 0 +#define VREG_VSEL1P2_MASK 0x1f +#define VREG_VSEL1P2_MIDDLE 0x0f + + uint32 miscVregCtrl1; /* 0x001c */ + uint32 miscVregCtrl2; /* 0x0020 */ + uint32 miscLedXorReg; /* 0x0024 */ + uint32 miscExtra2ChipIrqMask; /* 0x0028 */ + uint32 miscExtra2ChipIrqStatus; /* 0x002c */ + uint32 miscExtra2ChipIrqMask1; /* 0x0030 */ + uint32 miscExtra2ChipIrqStatus1; /* 0x0034 */ + uint32 miscDdrPllTestCtrl; /* 0x0038 */ + uint32 miscPadCtrlLow; /* 0x003c */ + uint32 miscPadCtrlHigh; /* 0x0040 */ +#define MISC_MII_SEL_SHIFT 30 +#define MISC_MII_SEL_3P3V 0 +#define MISC_MII_SEL_2P5V 1 +#define MISC_MII_SEL_1P5V 2 + uint32 miscPeriphEcoReg; /* 0x0044 */ + + uint32 miscIddqCtrl; /* 0x0048 */ +#define MISC_IDDQ_CONTROL_USBH (1<<6) +#define MISC_IDDQ_CONTROL_USBD (1<<5) + + uint32 miscAdslClkSample; /* 0x004c */ + + uint32 unused3[(0x0100 - 0x0050) / 4]; /* 0x0050 */ + uint32 miscAdslCtrl; /* 0x0100 */ + uint32 unused4[(0x0180 - 0x0104) / 4]; /* 0x0104 */ + uint32 miscMipsTestCtrl; /* 0x0180 */ + uint32 miscMipsTestStatus; /* 0x0184 */ + uint32 unused5[(0x0200 - 0x0188) / 4]; /* 0x0188 */ + uint32 miscPllCtrlSysPll0; /* 0x0200 */ + uint32 miscPllCtrlSysPll1; /* 0x0204 */ + uint32 miscPllCtrlSysPll2; /* 0x0208 */ + uint32 miscPllCtrlSysPll3; /* 0x020c */ + uint32 miscPllCtrlDdrPll; /* 0x0210 */ + uint32 miscPllCtrlXtalEcoReg; /* 0x0214 */ + uint32 unused6[(0x0240 - 0x0218) / 4]; /* 0x0218 */ + uint32 miscStrapBus; /* 0x0240 */ +#define MISC_STRAP_BUS_BOOT_SEL_SHIFT 18 +#define MISC_STRAP_BUS_BOOT_SEL_MASK (0x1<<MISC_STRAP_BUS_BOOT_SEL_SHIFT) +#define MISC_STRAP_BUS_BOOT_SERIAL 0x01 +#define MISC_STRAP_BUS_BOOT_NAND 0x00 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 7 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK (0x1F<<MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT) + + uint32 miscStrapOverride; /* 0x0244 */ + uint32 unused7[(0x0280 - 0x0248) / 4]; /* 0x0248 */ + uint32 miscRtcSleepModeEn; /* 0x0280 */ + uint32 miscRtcSleepRtcEn; /* 0x0284 */ + uint32 miscRtcSleepRtcCountLow; /* 0x0288 */ + uint32 miscRtcSleepRtcCountHigh; /* 0x028c */ + uint32 miscRtcSleepRtcEvent; /* 0x0290 */ + uint32 miscRtcSleepWakeupMask; /* 0x0294 */ + uint32 miscRtcSleepWakeupStatus; /* 0x0298 */ + uint32 miscRtcSleepDebounceCtrl; /* 0x029c */ + uint32 miscRtcSleepCpuScratchPad; /* 0x02a0 */ +} Misc; + +#define MISC ((volatile Misc * const) MISC_BASE) + +/* +** LedControl Register Set Definitions. +*/ + +#pragma pack(push, 4) +typedef struct LedControl { + uint32 ledInit; +#define LED_LED_TEST (1 << 31) +#define LED_SHIFT_TEST (1 << 30) +#define LED_SERIAL_LED_SHIFT_DIR (1 << 16) +#define LED_SERIAL_LED_DATA_PPOL (1 << 15) +#define LEDSERIAL_LED_CLK_NPOL (1 << 14) +#define LED_SERIAL_LED_MUX_SEL (1 << 13) +#define LED_SERIAL_LED_EN (1 << 12) +#define LED_FAST_INTV_SHIFT 6 +#define LED_FAST_INTV_MASK (0x3F<<LED_FAST_INTV_SHIFT) +#define LED_SLOW_INTV_SHIFT 0 +#define LED_SLOW_INTV_MASK (0x3F<<LED_SLOW_INTV_SHIFT) +#define LED_INTERVAL_20MS 1 + + uint64 ledMode; +#define LED_MODE_MASK (uint64)0x3 +#define LED_MODE_OFF (uint64)0x0 +#define LED_MODE_FLASH (uint64)0x1 +#define LED_MODE_BLINK (uint64)0x2 +#define LED_MODE_ON (uint64)0x3 + + uint32 ledHWDis; + uint32 ledStrobe; + uint32 ledLinkActSelHigh; +#define LED_ENET0 4 +#define LED_ENET1 5 +#define LED_ENET2 6 +#define LED_ENET3 7 +#define LED_4_ACT_SHIFT 0 +#define LED_5_ACT_SHIFT 4 +#define LED_6_ACT_SHIFT 8 +#define LED_7_ACT_SHIFT 12 +#define LED_4_LINK_SHIFT 16 +#define LED_5_LINK_SHIFT 20 +#define LED_6_LINK_SHIFT 24 +#define LED_7_LINK_SHIFT 28 + uint32 ledLinkActSelLow; +#define LED_INET 0 +#define LED_0_ACT_SHIFT 0 +#define LED_1_ACT_SHIFT 4 +#define LED_2_ACT_SHIFT 8 +#define LED_3_ACT_SHIFT 12 +#define LED_0_LINK_SHIFT 16 +#define LED_1_LINK_SHIFT 20 +#define LED_2_LINK_SHIFT 24 +#define LED_3_LINK_SHIFT 28 + + uint32 ledReadback; + uint32 ledSerialMuxSelect; +} LedControl; +#pragma pack(pop) + +#define LED ((volatile LedControl * const) LED_BASE) + +#define GPIO_NUM_TO_LED_MODE_SHIFT(X) \ + ((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \ + ((((X) & BP_GPIO_NUM_MASK) - 8) << 1)) + +/* +** Pcm Controller +*/ + +typedef struct PcmControlRegisters +{ + uint32 pcm_ctrl; // 00 offset from PCM_BASE +#define PCM_ENABLE 0x80000000 // PCM block master enable +#define PCM_ENABLE_SHIFT 31 +#define PCM_SLAVE_SEL 0x40000000 // PCM TDM slave mode select (1 - TDM slave, 0 - TDM master) +#define PCM_SLAVE_SEL_SHIFT 30 +#define PCM_CLOCK_INV 0x20000000 // PCM SCLK invert select (1 - invert, 0 - normal) +#define PCM_CLOCK_INV_SHIFT 29 +#define PCM_FS_INVERT 0x10000000 // PCM FS invert select (1 - invert, 0 - normal) +#define PCM_FS_INVERT_SHIFT 28 +#define PCM_FS_FREQ_16_8 0x08000000 // PCM FS 16/8 Khz select (1 - 16Khz, 0 - 8Khz) +#define PCM_FS_FREQ_16_8_SHIFT 27 +#define PCM_FS_LONG 0x04000000 // PCM FS long/short select (1 - long FS, 0 - short FS) +#define PCM_FS_LONG_SHIFT 26 +#define PCM_FS_TRIG 0x02000000 // PCM FS trigger (1 - falling edge, 0 - rising edge trigger) +#define PCM_FS_TRIG_SHIFT 25 +#define PCM_DATA_OFF 0x01000000 // PCM data offset from FS (1 - one clock from FS, 0 - no offset) +#define PCM_DATA_OFF_SHIFT 24 +#define PCM_DATA_16_8 0x00800000 // PCM data word length (1 - 16 bits, 0 - 8 bits) +#define PCM_DATA_16_8_SHIFT 23 +#define PCM_CLOCK_SEL 0x00700000 // PCM SCLK freq select +#define PCM_CLOCK_SEL_SHIFT 20 + // 000 - 8192 Khz + // 001 - 4096 Khz + // 010 - 2048 Khz + // 011 - 1024 Khz + // 100 - 512 Khz + // 101 - 256 Khz + // 110 - 128 Khz + // 111 - reserved +#define PCM_LSB_FIRST 0x00040000 // PCM shift direction (1 - LSBit first, 0 - MSBit first) +#define PCM_LSB_FIRST_SHIFT 18 +#define PCM_LOOPBACK 0x00020000 // PCM diagnostic loobback enable +#define PCM_LOOPBACK_SHIFT 17 +#define PCM_EXTCLK_SEL 0x00010000 // PCM external timing clock select -- Maybe removed in 6328 +#define PCM_EXTCLK_SEL_SHIFT 16 +#define PCM_NTR_ENABLE 0x00008000 // PCM NTR counter enable -- Nayve removed in 6328 +#define PCM_NTR_ENABLE_SHIFT 15 +#define PCM_BITS_PER_FRAME_1024 0x00000400 // 1024 - Max +#define PCM_BITS_PER_FRAME_256 0x00000100 // 256 +#define PCM_BITS_PER_FRAME_8 0x00000008 // 8 - Min + + uint32 pcm_chan_ctrl; // 04 +#define PCM_TX0_EN 0x00000001 // PCM transmit channel 0 enable +#define PCM_TX1_EN 0x00000002 // PCM transmit channel 1 enable +#define PCM_TX2_EN 0x00000004 // PCM transmit channel 2 enable +#define PCM_TX3_EN 0x00000008 // PCM transmit channel 3 enable +#define PCM_TX4_EN 0x00000010 // PCM transmit channel 4 enable +#define PCM_TX5_EN 0x00000020 // PCM transmit channel 5 enable +#define PCM_TX6_EN 0x00000040 // PCM transmit channel 6 enable +#define PCM_TX7_EN 0x00000080 // PCM transmit channel 7 enable +#define PCM_RX0_EN 0x00000100 // PCM receive channel 0 enable +#define PCM_RX1_EN 0x00000200 // PCM receive channel 1 enable +#define PCM_RX2_EN 0x00000400 // PCM receive channel 2 enable +#define PCM_RX3_EN 0x00000800 // PCM receive channel 3 enable +#define PCM_RX4_EN 0x00001000 // PCM receive channel 4 enable +#define PCM_RX5_EN 0x00002000 // PCM receive channel 5 enable +#define PCM_RX6_EN 0x00004000 // PCM receive channel 6 enable +#define PCM_RX7_EN 0x00008000 // PCM receive channel 7 enable +#define PCM_RX_PACKET_SIZE 0x00ff0000 // PCM Rx DMA quasi-packet size +#define PCM_RX_PACKET_SIZE_SHIFT 16 + + uint32 pcm_int_pending; // 08 + uint32 pcm_int_mask; // 0c +#define PCM_TX_UNDERFLOW 0x00000001 // PCM DMA receive overflow +#define PCM_RX_OVERFLOW 0x00000002 // PCM DMA transmit underflow +#define PCM_TDM_FRAME 0x00000004 // PCM frame boundary +#define PCM_RX_IRQ 0x00000008 // IUDMA interrupts +#define PCM_TX_IRQ 0x00000010 + + uint32 pcm_pll_ctrl1; // 10 +#define PCM_PLL_PWRDN 0x80000000 // PLL PWRDN +#define PCM_PLL_PWRDN_CH1 0x40000000 // PLL CH PWRDN +#define PCM_PLL_REFCMP_PWRDN 0x20000000 // PLL REFCMP PWRDN +#define PCM_CLK16_RESET 0x10000000 // 16.382 MHz PCM interface circuitry reset. +#define PCM_PLL_ARESET 0x08000000 // PLL Analog Reset +#define PCM_PLL_DRESET 0x04000000 // PLL Digital Reset + + uint32 pcm_pll_ctrl2; // 14 + uint32 pcm_pll_ctrl3; // 18 + uint32 pcm_pll_ctrl4; // 1c + + uint32 pcm_pll_stat; // 20 +#define PCM_PLL_LOCK 0x00000001 // Asserted when PLL is locked to programmed frequency + + uint32 pcm_ntr_counter; // 24 + + uint32 unused[6]; +#define PCM_MAX_TIMESLOT_REGS 16 // Number of PCM time slot registers in the table. + // Each register provides the settings for 8 timeslots (4 bits per timeslot) + uint32 pcm_slot_alloc_tbl[PCM_MAX_TIMESLOT_REGS]; +#define PCM_TS_VALID 0x8 // valid marker for TS alloc ram entry + + uint32 pcm_pll_ch2_ctrl; // +0xa080 + uint32 pcm_msif_intf; // +0xa084 +} PcmControlRegisters; + +#define PCM ((volatile PcmControlRegisters * const) PCM_BASE) + + +typedef struct PcmIudmaRegisters +{ + uint16 reserved0; + uint16 ctrlConfig; +#define BCM6328_IUDMA_REGS_CTRLCONFIG_MASTER_EN 0x0001 +#define BCM6328_IUDMA_REGS_CTRLCONFIG_FLOWC_CH1_EN 0x0002 +#define BCM6328_IUDMA_REGS_CTRLCONFIG_FLOWC_CH3_EN 0x0004 +#define BCM6328_IUDMA_REGS_CTRLCONFIG_FLOWC_CH5_EN 0x0008 +#define BCM6328_IUDMA_REGS_CTRLCONFIG_FLOWC_CH7_EN 0x0010 + + // Flow control Ch1 + uint16 reserved1; + uint16 ch1_FC_Low_Thr; + + uint16 reserved2; + uint16 ch1_FC_High_Thr; + + uint16 reserved3; + uint16 ch1_Buff_Alloc; + + // Flow control Ch3 + uint16 reserved4; + uint16 ch3_FC_Low_Thr; + + uint16 reserved5; + uint16 ch3_FC_High_Thr; + + uint16 reserved6; + uint16 ch3_Buff_Alloc; + + // Flow control Ch5 + uint16 reserved7; + uint16 ch5_FC_Low_Thr; + + uint16 reserved8; + uint16 ch5_FC_High_Thr; + + uint16 reserved9; + uint16 ch5_Buff_Alloc; + + // Flow control Ch7 + uint16 reserved10; + uint16 ch7_FC_Low_Thr; + + uint16 reserved11; + uint16 ch7_FC_High_Thr; + + uint16 reserved12; + uint16 ch7_Buff_Alloc; + + // Channel resets + uint16 reserved13; + uint16 channel_reset; + + uint16 reserved14; + uint16 channel_debug; + + // Spare register + uint32 dummy1; + + // Interrupt status registers + uint16 reserved15; + uint16 gbl_int_stat; + + // Interrupt mask registers + uint16 reserved16; + uint16 gbl_int_mask; +} PcmIudmaRegisters; + + +typedef struct PcmIudmaChannelCtrl +{ + uint16 reserved1; + uint16 config; +#define BCM6328_IUDMA_CONFIG_ENDMA 0x0001 +#define BCM6328_IUDMA_CONFIG_PKTHALT 0x0002 +#define BCM6328_IUDMA_CONFIG_BURSTHALT 0x0004 + + uint16 reserved2; + uint16 intStat; +#define BCM6328_IUDMA_INTSTAT_BDONE 0x0001 +#define BCM6328_IUDMA_INTSTAT_PDONE 0x0002 +#define BCM6328_IUDMA_INTSTAT_NOTVLD 0x0004 +#define BCM6328_IUDMA_INTSTAT_MASK 0x0007 +#define BCM6328_IUDMA_INTSTAT_ALL BCM6328_IUDMA_INTSTAT_MASK + + uint16 reserved3; + uint16 intMask; +#define BCM6328_IUDMA_INTMASK_BDONE 0x0001 +#define BCM6328_IUDMA_INTMASK_PDONE 0x0002 +#define BCM6328_IUDMA_INTMASK_NOTVLD 0x0004 + + uint32 maxBurst; +#define BCM6328_IUDMA_MAXBURST_SIZE 16 /* 32-bit words */ + +} PcmIudmaChannelCtrl; + + +typedef struct PcmIudmaStateRam +{ + uint32 baseDescPointer; /* pointer to first buffer descriptor */ + + uint32 stateBytesDoneRingOffset; /* state info: how manu bytes done and the offset of the + current descritor in process */ +#define BCM6328_IUDMA_STRAM_DESC_RING_OFFSET 0x3fff + + + uint32 flagsLengthStatus; /* Length and status field of the current descriptor */ + + uint32 currentBufferPointer; /* pointer to the current descriptor */ + +} PcmIudmaStateRam; + +#define BCM6328_MAX_PCM_DMA_CHANNELS 2 + +typedef struct PcmIudma +{ + PcmIudmaRegisters regs; // + uint32 reserved1[110]; // + PcmIudmaChannelCtrl ctrl[BCM6328_MAX_PCM_DMA_CHANNELS]; // + uint32 reserved2[120]; // + PcmIudmaStateRam stram[BCM6328_MAX_PCM_DMA_CHANNELS]; // + +} PcmIudma; + +#define PCM_IUDMA ((volatile PcmIudma * const) PCM_DMA_BASE) + + +#define IUDMA_MAX_CHANNELS 32 + +/* +** DMA Channel Configuration (1 .. 32) +*/ +typedef struct DmaChannelCfg { + uint32 cfg; /* (00) assorted configuration */ +#define DMA_ENABLE 0x00000001 /* set to enable channel */ +#define DMA_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ +#define DMA_BURST_HALT 0x00000004 /* idle after finish current memory burst */ + uint32 intStat; /* (04) interrupts control and status */ + uint32 intMask; /* (08) interrupts mask */ +#define DMA_BUFF_DONE 0x00000001 /* buffer done */ +#define DMA_DONE 0x00000002 /* packet xfer complete */ +#define DMA_NO_DESC 0x00000004 /* no valid descriptors */ + uint32 maxBurst; /* (0C) max burst length permitted */ +#define DMA_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */ +} DmaChannelCfg; + +/* +** DMA State RAM (1 .. 16) +*/ +typedef struct DmaStateRam { + uint32 baseDescPtr; /* (00) descriptor ring start address */ + uint32 state_data; /* (04) state/bytes done/ring offset */ + uint32 desc_len_status; /* (08) buffer descriptor status and len */ + uint32 desc_base_bufptr; /* (0C) buffer descrpitor current processing */ +} DmaStateRam; + + +/* +** DMA Registers +*/ +typedef struct DmaRegs { + uint32 controller_cfg; /* (00) controller configuration */ +#define DMA_MASTER_EN 0x00000001 +#define DMA_FLOWC_CH1_EN 0x00000002 +#define DMA_FLOWC_CH3_EN 0x00000004 + + // Flow control Ch1 + uint32 flowctl_ch1_thresh_lo; /* 004 */ + uint32 flowctl_ch1_thresh_hi; /* 008 */ + uint32 flowctl_ch1_alloc; /* 00c */ +#define DMA_BUF_ALLOC_FORCE 0x80000000 + + // Flow control Ch3 + uint32 flowctl_ch3_thresh_lo; /* 010 */ + uint32 flowctl_ch3_thresh_hi; /* 014 */ + uint32 flowctl_ch3_alloc; /* 018 */ + + // Flow control Ch5 + uint32 flowctl_ch5_thresh_lo; /* 01C */ + uint32 flowctl_ch5_thresh_hi; /* 020 */ + uint32 flowctl_ch5_alloc; /* 024 */ + + // Flow control Ch7 + uint32 flowctl_ch7_thresh_lo; /* 028 */ + uint32 flowctl_ch7_thresh_hi; /* 02C */ + uint32 flowctl_ch7_alloc; /* 030 */ + + uint32 ctrl_channel_reset; /* 034 */ + uint32 ctrl_channel_debug; /* 038 */ + uint32 reserved1; /* 03C */ + uint32 ctrl_global_interrupt_status; /* 040 */ + uint32 ctrl_global_interrupt_mask; /* 044 */ + + // Unused words + uint8 reserved2[0x200-0x48]; + + // Per channel registers/state ram + DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */ + union { + DmaStateRam s[IUDMA_MAX_CHANNELS]; + uint32 u32[4 * IUDMA_MAX_CHANNELS]; + } stram; /* (400-5FF) state ram */ +} DmaRegs; + +#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE) + +/* +** DMA Buffer +*/ +typedef struct DmaDesc { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ +} DmaDesc; + +/* +** 16 Byte DMA Buffer +*/ +typedef struct { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ + uint32 control; +#define GEM_ID_MASK 0x001F + uint32 reserved; +} DmaDesc16; + + +/* +** USB 2.0 Device Registers +*/ +typedef struct UsbRegisters { +#define USBD_CONTROL_APP_DONECSR 0x0001 +#define USBD_CONTROL_APP_RESUME 0x0002 +#define USBD_CONTROL_APP_RXFIFIO_INIT 0x0040 +#define USBD_CONTROL_APP_TXFIFIO_INIT 0x0080 +#define USBD_CONTROL_APP_FIFO_SEL_SHIFT 0x8 +#define USBD_CONTROL_APP_FIFO_INIT_SEL(x) (((x)&0x0f)<<USBD_CONTROL_APP_FIFO_SEL_SHIFT) +#define USBD_CONTROL_APP_AUTO_CSRS 0x2000 +#define USBD_CONTROL_APP_AUTO_INS_ZERO_LEN_PKT 0x4000 +#define EN_TXZLENINS (1<<14) +#define EN_RXZSCFG (1<<12) +#define APPSETUPERRLOCK (1<<5) + uint32 usbd_control ; +#define USBD_STRAPS_APP_SELF_PWR 0x0400 +#define USBD_STRAPS_APP_DEV_DISCON 0x0200 +#define USBD_STRAPS_APP_CSRPRG_SUP 0x0100 +#define USBD_STRAPS_APP_RAM_IF 0x0080 +#define USBD_STRAPS_APP_DEV_RMTWKUP 0x0040 +#define USBD_STRAPS_APP_PHYIF_8BIT 0x0004 +#define USBD_STRAPS_FULL_SPEED 0x0003 +#define USBD_STRAPS_LOW_SPEED 0x0002 +#define USBD_STRAPS_HIGH_SPEED 0x0000 +#define APPUTMIDIR(x) ((x&1)<<3) +#define UNIDIR 0 + uint32 usbd_straps; +#define USB_ENDPOINT_0 0x01 + uint32 usbd_stall; +#define USBD_ENUM_SPEED_SHIFT 12 +#define USBD_ENUM_SPEED 0x3000 +#define UDC20_ALTINTF(x) ((x>>8)&0xf) +#define UDC20_INTF(x) ((x>>4)&0xf) +#define UDC20_CFG(x) ((x>>0)&0xf) + uint32 usbd_status; +#define USBD_LINK (0x1<<10) +#define USBD_SET_CSRS 0x40 +#define USBD_SUSPEND 0x20 +#define USBD_EARLY_SUSPEND 0x10 +#define USBD_SOF 0x08 +#define USBD_ENUMON 0x04 +#define USBD_SETUP 0x02 +#define USBD_USBRESET 0x01 + uint32 usbd_events; + uint32 usbd_events_irq; +#define UPPER(x) (16+x) +#define ENABLE(x) (1<<x) +#define SWP_TXBSY (15) +#define SWP_RXBSY (14) +#define SETUP_ERR (13) +#define APPUDCSTALLCHG (12) +#define BUS_ERR (11) +#define USB_LINK (10) +#define HST_SETCFG (9) +#define HST_SETINTF (8) +#define ERRATIC_ERR (7) +#define SET_CSRS (6) +#define SUSPEND (5) +#define ERLY_SUSPEND (4) +#define SOF (3) +#define ENUM_ON (2) +#define SETUP (1) +#define USB_RESET (0) +#define RISING(x) (0x0<<2*x) +#define FALLING(x) (0x1<<2*x) +#define USBD_IRQCFG_ENUM_ON_FALLING_EDGE 0x00000010 + uint32 usbd_irqcfg_hi ; + uint32 usbd_irqcfg_lo ; +#define USBD_USB_RESET_IRQ 0x00000001 +#define USBD_USB_SETUP_IRQ 0x00000002 // non-standard setup cmd rcvd +#define USBD_USB_ENUM_ON_IRQ 0x00000004 +#define USBD_USB_SOF_IRQ 0x00000008 +#define USBD_USB_EARLY_SUSPEND_IRQ 0x00000010 +#define USBD_USB_SUSPEND_IRQ 0x00000020 // non-standard setup cmd rcvd +#define USBD_USB_SET_CSRS_IRQ 0x00000040 +#define USBD_USB_ERRATIC_ERR_IRQ 0x00000080 +#define USBD_USB_SETCFG_IRQ 0x00000200 +#define USBD_USB_LINK_IRQ 0x00000400 + uint32 usbd_events_irq_mask; + uint32 usbd_swcfg; + uint32 usbd_swtxctl; + uint32 usbd_swrxctl; + uint32 usbd_txfifo_rwptr; + uint32 usbd_rxfifo_rwptr; + uint32 usbd_txfifo_st_rwptr; + uint32 usbd_rxfifo_st_rwptr; + uint32 usbd_txfifo_config ; + uint32 usbd_rxfifo_config ; + uint32 usbd_txfifo_epsize ; + uint32 usbd_rxfifo_epsize ; +#define USBD_EPNUM_CTRL 0x0 +#define USBD_EPNUM_ISO 0x1 +#define USBD_EPNUM_BULK 0x2 +#define USBD_EPNUM_IRQ 0x3 +#define USBD_EPNUM_EPTYPE(x) (((x)&0x3)<<8) +#define USBD_EPNUM_EPDMACHMAP(x) (((x)&0xf)<<0) + uint32 usbd_epnum_typemap ; + uint32 usbd_reserved [0xB] ; + uint32 usbd_csr_setupaddr ; +#define USBD_EPNUM_MASK 0xf +#define USBD_EPNUM(x) ((x&USBD_EPNUM_MASK)<<0) +#define USBD_EPDIR_IN (1<<4) +#define USBD_EPDIR_OUT (0<<4) +#define USBD_EPTYP_CTRL (USBD_EPNUM_CTRL<<5) +#define USBD_EPTYP_ISO (USBD_EPNUM_ISO<<5) +#define USBD_EPTYP_BULK (USBD_EPNUM_BULK<<5) +#define USBD_EPTYP_IRQ (USBD_EPNUM_IRQ<<5) +#define USBD_EPCFG_MASK 0xf +#define USBD_EPCFG(x) ((x&USBD_EPCFG_MASK)<<7) +#define USBD_EPINTF_MASK 0xf +#define USBD_EPINTF(x) ((x&USBD_EPINTF_MASK)<<11) +#define USBD_EPAINTF_MASK 0xf +#define USBD_EPAINTF(x) ((x&USBD_EPAINTF_MASK)<<15) +#define USBD_EPMAXPKT_MSK 0x7ff +#define USBD_EPMAXPKT(x) ((x&USBD_EPMAXPKT_MSK)<<19) +#define USBD_EPISOPID_MASK 0x3 +#define USBD_EPISOPID(x) ((x&USBD_ISOPID_MASK)<<30) + uint32 usbd_csr_ep [5] ; +} UsbRegisters; + +#define USB ((volatile UsbRegisters * const) USB_CTL_BASE) + +typedef struct USBControl { + uint32 BrtControl1; + uint32 BrtControl2; + uint32 BrtStatus1; + uint32 BrtStatus2; + uint32 UTMIControl1; +#define USB_DEVICE_MODE_SEL (1<<0) + uint32 TestPortControl; + uint32 PllControl1; + uint32 SwapControl; +#define USB_DEVICE_SEL (1<<6) +#define EHCI_LOGICAL_ADDRESS_EN (1<<5) +#define EHCI_ENDIAN_SWAP (1<<4) +#define EHCI_DATA_SWAP (1<<3) +#define OHCI_LOGICAL_ADDRESS_EN (1<<2) +#define OHCI_ENDIAN_SWAP (1<<1) +#define OHCI_DATA_SWAP (1<<0) + uint32 GenericControl; +#define PLL_SUSPEND_EN (1<<1) + uint32 FrameAdjustValue; + uint32 Setup; +#define USBH_IOC (1<<4) + uint32 MDIO; + uint32 MDIO32; + uint32 USBSimControl; +} USBControl; + +#define USBH ((volatile USBControl * const) USBH_CFG_BASE) + +typedef struct EthSwRegs{ + byte port_traffic_ctrl[9]; /* 0x00 - 0x08 */ + byte reserved1[2]; /* 0x09 - 0x0a */ + byte switch_mode; /* 0x0b */ + unsigned short pause_quanta; /*0x0c */ + byte imp_port_state; /*0x0e */ + byte led_refresh; /* 0x0f */ + unsigned short led_function[2]; /* 0x10 */ + unsigned short led_function_map; /* 0x14 */ + unsigned short led_enable_map; /* 0x16 */ + unsigned short led_mode_map0; /* 0x18 */ + unsigned short led_function_map1; /* 0x1a */ + byte reserved2[5]; /* 0x1b - 0x20 */ + byte port_forward_ctrl; /* 0x21 */ + byte reserved3[2]; /* 0x22 - 0x23 */ + unsigned short protected_port_selection; /* 0x24 */ + unsigned short wan_port_select; /* 0x26 */ + unsigned int pause_capability; /* 0x28 */ + byte reserved4[3]; /* 0x2c - 0x2e */ + byte reserved_multicast_control; /* 0x2f */ + byte reserved5; /* 0x30 */ + byte txq_flush_mode_control; /* 0x31 */ + unsigned short ulf_forward_map; /* 0x32 */ + unsigned short mlf_forward_map; /* 0x34 */ + unsigned short mlf_impc_forward_map; /* 0x36 */ + unsigned short pause_pass_through_for_rx; /* 0x38 */ + unsigned short pause_pass_through_for_tx; /* 0x3a */ + unsigned short disable_learning; /* 0x3c */ + byte reserved6[26]; /* 0x3e - 0x57 */ + byte port_state_override[8]; /* 0x58 - 0x5f */ + byte reserved7[4]; /* 0x60 - 0x63 */ + byte imp_rgmii_ctrl_p4; /* 0x64 */ + byte imp_rgmii_ctrl_p5; /* 0x65 */ + byte reserved8[6]; /* 0x66 - 0x6b */ + byte rgmii_timing_delay_p4; /* 0x6c */ + byte gmii_timing_delay_p5; /* 0x6d */ + byte reserved9[11]; /* 0x6e - 0x78 */ + byte software_reset; /* 0x79 */ + byte reserved13[6]; /* 0x7a - 0x7f */ + byte pause_frame_detection; /* 0x80 */ + byte reserved10[7]; /* 0x81 - 0x87 */ + byte fast_aging_ctrl; /* 0x88 */ + byte fast_aging_port; /* 0x89 */ + byte fast_aging_vid; /* 0x8a */ + byte reserved11[21]; /* 0x8b - 0x9f */ + unsigned int swpkt_ctrl_sar; /*0xa0 */ + unsigned int swpkt_ctrl_usb; /*0xa4 */ + unsigned int iudma_ctrl; /*0xa8 */ + unsigned int rxfilt_ctrl; /*0xac */ + unsigned int mdio_ctrl; /*0xb0 */ + unsigned int mdio_data; /*0xb4 */ + byte reserved12[42]; /* 0xb6 - 0xdf */ + unsigned int sw_mem_test; /*0xe0 */ +} EthSwRegs; + +#define ETHSWREG ((volatile EthSwRegs * const) SWITCH_BASE) + +typedef struct EthSwMIBRegs { + unsigned int TxOctetsLo; + unsigned int TxOctetsHi; + unsigned int TxDropPkts; + unsigned int TxQoSPkts; + unsigned int TxBroadcastPkts; + unsigned int TxMulticastPkts; + unsigned int TxUnicastPkts; + unsigned int TxCol; + unsigned int TxSingleCol; + unsigned int TxMultipleCol; + unsigned int TxDeferredTx; + unsigned int TxLateCol; + unsigned int TxExcessiveCol; + unsigned int TxFrameInDisc; + unsigned int TxPausePkts; + unsigned int TxQoSOctetsLo; + unsigned int TxQoSOctetsHi; + unsigned int RxOctetsLo; + unsigned int RxOctetsHi; + unsigned int RxUndersizePkts; + unsigned int RxPausePkts; + unsigned int Pkts64Octets; + unsigned int Pkts65to127Octets; + unsigned int Pkts128to255Octets; + unsigned int Pkts256to511Octets; + unsigned int Pkts512to1023Octets; + unsigned int Pkts1024to1522Octets; + unsigned int RxOversizePkts; + unsigned int RxJabbers; + unsigned int RxAlignErrs; + unsigned int RxFCSErrs; + unsigned int RxGoodOctetsLo; + unsigned int RxGoodOctetsHi; + unsigned int RxDropPkts; + unsigned int RxUnicastPkts; + unsigned int RxMulticastPkts; + unsigned int RxBroadcastPkts; + unsigned int RxSAChanges; + unsigned int RxFragments; + unsigned int RxExcessSizeDisc; + unsigned int RxSymbolError; + unsigned int RxQoSPkts; + unsigned int RxQoSOctetsLo; + unsigned int RxQoSOctetsHi; + unsigned int Pkts1523to2047; + unsigned int Pkts2048to4095; + unsigned int Pkts4096to8191; + unsigned int Pkts8192to9728; +} EthSwMIBRegs; + +#define ETHSWMIBREG ((volatile EthSwMIBRegs * const) (SWITCH_BASE + 0x2000)) + +/* +** NAND Interrupt Controller Registers +*/ +typedef struct NandIntrCtrlRegs { + uint32 NandInterrupt; +#define NINT_ENABLE_MASK 0xffff0000 +#define NINT_STS_MASK 0x00000fff +#define NINT_ECC_ERROR_CORR 0x00000080 +#define NINT_ECC_ERROR_UNC 0x00000040 +#define NINT_DEV_RBPIN 0x00000020 +#define NINT_CTRL_READY 0x00000010 +#define NINT_PAGE_PGM 0x00000008 +#define NINT_COPY_BACK 0x00000004 +#define NINT_BLOCK_ERASE 0x00000002 +#define NINT_NP_READ 0x00000001 + + uint32 NandBaseAddr0; /* Default address when booting from NAND flash */ + uint32 reserved; + uint32 NandBaseAddr1; /* Secondary base address for NAND flash */ +} NandIntrCtrlRegs; + +#define NAND_INTR ((volatile NandIntrCtrlRegs * const) NAND_INTR_BASE) + +/* +** NAND Controller Registers +*/ +typedef struct NandCtrlRegs { + uint32 NandRevision; /* NAND Revision */ + uint32 NandCmdStart; /* Nand Flash Command Start */ +#define NCMD_MASK 0x0f000000 +#define NCMD_BLK_LOCK_STS 0x0d000000 +#define NCMD_BLK_UNLOCK 0x0c000000 +#define NCMD_BLK_LOCK_DOWN 0x0b000000 +#define NCMD_BLK_LOCK 0x0a000000 +#define NCMD_FLASH_RESET 0x09000000 +#define NCMD_BLOCK_ERASE 0x08000000 +#define NCMD_DEV_ID_READ 0x07000000 +#define NCMD_COPY_BACK 0x06000000 +#define NCMD_PROGRAM_SPARE 0x05000000 +#define NCMD_PROGRAM_PAGE 0x04000000 +#define NCMD_STS_READ 0x03000000 +#define NCMD_SPARE_READ 0x02000000 +#define NCMD_PAGE_READ 0x01000000 + + uint32 NandCmdExtAddr; /* Nand Flash Command Extended Address */ + uint32 NandCmdAddr; /* Nand Flash Command Address */ + uint32 NandCmdEndAddr; /* Nand Flash Command End Address */ + uint32 NandNandBootConfig; /* Nand Flash Boot Config */ +#define NBC_CS_LOCK 0x80000000 +#define NBC_AUTO_DEV_ID_CFG 0x40000000 +#define NBC_WR_PROT_BLK0 0x10000000 + + uint32 NandCsNandXor; /* Nand Flash EBI CS Address XOR with */ + /* 1FC0 Control */ + uint32 NandReserved; + uint32 NandSpareAreaReadOfs0; /* Nand Flash Spare Area Read Bytes 0-3 */ + uint32 NandSpareAreaReadOfs4; /* Nand Flash Spare Area Read Bytes 4-7 */ + uint32 NandSpareAreaReadOfs8; /* Nand Flash Spare Area Read Bytes 8-11 */ + uint32 NandSpareAreaReadOfsC; /* Nand Flash Spare Area Read Bytes 12-15*/ + uint32 NandSpareAreaWriteOfs0; /* Nand Flash Spare Area Write Bytes 0-3 */ + uint32 NandSpareAreaWriteOfs4; /* Nand Flash Spare Area Write Bytes 4-7 */ + uint32 NandSpareAreaWriteOfs8; /* Nand Flash Spare Area Write Bytes 8-11*/ + uint32 NandSpareAreaWriteOfsC; /* Nand Flash Spare Area Write Bytes12-15*/ + uint32 NandAccControl; /* Nand Flash Access Control */ + uint32 NandConfig; /* Nand Flash Config */ +#define NC_CONFIG_LOCK 0x80000000 +#define NC_PG_SIZE_MASK 0x00300000 +#define NC_PG_SIZE_2K 0x00100000 +#define NC_PG_SIZE_512B 0x00000000 +#define NC_BLK_SIZE_MASK 0x30000000 +#define NC_BLK_SIZE_512K 0x30000000 +#define NC_BLK_SIZE_128K 0x10000000 +#define NC_BLK_SIZE_16K 0x00000000 +#define NC_BLK_SIZE_8K 0x20000000 +#define NC_DEV_SIZE_MASK 0x0f000000 +#define NC_DEV_SIZE_SHIFT 24 +#define NC_DEV_WIDTH_MASK 0x00800000 +#define NC_DEV_WIDTH_16 0x00800000 +#define NC_DEV_WIDTH_8 0x00000000 +#define NC_FUL_ADDR_MASK 0x00070000 +#define NC_FUL_ADDR_SHIFT 16 +#define NC_BLK_ADDR_MASK 0x00000700 +#define NC_BLK_ADDR_SHIFT 8 + + uint32 NandTiming1; /* Nand Flash Timing Parameters 1 */ + uint32 NandTiming2; /* Nand Flash Timing Parameters 2 */ + uint32 NandSemaphore; /* Semaphore */ + uint32 NandFlashDeviceId; /* Nand Flash Device ID */ + uint32 NandBlockLockStatus; /* Nand Flash Block Lock Status */ + uint32 NandIntfcStatus; /* Nand Flash Interface Status */ +#define NIS_CTLR_READY 0x80000000 +#define NIS_FLASH_READY 0x40000000 +#define NIS_CACHE_VALID 0x20000000 +#define NIS_SPARE_VALID 0x10000000 +#define NIS_FLASH_STS_MASK 0x000000ff +#define NIS_WRITE_PROTECT 0x00000080 +#define NIS_DEV_READY 0x00000040 +#define NIS_PGM_ERASE_ERROR 0x00000001 + + uint32 NandEccCorrExtAddr; /* ECC Correctable Error Extended Address*/ + uint32 NandEccCorrAddr; /* ECC Correctable Error Address */ + uint32 NandEccUncExtAddr; /* ECC Uncorrectable Error Extended Addr */ + uint32 NandEccUncAddr; /* ECC Uncorrectable Error Address */ + uint32 NandFlashReadExtAddr; /* Flash Read Data Extended Address */ + uint32 NandFlashReadAddr; /* Flash Read Data Address */ + uint32 NandProgramPageExtAddr; /* Page Program Extended Address */ + uint32 NandProgramPageAddr; /* Page Program Address */ + uint32 NandCopyBackExtAddr; /* Copy Back Extended Address */ + uint32 NandCopyBackAddr; /* Copy Back Address */ + uint32 NandBlockEraseExtAddr; /* Block Erase Extended Address */ + uint32 NandBlockEraseAddr; /* Block Erase Address */ + uint32 NandInvReadExtAddr; /* Flash Invalid Data Extended Address */ + uint32 NandInvReadAddr; /* Flash Invalid Data Address */ + uint32 NandBlkWrProtect; /* Block Write Protect Enable and Size */ + /* for EBI_CS0b */ +} NandCtrlRegs; + +#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE) + +#define NAND_CACHE ((volatile uint8 * const) NAND_CACHE_BASE) + +/* +** PCI-E +*/ +typedef struct PcieRegs{ + uint32 devVenID; + uint16 command; + uint16 status; + uint32 revIdClassCode; + uint32 headerTypeLatCacheLineSize; + uint32 bar1; + uint32 bar2; + uint32 priSecBusNo; +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK 0x00ff0000 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT 16 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK 0x0000ff00 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT 8 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK 0x000000ff + + uint32 ioBaseLimit; + uint32 secStatus; + uint32 rcMemBaseLimit; + uint32 rcPrefBaseLimit; + uint32 rcPrefBaseHi; + uint32 rcPrefLimitHi; + uint32 rcIoBaseLimit; + uint32 capPointer; + uint32 expRomBase; + uint32 brdigeCtrlIntPinIntLine; + uint32 bridgeCtrl; + uint32 unused1[27]; + + /* PcieExpressCtrlRegs */ + uint16 pciExpressCap; + uint16 pcieCapabilitiy; + uint32 deviceCapability; + uint16 deviceControl; + uint16 deviceStatus; + uint32 linkCapability; + uint16 linkControl; + uint16 linkStatus; + uint32 slotCapability; + uint16 slotControl; + uint16 slotStatus; + uint16 rootControl; + uint16 rootCap; + uint32 rootStatus; + uint32 deviceCapability2; + uint16 deviceControl2; + uint16 deviceStatus2; + uint32 linkCapability2; + uint16 linkControl2; + uint16 linkStatus2; + uint32 slotCapability2; + uint16 slotControl2; + uint16 slotStatus2; + uint32 unused2[6]; + + /* PcieErrorRegs */ + uint16 advErrCapId; + uint16 advErrCapOff; + uint32 ucErrStatus; + uint32 ucorrErrMask; + uint32 ucorrErrSevr; + uint32 corrErrStatus; + uint32 corrErrMask; + uint32 advErrCapControl; + uint32 headerLog1; + uint32 headerLog2; + uint32 headerLog3; + uint32 headerLog4; + uint32 rootErrorCommand; + uint32 rootErrorStatus; + uint32 rcCorrId; + uint32 rcFatalNonfatalId; + uint32 unused3[10]; + + /* PcieVcRegs */ + uint16 vcCapId; + uint16 vcCapOffset; + uint32 prtVcCapability; + uint32 portVcCapability2; + uint16 portVcControl; + uint16 portVcCtatus; + uint32 portArbStatus; + uint32 vcRsrcControl; + uint32 vcRsrcStatus; + uint32 unused4[1]; + + /* PcieVendor */ + uint32 vendorCapability; + uint32 vendorSpecificHdr; +} PcieRegs; + +typedef struct PcieBlk404Regs{ + uint32 unused; /* 0x404 */ + uint32 config2; /* 0x408 */ +#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK 0x0000000f +#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE 0 + uint32 config3; /* 0x40c */ + uint32 pmDataA; /* 0x410 */ + uint32 pmDataB; /* 0x414 */ +} PcieBlk404Regs; + +typedef struct PcieBlk428Regs{ + uint32 vpdIntf; /* 0x428 */ + uint16 unused_g; /* 0x42c */ + uint16 vpdAddrFlag; /* 0x42e */ + uint32 vpdData; /* 0x430 */ + uint32 idVal1; /* 0x434 */ + uint32 idVal2; /* 0x438 */ + uint32 idVal3; /* 0x43c */ +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK 0xff000000 +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT 24 +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK 0x00ffffff +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT 16 +#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT 8 + + uint32 idVal4; + uint32 idVal5; + uint32 unused_h; + uint32 idVal6; + uint32 msiData; + uint32 msiAddr_h; + uint32 msiAddr_l; + uint32 msiMask; + uint32 msiPend; + uint32 pmData_c; + uint32 msixControl; + uint32 msixTblOffBir; + uint32 msixPbaOffBit; + uint32 unused_k; + uint32 pcieCapability; + uint32 deviceCapability; + uint32 unused_l; + uint32 linkCapability; + uint32 bar2Config; + uint32 pcieDeviceCapability2; + uint32 pcieLinkCapability2; + uint32 pcieLinkControl; + uint32 pcieLinkCapabilityRc; + uint32 bar3Config; + uint32 rootCap; + uint32 devSerNumCapId; + uint32 lowerSerNum; + uint32 upperSerNum; + uint32 advErrCap; + uint32 pwrBdgtData0; + uint32 pwrBdgtData1; + uint32 pwrBdgtData2; + uint32 pwdBdgtData3; + uint32 pwrBdgtData4; + uint32 pwrBdgtData5; + uint32 pwrBdgtData6; + uint32 pwrBdgtData7; + uint32 pwrBdgtCapability; + uint32 vsecHdr; + uint32 rcUserMemLo1; + uint32 rcUserMemHi1; + uint32 rcUserMemLo2; + uint32 rcUserMemHi2; +}PcieBlk428Regs; + +typedef struct PcieBlk800Regs{ +#define NUM_PCIE_BLK_800_CTRL_REGS 6 + uint32 tlControl[NUM_PCIE_BLK_800_CTRL_REGS]; + uint32 tlCtlStat0; + uint32 pmStatus0; + uint32 pmStatus1; + +#define NUM_PCIE_BLK_800_TAGS 32 + uint32 tlStatus[NUM_PCIE_BLK_800_TAGS]; + uint32 tlHdrFcStatus; + uint32 tlDataFcStatus; + uint32 tlHdrFcconStatus; + uint32 tlDataFcconStatus; + uint32 tlTargetCreditStatus; + uint32 tlCreditAllocStatus; + uint32 tlSmlogicStatus; +} PcieBlk800Regs; + + +typedef struct PcieBlk1000Regs{ +#define NUM_PCIE_BLK_1000_PDL_CTRL_REGS 16 + uint32 pdlControl[NUM_PCIE_BLK_1000_PDL_CTRL_REGS]; + uint32 dlattnVec; + uint32 dlAttnMask; + uint32 dlStatus; /* 0x1048 */ +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK 0x00002000 +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT 13 + uint32 dlTxChecksum; + uint32 dlForcedUpdateGen1; + uint32 mdioAddr; + uint32 mdioWrData; + uint32 mdioRdData; + uint32 dlRxPFcCl; + uint32 dlRxCFcCl; + uint32 dlRxAckNack; + uint32 dlTxRxSeqnb; + uint32 dlTxPFcAl; + uint32 dlTxNpFcAl; + uint32 regDlSpare; + uint32 dlRegSpare; + uint32 dlTxRxSeq; + uint32 dlRxNpFcCl; +}PcieBlk1000Regs; + +typedef struct PcieBlk1800Regs{ +#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS 5 + uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS]; +#define REG_POWERDOWN_P1PLL_ENA (1<<12) + uint32 phyErrorAttnVec; + uint32 phyErrorAttnMask; + uint32 phyReceivedMcpErrors; + uint32 phyTransmittedMcpErrors; + uint32 phyGenDebug; + uint32 phyRecoveryHist; +#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS 3 + uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS]; +#define NUM_PCIE_BLK_1800_PHY_DBG_REGS 11 + uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS]; +} PcieBlk1800Regs; + +typedef struct PcieBridgeRegs{ + uint32 bar1Remap; /* 0x0818*/ +#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK 0xffff0000 +#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK_SHIFT 16 +#define PCIE_BRIDGE_BAR1_REMAP_remap_enable (1<<1) +#define PCIE_BRIDGE_BAR1_REMAP_swap_enable 1 + + uint32 bar2Remap; /* 0x081c*/ +#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK 0xffff0000 +#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK_SHIFT 16 +#define PCIE_BRIDGE_BAR2_REMAP_remap_enable (1<<1) +#define PCIE_BRIDGE_BAR2_REMAP_swap_enable 1 + + uint32 bridgeOptReg1; /* 0x0820*/ +#define PCIE_BRIDGE_OPT_REG1_en_l1_int_status_mask_polarity (1<<12) +#define PCIE_BRIDGE_OPT_REG1_en_pcie_bridge_hole_detection (1<<11) +#define PCIE_BRIDGE_OPT_REG1_en_rd_reply_be_fix (1<<9) +#define PCIE_BRIDGE_OPT_REG1_enable_rd_be_opt (1<<7) + + uint32 bridgeOptReg2; /* 0x0824*/ +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK 0xe0000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT 29 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK 0x1f000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT 24 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK 0x00ff0000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT 16 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK 0x00000080 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT 7 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK 0x00000040 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT 6 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK 0x00000020 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT 5 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK 0x00000010 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT 4 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK 0x00000004 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT 2 +#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK 0x0000ff0b + + uint32 Ubus2PcieBar0BaseMask; /* 0x0828 */ +#define PCIE_BRIDGE_BAR0_BASE_base_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR0_BASE_base_MASK_SHIFT 20 +#define PCIE_BRIDGE_BAR0_BASE_mask_MASK 0x0000fff0 +#define PCIE_BRIDGE_BAR0_BASE_mask_MASK_SHIFT 4 +#define PCIE_BRIDGE_BAR0_BASE_swap_enable (1<<1) +#define PCIE_BRIDGE_BAR0_BASE_remap_enable 1 + + uint32 Ubus2PcieBar0RemapAdd; /* 0x082c */ +#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_SHIFT 20 + + uint32 Ubus2PcieBar1BaseMask; /* 0x0830 */ +#define PCIE_BRIDGE_BAR1_BASE_base_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR1_BASE_base_MASK_SHIFT 20 +#define PCIE_BRIDGE_BAR1_BASE_mask_MASK 0x0000fff0 +#define PCIE_BRIDGE_BAR1_BASE_mask_MASK_SHIFT 4 +#define PCIE_BRIDGE_BAR1_BASE_swap_enable (1<<1) +#define PCIE_BRIDGE_BAR1_BASE_remap_enable 1 + + uint32 Ubus2PcieBar1RemapAdd; /* 0x0834 */ +#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_SHIFT 20 + + uint32 bridgeErrStatus; /* 0x0838 */ + uint32 bridgeErrMask; /* 0x083c */ + uint32 coreErrStatus2; /* 0x0840 */ + uint32 coreErrMask2; /* 0x0844 */ + uint32 coreErrStatus1; /* 0x0848 */ + uint32 coreErrMask1; /* 0x084c */ + uint32 rcInterruptStatus; /* 0x0850 */ + uint32 rcInterruptMask; /* 0x0854 */ +#define PCIE_BRIDGE_INTERRUPT_MASK_int_a_MASK (1<<0) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_b_MASK (1<<1) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_c_MASK (1<<2) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_d_MASK (1<<3) + +}PcieBridgeRegs; + +#define PCIEH_DEV_OFFSET 0x8000 +#define PCIEH ((volatile uint32 * const) PCIE_BASE) +#define PCIEH_REGS ((volatile PcieRegs * const) PCIE_BASE) + +#define PCIEH_BLK_404_REGS ((volatile PcieBlk404Regs * const) \ + (PCIE_BASE+0x404)) +#define PCIEH_BLK_428_REGS ((volatile PcieBlk428Regs * const) \ + (PCIE_BASE+0x428)) +#define PCIEH_BLK_800_REGS ((volatile PcieBlk800Regs * const) \ + (PCIE_BASE+0x800)) +#define PCIEH_BLK_1000_REGS ((volatile PcieBlk1000Regs * const) \ + (PCIE_BASE+0x1000)) +#define PCIEH_BLK_1800_REGS ((volatile PcieBlk1800Regs * const) \ + (PCIE_BASE+0x1800)) +#define PCIEH_BRIDGE_REGS ((volatile PcieBridgeRegs * const) \ + (PCIE_BASE+0x2818)) + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/shared/broadcom/include/bcm963xx/6362_common.h b/shared/broadcom/include/bcm963xx/6362_common.h new file mode 100755 index 0000000..843355a --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6362_common.h @@ -0,0 +1,326 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6362_common.h */ +/* DATE: 02/01/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6362 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6362_MAP_COMMON_H +#define __BCM6362_MAP_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define NAND_INTR_BASE 0xb0000070 /* nand interrupt control registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 +#define OTP_BASE 0xb0000400 +#define UBUS_STAT_BASE 0xb0000500 +#define NAND_CACHE_BASE 0xb0000600 +#define SPI_BASE 0xb0000800 /* SPI master controller registers */ +#define HSSPIM_BASE 0xb0001000 /* High-Speed SPI registers */ +#define ADSL_CTRL_BASE 0xb0001800 +#define MISC_BASE 0xb0001800 /* Miscellaneous Registers */ +#define LED_BASE 0xb0001900 /* LED control registers */ +#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10002500 /* USB host registers */ +#define USB_OHCI_BASE 0x10002600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0002700 +#define IPSEC_BASE 0xb0002800 +#define DDR_BASE 0xb0003000 /* Memory control registers */ +#define WLAN_CHIPC_BASE 0x10004000 /* WLAN ChipCommon registers, use 1xxx for ioremap */ +#define WLAN_MAC_BASE 0x10005000 /* WLAN d11mac registers */ +#define WLAN_SHIM_BASE 0xb0007000 /* shim interface to WLAN */ +#define PCM_BASE 0xb000a000 +#define PCM_DMA_BASE 0xb000a800 /* PCM UIDMA register base */ +#define SAR_DMA_BASE 0xb000b800 /* ATM SAR DMA control registers */ +#define USB_DMA_BASE 0xb000c000 /* USB 2.0 device DMA regiseters */ +#define IPSEC_DMA_BASE 0xb000d000 +#define SWITCH_DMA_BASE 0xb000d800 +#define SWITCH_BASE 0xb0e00000 +#define PCIE_BASE 0xb0e40000 +#define DECT_SHIM_CTRL_BASE 0xb000b000 +#define DECT_SHIM_DMA_CTRL_BASE 0xb000b050 +#define DECT_SHIM_TEST_BASE 0xb000b0f0 +#define DECT_APB_REG_BASE 0xb000e000 +#define DECT_AHB_SHARED_RAM_BASE 0xb0e50000 +#define DECT_AHB_REG_BASE 0xb0e57f80 + + +/* +##################################################################### +# System PLL Control Register +##################################################################### +*/ + +/* +##################################################################### +# GPIO Control Registers +##################################################################### +*/ +/* +##################################################################### +# Miscellaneous Registers +##################################################################### +*/ +#define MISC_MEMC_CONTROL 0x10 +#define MISC_STRAP_BUS 0x14 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 1 + +#define MISC_VREG_CONTROL0 0x1C +#define MISC_VREG_CONTROL0_VREG_ADJ_SHIFT 8 +#define MISC_VREG_CONTROL0_VREG_OSC1P2_SHIFT 20 +#define MISC_VREG_CONTROL0_VREG_OSC1P8_SHIFT 22 +#define MISC_VREG_CONTROL0_VREG_RAMP1P2_SHIFT 26 +#define MISC_VREG_CONTROL0_VREG_RAMP1P8_SHIFT 29 + +#define MISC_VREG_CONTROL1 0x20 +#define MISC_VREG_CONTROL1_VREG_ISEL2P5_SHIFT 13 +#define MISC_VREG_CONTROL1_VREG_ISEL2P5_MASK 0x0001e000 +#define MISC_VREG_LDO_2P61 1 + +#define MISC_VREG_CONTROL2 0x24 + +/* +##################################################################### +# Memory Control Registers +##################################################################### +*/ +#define DDR_CTL_CNFG 0x000 +#define DDR_CTL_CSST 0x004 +#define DDR_CTL_CSEND 0x008 +#define DDR_CTL_ROW00_0 0x010 +#define DDR_CTL_ROW00_1 0x014 +#define DDR_CTL_ROW01_0 0x018 +#define DDR_CTL_ROW01_1 0x01c +#define DDR_CTL_ROW20_0 0x030 +#define DDR_CTL_ROW20_1 0x034 +#define DDR_CTL_ROW21_0 0x038 +#define DDR_CTL_ROW21_1 0x03c +#define DDR_CTL_COL00_0 0x050 +#define DDR_CTL_COL00_1 0x054 +#define DDR_CTL_COL01_0 0x058 +#define DDR_CTL_COL01_1 0x05c +#define DDR_CTL_COL20_0 0x070 +#define DDR_CTL_COL20_1 0x074 +#define DDR_CTL_COL21_0 0x078 +#define DDR_CTL_COL21_1 0x07c +#define DDR_CTL_BNK10 0x090 +#define DDR_CTL_BNK32 0x094 +#define DDR_CTL_DCMD 0x100 +#define DDR_CTL_DMODE_0 0x104 +#define DDR_CTL_DMODE_1 0x108 +#define DDR_CTL_CLKS 0x10c +#define DDR_CTL_ODT 0x110 +#define DDR_CTL_TIM1_0 0x114 +#define DDR_CTL_TIM1_1 0x118 +#define DDR_CTL_TIM2 0x11c +#define DDR_CTL_CTL_CRC 0x120 +#define DDR_CTL_DOUT_CRC 0x124 +#define DDR_CTL_DIN_CRC 0x128 +#define PHY_CONTROL_REGS_REVISION 0x200 +#define PHY_CONTROL_REGS_CLK_PM_CTRL 0x204 +#define PHY_CONTROL_REGS_PLL_STATUS 0x210 +#define PHY_CONTROL_REGS_PLL_CONFIG 0x214 +#define PHY_CONTROL_REGS_PLL_PRE_DIVIDER 0x218 +#define PHY_CONTROL_REGS_PLL_DIVIDER 0x21c +#define PHY_CONTROL_REGS_PLL_CONTROL1 0x220 +#define PHY_CONTROL_REGS_PLL_CONTROL2 0x224 +#define PHY_CONTROL_REGS_PLL_SS_EN 0x228 +#define PHY_CONTROL_REGS_PLL_SS_CFG 0x22c +#define PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE 0x230 +#define PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE 0x234 +#define PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x238 +#define PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL 0x23c +#define PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x240 +#define PHY_BYTE_LANE_0_REVISION 0x300 +#define PHY_BYTE_LANE_0_VDL_CALIBRATE 0x304 +#define PHY_BYTE_LANE_0_VDL_STATUS 0x308 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_0 0x310 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_1 0x314 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_2 0x318 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_3 0x31c +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_4 0x320 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_5 0x324 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_6 0x328 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_7 0x32c +#define PHY_BYTE_LANE_0_READ_CONTROL 0x330 +#define PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x334 +#define PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x338 +#define PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x33c +#define PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x340 +#define PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE 0x344 +#define PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x348 +#define PHY_BYTE_LANE_1_REVISION 0x400 +#define PHY_BYTE_LANE_1_VDL_CALIBRATE 0x404 +#define PHY_BYTE_LANE_1_VDL_STATUS 0x408 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_0 0x410 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_1 0x414 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_2 0x418 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_3 0x41c +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_4 0x420 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_5 0x424 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_6 0x428 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_7 0x42c +#define PHY_BYTE_LANE_1_READ_CONTROL 0x430 +#define PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x434 +#define PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x438 +#define PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x43c +#define PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x440 +#define PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE 0x444 +#define PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x448 +#define PHY_BYTE_LANE_2_REVISION 0x500 +#define PHY_BYTE_LANE_2_VDL_CALIBRATE 0x504 +#define PHY_BYTE_LANE_2_VDL_STATUS 0x508 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_0 0x510 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_1 0x514 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_2 0x518 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_3 0x51c +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_4 0x520 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_5 0x524 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_6 0x528 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_7 0x52c +#define PHY_BYTE_LANE_2_READ_CONTROL 0x530 +#define PHY_BYTE_LANE_2_READ_FIFO_STATUS 0x534 +#define PHY_BYTE_LANE_2_READ_FIFO_CLEAR 0x538 +#define PHY_BYTE_LANE_2_IDLE_PAD_CONTROL 0x53c +#define PHY_BYTE_LANE_2_DRIVE_PAD_CTL 0x540 +#define PHY_BYTE_LANE_2_CLOCK_PAD_DISABLE 0x544 +#define PHY_BYTE_LANE_2_WR_PREAMBLE_MODE 0x548 +#define PHY_BYTE_LANE_3_REVISION 0x600 +#define PHY_BYTE_LANE_3_VDL_CALIBRATE 0x604 +#define PHY_BYTE_LANE_3_VDL_STATUS 0x608 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_0 0x610 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_1 0x614 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_2 0x618 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_3 0x61c +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_4 0x620 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_5 0x624 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_6 0x628 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_7 0x62c +#define PHY_BYTE_LANE_3_READ_CONTROL 0x630 +#define PHY_BYTE_LANE_3_READ_FIFO_STATUS 0x634 +#define PHY_BYTE_LANE_3_READ_FIFO_CLEAR 0x638 +#define PHY_BYTE_LANE_3_IDLE_PAD_CONTROL 0x63c +#define PHY_BYTE_LANE_3_DRIVE_PAD_CTL 0x640 +#define PHY_BYTE_LANE_3_CLOCK_PAD_DISABLE 0x644 +#define PHY_BYTE_LANE_3_WR_PREAMBLE_MODE 0x648 +#define DDR_CTL_GCFG 0x800 +#define DDR_CTL_LBIST_CFG 0x804 +#define DDR_CTL_LBIST_SEED 0x808 +#define DDR_CTL_ARB 0x80c +#define DDR_CTL_PI_GCF 0x810 +#define DDR_CTL_PI_UBUS_CTL 0x814 +#define DDR_CTL_PI_MIPS_CTL 0x818 +#define DDR_CTL_PI_DSL_MIPS_CTL 0x81c +#define DDR_CTL_PI_DSL_PHY_CTL 0x820 +#define DDR_CTL_PI_UBUS_ST 0x824 +#define DDR_CTL_PI_MIPS_ST 0x828 +#define DDR_CTL_PI_DSL_MIPS_ST 0x82c +#define DDR_CTL_PI_DSL_PHY_ST 0x830 +#define DDR_CTL_PI_UBUS_SMPL 0x834 +#define DDR_CTL_TESTMODE 0x838 +#define DDR_CTL_TEST_CFG1 0x83c +#define DDR_CTL_TEST_PAT 0x840 +#define DDR_CTL_TEST_COUNT 0x844 +#define DDR_CTL_TEST_CURR_COUNT 0x848 +#define DDR_CTL_TEST_ADDR_UPDT 0x84c +#define DDR_CTL_TEST_ADDR 0x850 +#define DDR_CTL_TEST_DATA0 0x854 +#define DDR_CTL_TEST_DATA1 0x858 +#define DDR_CTL_TEST_DATA2 0x85c +#define DDR_CTL_TEST_DATA3 0x860 + + +/* +##################################################################### +# UART Control Registers +##################################################################### +*/ +#define UART0CONTROL 0x01 +#define UART0CONFIG 0x02 +#define UART0RXTIMEOUT 0x03 +#define UART0BAUD 0x04 +#define UART0FIFOCFG 0x0a +#define UART0INTMASK 0x10 +#define UART0INTSTAT 0x12 +#define UART0DATA 0x17 + +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + +#define XMITBREAK 0x40 /* Config register */ +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + + +/* +##################################################################### +# DECT IP Control Registers +##################################################################### +*/ +#define DECT_STARTCTL 0xb0e50818 +#define PCM_BUFF_CTL3 0xb0e5082c +#define PCM_BUFF_CTL7 0xb0e5083c +#define DECT_AHB_CHAN0_RX 0xb0e50a20 +#define DECT_AHB_CHAN1_RX 0xb0e50de0 +#define DECT_AHB_CHAN2_RX 0xb0e511a0 +#define DECT_AHB_CHAN3_RX 0xb0e51560 +#define DECT_AHB_CHAN0_TX 0xb0e50840 +#define DECT_AHB_CHAN1_TX 0xb0e50c00 +#define DECT_AHB_CHAN2_TX 0xb0e50fc0 +#define DECT_AHB_CHAN3_TX 0xb0e51380 +#define DECT_CLKEN 0x00000040 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/broadcom/include/bcm963xx/6362_map.h b/shared/broadcom/include/bcm963xx/6362_map.h new file mode 100755 index 0000000..d0fa38f --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6362_map.h @@ -0,0 +1,2251 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6362_map.h */ +/* DATE: 05/30/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6362 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6362_MAP_H +#define __BCM6362_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "bcmtypes.h" +#include "6362_common.h" +#include "6362_intr.h" + +/* macro to convert logical data addresses to physical */ +/* DMA hardware must see physical address */ +#define LtoP( x ) ( (uint32)x & 0x1fffffff ) +#define PtoL( x ) ( LtoP(x) | 0xa0000000 ) + +typedef struct DDRPhyControl { + uint32 REVISION; /* 0x00 */ + uint32 CLK_PM_CTRL; /* 0x04 */ + uint32 unused0[2]; /* 0x08-0x10 */ + uint32 PLL_STATUS; /* 0x10 */ + uint32 PLL_CONFIG; /* 0x14 */ + uint32 PLL_PRE_DIVIDER; /* 0x18 */ + uint32 PLL_DIVIDER; /* 0x1c */ + uint32 PLL_CONTROL1; /* 0x20 */ + uint32 PLL_CONTROL2; /* 0x24 */ + uint32 PLL_SS_EN; /* 0x28 */ + uint32 PLL_SS_CFG; /* 0x2c */ + uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ + uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ + uint32 IDLE_PAD_CONTROL; /* 0x38 */ + uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_REG_CONTROL; /* 0x44 */ + uint32 unused1[46]; +} DDRPhyControl; + +typedef struct DDRPhyByteLaneControl { + uint32 REVISION; /* 0x00 */ + uint32 VDL_CALIBRATE; /* 0x04 */ + uint32 VDL_STATUS; /* 0x08 */ + uint32 unused; /* 0x0c */ + uint32 VDL_OVERRIDE_0; /* 0x10 */ + uint32 VDL_OVERRIDE_1; /* 0x14 */ + uint32 VDL_OVERRIDE_2; /* 0x18 */ + uint32 VDL_OVERRIDE_3; /* 0x1c */ + uint32 VDL_OVERRIDE_4; /* 0x20 */ + uint32 VDL_OVERRIDE_5; /* 0x24 */ + uint32 VDL_OVERRIDE_6; /* 0x28 */ + uint32 VDL_OVERRIDE_7; /* 0x2c */ + uint32 READ_CONTROL; /* 0x30 */ + uint32 READ_FIFO_STATUS; /* 0x34 */ + uint32 READ_FIFO_CLEAR; /* 0x38 */ + uint32 IDLE_PAD_CONTROL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_PAD_DISABLE; /* 0x44 */ + uint32 WR_PREAMBLE_MODE; /* 0x48 */ + uint32 CLOCK_REG_CONTROL; /* 0x4C */ + uint32 unused0[44]; +} DDRPhyByteLaneControl; + +typedef struct DDRControl { + uint32 CNFG; /* 0x000 */ + uint32 CSST; /* 0x004 */ + uint32 CSEND; /* 0x008 */ + uint32 unused; /* 0x00c */ + uint32 ROW00_0; /* 0x010 */ + uint32 ROW00_1; /* 0x014 */ + uint32 ROW01_0; /* 0x018 */ + uint32 ROW01_1; /* 0x01c */ + uint32 unused0[4]; + uint32 ROW20_0; /* 0x030 */ + uint32 ROW20_1; /* 0x034 */ + uint32 ROW21_0; /* 0x038 */ + uint32 ROW21_1; /* 0x03c */ + uint32 unused1[4]; + uint32 COL00_0; /* 0x050 */ + uint32 COL00_1; /* 0x054 */ + uint32 COL01_0; /* 0x058 */ + uint32 COL01_1; /* 0x05c */ + uint32 unused2[4]; + uint32 COL20_0; /* 0x070 */ + uint32 COL20_1; /* 0x074 */ + uint32 COL21_0; /* 0x078 */ + uint32 COL21_1; /* 0x07c */ + uint32 unused3[4]; + uint32 BNK10; /* 0x090 */ + uint32 BNK32; /* 0x094 */ + uint32 unused4[26]; + uint32 DCMD; /* 0x100 */ +#define DCMD_CS1 (1 << 5) +#define DCMD_CS0 (1 << 4) +#define DCMD_SET_SREF 4 + uint32 DMODE_0; /* 0x104 */ + uint32 DMODE_1; /* 0x108 */ +#define DMODE_1_DRAMSLEEP (1 << 11) + uint32 CLKS; /* 0x10c */ + uint32 ODT; /* 0x110 */ + uint32 TIM1_0; /* 0x114 */ + uint32 TIM1_1; /* 0x118 */ + uint32 TIM2; /* 0x11c */ + uint32 CTL_CRC; /* 0x120 */ + uint32 DOUT_CRC; /* 0x124 */ + uint32 DIN_CRC; /* 0x128 */ + uint32 unused5[53]; + + DDRPhyControl PhyControl; /* 0x200 */ + DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ + DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ + DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ + DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ + uint32 unused6[64]; + + uint32 GCFG; /* 0x800 */ + uint32 LBIST_CFG; /* 0x804 */ + uint32 LBIST_SEED; /* 0x808 */ + uint32 ARB; /* 0x80c */ + uint32 PI_GCF; /* 0x810 */ + uint32 PI_UBUS_CTL; /* 0x814 */ + uint32 PI_MIPS_CTL; /* 0x818 */ + uint32 PI_DSL_MIPS_CTL; /* 0x81c */ + uint32 PI_DSL_PHY_CTL; /* 0x820 */ + uint32 PI_UBUS_ST; /* 0x824 */ + uint32 PI_MIPS_ST; /* 0x828 */ + uint32 PI_DSL_MIPS_ST; /* 0x82c */ + uint32 PI_DSL_PHY_ST; /* 0x830 */ + uint32 PI_UBUS_SMPL; /* 0x834 */ + uint32 TESTMODE; /* 0x838 */ + uint32 TEST_CFG1; /* 0x83c */ + uint32 TEST_PAT; /* 0x840 */ + uint32 TEST_COUNT; /* 0x844 */ + uint32 TEST_CURR_COUNT; /* 0x848 */ + uint32 TEST_ADDR_UPDT; /* 0x84c */ + uint32 TEST_ADDR; /* 0x850 */ + uint32 TEST_DATA0; /* 0x854 */ + uint32 TEST_DATA1; /* 0x858 */ + uint32 TEST_DATA2; /* 0x85c */ + uint32 TEST_DATA3; /* 0x860 */ +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define NAND_CLK_EN (1 << 20) +#define PHYMIPS_CLK_EN (1 << 19) +#define FAP_CLK_EN (1 << 18) +#define PCIE_CLK_EN (1 << 17) +#define HS_SPI_CLK_EN (1 << 16) +#define SPI_CLK_EN (1 << 15) +#define IPSEC_CLK_EN (1 << 14) +#define USBH_CLK_EN (1 << 13) +#define USBD_CLK_EN (1 << 12) +#define PCM_CLK_EN (1 << 11) +#define ROBOSW_CLK_EN (1 << 10) +#define SAR_CLK_EN (1 << 9) +#define SWPKT_SAR_CLK_EN (1 << 8) +#define SWPKT_USB_CLK_EN (1 << 7) +#define WLAN_OCP_CLK_EN (1 << 5) +#define MIPS_CLK_EN (1 << 4) +#define ADSL_CLK_EN (1 << 3) +#define ADSL_AFE_EN (1 << 2) +#define ADSL_QPROC_EN (1 << 1) +#define DISABLE_GLESS (1 << 0) + + uint32 pll_control; /* (08) word 2 */ +#define SOFT_RESET 0x00000001 // 0 + + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_WLAN_SHIM_UBUS (1 << 14) +#define SOFT_RST_FAP (1 << 13) +#define SOFT_RST_DDR_PHY (1 << 12) +#define SOFT_RST_WLAN_SHIM (1 << 11) +#define SOFT_RST_PCIE_EXT (1 << 10) +#define SOFT_RST_PCIE (1 << 9) +#define SOFT_RST_PCIE_CORE (1 << 8) +#define SOFT_RST_PCM (1 << 7) +#define SOFT_RST_USBH (1 << 6) +#define SOFT_RST_USBD (1 << 5) +#define SOFT_RST_SWITCH (1 << 4) +#define SOFT_RST_SAR (1 << 3) +#define SOFT_RST_EPHY (1 << 2) +#define SOFT_RST_IPSEC (1 << 1) +#define SOFT_RST_SPI (1 << 0) + + uint32 diagControl; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 unused1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo<thresh + */ + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1) + * if these bits are also enabled to GPIO_o + */ +#define DTREN 0x01 +#define RTSEN 0x02 + + byte unused1; + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to + * detect irq on rising AND falling + * edges for corresponding GPIO_i + * if enabled (edge insensitive) + */ + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense + * 0 for negedge sense if + * not configured for edge + * insensitive (see above) + * Lower 4 bits: Mask to enable change + * detection IRQ for corresponding + * GPIO_i + */ + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits + * have changed (may set IRQ). + * read automatically clears bit + * Lower 4 bits are actual status + */ + + uint16 intMask; /* Same Bit defs for Mask and status */ + uint16 intStatus; +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + + uint16 unused2; + uint16 Data; /* Write to TX, Read from RX */ + /* bits 11:8 are BRK,PAR,FRM errors */ + + uint32 unused3; + uint32 unused4; +} Uart; + +#define UART ((volatile Uart * const) UART_BASE) + +/* +** Gpio Controller +*/ + +typedef struct GpioControl { + uint64 GPIODir; /* 0 */ + uint64 GPIOio; /* 8 */ + uint32 LEDCtrl; /* 10 */ + uint32 SpiSlaveCfg; /* 14 */ + uint32 GPIOMode; /* 18 */ +#define GPIO_MODE_EXT_IRQ3 (1<<27) +#define GPIO_MODE_EXT_IRQ2 (1<<26) +#define GPIO_MODE_EXT_IRQ1 (1<<25) +#define GPIO_MODE_EXT_IRQ0 (1<<24) +#define GPIO_MODE_EPHY3_LED (1<<23) +#define GPIO_MODE_EPHY2_LED (1<<22) +#define GPIO_MODE_EPHY1_LED (1<<21) +#define GPIO_MODE_EPHY0_LED (1<<20) +#define GPIO_MODE_ADSL_SPI_SSB (1<<19) +#define GPIO_MODE_ADSL_SPI_CLK (1<<18) +#define GPIO_MODE_ADSL_SPI_MOSI (1<<17) +#define GPIO_MODE_ADSL_SPI_MISO (1<<16) +#define GPIO_MODE_UART2_SDOUT (1<<15) +#define GPIO_MODE_UART2_SDIN (1<<14) +#define GPIO_MODE_UART2_SRTS (1<<13) +#define GPIO_MODE_UART2_SCTS (1<<12) +#define GPIO_MODE_NTR_PULSE (1<<11) +#define GPIO_MODE_LS_SPIM_SSB3 (1<<10) +#define GPIO_MODE_LS_SPIM_SSB2 (1<<9) +#define GPIO_MODE_INET_LED (1<<8) +#define GPIO_MODE_ROBOSW_LED1 (1<<7) +#define GPIO_MODE_ROBOSW_LED0 (1<<6) +#define GPIO_MODE_ROBOSW_LED_CLK (1<<5) +#define GPIO_MODE_ROBOSW_LED_DATA (1<<4) +#define GPIO_MODE_SERIAL_LED_DATA (1<<3) +#define GPIO_MODE_SERIAL_LED_CLK (1<<2) +#define GPIO_MODE_SYS_IRQ (1<<1) +#define GPIO_MODE_USBD_LED (1<<0) + + uint32 GPIOCtrl; /* 1C */ + uint32 unused3[2]; /* 20 - 24*/ + uint32 TestControl; /* 28 */ + uint32 OscControl; /* 2C */ + uint32 RoboSWLEDControl; /* 30 */ + uint32 RoboSWLEDLSR; /* 34 */ + uint32 GPIOBaseMode; /* 38 */ +#define NAND_GPIO_OVERRIDE (1<<2) + uint32 RoboswEphyCtrl; /* 3C */ +#define EPHY_PLL_LOCK (1<<27) +#define EPHY_ATEST_25MHZ_EN (1<<26) +#define EPHY_PWR_DOWN_DLL (1<<25) +#define EPHY_PWR_DOWN_BIAS (1<<24) +#define EPHY_PWR_DOWN_TX_4 (1<<23) +#define EPHY_PWR_DOWN_TX_3 (1<<22) +#define EPHY_PWR_DOWN_TX_2 (1<<21) +#define EPHY_PWR_DOWN_TX_1 (1<<20) +#define EPHY_PWR_DOWN_RX_4 (1<<19) +#define EPHY_PWR_DOWN_RX_3 (1<<18) +#define EPHY_PWR_DOWN_RX_2 (1<<17) +#define EPHY_PWR_DOWN_RX_1 (1<<16) +#define EPHY_PWR_DOWN_SD_4 (1<<15) +#define EPHY_PWR_DOWN_SD_3 (1<<14) +#define EPHY_PWR_DOWN_SD_2 (1<<13) +#define EPHY_PWR_DOWN_SD_1 (1<<12) +#define EPHY_PWR_DOWN_RD_4 (1<<11) +#define EPHY_PWR_DOWN_RD_3 (1<<10) +#define EPHY_PWR_DOWN_RD_2 (1<<9) +#define EPHY_PWR_DOWN_RD_1 (1<<8) +#define EPHY_PWR_DOWN_4 (1<<7) +#define EPHY_PWR_DOWN_3 (1<<6) +#define EPHY_PWR_DOWN_2 (1<<5) +#define EPHY_PWR_DOWN_1 (1<<4) +#define EPHY_RST_4 (1<<3) +#define EPHY_RST_3 (1<<2) +#define EPHY_RST_2 (1<<1) +#define EPHY_RST_1 (1<<0) + uint32 RoboswSwitchCtrl; /* 40 */ +#define RSW_MII_2_IFC_EN (1<<23) +#define RSW_MII_2_AMP_EN (1<<22) +#define RSW_MII_2_SEL_SHIFT 20 +#define RSW_MII_SEL_3P3V 0 +#define RSW_MII_SEL_2P5V 1 +#define RSW_MII_SEL_1P5V 2 +#define RSW_MII_AMP_EN (1<<18) +#define RSW_MII_SEL_SHIFT 16 +#define RSW_SPI_MODE (1<<11) +#define RSW_BC_SUPP_EN (1<<10) +#define RSW_CLK_FREQ_MASK (3<<8) +#define RSW_ENF_DFX_FLOW (1<<7) +#define RSW_ENH_DFX_FLOW (1<<6) +#define RSW_GRX_0_SETUP (1<<5) +#define RSW_GTX_0_SETUP (1<<4) +#define RSW_HW_FWDG_EN (1<<3) +#define RSW_QOS_EN (1<<2) +#define RSW_WD_CLR_EN (1<<1) +#define RSW_MII_DUMB_FWDG_EN (1<<0) + + uint32 RegFileTmCtl; /* 44 */ + + uint32 RingOscCtrl0; /* 48 */ +#define RING_OSC_256_CYCLES 8 +#define RING_OSC_512_CYCLES 9 +#define RING_OSC_1024_CYCLES 10 + + uint32 RingOscCtrl1; /* 4C */ +#define RING_OSC_ENABLE_MASK (0x0f<<24) +#define RING_OSC_ENABLE_SHIFT 24 +#define RING_OSC_MAX 4 +#define RING_OSC_COUNT_RESET (0x1<<23) +#define RING_OSC_SELECT_MASK (0x7<<20) +#define RING_OSC_SELECT_SHIFT 20 +#define RING_OSC_IRQ (0x1<<18) +#define RING_OSC_COUNTER_OVERFLOW (0x1<<17) +#define RING_OSC_COUNTER_BUSY (0x1<<16) +#define RING_OSC_COUNT_MASK 0x0000ffff + + uint32 unused4[6]; /* 50 - 64 */ + uint32 DieRevID; /* 68 */ + uint32 unused5; /* 6c */ + uint32 DiagSelControl; /* 70 */ + uint32 DiagReadBack; /* 74 */ + uint32 DiagReadBackHi; /* 78 */ + uint32 DiagMiscControl; /* 7c */ +} GpioControl; + +#define GPIO ((volatile GpioControl * const) GPIO_BASE) + +/* Number to mask conversion macro used for GPIODir and GPIOio */ +#define GPIO_NUM_MAX 48 +#define GPIO_NUM_TO_MASK(X) ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) ) + +/* +** OTP +*/ +typedef struct Otp { + uint32 Config; /* 0x0 */ + uint32 Control; /* 0x4 */ + uint32 Addr; /* 0x8 */ + uint32 WriteData; /* 0xc */ + uint32 Status; /* 0x10 */ + uint32 DOut; /* 0x14 */ + uint32 UserBits[8]; /* 0x18 - 0x34 */ +#define OTP_WLAN_DISABLE 34 +#define OTP_DECT_DISABLE 38 +#define OTP_IPSED_DISABLE 39 + uint32 unused[2]; /* 0x38 - 0x3c */ + uint32 RAMRepair[16]; /* 0x40 - 0x7c */ +} Otp; + +#define OTP ((volatile Otp * const) OTP_BASE) + +/* Word order is reversed for User OTP bits */ +#define OTP_GET_USER_BIT(x) ((OTP->UserBits[((sizeof(OTP->UserBits)/4) - (x)/32 - 1)] >> ((x) % 32)) & 1) + +/* +** Spi Controller +*/ + +typedef struct SpiControl { + uint16 spiMsgCtl; /* (0x0) control byte */ +#define FULL_DUPLEX_RW 0 +#define HALF_DUPLEX_W 1 +#define HALF_DUPLEX_R 2 +#define SPI_MSG_TYPE_SHIFT 14 +#define SPI_BYTE_CNT_SHIFT 0 + byte spiMsgData[0x21e]; /* (0x02 - 0x21f) msg data */ + byte unused0[0x1e0]; + byte spiRxDataFifo[0x220]; /* (0x400 - 0x61f) rx data */ + byte unused1[0xe0]; + + uint16 spiCmd; /* (0x700): SPI command */ +#define SPI_CMD_NOOP 0 +#define SPI_CMD_SOFT_RESET 1 +#define SPI_CMD_HARD_RESET 2 +#define SPI_CMD_START_IMMEDIATE 3 + +#define SPI_CMD_COMMAND_SHIFT 0 +#define SPI_CMD_COMMAND_MASK 0x000f + +#define SPI_CMD_DEVICE_ID_SHIFT 4 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 +#define SPI_CMD_ONE_BYTE_SHIFT 11 +#define SPI_CMD_ONE_WIRE_SHIFT 12 +#define SPI_DEV_ID_0 0 +#define SPI_DEV_ID_1 1 +#define SPI_DEV_ID_2 2 +#define SPI_DEV_ID_3 3 + + byte spiIntStatus; /* (0x702): SPI interrupt status */ + byte spiMaskIntStatus; /* (0x703): SPI masked interrupt status */ + + byte spiIntMask; /* (0x704): SPI interrupt mask */ +#define SPI_INTR_CMD_DONE 0x01 +#define SPI_INTR_RX_OVERFLOW 0x02 +#define SPI_INTR_INTR_TX_UNDERFLOW 0x04 +#define SPI_INTR_TX_OVERFLOW 0x08 +#define SPI_INTR_RX_UNDERFLOW 0x10 +#define SPI_INTR_CLEAR_ALL 0x1f + + byte spiStatus; /* (0x705): SPI status */ +#define SPI_RX_EMPTY 0x02 +#define SPI_CMD_BUSY 0x04 +#define SPI_SERIAL_BUSY 0x08 + + byte spiClkCfg; /* (0x706): SPI clock configuration */ +#define SPI_CLK_0_391MHZ 1 +#define SPI_CLK_0_781MHZ 2 /* default */ +#define SPI_CLK_1_563MHZ 3 +#define SPI_CLK_3_125MHZ 4 +#define SPI_CLK_6_250MHZ 5 +#define SPI_CLK_12_50MHZ 6 +#define SPI_CLK_MASK 0x07 +#define SPI_SSOFFTIME_MASK 0x38 +#define SPI_SSOFFTIME_SHIFT 3 +#define SPI_BYTE_SWAP 0x80 + + byte spiFillByte; /* (0x707): SPI fill byte */ + byte unused2; + byte spiMsgTail; /* (0x709): msgtail */ + byte unused3; + byte spiRxTail; /* (0x70B): rxtail */ +} SpiControl; + +#define SPI ((volatile SpiControl * const) SPI_BASE) + + +/* +** High-Speed SPI Controller +*/ + +#define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start) +typedef struct HsSpiControl { + + uint32 hs_spiGlobalCtrl; // 0x0000 +#define HS_SPI_MOSI_IDLE (1 << 18) +#define HS_SPI_CLK_POLARITY (1 << 17) +#define HS_SPI_CLK_GATE_SSOFF (1 << 16) +#define HS_SPI_PLL_CLK_CTRL (8) +#define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL) +#define HS_SPI_SS_POLARITY (0) +#define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY) + + uint32 hs_spiExtTrigCtrl; // 0x0004 +#define HS_SPI_TRIG_RAW_STATE (24) +#define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE) +#define HS_SPI_TRIG_LATCHED (16) +#define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED) +#define HS_SPI_TRIG_SENSE (8) +#define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE) +#define HS_SPI_TRIG_TYPE (0) +#define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE) +#define HS_SPI_TRIG_TYPE_EDGE (0) +#define HS_SPI_TRIG_TYPE_LEVEL (1) + + uint32 hs_spiIntStatus; // 0x0008 +#define HS_SPI_IRQ_PING1_USER (28) +#define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER) +#define HS_SPI_IRQ_PING0_USER (24) +#define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER) + +#define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQ_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQ_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntStatusMasked; // 0x000C +#define HS_SPI_IRQSM__PING1_USER (28) +#define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER) +#define HS_SPI_IRQSM__PING0_USER (24) +#define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER) + +#define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntMask; // 0x0010 +#define HS_SPI_IRQM_PING1_USER (28) +#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER) +#define HS_SPI_IRQM_PING0_USER (24) +#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER) + +#define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQM_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQM_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0) + +#define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F) + + uint32 hs_spiFlashCtrl; // 0x0014 +#define HS_SPI_FCTRL_MB_ENABLE (1 << 23) +#define HS_SPI_FCTRL_SS_NUM (20) +#define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM) +#define HS_SPI_FCTRL_PROFILE_NUM (16) +#define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM) +#define HS_SPI_FCTRL_DUMMY_BYTES (10) +#define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES (8) +#define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES_2 (0) +#define HS_SPI_FCTRL_ADDR_BYTES_3 (1) +#define HS_SPI_FCTRL_ADDR_BYTES_4 (2) +#define HS_SPI_FCTRL_READ_OPCODE (0) +#define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE) + + uint32 hs_spiFlashAddrBase; // 0x0018 + + char fill0[0x80 - 0x18]; + + uint32 hs_spiPP_0_Cmd; // 0x0080 +#define HS_SPI_PP_SS_NUM (12) +#define HS_SPI_PP_SS_NUM_MASK __mask(14, HS_SPI_PP_SS_NUM) +#define HS_SPI_PP_PROFILE_NUM (8) +#define HS_SPI_PP_PROFILE_NUM_MASK __mask(10, HS_SPI_PP_PROFILE_NUM) + +} HsSpiControl; + +typedef struct HsSpiPingPong { + + uint32 command; +#define HS_SPI_SS_NUM (12) +#define HS_SPI_PROFILE_NUM (8) +#define HS_SPI_TRIGGER_NUM (4) +#define HS_SPI_COMMAND_VALUE (0) + #define HS_SPI_COMMAND_NOOP (0) + #define HS_SPI_COMMAND_START_NOW (1) + #define HS_SPI_COMMAND_START_TRIGGER (2) + #define HS_SPI_COMMAND_HALT (3) + #define HS_SPI_COMMAND_FLUSH (4) + + uint32 status; +#define HS_SPI_ERROR_BYTE_OFFSET (16) +#define HS_SPI_WAIT_FOR_TRIGGER (2) +#define HS_SPI_SOURCE_BUSY (1) +#define HS_SPI_SOURCE_GNT (0) + + uint32 fifo_status; + uint32 control; + +} HsSpiPingPong; + +typedef struct HsSpiProfile { + + uint32 clk_ctrl; +#define HS_SPI_ACCUM_RST_ON_LOOP (15) +#define HS_SPI_SPI_CLK_2X_SEL (14) +#define HS_SPI_FREQ_CTRL_WORD (0) + + uint32 signal_ctrl; +#define HS_SPI_ASYNC_INPUT_PATH (1 << 16) +#define HS_SPI_LAUNCH_RISING (1 << 13) +#define HS_SPI_LATCH_RISING (1 << 12) + + uint32 mode_ctrl; +#define HS_SPI_PREPENDBYTE_CNT (24) +#define HS_SPI_MODE_ONE_WIRE (20) +#define HS_SPI_MULTIDATA_WR_SIZE (18) +#define HS_SPI_MULTIDATA_RD_SIZE (16) +#define HS_SPI_MULTIDATA_WR_STRT (12) +#define HS_SPI_MULTIDATA_RD_STRT (8) +#define HS_SPI_FILLBYTE (0) + + uint32 polling_config; + uint32 polling_and_mask; + uint32 polling_compare; + uint32 polling_timeout; + uint32 reserved; + +} HsSpiProfile; + +#define HS_SPI_OP_CODE 13 + #define HS_SPI_OP_SLEEP (0) + #define HS_SPI_OP_READ_WRITE (1) + #define HS_SPI_OP_WRITE (2) + #define HS_SPI_OP_READ (3) + #define HS_SPI_OP_SETIRQ (4) + +#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE) +#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80)) +#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0)) +#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100)) +#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200)) +#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400)) + + +/* +** Misc Register Set Definitions. +*/ + +typedef struct Misc { + uint32 unused1; /* 0x00 */ + uint32 miscSerdesCtrl; /* 0x04 */ +#define SERDES_PCIE_ENABLE 0x00000001 +#define SERDES_PCIE_EXD_ENABLE (1<<15) + + uint32 miscSerdesSts; /* 0x08 */ + uint32 miscIrqOutMask; /* 0x0C */ +#define MISC_PCIE_EP_IRQ_MASK0 (1<<0) +#define MISC_PCIE_EP_IRQ_MASK1 (1<<1) + + uint32 miscMemcControl; /* 0x10 */ +#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE (1<<3) +#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE (1<<2) +#define MISC_MEMC_CONTROL_DDR_TEST_DONE (1<<1) +#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE (1<<0) + + uint32 miscStrapBus; /* 0x14 */ +#define MISC_STRAP_BUS_RESET_CFG_DELAY (1<<18) +#define MISC_STRAP_BUS_RESET_OUT_SHIFT 16 +#define MISC_STRAP_BUS_RESET_OUT_MASK (3<<MISC_STRAP_BUS_RESET_OUT_SHIFT) +#define MISC_STRAP_BUS_BOOT_SEL_SHIFT 15 +#define MISC_STRAP_BUS_BOOT_SEL_MASK (0x1<<MISC_STRAP_BUS_BOOT_SEL_SHIFT) +#define MISC_STRAP_BUS_BOOT_SERIAL 0x01 +#define MISC_STRAP_BUS_BOOT_NAND 0x00 +#define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR (1<<14) +#define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR (1<<14) +#define MISC_STRAP_BUS_HS_SPIM_CLK_SLOW_N_FAST (1<<13) +#define MISC_STRAP_BUS_LS_SPIM_CLK_FAST_N_SLOW (1<<12) +#define MISC_STRAP_BUS_LS_SPI_MASTER_N_SLAVE (1<<11) +#define MISC_STRAP_BUS_PLL_USE_LOCK (1<<10) +#define MISC_STRAP_BUS_PLL_MIPS_WAIT_FAST_N (1<<9) +#define MISC_STRAP_BUS_ROBOSW_P4_MODE_SHIFT 7 +#define MISC_STRAP_BUS_ROBOSW_P4_MODE_MASK (3<<MISC_STRAP_BUS_ROBOSW_P4_MODE_SHIFT) +#define MISC_STRAP_BUS_HARD_RESET_DELAY (1<<6) +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 1 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK (0x1F<<MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT) +#define MISC_STRAP_BUS_PCIE_ROOT_COMPLEX (1<<0) + + uint32 miscStrapOverride; /* 0x18 */ + uint32 miscVregCtrl0; /* 0x1C */ + + uint32 miscVregCtrl1; /* 0x20 */ +#define VREG_VSEL1P2_SHIFT 0 +#define VREG_VSEL1P2_MASK 0x1f +#define VREG_VSEL1P2_MIDDLE 0x0f + + uint32 miscVregCtrl2; /* 0x24 */ + uint32 miscExtra2ChipsIrqMask; /* 0x28 */ + uint32 miscExtra2ChipsIrqSts; /* 0x2C */ + uint32 miscExtra2ChipsIrqMask1; /* 0x30 */ + uint32 miscExtra2ChipsIrqSts1; /* 0x34 */ + uint32 miscFapIrqMask; /* 0x38 */ + uint32 miscExtraFapIrqMask; /* 0x3C */ + uint32 miscExtra2FapIrqMask; /* 0x40 */ + uint32 miscAdsl_clock_sample; /* 0x44 */ + + uint32 miscIddqCtrl; /* 0x48 */ +#define MISC_IDDQ_CONTROL_USBD (1<<5) +#define MISC_IDDQ_CONTROL_USBH (1<<4) + + uint32 miscSleep; /* 0x4C */ + uint32 miscRtc_enable; /* 0x50 */ + uint32 miscRtc_count_L; /* 0x54 */ + uint32 miscRtc_count_H; /* 0x58 */ + uint32 miscRtc_event; /* 0x5C */ + uint32 miscWakeup_mask; /* 0x60 */ + uint32 miscWakeup_status; /* 0x64 */ +} Misc; + +#define MISC ((volatile Misc * const) MISC_BASE) + +/* +** LedControl Register Set Definitions. +*/ + +#pragma pack(push, 4) +typedef struct LedControl { + uint32 ledInit; +#define LED_LED_TEST (1 << 31) +#define LED_SHIFT_TEST (1 << 30) +#define LED_SERIAL_LED_SHIFT_DIR (1 << 16) +#define LED_SERIAL_LED_DATA_PPOL (1 << 15) +#define LEDSERIAL_LED_CLK_NPOL (1 << 14) +#define LED_SERIAL_LED_MUX_SEL (1 << 13) +#define LED_SERIAL_LED_EN (1 << 12) +#define LED_FAST_INTV_SHIFT 6 +#define LED_FAST_INTV_MASK (0x3F<<LED_FAST_INTV_SHIFT) +#define LED_SLOW_INTV_SHIFT 0 +#define LED_SLOW_INTV_MASK (0x3F<<LED_SLOW_INTV_SHIFT) +#define LED_INTERVAL_20MS 1 + + uint64 ledMode; +#define LED_MODE_MASK (uint64)0x3 +#define LED_MODE_OFF (uint64)0x0 +#define LED_MODE_FLASH (uint64)0x1 +#define LED_MODE_BLINK (uint64)0x2 +#define LED_MODE_ON (uint64)0x3 + + uint32 ledHWDis; + uint32 ledStrobe; + uint32 ledLinkActSelHigh; +#define LED_ENET0 4 +#define LED_ENET1 5 +#define LED_ENET2 6 +#define LED_ENET3 7 +#define LED_4_ACT_SHIFT 0 +#define LED_5_ACT_SHIFT 4 +#define LED_6_ACT_SHIFT 8 +#define LED_7_ACT_SHIFT 12 +#define LED_4_LINK_SHIFT 16 +#define LED_5_LINK_SHIFT 20 +#define LED_6_LINK_SHIFT 24 +#define LED_7_LINK_SHIFT 28 + uint32 ledLinkActSelLow; +#define LED_USB 0 +#define LED_INET 1 +#define LED_0_ACT_SHIFT 0 +#define LED_1_ACT_SHIFT 4 +#define LED_2_ACT_SHIFT 8 +#define LED_3_ACT_SHIFT 12 +#define LED_0_LINK_SHIFT 16 +#define LED_1_LINK_SHIFT 20 +#define LED_2_LINK_SHIFT 24 +#define LED_3_LINK_SHIFT 28 + + uint32 ledReadback; + uint32 ledSerialMuxSelect; +} LedControl; +#pragma pack(pop) + +#define LED ((volatile LedControl * const) LED_BASE) + +#define GPIO_NUM_TO_LED_MODE_SHIFT(X) \ + ((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \ + (((X) & BP_GPIO_SERIAL) ? ((((X) & BP_GPIO_NUM_MASK) - 8) << 1) : \ + (((X) & BP_GPIO_NUM_MASK) < 16) ? (32 + ((((X) & BP_GPIO_NUM_MASK) - 8) << 1)) : \ + ((((X) & BP_GPIO_NUM_MASK) - 16) << 1))) + +/* +** Pcm Controller +*/ + +typedef struct PcmControlRegisters +{ + uint32 pcm_ctrl; // 00 offset from PCM_BASE +#define PCM_ENABLE 0x80000000 // PCM block master enable +#define PCM_ENABLE_SHIFT 31 +#define PCM_SLAVE_SEL 0x40000000 // PCM TDM slave mode select (1 - TDM slave, 0 - TDM master) +#define PCM_SLAVE_SEL_SHIFT 30 +#define PCM_CLOCK_INV 0x20000000 // PCM SCLK invert select (1 - invert, 0 - normal) +#define PCM_CLOCK_INV_SHIFT 29 +#define PCM_FS_INVERT 0x10000000 // PCM FS invert select (1 - invert, 0 - normal) +#define PCM_FS_INVERT_SHIFT 28 +#define PCM_FS_FREQ_16_8 0x08000000 // PCM FS 16/8 Khz select (1 - 16Khz, 0 - 8Khz) +#define PCM_FS_FREQ_16_8_SHIFT 27 +#define PCM_FS_LONG 0x04000000 // PCM FS long/short select (1 - long FS, 0 - short FS) +#define PCM_FS_LONG_SHIFT 26 +#define PCM_FS_TRIG 0x02000000 // PCM FS trigger (1 - falling edge, 0 - rising edge trigger) +#define PCM_FS_TRIG_SHIFT 25 +#define PCM_DATA_OFF 0x01000000 // PCM data offset from FS (1 - one clock from FS, 0 - no offset) +#define PCM_DATA_OFF_SHIFT 24 +#define PCM_DATA_16_8 0x00800000 // PCM data word length (1 - 16 bits, 0 - 8 bits) +#define PCM_DATA_16_8_SHIFT 23 +#define PCM_CLOCK_SEL 0x00700000 // PCM SCLK freq select +#define PCM_CLOCK_SEL_SHIFT 20 + // 000 - 8192 Khz + // 001 - 4096 Khz + // 010 - 2048 Khz + // 011 - 1024 Khz + // 100 - 512 Khz + // 101 - 256 Khz + // 110 - 128 Khz + // 111 - reserved +#define PCM_LSB_FIRST 0x00040000 // PCM shift direction (1 - LSBit first, 0 - MSBit first) +#define PCM_LSB_FIRST_SHIFT 18 +#define PCM_LOOPBACK 0x00020000 // PCM diagnostic loobback enable +#define PCM_LOOPBACK_SHIFT 17 +#define PCM_EXTCLK_SEL 0x00010000 // PCM external timing clock select -- Maybe removed in 6362 +#define PCM_EXTCLK_SEL_SHIFT 16 +#define PCM_NTR_ENABLE 0x00008000 // PCM NTR counter enable -- Nayve removed in 6362 +#define PCM_NTR_ENABLE_SHIFT 15 +#define PCM_BITS_PER_FRAME_1024 0x00000400 // 1024 - Max +#define PCM_BITS_PER_FRAME_256 0x00000100 // 256 +#define PCM_BITS_PER_FRAME_8 0x00000008 // 8 - Min + + uint32 pcm_chan_ctrl; // 04 +#define PCM_TX0_EN 0x00000001 // PCM transmit channel 0 enable +#define PCM_TX1_EN 0x00000002 // PCM transmit channel 1 enable +#define PCM_TX2_EN 0x00000004 // PCM transmit channel 2 enable +#define PCM_TX3_EN 0x00000008 // PCM transmit channel 3 enable +#define PCM_TX4_EN 0x00000010 // PCM transmit channel 4 enable +#define PCM_TX5_EN 0x00000020 // PCM transmit channel 5 enable +#define PCM_TX6_EN 0x00000040 // PCM transmit channel 6 enable +#define PCM_TX7_EN 0x00000080 // PCM transmit channel 7 enable +#define PCM_RX0_EN 0x00000100 // PCM receive channel 0 enable +#define PCM_RX1_EN 0x00000200 // PCM receive channel 1 enable +#define PCM_RX2_EN 0x00000400 // PCM receive channel 2 enable +#define PCM_RX3_EN 0x00000800 // PCM receive channel 3 enable +#define PCM_RX4_EN 0x00001000 // PCM receive channel 4 enable +#define PCM_RX5_EN 0x00002000 // PCM receive channel 5 enable +#define PCM_RX6_EN 0x00004000 // PCM receive channel 6 enable +#define PCM_RX7_EN 0x00008000 // PCM receive channel 7 enable +#define PCM_RX_PACKET_SIZE 0x00ff0000 // PCM Rx DMA quasi-packet size +#define PCM_RX_PACKET_SIZE_SHIFT 16 + + uint32 pcm_int_pending; // 08 + uint32 pcm_int_mask; // 0c +#define PCM_TX_UNDERFLOW 0x00000001 // PCM DMA receive overflow +#define PCM_RX_OVERFLOW 0x00000002 // PCM DMA transmit underflow +#define PCM_TDM_FRAME 0x00000004 // PCM frame boundary +#define PCM_RX_IRQ 0x00000008 // IUDMA interrupts +#define PCM_TX_IRQ 0x00000010 + + uint32 pcm_pll_ctrl1; // 10 +#define PCM_PLL_PWRDN 0x80000000 // PLL PWRDN +#define PCM_PLL_PWRDN_CH1 0x40000000 // PLL CH PWRDN +#define PCM_PLL_REFCMP_PWRDN 0x20000000 // PLL REFCMP PWRDN +#define PCM_CLK16_RESET 0x10000000 // 16.382 MHz PCM interface circuitry reset. +#define PCM_PLL_ARESET 0x08000000 // PLL Analog Reset +#define PCM_PLL_DRESET 0x04000000 // PLL Digital Reset + + uint32 pcm_pll_ctrl2; // 14 + uint32 pcm_pll_ctrl3; // 18 + uint32 pcm_pll_ctrl4; // 1c + + uint32 pcm_pll_stat; // 20 +#define PCM_PLL_LOCK 0x00000001 // Asserted when PLL is locked to programmed frequency + + uint32 pcm_ntr_counter; // 24 + + uint32 unused[6]; +#define PCM_MAX_TIMESLOT_REGS 16 // Number of PCM time slot registers in the table. + // Each register provides the settings for 8 timeslots (4 bits per timeslot) + uint32 pcm_slot_alloc_tbl[PCM_MAX_TIMESLOT_REGS]; +#define PCM_TS_VALID 0x8 // valid marker for TS alloc ram entry + + uint32 pcm_pll_ch2_ctrl; // +0xa080 + uint32 pcm_msif_intf; // +0xa084 +} PcmControlRegisters; + +#define PCM ((volatile PcmControlRegisters * const) PCM_BASE) + + +typedef struct PcmIudmaRegisters +{ + uint16 reserved0; + uint16 ctrlConfig; +#define BCM6362_IUDMA_REGS_CTRLCONFIG_MASTER_EN 0x0001 +#define BCM6362_IUDMA_REGS_CTRLCONFIG_FLOWC_CH1_EN 0x0002 +#define BCM6362_IUDMA_REGS_CTRLCONFIG_FLOWC_CH3_EN 0x0004 +#define BCM6362_IUDMA_REGS_CTRLCONFIG_FLOWC_CH5_EN 0x0008 +#define BCM6362_IUDMA_REGS_CTRLCONFIG_FLOWC_CH7_EN 0x0010 + + // Flow control Ch1 + uint16 reserved1; + uint16 ch1_FC_Low_Thr; + + uint16 reserved2; + uint16 ch1_FC_High_Thr; + + uint16 reserved3; + uint16 ch1_Buff_Alloc; + + // Flow control Ch3 + uint16 reserved4; + uint16 ch3_FC_Low_Thr; + + uint16 reserved5; + uint16 ch3_FC_High_Thr; + + uint16 reserved6; + uint16 ch3_Buff_Alloc; + + // Flow control Ch5 + uint16 reserved7; + uint16 ch5_FC_Low_Thr; + + uint16 reserved8; + uint16 ch5_FC_High_Thr; + + uint16 reserved9; + uint16 ch5_Buff_Alloc; + + // Flow control Ch7 + uint16 reserved10; + uint16 ch7_FC_Low_Thr; + + uint16 reserved11; + uint16 ch7_FC_High_Thr; + + uint16 reserved12; + uint16 ch7_Buff_Alloc; + + // Channel resets + uint16 reserved13; + uint16 channel_reset; + + uint16 reserved14; + uint16 channel_debug; + + // Spare register + uint32 dummy1; + + // Interrupt status registers + uint16 reserved15; + uint16 gbl_int_stat; + + // Interrupt mask registers + uint16 reserved16; + uint16 gbl_int_mask; +} PcmIudmaRegisters; + + +typedef struct PcmIudmaChannelCtrl +{ + uint16 reserved1; + uint16 config; +#define BCM6362_IUDMA_CONFIG_ENDMA 0x0001 +#define BCM6362_IUDMA_CONFIG_PKTHALT 0x0002 +#define BCM6362_IUDMA_CONFIG_BURSTHALT 0x0004 + + uint16 reserved2; + uint16 intStat; +#define BCM6362_IUDMA_INTSTAT_BDONE 0x0001 +#define BCM6362_IUDMA_INTSTAT_PDONE 0x0002 +#define BCM6362_IUDMA_INTSTAT_NOTVLD 0x0004 +#define BCM6362_IUDMA_INTSTAT_MASK 0x0007 +#define BCM6362_IUDMA_INTSTAT_ALL BCM6362_IUDMA_INTSTAT_MASK + + uint16 reserved3; + uint16 intMask; +#define BCM6362_IUDMA_INTMASK_BDONE 0x0001 +#define BCM6362_IUDMA_INTMASK_PDONE 0x0002 +#define BCM6362_IUDMA_INTMASK_NOTVLD 0x0004 + + uint32 maxBurst; +#define BCM6362_IUDMA_MAXBURST_SIZE 16 /* 32-bit words */ + +} PcmIudmaChannelCtrl; + + +typedef struct PcmIudmaStateRam +{ + uint32 baseDescPointer; /* pointer to first buffer descriptor */ + + uint32 stateBytesDoneRingOffset; /* state info: how manu bytes done and the offset of the + current descritor in process */ +#define BCM6362_IUDMA_STRAM_DESC_RING_OFFSET 0x3fff + + + uint32 flagsLengthStatus; /* Length and status field of the current descriptor */ + + uint32 currentBufferPointer; /* pointer to the current descriptor */ + +} PcmIudmaStateRam; + +#define BCM6362_MAX_PCM_DMA_CHANNELS 2 + +typedef struct PcmIudma +{ + PcmIudmaRegisters regs; // + uint32 reserved1[110]; // + PcmIudmaChannelCtrl ctrl[BCM6362_MAX_PCM_DMA_CHANNELS]; // + uint32 reserved2[120]; // + PcmIudmaStateRam stram[BCM6362_MAX_PCM_DMA_CHANNELS]; // + +} PcmIudma; + +#define PCM_IUDMA ((volatile PcmIudma * const) PCM_DMA_BASE) + + +#define IUDMA_MAX_CHANNELS 32 + +/* +** DMA Channel Configuration (1 .. 32) +*/ +typedef struct DmaChannelCfg { + uint32 cfg; /* (00) assorted configuration */ +#define DMA_ENABLE 0x00000001 /* set to enable channel */ +#define DMA_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ +#define DMA_BURST_HALT 0x00000004 /* idle after finish current memory burst */ + uint32 intStat; /* (04) interrupts control and status */ + uint32 intMask; /* (08) interrupts mask */ +#define DMA_BUFF_DONE 0x00000001 /* buffer done */ +#define DMA_DONE 0x00000002 /* packet xfer complete */ +#define DMA_NO_DESC 0x00000004 /* no valid descriptors */ + uint32 maxBurst; /* (0C) max burst length permitted */ +#define DMA_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */ +} DmaChannelCfg; + +/* +** DMA State RAM (1 .. 16) +*/ +typedef struct DmaStateRam { + uint32 baseDescPtr; /* (00) descriptor ring start address */ + uint32 state_data; /* (04) state/bytes done/ring offset */ + uint32 desc_len_status; /* (08) buffer descriptor status and len */ + uint32 desc_base_bufptr; /* (0C) buffer descrpitor current processing */ +} DmaStateRam; + + +/* +** DMA Registers +*/ +typedef struct DmaRegs { + uint32 controller_cfg; /* (00) controller configuration */ +#define DMA_MASTER_EN 0x00000001 +#define DMA_FLOWC_CH1_EN 0x00000002 +#define DMA_FLOWC_CH3_EN 0x00000004 + + // Flow control Ch1 + uint32 flowctl_ch1_thresh_lo; /* 004 */ + uint32 flowctl_ch1_thresh_hi; /* 008 */ + uint32 flowctl_ch1_alloc; /* 00c */ +#define DMA_BUF_ALLOC_FORCE 0x80000000 + + // Flow control Ch3 + uint32 flowctl_ch3_thresh_lo; /* 010 */ + uint32 flowctl_ch3_thresh_hi; /* 014 */ + uint32 flowctl_ch3_alloc; /* 018 */ + + // Flow control Ch5 + uint32 flowctl_ch5_thresh_lo; /* 01C */ + uint32 flowctl_ch5_thresh_hi; /* 020 */ + uint32 flowctl_ch5_alloc; /* 024 */ + + // Flow control Ch7 + uint32 flowctl_ch7_thresh_lo; /* 028 */ + uint32 flowctl_ch7_thresh_hi; /* 02C */ + uint32 flowctl_ch7_alloc; /* 030 */ + + uint32 ctrl_channel_reset; /* 034 */ + uint32 ctrl_channel_debug; /* 038 */ + uint32 reserved1; /* 03C */ + uint32 ctrl_global_interrupt_status; /* 040 */ + uint32 ctrl_global_interrupt_mask; /* 044 */ + + // Unused words + uint8 reserved2[0x200-0x48]; + + // Per channel registers/state ram + DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */ + union { + DmaStateRam s[IUDMA_MAX_CHANNELS]; + uint32 u32[4 * IUDMA_MAX_CHANNELS]; + } stram; /* (400-5FF) state ram */ +} DmaRegs; + +#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE) + +/* +** DMA Buffer +*/ +typedef struct DmaDesc { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ +} DmaDesc; + +/* +** 16 Byte DMA Buffer +*/ +typedef struct { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ + uint32 control; +#define GEM_ID_MASK 0x001F + uint32 reserved; +} DmaDesc16; + + +/* +** USB 2.0 Device Registers +*/ +typedef struct UsbRegisters { +#define USBD_CONTROL_APP_DONECSR 0x0001 +#define USBD_CONTROL_APP_RESUME 0x0002 +#define USBD_CONTROL_APP_RXFIFIO_INIT 0x0040 +#define USBD_CONTROL_APP_TXFIFIO_INIT 0x0080 +#define USBD_CONTROL_APP_FIFO_SEL_SHIFT 0x8 +#define USBD_CONTROL_APP_FIFO_INIT_SEL(x) (((x)&0x0f)<<USBD_CONTROL_APP_FIFO_SEL_SHIFT) +#define USBD_CONTROL_APP_AUTO_CSRS 0x2000 +#define USBD_CONTROL_APP_AUTO_INS_ZERO_LEN_PKT 0x4000 +#define EN_TXZLENINS (1<<14) +#define EN_RXZSCFG (1<<12) +#define APPSETUPERRLOCK (1<<5) + uint32 usbd_control ; +#define USBD_STRAPS_APP_SELF_PWR 0x0400 +#define USBD_STRAPS_APP_DEV_DISCON 0x0200 +#define USBD_STRAPS_APP_CSRPRG_SUP 0x0100 +#define USBD_STRAPS_APP_RAM_IF 0x0080 +#define USBD_STRAPS_APP_DEV_RMTWKUP 0x0040 +#define USBD_STRAPS_APP_PHYIF_8BIT 0x0004 +#define USBD_STRAPS_FULL_SPEED 0x0003 +#define USBD_STRAPS_LOW_SPEED 0x0002 +#define USBD_STRAPS_HIGH_SPEED 0x0000 +#define APPUTMIDIR(x) ((x&1)<<3) +#define UNIDIR 0 + uint32 usbd_straps; +#define USB_ENDPOINT_0 0x01 + uint32 usbd_stall; +#define USBD_ENUM_SPEED_SHIFT 12 +#define USBD_ENUM_SPEED 0x3000 +#define UDC20_ALTINTF(x) ((x>>8)&0xf) +#define UDC20_INTF(x) ((x>>4)&0xf) +#define UDC20_CFG(x) ((x>>0)&0xf) + uint32 usbd_status; +#define USBD_LINK (0x1<<10) +#define USBD_SET_CSRS 0x40 +#define USBD_SUSPEND 0x20 +#define USBD_EARLY_SUSPEND 0x10 +#define USBD_SOF 0x08 +#define USBD_ENUMON 0x04 +#define USBD_SETUP 0x02 +#define USBD_USBRESET 0x01 + uint32 usbd_events; + uint32 usbd_events_irq; +#define UPPER(x) (16+x) +#define ENABLE(x) (1<<x) +#define SWP_TXBSY (15) +#define SWP_RXBSY (14) +#define SETUP_ERR (13) +#define APPUDCSTALLCHG (12) +#define BUS_ERR (11) +#define USB_LINK (10) +#define HST_SETCFG (9) +#define HST_SETINTF (8) +#define ERRATIC_ERR (7) +#define SET_CSRS (6) +#define SUSPEND (5) +#define ERLY_SUSPEND (4) +#define SOF (3) +#define ENUM_ON (2) +#define SETUP (1) +#define USB_RESET (0) +#define RISING(x) (0x0<<2*x) +#define FALLING(x) (0x1<<2*x) +#define USBD_IRQCFG_ENUM_ON_FALLING_EDGE 0x00000010 + uint32 usbd_irqcfg_hi ; + uint32 usbd_irqcfg_lo ; +#define USBD_USB_RESET_IRQ 0x00000001 +#define USBD_USB_SETUP_IRQ 0x00000002 // non-standard setup cmd rcvd +#define USBD_USB_ENUM_ON_IRQ 0x00000004 +#define USBD_USB_SOF_IRQ 0x00000008 +#define USBD_USB_EARLY_SUSPEND_IRQ 0x00000010 +#define USBD_USB_SUSPEND_IRQ 0x00000020 // non-standard setup cmd rcvd +#define USBD_USB_SET_CSRS_IRQ 0x00000040 +#define USBD_USB_ERRATIC_ERR_IRQ 0x00000080 +#define USBD_USB_SETCFG_IRQ 0x00000200 +#define USBD_USB_LINK_IRQ 0x00000400 + uint32 usbd_events_irq_mask; + uint32 usbd_swcfg; + uint32 usbd_swtxctl; + uint32 usbd_swrxctl; + uint32 usbd_txfifo_rwptr; + uint32 usbd_rxfifo_rwptr; + uint32 usbd_txfifo_st_rwptr; + uint32 usbd_rxfifo_st_rwptr; + uint32 usbd_txfifo_config ; + uint32 usbd_rxfifo_config ; + uint32 usbd_txfifo_epsize ; + uint32 usbd_rxfifo_epsize ; +#define USBD_EPNUM_CTRL 0x0 +#define USBD_EPNUM_ISO 0x1 +#define USBD_EPNUM_BULK 0x2 +#define USBD_EPNUM_IRQ 0x3 +#define USBD_EPNUM_EPTYPE(x) (((x)&0x3)<<8) +#define USBD_EPNUM_EPDMACHMAP(x) (((x)&0xf)<<0) + uint32 usbd_epnum_typemap ; + uint32 usbd_reserved [0xB] ; + uint32 usbd_csr_setupaddr ; +#define USBD_EPNUM_MASK 0xf +#define USBD_EPNUM(x) ((x&USBD_EPNUM_MASK)<<0) +#define USBD_EPDIR_IN (1<<4) +#define USBD_EPDIR_OUT (0<<4) +#define USBD_EPTYP_CTRL (USBD_EPNUM_CTRL<<5) +#define USBD_EPTYP_ISO (USBD_EPNUM_ISO<<5) +#define USBD_EPTYP_BULK (USBD_EPNUM_BULK<<5) +#define USBD_EPTYP_IRQ (USBD_EPNUM_IRQ<<5) +#define USBD_EPCFG_MASK 0xf +#define USBD_EPCFG(x) ((x&USBD_EPCFG_MASK)<<7) +#define USBD_EPINTF_MASK 0xf +#define USBD_EPINTF(x) ((x&USBD_EPINTF_MASK)<<11) +#define USBD_EPAINTF_MASK 0xf +#define USBD_EPAINTF(x) ((x&USBD_EPAINTF_MASK)<<15) +#define USBD_EPMAXPKT_MSK 0x7ff +#define USBD_EPMAXPKT(x) ((x&USBD_EPMAXPKT_MSK)<<19) +#define USBD_EPISOPID_MASK 0x3 +#define USBD_EPISOPID(x) ((x&USBD_ISOPID_MASK)<<30) + uint32 usbd_csr_ep [5] ; +} UsbRegisters; + +#define USB ((volatile UsbRegisters * const) USB_CTL_BASE) + +typedef struct USBControl { + uint32 BrtControl1; + uint32 BrtControl2; + uint32 BrtStatus1; + uint32 BrtStatus2; + uint32 UTMIControl1; + uint32 TestPortControl; + uint32 PllControl1; + uint32 SwapControl; +#define USB_DEVICE_SEL (1<<6) +#define EHCI_LOGICAL_ADDRESS_EN (1<<5) +#define EHCI_ENDIAN_SWAP (1<<4) +#define EHCI_DATA_SWAP (1<<3) +#define OHCI_LOGICAL_ADDRESS_EN (1<<2) +#define OHCI_ENDIAN_SWAP (1<<1) +#define OHCI_DATA_SWAP (1<<0) + uint32 unused1; + uint32 FrameAdjustValue; + uint32 Setup; +#define USBH_IOC (1<<4) + uint32 MDIO; + uint32 MDIO32; + uint32 USBSimControl; +} USBControl; + +#define USBH ((volatile USBControl * const) USBH_CFG_BASE) + +typedef struct EthSwRegs{ + byte port_traffic_ctrl[9]; /* 0x00 - 0x08 */ + byte reserved1[2]; /* 0x09 - 0x0a */ + byte switch_mode; /* 0x0b */ + unsigned short pause_quanta; /*0x0c */ + byte imp_port_state; /*0x0e */ + byte led_refresh; /* 0x0f */ + unsigned short led_function[2]; /* 0x10 */ + unsigned short led_function_map; /* 0x14 */ + unsigned short led_enable_map; /* 0x16 */ + unsigned short led_mode_map0; /* 0x18 */ + unsigned short led_function_map1; /* 0x1a */ + byte reserved2[5]; /* 0x1b - 0x20 */ + byte port_forward_ctrl; /* 0x21 */ + byte reserved3[2]; /* 0x22 - 0x23 */ + unsigned short protected_port_selection; /* 0x24 */ + unsigned short wan_port_select; /* 0x26 */ + unsigned int pause_capability; /* 0x28 */ + byte reserved4[3]; /* 0x2c - 0x2e */ + byte reserved_multicast_control; /* 0x2f */ + byte reserved5; /* 0x30 */ + byte txq_flush_mode_control; /* 0x31 */ + unsigned short ulf_forward_map; /* 0x32 */ + unsigned short mlf_forward_map; /* 0x34 */ + unsigned short mlf_impc_forward_map; /* 0x36 */ + unsigned short pause_pass_through_for_rx; /* 0x38 */ + unsigned short pause_pass_through_for_tx; /* 0x3a */ + unsigned short disable_learning; /* 0x3c */ + byte reserved6[26]; /* 0x3e - 0x57 */ + byte port_state_override[8]; /* 0x58 - 0x5f */ + byte reserved7[4]; /* 0x60 - 0x63 */ + byte imp_rgmii_ctrl_p4; /* 0x64 */ + byte imp_rgmii_ctrl_p5; /* 0x65 */ + byte reserved8[6]; /* 0x66 - 0x6b */ + byte rgmii_timing_delay_p4; /* 0x6c */ + byte gmii_timing_delay_p5; /* 0x6d */ + byte reserved9[11]; /* 0x6e - 0x78 */ + byte software_reset; /* 0x79 */ + byte reserved13[6]; /* 0x7a - 0x7f */ + byte pause_frame_detection; /* 0x80 */ + byte reserved10[7]; /* 0x81 - 0x87 */ + byte fast_aging_ctrl; /* 0x88 */ + byte fast_aging_port; /* 0x89 */ + byte fast_aging_vid; /* 0x8a */ + byte reserved11[21]; /* 0x8b - 0x9f */ + unsigned int swpkt_ctrl_sar; /*0xa0 */ + unsigned int swpkt_ctrl_usb; /*0xa4 */ + unsigned int iudma_ctrl; /*0xa8 */ + unsigned int rxfilt_ctrl; /*0xac */ + unsigned int mdio_ctrl; /*0xb0 */ + unsigned int mdio_data; /*0xb4 */ + byte reserved12[42]; /* 0xb6 - 0xdf */ + unsigned int sw_mem_test; /*0xe0 */ +} EthSwRegs; + +#define ETHSWREG ((volatile EthSwRegs * const) SWITCH_BASE) + +typedef struct EthSwMIBRegs { + unsigned int TxOctetsLo; + unsigned int TxOctetsHi; + unsigned int TxDropPkts; + unsigned int TxQoSPkts; + unsigned int TxBroadcastPkts; + unsigned int TxMulticastPkts; + unsigned int TxUnicastPkts; + unsigned int TxCol; + unsigned int TxSingleCol; + unsigned int TxMultipleCol; + unsigned int TxDeferredTx; + unsigned int TxLateCol; + unsigned int TxExcessiveCol; + unsigned int TxFrameInDisc; + unsigned int TxPausePkts; + unsigned int TxQoSOctetsLo; + unsigned int TxQoSOctetsHi; + unsigned int RxOctetsLo; + unsigned int RxOctetsHi; + unsigned int RxUndersizePkts; + unsigned int RxPausePkts; + unsigned int Pkts64Octets; + unsigned int Pkts65to127Octets; + unsigned int Pkts128to255Octets; + unsigned int Pkts256to511Octets; + unsigned int Pkts512to1023Octets; + unsigned int Pkts1024to1522Octets; + unsigned int RxOversizePkts; + unsigned int RxJabbers; + unsigned int RxAlignErrs; + unsigned int RxFCSErrs; + unsigned int RxGoodOctetsLo; + unsigned int RxGoodOctetsHi; + unsigned int RxDropPkts; + unsigned int RxUnicastPkts; + unsigned int RxMulticastPkts; + unsigned int RxBroadcastPkts; + unsigned int RxSAChanges; + unsigned int RxFragments; + unsigned int RxExcessSizeDisc; + unsigned int RxSymbolError; + unsigned int RxQoSPkts; + unsigned int RxQoSOctetsLo; + unsigned int RxQoSOctetsHi; + unsigned int Pkts1523to2047; + unsigned int Pkts2048to4095; + unsigned int Pkts4096to8191; + unsigned int Pkts8192to9728; +} EthSwMIBRegs; + +#define ETHSWMIBREG ((volatile EthSwMIBRegs * const) (SWITCH_BASE + 0x2000)) + +/* +** NAND Interrupt Controller Registers +*/ +typedef struct NandIntrCtrlRegs { + uint32 NandInterrupt; +#define NINT_ENABLE_MASK 0xffff0000 +#define NINT_STS_MASK 0x00000fff +#define NINT_ECC_ERROR_CORR 0x00000080 +#define NINT_ECC_ERROR_UNC 0x00000040 +#define NINT_DEV_RBPIN 0x00000020 +#define NINT_CTRL_READY 0x00000010 +#define NINT_PAGE_PGM 0x00000008 +#define NINT_COPY_BACK 0x00000004 +#define NINT_BLOCK_ERASE 0x00000002 +#define NINT_NP_READ 0x00000001 + + uint32 NandBaseAddr0; /* Default address when booting from NAND flash */ + uint32 reserved; + uint32 NandBaseAddr1; /* Secondary base address for NAND flash */ +} NandIntrCtrlRegs; + +#define NAND_INTR ((volatile NandIntrCtrlRegs * const) NAND_INTR_BASE) + +/* +** NAND Controller Registers +*/ +typedef struct NandCtrlRegs { + uint32 NandRevision; /* NAND Revision */ + uint32 NandCmdStart; /* Nand Flash Command Start */ +#define NCMD_MASK 0x0f000000 +#define NCMD_BLK_LOCK_STS 0x0d000000 +#define NCMD_BLK_UNLOCK 0x0c000000 +#define NCMD_BLK_LOCK_DOWN 0x0b000000 +#define NCMD_BLK_LOCK 0x0a000000 +#define NCMD_FLASH_RESET 0x09000000 +#define NCMD_BLOCK_ERASE 0x08000000 +#define NCMD_DEV_ID_READ 0x07000000 +#define NCMD_COPY_BACK 0x06000000 +#define NCMD_PROGRAM_SPARE 0x05000000 +#define NCMD_PROGRAM_PAGE 0x04000000 +#define NCMD_STS_READ 0x03000000 +#define NCMD_SPARE_READ 0x02000000 +#define NCMD_PAGE_READ 0x01000000 + + uint32 NandCmdExtAddr; /* Nand Flash Command Extended Address */ + uint32 NandCmdAddr; /* Nand Flash Command Address */ + uint32 NandCmdEndAddr; /* Nand Flash Command End Address */ + uint32 NandNandBootConfig; /* Nand Flash Boot Config */ +#define NBC_CS_LOCK 0x80000000 +#define NBC_AUTO_DEV_ID_CFG 0x40000000 +#define NBC_WR_PROT_BLK0 0x10000000 + + uint32 NandCsNandXor; /* Nand Flash EBI CS Address XOR with */ + /* 1FC0 Control */ + uint32 NandReserved; + uint32 NandSpareAreaReadOfs0; /* Nand Flash Spare Area Read Bytes 0-3 */ + uint32 NandSpareAreaReadOfs4; /* Nand Flash Spare Area Read Bytes 4-7 */ + uint32 NandSpareAreaReadOfs8; /* Nand Flash Spare Area Read Bytes 8-11 */ + uint32 NandSpareAreaReadOfsC; /* Nand Flash Spare Area Read Bytes 12-15*/ + uint32 NandSpareAreaWriteOfs0; /* Nand Flash Spare Area Write Bytes 0-3 */ + uint32 NandSpareAreaWriteOfs4; /* Nand Flash Spare Area Write Bytes 4-7 */ + uint32 NandSpareAreaWriteOfs8; /* Nand Flash Spare Area Write Bytes 8-11*/ + uint32 NandSpareAreaWriteOfsC; /* Nand Flash Spare Area Write Bytes12-15*/ + uint32 NandAccControl; /* Nand Flash Access Control */ + uint32 NandConfig; /* Nand Flash Config */ +#define NC_CONFIG_LOCK 0x80000000 +#define NC_PG_SIZE_MASK 0x00300000 +#define NC_PG_SIZE_2K 0x00100000 +#define NC_PG_SIZE_512B 0x00000000 +#define NC_BLK_SIZE_MASK 0x30000000 +#define NC_BLK_SIZE_512K 0x30000000 +#define NC_BLK_SIZE_128K 0x10000000 +#define NC_BLK_SIZE_16K 0x00000000 +#define NC_BLK_SIZE_8K 0x20000000 +#define NC_DEV_SIZE_MASK 0x0f000000 +#define NC_DEV_SIZE_SHIFT 24 +#define NC_DEV_WIDTH_MASK 0x00800000 +#define NC_DEV_WIDTH_16 0x00800000 +#define NC_DEV_WIDTH_8 0x00000000 +#define NC_FUL_ADDR_MASK 0x00070000 +#define NC_FUL_ADDR_SHIFT 16 +#define NC_BLK_ADDR_MASK 0x00000700 +#define NC_BLK_ADDR_SHIFT 8 + + uint32 NandTiming1; /* Nand Flash Timing Parameters 1 */ + uint32 NandTiming2; /* Nand Flash Timing Parameters 2 */ + uint32 NandSemaphore; /* Semaphore */ + uint32 NandFlashDeviceId; /* Nand Flash Device ID */ + uint32 NandBlockLockStatus; /* Nand Flash Block Lock Status */ + uint32 NandIntfcStatus; /* Nand Flash Interface Status */ +#define NIS_CTLR_READY 0x80000000 +#define NIS_FLASH_READY 0x40000000 +#define NIS_CACHE_VALID 0x20000000 +#define NIS_SPARE_VALID 0x10000000 +#define NIS_FLASH_STS_MASK 0x000000ff +#define NIS_WRITE_PROTECT 0x00000080 +#define NIS_DEV_READY 0x00000040 +#define NIS_PGM_ERASE_ERROR 0x00000001 + + uint32 NandEccCorrExtAddr; /* ECC Correctable Error Extended Address*/ + uint32 NandEccCorrAddr; /* ECC Correctable Error Address */ + uint32 NandEccUncExtAddr; /* ECC Uncorrectable Error Extended Addr */ + uint32 NandEccUncAddr; /* ECC Uncorrectable Error Address */ + uint32 NandFlashReadExtAddr; /* Flash Read Data Extended Address */ + uint32 NandFlashReadAddr; /* Flash Read Data Address */ + uint32 NandProgramPageExtAddr; /* Page Program Extended Address */ + uint32 NandProgramPageAddr; /* Page Program Address */ + uint32 NandCopyBackExtAddr; /* Copy Back Extended Address */ + uint32 NandCopyBackAddr; /* Copy Back Address */ + uint32 NandBlockEraseExtAddr; /* Block Erase Extended Address */ + uint32 NandBlockEraseAddr; /* Block Erase Address */ + uint32 NandInvReadExtAddr; /* Flash Invalid Data Extended Address */ + uint32 NandInvReadAddr; /* Flash Invalid Data Address */ + uint32 NandBlkWrProtect; /* Block Write Protect Enable and Size */ + /* for EBI_CS0b */ +} NandCtrlRegs; + +#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE) + +#define NAND_CACHE ((volatile uint8 * const) NAND_CACHE_BASE) + +/* +** PCI-E +*/ +typedef struct PcieRegs{ + uint32 devVenID; + uint16 command; + uint16 status; + uint32 revIdClassCode; + uint32 headerTypeLatCacheLineSize; + uint32 bar1; + uint32 bar2; + uint32 priSecBusNo; +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK 0x00ff0000 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT 16 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK 0x0000ff00 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT 8 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK 0x000000ff + + uint32 ioBaseLimit; + uint32 secStatus; + uint32 rcMemBaseLimit; + uint32 rcPrefBaseLimit; + uint32 rcPrefBaseHi; + uint32 rcPrefLimitHi; + uint32 rcIoBaseLimit; + uint32 capPointer; + uint32 expRomBase; + uint32 brdigeCtrlIntPinIntLine; + uint32 bridgeCtrl; + uint32 unused1[27]; + + /* PcieExpressCtrlRegs */ + uint16 pciExpressCap; + uint16 pcieCapabilitiy; + uint32 deviceCapability; + uint16 deviceControl; + uint16 deviceStatus; + uint32 linkCapability; + uint16 linkControl; + uint16 linkStatus; + uint32 slotCapability; + uint16 slotControl; + uint16 slotStatus; + uint16 rootControl; + uint16 rootCap; + uint32 rootStatus; + uint32 deviceCapability2; + uint16 deviceControl2; + uint16 deviceStatus2; + uint32 linkCapability2; + uint16 linkControl2; + uint16 linkStatus2; + uint32 slotCapability2; + uint16 slotControl2; + uint16 slotStatus2; + uint32 unused2[6]; + + /* PcieErrorRegs */ + uint16 advErrCapId; + uint16 advErrCapOff; + uint32 ucErrStatus; + uint32 ucorrErrMask; + uint32 ucorrErrSevr; + uint32 corrErrStatus; + uint32 corrErrMask; + uint32 advErrCapControl; + uint32 headerLog1; + uint32 headerLog2; + uint32 headerLog3; + uint32 headerLog4; + uint32 rootErrorCommand; + uint32 rootErrorStatus; + uint32 rcCorrId; + uint32 rcFatalNonfatalId; + uint32 unused3[10]; + + /* PcieVcRegs */ + uint16 vcCapId; + uint16 vcCapOffset; + uint32 prtVcCapability; + uint32 portVcCapability2; + uint16 portVcControl; + uint16 portVcCtatus; + uint32 portArbStatus; + uint32 vcRsrcControl; + uint32 vcRsrcStatus; + uint32 unused4[1]; + + /* PcieVendor */ + uint32 vendorCapability; + uint32 vendorSpecificHdr; +} PcieRegs; + +typedef struct PcieBlk404Regs{ + uint32 unused; /* 0x404 */ + uint32 config2; /* 0x408 */ +#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK 0x0000000f +#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE 0 + uint32 config3; /* 0x40c */ + uint32 pmDataA; /* 0x410 */ + uint32 pmDataB; /* 0x414 */ +} PcieBlk404Regs; + +typedef struct PcieBlk428Regs{ + uint32 vpdIntf; /* 0x428 */ + uint16 unused_g; /* 0x42c */ + uint16 vpdAddrFlag; /* 0x42e */ + uint32 vpdData; /* 0x430 */ + uint32 idVal1; /* 0x434 */ + uint32 idVal2; /* 0x438 */ + uint32 idVal3; /* 0x43c */ +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK 0xff000000 +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT 24 +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK 0x00ffffff +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT 16 +#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT 8 + + uint32 idVal4; + uint32 idVal5; + uint32 unused_h; + uint32 idVal6; + uint32 msiData; + uint32 msiAddr_h; + uint32 msiAddr_l; + uint32 msiMask; + uint32 msiPend; + uint32 pmData_c; + uint32 msixControl; + uint32 msixTblOffBir; + uint32 msixPbaOffBit; + uint32 unused_k; + uint32 pcieCapability; + uint32 deviceCapability; + uint32 unused_l; + uint32 linkCapability; + uint32 bar2Config; + uint32 pcieDeviceCapability2; + uint32 pcieLinkCapability2; + uint32 pcieLinkControl; + uint32 pcieLinkCapabilityRc; + uint32 bar3Config; + uint32 rootCap; + uint32 devSerNumCapId; + uint32 lowerSerNum; + uint32 upperSerNum; + uint32 advErrCap; + uint32 pwrBdgtData0; + uint32 pwrBdgtData1; + uint32 pwrBdgtData2; + uint32 pwdBdgtData3; + uint32 pwrBdgtData4; + uint32 pwrBdgtData5; + uint32 pwrBdgtData6; + uint32 pwrBdgtData7; + uint32 pwrBdgtCapability; + uint32 vsecHdr; + uint32 rcUserMemLo1; + uint32 rcUserMemHi1; + uint32 rcUserMemLo2; + uint32 rcUserMemHi2; +}PcieBlk428Regs; + +typedef struct PcieBlk800Regs{ +#define NUM_PCIE_BLK_800_CTRL_REGS 6 + uint32 tlControl[NUM_PCIE_BLK_800_CTRL_REGS]; + uint32 tlCtlStat0; + uint32 pmStatus0; + uint32 pmStatus1; + +#define NUM_PCIE_BLK_800_TAGS 32 + uint32 tlStatus[NUM_PCIE_BLK_800_TAGS]; + uint32 tlHdrFcStatus; + uint32 tlDataFcStatus; + uint32 tlHdrFcconStatus; + uint32 tlDataFcconStatus; + uint32 tlTargetCreditStatus; + uint32 tlCreditAllocStatus; + uint32 tlSmlogicStatus; +} PcieBlk800Regs; + + +typedef struct PcieBlk1000Regs{ +#define NUM_PCIE_BLK_1000_PDL_CTRL_REGS 16 + uint32 pdlControl[NUM_PCIE_BLK_1000_PDL_CTRL_REGS]; + uint32 dlattnVec; + uint32 dlAttnMask; + uint32 dlStatus; /* 0x1048 */ +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK 0x00002000 +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT 13 + uint32 dlTxChecksum; + uint32 dlForcedUpdateGen1; + uint32 mdioAddr; + uint32 mdioWrData; + uint32 mdioRdData; + uint32 dlRxPFcCl; + uint32 dlRxCFcCl; + uint32 dlRxAckNack; + uint32 dlTxRxSeqnb; + uint32 dlTxPFcAl; + uint32 dlTxNpFcAl; + uint32 regDlSpare; + uint32 dlRegSpare; + uint32 dlTxRxSeq; + uint32 dlRxNpFcCl; +}PcieBlk1000Regs; + +typedef struct PcieBlk1800Regs{ +#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS 5 + uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS]; +#define REG_POWERDOWN_P1PLL_ENA (1<<12) + uint32 phyErrorAttnVec; + uint32 phyErrorAttnMask; + uint32 phyReceivedMcpErrors; + uint32 phyTransmittedMcpErrors; + uint32 phyGenDebug; + uint32 phyRecoveryHist; +#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS 3 + uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS]; +#define NUM_PCIE_BLK_1800_PHY_DBG_REGS 11 + uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS]; +} PcieBlk1800Regs; + +typedef struct PcieBridgeRegs{ + uint32 bar1Remap; /* 0x0818*/ +#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK 0xffff0000 +#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK_SHIFT 16 +#define PCIE_BRIDGE_BAR1_REMAP_remap_enable (1<<1) +#define PCIE_BRIDGE_BAR1_REMAP_swap_enable 1 + + uint32 bar2Remap; /* 0x081c*/ +#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK 0xffff0000 +#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK_SHIFT 16 +#define PCIE_BRIDGE_BAR2_REMAP_remap_enable (1<<1) +#define PCIE_BRIDGE_BAR2_REMAP_swap_enable 1 + + uint32 bridgeOptReg1; /* 0x0820*/ +#define PCIE_BRIDGE_OPT_REG1_en_l1_int_status_mask_polarity (1<<12) +#define PCIE_BRIDGE_OPT_REG1_en_pcie_bridge_hole_detection (1<<11) +#define PCIE_BRIDGE_OPT_REG1_en_rd_reply_be_fix (1<<9) +#define PCIE_BRIDGE_OPT_REG1_enable_rd_be_opt (1<<7) + + uint32 bridgeOptReg2; /* 0x0824*/ +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK 0xe0000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT 29 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK 0x1f000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT 24 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK 0x00ff0000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT 16 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK 0x00000080 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT 7 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK 0x00000040 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT 6 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK 0x00000020 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT 5 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK 0x00000010 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT 4 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK 0x00000004 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT 2 +#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK 0x0000ff0b + + uint32 Ubus2PcieBar0BaseMask; /* 0x0828 */ +#define PCIE_BRIDGE_BAR0_BASE_base_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR0_BASE_base_MASK_SHIFT 20 +#define PCIE_BRIDGE_BAR0_BASE_mask_MASK 0x0000fff0 +#define PCIE_BRIDGE_BAR0_BASE_mask_MASK_SHIFT 4 +#define PCIE_BRIDGE_BAR0_BASE_swap_enable (1<<1) +#define PCIE_BRIDGE_BAR0_BASE_remap_enable 1 + + uint32 Ubus2PcieBar0RemapAdd; /* 0x082c */ +#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_SHIFT 20 + + uint32 Ubus2PcieBar1BaseMask; /* 0x0830 */ +#define PCIE_BRIDGE_BAR1_BASE_base_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR1_BASE_base_MASK_SHIFT 20 +#define PCIE_BRIDGE_BAR1_BASE_mask_MASK 0x0000fff0 +#define PCIE_BRIDGE_BAR1_BASE_mask_MASK_SHIFT 4 +#define PCIE_BRIDGE_BAR1_BASE_swap_enable (1<<1) +#define PCIE_BRIDGE_BAR1_BASE_remap_enable 1 + + uint32 Ubus2PcieBar1RemapAdd; /* 0x0834 */ +#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_SHIFT 20 + + uint32 bridgeErrStatus; /* 0x0838 */ + uint32 bridgeErrMask; /* 0x083c */ + uint32 coreErrStatus2; /* 0x0840 */ + uint32 coreErrMask2; /* 0x0844 */ + uint32 coreErrStatus1; /* 0x0848 */ + uint32 coreErrMask1; /* 0x084c */ + uint32 rcInterruptStatus; /* 0x0850 */ + uint32 rcInterruptMask; /* 0x0854 */ +#define PCIE_BRIDGE_INTERRUPT_MASK_int_a_MASK (1<<0) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_b_MASK (1<<1) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_c_MASK (1<<2) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_d_MASK (1<<3) + +}PcieBridgeRegs; + +#define PCIEH_DEV_OFFSET 0x8000 +#define PCIEH ((volatile uint32 * const) PCIE_BASE) +#define PCIEH_REGS ((volatile PcieRegs * const) PCIE_BASE) + +#define PCIEH_BLK_404_REGS ((volatile PcieBlk404Regs * const) \ + (PCIE_BASE+0x404)) +#define PCIEH_BLK_428_REGS ((volatile PcieBlk428Regs * const) \ + (PCIE_BASE+0x428)) +#define PCIEH_BLK_800_REGS ((volatile PcieBlk800Regs * const) \ + (PCIE_BASE+0x800)) +#define PCIEH_BLK_1000_REGS ((volatile PcieBlk1000Regs * const) \ + (PCIE_BASE+0x1000)) +#define PCIEH_BLK_1800_REGS ((volatile PcieBlk1800Regs * const) \ + (PCIE_BASE+0x1800)) +#define PCIEH_BRIDGE_REGS ((volatile PcieBridgeRegs * const) \ + (PCIE_BASE+0x2818)) + +typedef struct WlanShimRegs_a0 { + uint32 CcIdA; /* CC desc A */ + uint32 CcIdB; /* CC desc B */ + uint32 CcAddr; /* CC base addr */ + uint32 MacIdA; /* MAC desc A */ + uint32 MacIdB; /* MAC desc B */ + uint32 MacAddr; /* MAC base addr */ + uint32 ShimIdA; /* SHIM desc A */ + uint32 ShimIdB; /* SHIM desc B */ + uint32 ShimAddr; /* SHIM addr */ + uint32 ShimEot; /* EOT */ + uint32 CcControl; /* CC control */ + uint32 CcStatus; /* CC status */ + uint32 MacControl; /* MAC control */ + uint32 MacStatus; /* MAC status */ + uint32 ShimMisc; /* SHIM control registers */ + uint32 ShimStatus; /* SHIM status */ +}WlanShimRegs_a0; + +typedef struct WlanShimRegs_b0 { + uint32 ShimMisc; /* SHIM control registers */ +#define WLAN_SHIM_FORCE_CLOCKS_ON (1 << 2) +#define WLAN_SHIM_MACRO_DISABLE (1 << 1) +#define WLAN_SHIM_MACRO_SOFT_RESET (1 << 0) + + uint32 ShimStatus; /* SHIM status */ + + uint32 CcControl; /* CC control */ +#define SICF_WOC_CORE_RESET 0x10000 +#define SICF_BIST_EN 0x8000 +#define SICF_PME_EN 0x4000 +#define SICF_CORE_BITS 0x3ffc +#define SICF_FGC 0x0002 +#define SICF_CLOCK_EN 0x0001 + + uint32 CcStatus; /* CC status */ +#define SISF_BIST_DONE 0x8000 +#define SISF_BIST_ERROR 0x4000 +#define SISF_GATED_CLK 0x2000 +#define SISF_DMA64 0x1000 +#define SISF_CORE_BITS 0x0fff + + uint32 MacControl; /* MAC control */ + uint32 MacStatus; /* MAC status */ + + uint32 CcIdA; /* CC desc A */ + uint32 CcIdB; /* CC desc B */ + uint32 CcAddr; /* CC base addr */ + uint32 MacIdA; /* MAC desc A */ + uint32 MacIdB; /* MAC desc B */ + uint32 MacAddr; /* MAC base addr */ + uint32 ShimIdA; /* SHIM desc A */ + uint32 ShimIdB; /* SHIM desc B */ + uint32 ShimAddr; /* SHIM addr */ + uint32 ShimEot; /* EOT */ +}WlanShimRegs_b0; + +typedef union WlanShimRegs { + WlanShimRegs_a0 a0; + WlanShimRegs_b0 b0; /* SHIM control registers */ +}WlanShimRegs; + +#define WLAN_SHIM ((volatile WlanShimRegs * const)WLAN_SHIM_BASE) + +/* +** DECT IP Device Registers +*/ +typedef enum DECT_SHM_ENABLE_BITS +{ + DECT_SHM_IRQ_DSP_INT, + DECT_SHM_IRQ_DSP_IRQ_OUT, + DECT_SHM_IRQ_DIP_INT, + DECT_SHM_H2D_BUS_ERR, + DECT_SHM_IRQ_TX_DMA_DONE, + DECT_SHM_IRQ_RX_DMA_DONE, + DECT_SHM_IRQ_PLL_PHASE_LOCK = DECT_SHM_IRQ_RX_DMA_DONE + 2, /* Skip reserved bit */ + DECT_SHM_REG_DSP_BREAK, + DECT_SHM_REG_DIP_BREAK, + DECT_SHM_REG_IRQ_TO_IP = DECT_SHM_REG_DIP_BREAK + 2, /* Skip reserved bit */ + DECT_SHM_TX_DMA_DONE_TO_IP, + DECT_SHM_RX_DMA_DONE_TO_IP, +} DECT_SHM_ENABLE_BITS; + +typedef struct DECTShimControl +{ + uint32 dect_shm_ctrl; /* 0xb000b000 DECT shim control registers */ +#define APB_SWAP_MASK 0x0000C000 +#define APB_SWAP_16_BIT 0x00000000 +#define APB_SWAP_8_BIT 0x00004000 +#define AHB_SWAP_MASK 0x00003000 +#define AHB_SWAP_16_BIT 0x00003000 +#define AHB_SWAP_8_BIT 0x00002000 +#define AHB_SWAP_ACCESS 0x00001000 +#define AHB_SWAP_NONE 0x00000000 +#define DECT_PULSE_COUNT_ENABLE 0x00000200 +#define PCM_PULSE_COUNT_ENABLE 0x00000100 +#define DECT_SOFT_RESET 0x00000010 +#define PHCNT_CLK_SRC_PLL 0x00000008 +#define PHCNT_CLK_SRC_XTAL 0x00000000 +#define DECT_CLK_OUT_PLL 0x00000004 +#define DECT_CLK_OUT_XTAL 0x00000000 +#define DECT_CLK_CORE_PCM 0x00000002 +#define DECT_CLK_CORE_DECT 0x00000000 +#define DECT_PLL_REF_PCM 0x00000001 +#define DECT_PLL_REF_DECT 0x00000000 + + uint32 dect_shm_pcm_clk_cntr; /* 0xb000b004 PCM clock counter */ + uint32 dect_shm_dect_clk_cntr; /* 0xb000b008 DECT clock counter */ + uint32 dect_shm_dect_clk_cntr_sh; /* 0xb000b00c DECT clock counter snapshot */ + uint32 dect_shm_irq_enable; /* 0xb000b010 DECT interrupt enable register */ + uint32 dect_shm_irq_status; /* 0xb000b014 DECT Interrupt status register */ + uint32 dect_shm_irq_trig; /* 0xb000b018 DECT DSP ext IRQ trigger and IRQ test register */ + uint32 dect_shm_dma_status; /* 0xb000b01c DECT DMA STATUS register */ + uint32 dect_shm_xtal_ctrl; /* 0xb000b020 DECT analog tunable XTAL control register */ + uint32 dect_shm_bandgap_ctrl; /* 0xb000b024 DECT analog bandgap control register */ + uint32 dect_shm_afe_tx_ctrl; /* 0xb000b028 DECT analog TX DAC control register */ + uint32 dect_shm_afe_test_ctrl; /* 0xb000b02c DECT analog test control register */ + uint32 dect_shm_pll_reg_0; /* 0xb000b030 DECT PLL configuration register 0 */ + uint32 dect_shm_pll_reg_1; /* 0xb000b034 DECT PLL configuration register 1 */ +#define PLL_PWRDWN 0x01000000 +#define PLL_REFCOMP_PWRDOWN 0x02000000 +#define PLL_NDIV_PWRDOWN 0x04000000 +#define PLL_CH1_PWRDOWN 0x08000000 +#define PLL_CH2_PWRDOWN 0x10000000 +#define PLL_CH3_PWRDOWN 0x20000000 +#define PLL_DRESET 0x40000000 +#define PLL_ARESET 0x80000000 + + uint32 dect_shm_pll_reg_2; /* 0xb000b038 DECT PLL Ndiv configuration register */ + uint32 dect_shm_pll_reg_3; /* 0xb000b03c DECT PLL Pdiv and Mdiv configuration register */ +} DECTShimControl; + +#define DECT_CTRL ((volatile DECTShimControl * const) DECT_SHIM_CTRL_BASE) + +typedef struct DECTShimDmaControl +{ + uint32 dect_shm_dma_ctrl; /* 0xb000b050 DECT DMA control register */ +#define DMA_CLEAR 0x80000000 +#define DMA_SWAP_16_BIT 0x03000000 +#define DMA_SWAP_8_BIT 0x02000000 +#define DMA_SWAP_NONE 0x01000000 +#define DMA_SUBWORD_SWAP_MASK 0x03000000 +#define TRIG_CNT_CLK_SEL_PCM 0x00800000 +#define TRIG_CNT_IRQ_EN 0x00400000 +#define RX_CNT_TRIG_EN 0x00200000 +#define TX_CNT_TRIG_EN 0x00100000 +#define RX_INT_TRIG_EN 0x00080000 +#define TX_INT_TRIG_EN 0x00040000 +#define RX_REG_TRIG_EN 0x00020000 +#define TX_REG_TRIG_EN 0x00010000 +#define RX_TRIG_FIRST 0x00008000 +#define MAX_BURST_CYCLE_MASK 0x00001F00 +#define MAX_BURST_CYCLE_SHIFT 8 +#define RX_EN_3 0x00000080 +#define RX_EN_2 0x00000040 +#define RX_EN_1 0x00000020 +#define RX_EN_0 0x00000010 +#define TX_EN_3 0x00000008 +#define TX_EN_2 0x00000004 +#define TX_EN_1 0x00000002 +#define TX_EN_0 0x00000001 + + uint32 dect_shm_dma_trig_cnt_preset; /* 0xb000b054 DECT DMA trigger counter preset value */ + uint32 dect_shm_dma_ddr_saddr_tx_s0; /* 0xb000b058 DECT DMA DDR buffer starting address for TX slot 0 */ + uint32 dect_shm_dma_ddr_saddr_tx_s1; /* 0xb000b05c DECT DMA DDR buffer starting address for TX slot 1 */ + uint32 dect_shm_dma_ddr_saddr_tx_s2; /* 0xb000b060 DECT DMA DDR buffer starting address for TX slot 2 */ + uint32 dect_shm_dma_ddr_saddr_tx_s3; /* 0xb000b064 DECT DMA DDR buffer starting address for TX slot 3 */ + uint32 dect_shm_dma_ddr_saddr_rx_s0; /* 0xb000b068 DECT DMA DDR buffer starting address for RX slot 0 */ + uint32 dect_shm_dma_ddr_saddr_rx_s1; /* 0xb000b06c DECT DMA DDR buffer starting address for RX slot 1 */ + uint32 dect_shm_dma_ddr_saddr_rx_s2; /* 0xb000b070 DECT DMA DDR buffer starting address for RX slot 2 */ + uint32 dect_shm_dma_ddr_saddr_rx_s3; /* 0xb000b074 DECT DMA DDR buffer starting address for RX slot 3 */ + uint32 dect_shm_dma_ahb_saddr_tx_s01; /* 0xb000b078 DECT DMA AHB shared memory buffer starting address for TX slots 0 and 1 */ + uint32 dect_shm_dma_ahb_saddr_tx_s23; /* 0xb000b07c DECT DMA AHB shared memory buffer starting address for TX slots 2 and 3 */ + uint32 dect_shm_dma_ahb_saddr_rx_s01; /* 0xb000b080 DECT DMA AHB shared memory buffer starting address for RX slots 0 and 1 */ + uint32 dect_shm_dma_ahb_saddr_rx_s23; /* 0xb000b084 DECT DMA AHB shared memory buffer starting address for RX slots 2 and 3 */ + uint32 dect_shm_dma_xfer_size_tx; /* 0xb000b088 DECT DMA TX slots transfer size of each trigger */ + uint32 dect_shm_dma_xfer_size_rx; /* 0xb000b08c DECT DMA RX slots transfer size of each trigger */ + uint32 dect_shm_dma_buf_size_tx; /* 0xb000b090 DECT DMA TX slots memory buffer size */ + uint32 dect_shm_dma_buf_size_rx; /* 0xb000b094 DECT DMA RX slots memory buffer size */ + uint32 dect_shm_dma_offset_addr_tx_s01; /* 0xb000b098 DECT DMA access offset address for TX slots 0 and 1 */ + uint32 dect_shm_dma_offset_addr_tx_s23; /* 0xb000b09c DECT DMA access offset address for TX slots 2 and 3 */ + uint32 dect_shm_dma_offset_addr_rx_s01; /* 0xb000b0a0 DECT DMA access offset address for RX slots 0 and 1 */ + uint32 dect_shm_dma_offset_addr_rx_s23; /* 0xb000b0a4 DECT DMA access offset address for RX slots 2 and 3 */ + uint32 dect_shm_dma_xfer_cntr_tx; /* 0xb000b0a8 DECT DMA transfer count per slot in number of DMA transfer size */ + uint32 dect_shm_dma_xfer_cntr_rx; /* 0xb000b0a8 DECT DMA transfer count per slot in number of DMA transfer size */ +} DECTShimDmaControl; + +#define DECT_DMA_CTRL ((volatile DECTShimDmaControl * const) DECT_SHIM_DMA_CTRL_BASE) + + +typedef struct ahbRegisters +{ + uint16 dsp_main_sync0; /* 0xb0e57f80 DSP main counter outputs sel reg 0 */ + uint16 dsp_main_sync1; /* 0xb0e57f82 DSP main counter outputs sel reg 1 */ + uint16 dsp_main_cnt; /* 0xb0e57f84 DSP main counter reg */ + uint16 reserved1; /* 0xb0e57f86 Reserved */ + uint16 reserved2; /* 0xb0e57f88 Reserved */ + uint16 reserved3; /* 0xb0e57f8a Reserved */ + uint16 reserved4; /* 0xb0e57f8c Reserved */ + uint16 reserved5; /* 0xb0e57f8e Reserved */ + uint16 reserved6; /* 0xb0e57f90 Reserved */ + uint16 dsp_ram_out0; /* 0xb0e57f92 DSP RAM output register 0 */ + uint16 dsp_ram_out1; /* 0xb0e57f94 DSP RAM output register 1 */ + uint16 dsp_ram_out2; /* 0xb0e57f96 DSP RAM output register 2 */ + uint16 dsp_ram_out3; /* 0xb0e57f98 DSP RAM output register 3 */ + uint16 dsp_ram_in0; /* 0xb0e57f9a DSP RAM input register 0 */ + uint16 dsp_ram_in1; /* 0xb0e57f9c DSP RAM input register 1 */ + uint16 dsp_ram_in2; /* 0xb0e57f9e DSP RAM input register 2 */ + uint16 dsp_ram_in3; /* 0xb0e57fa0 DSP RAM input register 3 */ + uint16 dsp_zcross1_out; /* 0xb0e57fa2 DSP RAM zero crossing 1 output reg */ + uint16 dsp_zcross2_out; /* 0xb0e57fa4 DSP RAM zero crossing 2 output reg */ + uint16 reserved7; /* 0xb0e57fa6 Reserved */ + uint16 reserved8; /* 0xb0e57fa8 Reserved */ + uint16 reserved9; /* 0xb0e57faa Reserved */ + uint16 reserved10; /* 0xb0e57fac Reserved */ + uint16 reserved11; /* 0xb0e57fae Reserved */ + uint16 reserved12; /* 0xb0e57fb0 Reserved */ + uint16 reserved13; /* 0xb0e57fb2 Reserved */ + uint16 reserved14; /* 0xb0e57fb4 Reserved */ + uint16 reserved15; /* 0xb0e57fb6 Reserved */ + uint16 reserved16; /* 0xb0e57fb8 Reserved */ + uint16 reserved17; /* 0xb0e57fba Reserved */ + uint16 dsp_main_ctrl; /* 0xb0e57fbc DSP main counter control and preset reg */ + uint16 reserved18; /* 0xb0e57fbe Reserved */ + uint16 reserved19; /* 0xb0e57fc0 Reserved */ + uint16 reserved20; /* 0xb0e57fc2 Reserved */ + uint16 reserved21; /* 0xb0e57fc4 Reserved */ + uint16 reserved22; /* 0xb0e57fc6 Reserved */ + uint16 reserved23; /* 0xb0e57fc8 Reserved */ + uint16 reserved24; /* 0xb0e57fca Reserved */ + uint16 reserved25; /* 0xb0e57fce Reserved */ + uint16 dsp_ctrl; /* 0xb0e57fd0 DSP control reg */ + uint16 dsp_pc; /* 0xb0e57fd2 DSP program counter */ + uint16 dsp_pc_start; /* 0xb0e57fd4 DSP program counter start */ + uint16 dsp_irq_start; /* 0xb0e57fd6 DSP interrupt vector start */ + uint16 dsp_int; /* 0xb0e57fd8 DSP to system bus interrupt vector */ + uint16 dsp_int_mask; /* 0xb0e57fda DSP to system bus interrupt vector mask */ + uint16 dsp_int_prio1; /* 0xb0e57fdc DSP interrupt mux 1 */ + uint16 dsp_int_prio2; /* 0xb0e57fde DSP interrupt mux 2 */ + uint16 dsp_overflow; /* 0xb0e57fe0 DSP to system bus interrupt overflow reg */ + uint16 dsp_jtbl_start; /* 0xb0e57fe2 DSP jump table start address */ + uint16 reserved26; /* 0xb0e57fe4 Reserved */ + uint16 reserved27; /* 0xb0e57fe6 Reserved */ + uint16 reserved28; /* 0xb0e57fe8 Reserved */ + uint16 reserved29; /* 0xb0e57fea Reserved */ + uint16 reserved30; /* 0xb0e57fec Reserved */ + uint16 reserved31; /* 0xb0e57fee Reserved */ + uint16 dsp_debug_inst; /* 0xb0e57ff0 DSP debug instruction register */ + uint16 reserved32; /* 0xb0e57ff2 Reserved */ + uint16 dsp_debug_inout_l; /* 0xb0e57ff4 DSP debug data (LSW) */ + uint16 dsp_debug_inout_h; /* 0xb0e57ff6 DSP debug data (MSW) */ + uint16 reserved33; /* 0xb0e57ff8 Reserved */ + uint16 reserved34; /* 0xb0e57ffa Reserved */ + uint16 reserved35; /* 0xb0e57ffc Reserved */ + uint16 reserved36; /* 0xb0e57ffe Reserved */ +} ahbRegisters; + +#define AHB_REGISTERS ((volatile ahbRegisters * const) DECT_AHB_REG_BASE) + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/shared/broadcom/include/bcm963xx/6368_common.h b/shared/broadcom/include/bcm963xx/6368_common.h new file mode 100755 index 0000000..1df5be5 --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6368_common.h @@ -0,0 +1,270 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6368_common.h */ +/* DATE: 02/06/07 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6368 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6368_MAP_COMMON_H +#define __BCM6368_MAP_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define NAND_INTR_BASE 0xb0000070 /* nand interrupt control registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 +#define NAND_SEC_BASE 0xb0000300 +#define OTP_BASE 0xb0000400 +#define UBUS_STAT_BASE 0xb0000500 +#define NAND_CACHE_BASE 0xb0000600 +#define SPI_BASE 0xb0000800 /* SPI master controller registers */ +#define MPI_BASE 0xb0001000 /* MPI control registers */ +#define MEMC_BASE 0xb0001200 /* Memory control registers */ +#define DDR_BASE 0xb0001280 /* DDR IO Buf Control registers */ +#define USB_CTL_BASE 0xb0001400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10001500 /* USB host registers */ +#define USB_OHCI_BASE 0x10001600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0001700 +#define SAR_BASE 0xb0001800 /* ATM SAR control registers */ +#define SAR_CMF_BASE 0xb0002000 /* ATM SAR CMF control registers */ +#define PCM_BASE 0xb0004000 /* PCM control registers */ +#define IPSEC_BASE 0xb0004100 +#define USB_DMA_BASE 0xb0004800 /* USB 2.0 device DMA regiseters */ +#define SAR_DMA_BASE 0xb0005000 /* ATM SAR DMA control registers */ +#define PCM_DMA_BASE 0xb0005800 /* PCM UIDMA register base */ +#define IPSEC_DMA_BASE 0xb0006000 +#define SWITCH_DMA_BASE 0xb0006800 +#define SWITCH_BASE 0xb0f00000 +#define SWITCH_CMF_BASE 0xb0f0a000 /* Switch CMF register base */ + +#define ADSL_PHY_BASE 0xb0f40000 +#define ADSL_ENUM_BASE 0xb0f56000 +#define ADSL_LMEM_BASE 0xb0f80000 + +/* +##################################################################### +# System PLL Control Register +##################################################################### +*/ + + +/* +##################################################################### +# GPIO Control Registers +##################################################################### +*/ + + +/* +##################################################################### +# Memory Control Registers +##################################################################### +*/ +#define MEMC_CONTROL 0x0 +#define MEMC_CONFIG 0x4 +#define MEMC_REF_PD_CONTROL 0x8 +#define MEMC_BIST_STATUS 0xc +#define MEMC_M_EM_BUF 0x10 +#define MEMC_BANK_CLS_TIM 0x14 +#define MEMC_PRIOR_INV_TIM 0x18 +#define MEMC_DRAM_TIM 0x1c +#define MEMC_INT_STATUS 0x20 +#define MEMC_INT_MASK 0x24 +#define MEMC_INT_INFO 0x28 +#define MEMC_BARRIER 0x50 +#define MEMC_CORE_ID 0x54 + +#define DDR_REV_ID 0x0 +#define DDR_PAD_SSTL_MODE 0x4 +#define DDR_CMD_PAD_CNTL 0x8 +#define DDR_DQ_PAD_CNTL 0xc +#define DDR_DQS_PAD_CNTL 0x10 +#define DDR_CLK_PAD_CNTL 0x14 +#define DDR_PLL_CNTL0 0x18 +#define DDR_PLL_CNTL1 0x1c +#define DDR_MIPSDDR_PLL_CONFIG 0x20 +#define DDR_MIPSDDR_PLL_MDIV 0x24 +#define DDR_DSL_PHY_PHASE_CNTL 0x28 +#define DDR_DSL_CPU_PHASE_CNTL 0x2c +#define DDR_MIPS_PHASE_CNTL 0x30 +#define DDR_DDR1_2_PHASE_CNTL 0x34 +#define DDR_DDR3_4_PHASE_CNTL 0x38 +#define DDR_VCDL_PHASE_CNTL0 0x3c +#define DDR_VCDL_PHASE_CNTL1 0x40 +#define DDR_BSLICE_CNTL 0x44 +#define DDR_DESKEW_DLL_CNTL 0x48 +#define DDR_DESKEW_DLL_RESET 0x4c +#define DDR_DESKEW_DLL_PHASE 0x50 +#define DDR_ANALOG_TEST_CNTL 0x54 +#define DDR_RD_DQS_GATE_CNTL 0x58 +#define DDR_MISC 0x5c +#define DDR_SPARE0 0x60 +#define DDR_SPARE1 0x64 +#define DDR_SPARE2 0x68 +#define DDR_CLBIST 0x6c +#define DDR_LBIST_CRC 0x70 +#define DDR_UBUS_PHASE_CNTR 0x74 +#define DDR_UBUS_PI_DSK0 0x78 +#define DDR_UBUS_PI_DSK1 0x7c + +// Some bit/field definitions for the MEMC_CONFIG register. +#define MEMC_EARLY_HDR_CNT_SHFT 25 +#define MEMC_EARLY_HDR_CNT_MASK (0x7<<MEMC_EARLYHDRCNT_SHFT) +#define MEMC_USE_HDR_CNT (1<<24) +#define MEMC_EN_FAST_REPLY (1<<23) +#define MEMC_RR_ARB (1<<22) +#define MEMC_SFX_NO_MRS2 (1<<21) +#define MEMC_SFX_NO_DLL_RST (1<<20) +#define MEMC_LLMB_ONE_REQ (1<<19) +#define MEMC_SYS_PORT_CMD_MODE (1<<18) +#define MEMC_PAD_OP_MODE (1<<17) +#define MEMC_DQS_GATE_EN (1<<16) +#define MEMC_PRED_RD_STROBE_EN (1<<15) +#define MEMC_PRED_RD_LATENCY_SEL (1<<14) +#define MEMC_UBUS_CLF_EN (1<<8) + +#define MEMC_ROW_SHFT 6 +#define MEMC_ROW_MASK (0x3<<MEMC_ROW_SHFT) +#define MEMC_11BIT_ROW 0 +#define MEMC_12BIT_ROW 1 +#define MEMC_13BIT_ROW 2 +#define MEMC_14BIT_ROW 3 + +#define MEMC_COL_SHFT 3 +#define MEMC_COL_MASK (0x7<<MEMC_COL_SHFT) +#define MEMC_8BIT_COL 0 +#define MEMC_9BIT_COL 1 +#define MEMC_10BIT_COL 2 +#define MEMC_11BIT_COL 3 + +#define MEMC_SEL_PRIORITY (1<<2) + +#define MEMC_WIDTH_SHFT 1 +#define MEMC_WIDTH_MASK (0x1<<MEMC_WIDTH_SHFT) +#define MEMC_32BIT_BUS 0 +#define MEMC_16BIT_BUS 1 + +#define MEMC_MEMTYPE_SDR (0<<0) +#define MEMC_MEMTYPE_DDR (1<<0) + +/* +##################################################################### +# MPI Control Registers +##################################################################### +*/ +#define CS0BASE 0x00 +#define CS0CNTL 0x04 + +/* +# CSxBASE settings +# Size in low 4 bits +# Base Address for match in upper 24 bits +*/ +#define EBI_SIZE_8K 0 +#define EBI_SIZE_16K 1 +#define EBI_SIZE_32K 2 +#define EBI_SIZE_64K 3 +#define EBI_SIZE_128K 4 +#define EBI_SIZE_256K 5 +#define EBI_SIZE_512K 6 +#define EBI_SIZE_1M 7 +#define EBI_SIZE_2M 8 +#define EBI_SIZE_4M 9 +#define EBI_SIZE_8M 10 +#define EBI_SIZE_16M 11 +#define EBI_SIZE_32M 12 +#define EBI_SIZE_64M 13 +#define EBI_SIZE_128M 14 +#define EBI_SIZE_256M 15 + +/* CSxCNTL settings */ +#define EBI_ENABLE 0x00000001 /* .. enable this range */ +#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */ +#define ZEROWT 0x00000000 /* .. 0 WS */ +#define ONEWT 0x00000002 /* .. 1 WS */ +#define TWOWT 0x00000004 /* .. 2 WS */ +#define THREEWT 0x00000006 /* .. 3 WS */ +#define FOURWT 0x00000008 /* .. 4 WS */ +#define FIVEWT 0x0000000a /* .. 5 WS */ +#define SIXWT 0x0000000c /* .. 6 WS */ +#define SEVENWT 0x0000000e /* .. 7 WS */ +#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */ +#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */ +#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */ +#define EBI_FIFO 0x00000200 /* .. enable fifo */ +#define EBI_RE 0x00000400 /* .. Reverse Endian */ + +/* +##################################################################### +# UART Control Registers +##################################################################### +*/ +#define UART0CONTROL 0x01 +#define UART0CONFIG 0x02 +#define UART0RXTIMEOUT 0x03 +#define UART0BAUD 0x04 +#define UART0FIFOCFG 0x0a +#define UART0INTMASK 0x10 +#define UART0INTSTAT 0x12 +#define UART0DATA 0x17 + +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + +#define XMITBREAK 0x40 /* Config register */ +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/broadcom/include/bcm963xx/6368_map.h b/shared/broadcom/include/bcm963xx/6368_map.h new file mode 100755 index 0000000..590e06d --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6368_map.h @@ -0,0 +1,1592 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6368_map.h */ +/* DATE: 02/06/07 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6368 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6368_MAP_H +#define __BCM6368_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" +#include "6368_common.h" +#include "6368_intr.h" + +/* macro to convert logical data addresses to physical */ +/* DMA hardware must see physical address */ +#define LtoP( x ) ( (uint32)x & 0x1fffffff ) +#define PtoL( x ) ( LtoP(x) | 0xa0000000 ) + +typedef struct MemoryControl +{ + uint32 Control; /* (00) */ +#define MEMC_SELF_REFRESH (1<<6) // enable self refresh mode +#define MEMC_MRS (1<<4) // generate a mode register select cycle +#define MEMC_PRECHARGE (1<<3) // generate a precharge cycle +#define MEMC_REFRESH (1<<2) // generate an auto refresh cycle +#define MEMC_SEQUENCE_ENABLE (1<<1) // enable memory controller sequencer +#define MEMC_MASTER_ENABLE (1<<0) // enable accesses to external sdram + + uint32 Config; /* (04) */ +#define MEMC_EARLY_HDR_CNT_SHFT 25 +#define MEMC_EARLY_HDR_CNT_MASK (0x7<<MEMC_EARLYHDRCNT_SHFT) +#define MEMC_USE_HDR_CNT (1<<24) +#define MEMC_EN_FAST_REPLY (1<<23) +#define MEMC_RR_ARB (1<<22) +#define MEMC_SFX_NO_MRS2 (1<<21) +#define MEMC_SFX_NO_DLL_RST (1<<20) +#define MEMC_LLMB_ONE_REQ (1<<19) +#define MEMC_SYS_PORT_CMD_MODE (1<<18) +#define MEMC_PAD_OP_MODE (1<<17) +#define MEMC_DQS_GATE_EN (1<<16) +#define MEMC_PRED_RD_STROBE_EN (1<<15) +#define MEMC_PRED_RD_LATENCY_SEL (1<<14) +#define MEMC_UBUS_CLF_EN (1<<8) + +#define MEMC_ROW_SHFT 6 +#define MEMC_ROW_MASK (0x3<<MEMC_ROW_SHFT) +#define MEMC_11BIT_ROW 0 +#define MEMC_12BIT_ROW 1 +#define MEMC_13BIT_ROW 2 +#define MEMC_14BIT_ROW 3 + +#define MEMC_COL_SHFT 3 +#define MEMC_COL_MASK (0x7<<MEMC_COL_SHFT) +#define MEMC_8BIT_COL 0 +#define MEMC_9BIT_COL 1 +#define MEMC_10BIT_COL 2 +#define MEMC_11BIT_COL 3 + +#define MEMC_SEL_PRIORITY (1<<2) + +#define MEMC_WIDTH_SHFT 1 +#define MEMC_WIDTH_MASK (0x1<<MEMC_WIDTH_SHFT) +#define MEMC_32BIT_BUS 0 +#define MEMC_16BIT_BUS 1 + +#define MEMC_MEMTYPE_SDR (0<<0) +#define MEMC_MEMTYPE_DDR (1<<0) + + uint32 RefreshPdControl; /* (08) */ +#define MEMC_REFRESH_ENABLE (1<<15) + + uint32 BistStatus; /* (0C) */ + uint32 ExtendedModeBuffer; /* (10) */ + uint32 BankClosingTimer; /* (14) */ + uint32 PriorityInversionTimer; /* (18) */ + + uint32 DramTiming; /* (1c) */ +#define MEMC_WR_NOP_RD (1<<23) +#define MEMC_WR_NOP_WR (1<<22) +#define MEMC_RD_NOP_WR (1<<21) +#define MEMC_RD_NOP_RD (1<<20) +#define MEMC_CAS_LATENCY_2 (0) +#define MEMC_CAS_LATENCY_2_5 (1) +#define MEMC_CAS_LATENCY_3 (2) + + uint32 IntStatus; /* (20) */ + uint32 IntMask; /* (24) */ +#define MEMC_INT3 (1<<3) +#define MEMC_INT2 (2<<3) +#define MEMC_INT1 (1<<3) +#define MEMC_INT0 (0<<3) + + uint32 IntInfo; /* (28) */ + uint8 unused5[0x50-0x2c]; /* (2c) */ + uint32 Barrier; /* (50) */ + uint32 CoreId; /* (54) */ +} MemoryControl; + +#define MEMC ((volatile MemoryControl * const) MEMC_BASE) + +typedef struct DDRControl { + uint32 RevID; /* 00 */ + uint32 PadSSTLMode; /* 04 */ + uint32 CmdPadCntl; /* 08 */ + uint32 DQPadCntl; /* 0c */ + uint32 DQSPadCntl; /* 10 */ + uint32 ClkPadCntl0; /* 14 */ + uint32 MIPSDDRPLLCntl0; /* 18 */ + uint32 MIPSDDRPLLCntl1; /* 1c */ + uint32 MIPSDDRPLLConfig; /* 20 */ +#define MIPSDDR_NDIV_SHFT 16 +#define MIPSDDR_NDIV_MASK (0x1ff<<MIPSDDR_NDIV_SHFT) +#define REF_MDIV_SHFT 8 +#define REF_MDIV_MASK (0xff<<REF_MDIV_SHFT) +#define MIPSDDR_P2_SHFT 4 +#define MIPSDDR_P2_MASK (0xf<<MIPSDDR_P2_SHFT) +#define MIPSDDR_P1_SHFT 0 +#define MIPSDDR_P1_MASK (0xf<<MIPSDDR_P1_SHFT) + uint32 MIPSDDRPLLMDiv; /* 24 */ +#define DDR_MDIV_SHFT 8 +#define DDR_MDIV_MASK (0xff<<DDR_MDIV_SHFT) +#define MIPS_MDIV_SHFT 0 +#define MIPS_MDIV_MASK (0xff<<MIPS_MDIV_SHFT) + uint32 DSLCorePhaseCntl; /* 28 */ + uint32 DSLCpuPhaseCntr; /* 2c */ +#define DSL_PHY_AFE_PI_CNTR_CYCLES_SHIFT 28 +#define DSL_PHY_AFE_PI_CNTR_CYCLES_MASK (0xF << DSL_PHY_AFE_PI_CNTR_CYCLES_SHIFT) +#define DSL_PHY_PI_CNTR_CYCLES_SHIFT 24 +#define DSL_PHY_PI_CNTR_CYCLES_MASK (0xF << DSL_PHY_PI_CNTR_CYCLES_SHIFT) +#define DSL_PHY_AFE_PI_CNTR_EN (1 << 22) +#define DSL_PHY_PI_CNTR_EN (1 << 21) +#define DSL_CPU_PI_CNTR_EN (1 << 20) +#define DSL_CPU_PI_CNTR_CYCLES_SHIFT 16 +#define DSL_CPU_PI_CNTR_CYCLES_MASK (0xF << DSL_CPU_PI_CNTR_CYCLES_SHIFT) + uint32 MIPSPhaseCntl; /* 30 */ +#define PH_CNTR_EN (1 << 20) + uint32 DDR1_2PhaseCntl0; /* 34 */ + uint32 DDR3_4PhaseCntl0; /* 38 */ + uint32 VCDLPhaseCntl0; /* 3c */ + uint32 VCDLPhaseCntl1; /* 40 */ + uint32 WSliceCntl; /* 44 */ + uint32 DeskewDLLCntl; /* 48 */ + uint32 DeskewDLLReset; /* 4c */ + uint32 DeskewDLLPhase; /* 50 */ + uint32 AnalogTestCntl; /* 54 */ + uint32 RdDQSGateCntl; /* 58 */ + uint32 PLLTestReg; /* 5c */ + uint32 Spare0; /* 60 */ + uint32 Spare1; /* 64 */ + uint32 Spare2; /* 68 */ + uint32 CLBist; /* 6c */ + uint32 LBistCRC; /* 70 */ + uint32 UBUSPhaseCntl; /* 74 */ + uint32 UBUSPIDeskewLLMB0; /* 78 */ + uint32 UBUSPIDeskewLLMB1; /* 7C */ + +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define USBH_IDDQ_EN (1 << 19) +#define IPSEC_CLK_EN (1 << 18) +#define NAND_CLK_EN (1 << 17) +#define DISABLE_GLESS (1 << 16) +#define USBH_CLK_EN (1 << 15) +#define PCM_CLK_EN (1 << 14) +#define UTOPIA_CLK_EN (1 << 13) +#define ROBOSW_CLK_EN (1 << 12) +#define SAR_CLK_EN (1 << 11) +#define USBD_CLK_EN (1 << 10) +#define SPI_CLK_EN (1 << 9) +#define SWPKT_SAR_CLK_EN (1 << 8) +#define SWPKT_USB_CLK_EN (1 << 7) +#define PHYMIPS_CLK_EN (1 << 6) +#define VDSL_CLK_EN (1 << 5) +#define VDSL_BONDING_EN (1 << 4) +#define VDSL_AFE_EN (1 << 3) +#define VDSL_QPROC_EN (1 << 2) + + uint32 pll_control; /* (08) word 2 */ +#define SOFT_RESET 0x00000001 // 0 + + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_PCM (1 << 13) +#define SOFT_RST_USBH (1 << 12) +#define SOFT_RST_USBD (1 << 11) +#define SOFT_RST_SWITCH (1 << 10) +#define SOFT_RST_SAR (1 << 7) +#define SOFT_RST_EPHY (1 << 6) +#define SOFT_RST_IPSEC (1 << 4) +#define SOFT_RST_MPI (1 << 3) +#define SOFT_RST_SPI (1 << 0) + + uint32 unused1; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 ExtIrqCfg1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo<thresh + */ + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1) + * if these bits are also enabled to GPIO_o + */ +#define DTREN 0x01 +#define RTSEN 0x02 + + byte unused1; + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to + * detect irq on rising AND falling + * edges for corresponding GPIO_i + * if enabled (edge insensitive) + */ + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense + * 0 for negedge sense if + * not configured for edge + * insensitive (see above) + * Lower 4 bits: Mask to enable change + * detection IRQ for corresponding + * GPIO_i + */ + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits + * have changed (may set IRQ). + * read automatically clears bit + * Lower 4 bits are actual status + */ + + uint16 intMask; /* Same Bit defs for Mask and status */ + uint16 intStatus; +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + + uint16 unused2; + uint16 Data; /* Write to TX, Read from RX */ + /* bits 11:8 are BRK,PAR,FRM errors */ + + uint32 unused3; + uint32 unused4; +} Uart; + +#define UART ((volatile Uart * const) UART_BASE) + +/* +** Gpio Controller +*/ + +typedef struct GpioControl { + uint64 GPIODir; /* 0 */ + uint64 GPIOio; /* 8 */ + uint32 LEDCtrl; +#define LED_ALL_STROBE 0x0f000000 +#define LED3_STROBE 0x08000000 +#define LED2_STROBE 0x04000000 +#define LED1_STROBE 0x02000000 +#define LED0_STROBE 0x01000000 +#define LED_TEST 0x00010000 +#define DISABLE_LINK_ACT_ALL 0x0000f000 +#define DISABLE_LINK_ACT_3 0x00008000 +#define DISABLE_LINK_ACT_2 0x00004000 +#define DISABLE_LINK_ACT_1 0x00002000 +#define DISABLE_LINK_ACT_0 0x00001000 +#define LED_INTERVAL_SET_MASK 0x00000f00 +#define LED_INTERVAL_SET_1280MS 0x00000700 +#define LED_INTERVAL_SET_640MS 0x00000600 +#define LED_INTERVAL_SET_320MS 0x00000500 +#define LED_INTERVAL_SET_160MS 0x00000400 +#define LED_INTERVAL_SET_80MS 0x00000300 +#define LED_INTERVAL_SET_40MS 0x00000200 +#define LED_INTERVAL_SET_20MS 0x00000100 +#define LED_ON_ALL 0x000000f0 +#define LED_ON_3 0x00000080 +#define LED_ON_2 0x00000040 +#define LED_ON_1 0x00000020 +#define LED_ON_0 0x00000010 +#define LED_ENABLE_ALL 0x0000000f +#define LED_ENABLE_3 0x00000008 +#define LED_ENABLE_2 0x00000004 +#define LED_ENABLE_1 0x00000002 +#define LED_ENABLE_0 0x00000001 + uint32 SpiSlaveCfg; /* 14 */ + uint32 GPIOMode; /* 18 */ +#define GPIO_MODE_SPI_SSN5 (1<<31) +#define GPIO_MODE_SPI_SSN4 (1<<30) +#define GPIO_MODE_SPI_SSN3 (1<<29) +#define GPIO_MODE_SPI_SSN2 (1<<28) +#define GPIO_MODE_EBI_CS3 (1<<27) +#define GPIO_MODE_EBI_CS2 (1<<26) +#define GPIO_MODE_PCMCIA_VS2 (1<<25) +#define GPIO_MODE_PCMCIA_VS1 (1<<24) +#define GPIO_MODE_PCMCIA_CD2 (1<<23) +#define GPIO_MODE_PCMCIA_CD1 (1<<22) +#define GPIO_MODE_PCI_GNT0 (1<<20) +#define GPIO_MODE_PCI_REQ0 (1<<19) +#define GPIO_MODE_PCI_INTB (1<<18) +#define GPIO_MODE_PCI_GNT1 (1<<17) +#define GPIO_MODE_PCI_REQ1 (1<<16) +#define GPIO_MODE_USBD_LED (1<<14) +#define GPIO_MODE_ROBOSW_LED1 (1<<13) +#define GPIO_MODE_ROBOSW_LED0 (1<<12) +#define GPIO_MODE_ROBOSW_LED_CLK (1<<11) +#define GPIO_MODE_ROBOSW_LED_DATA (1<<10) +#define GPIO_MODE_EPHY3_LED (1<<9) +#define GPIO_MODE_EPHY2_LED (1<<8) +#define GPIO_MODE_EPHY1_LED (1<<7) +#define GPIO_MODE_EPHY0_LED (1<<6) +#define GPIO_MODE_INET_LED (1<<5) +#define GPIO_MODE_SERIAL_LED_CLK (1<<4) +#define GPIO_MODE_SERIAL_LED_DATA (1<<3) +#define GPIO_MODE_SYS_IRQ (1<<2) +#define GPIO_MODE_ANALOG_AFE_1 (1<<1) +#define GPIO_MODE_ANALOG_AFE_0 (1<<0) + + uint32 VregConfig; /* 1C */ +#define VREG_VSEL1P2_SHIFT 8 +#define VREG_VSEL1P2_MASK (0x0f<<8) +#define VREG_VSEL1P2_MIDDLE 9 + + uint32 AuxLedInterval; /* 20 */ +#define AUX_LED_IN_7 0x80000000 +#define AUX_LED_IN_6 0x40000000 +#define AUX_LED_IN_5 0x20000000 +#define AUX_LED_IN_4 0x10000000 +#define AUX_LED_IN_MASK 0xf0000000 +#define LED_IN_3 0x08000000 +#define LED_IN_2 0x04000000 +#define LED_IN_1 0x02000000 +#define LED_IN_0 0x01000000 +#define AUX_LED_TEST 0x00400000 +#define USE_NEW_INTV 0x00200000 +#define LED7_LNK_ORAND 0x00100000 +#define LED7_LNK_MASK 0x000f0000 +#define LED7_LNK_MASK_SHFT 16 +#define LED7_ACT_MASK 0x0000f000 +#define LED7_ACT_MASK_SHFT 12 +#define AUX_FLASH_INTV 0x00000fc0 +#define AUX_FLASH_INTV_SHFT 6 +#define AUX_BLINK_INTV 0x0000003f + uint32 AuxLedCtrl; /* 24 */ +#define AUX_HW_DISAB_7 0x80000000 +#define AUX_STROBE_7 0x40000000 +#define AUX_MODE_7 0x30000000 +#define AUX_MODE_SHFT_7 28 +#define AUX_HW_DISAB_6 0x08000000 +#define AUX_STROBE_6 0x04000000 +#define AUX_MODE_6 0x03000000 +#define AUX_MODE_SHFT_6 24 +#define AUX_HW_DISAB_5 0x00800000 +#define AUX_STROBE_5 0x00400000 +#define AUX_MODE_5 0x00300000 +#define AUX_MODE_SHFT_5 20 +#define AUX_HW_DISAB_4 0x00080000 +#define AUX_STROBE_4 0x00040000 +#define AUX_MODE_4 0x00030000 +#define AUX_MODE_SHFT_4 16 +#define AUX_HW_DISAB_3 0x00008000 +#define AUX_STROBE_3 0x00004000 +#define AUX_MODE_3 0x00003000 +#define AUX_MODE_SHFT_3 12 +#define AUX_HW_DISAB_2 0x00000800 +#define AUX_STROBE_2 0x00000400 +#define AUX_MODE_2 0x00000300 +#define AUX_MODE_SHFT_2 8 +#define AUX_HW_DISAB_1 0x00000080 +#define AUX_STROBE_1 0x00000040 +#define AUX_MODE_1 0x00000030 +#define AUX_MODE_SHFT_1 4 +#define AUX_HW_DISAB_0 0x00000008 +#define AUX_STROBE_0 0x00000004 +#define AUX_MODE_0 0x00000003 +#define AUX_MODE_SHFT_0 0 + +#define LED_STEADY_OFF 0x0 +#define LED_FLASH 0x1 +#define LED_BLINK 0x2 +#define LED_STEADY_ON 0x3 + + uint32 TestControl; /* 28 */ + + uint32 VDSLControl; /* 2C */ +#define VDSL_CORE_RESET (1<<2) +#define VDSL_MIPS_RESET (1<<1) +#define VDSL_MIPS_POR_RESET (1<<0) +#define VDSL_CLK_RATIO_SHIFT 8 +#define VDSL_CLK_RATIO_MSK (0x1F << VDSL_CLK_RATIO_SHIFT) + uint32 RoboSWLEDControl; /* 30 */ + uint32 RoboSWLEDLSR; /* 34 */ + uint32 GPIOBaseMode; /* 38 */ +#define EN_PCI_CLK_66 (1<<20) +#define EN_UTO_CLK_FAST (1<<19) +#define EN_UTO (1<<18) +#define EN_GMII2 (1<<17) +#define EN_GMII1 (1<<16) + uint32 RoboswEphyCtrl; /* 3C */ +#define RSW_HW_FWDG_EN (1<<19) +#define RSW_MII_DUMB_FWDG_EN (1<<16) +#define EPHY_RST_4 (1<<9) +#define EPHY_RST_3 (1<<8) +#define EPHY_RST_2 (1<<7) +#define EPHY_RST_1 (1<<6) +#define EPHY_PWR_DOWN_4 (1<<5) +#define EPHY_PWR_DOWN_3 (1<<4) +#define EPHY_PWR_DOWN_2 (1<<3) +#define EPHY_PWR_DOWN_1 (1<<2) +#define EPHY_PWR_DOWN_DLL (1<<1) +#define EPHY_PWR_DOWN_BIAS (1<<0) + uint32 StrapBus; /* 40 */ +#define UTOPIA_MASTER_ON (1<<14) +#define MISC_STRAP_BUS_BOOT_SEL_MASK 0x3 +#define MISC_STRAP_BUS_BOOT_SEL_SHIFT 0 +#define MISC_STRAP_BUS_BOOT_PARALLEL 0x03 +#define MISC_STRAP_BUS_BOOT_SERIAL 0x01 +#define MISC_STRAP_BUS_BOOT_NAND 0x00 + uint32 StrapOverride; /* 44 */ + + uint32 RingOscCtrl0; /* 48 */ +#define RING_OSC_256_CYCLES 8 +#define RING_OSC_512_CYCLES 9 +#define RING_OSC_1024_CYCLES 10 + + uint32 RingOscCtrl1; /* 4C */ +#define RING_OSC_ENABLE_MASK (0x7f<<24) +#define RING_OSC_ENABLE_SHIFT 24 +#define RING_OSC_MAX 7 +#define RING_OSC_COUNT_RESET (0x1<<23) +#define RING_OSC_SELECT_MASK (0x7<<20) +#define RING_OSC_SELECT_SHIFT 20 +#define RING_OSC_IRQ (0x1<<18) +#define RING_OSC_COUNTER_OVERFLOW (0x1<<17) +#define RING_OSC_COUNTER_BUSY (0x1<<16) +#define RING_OSC_COUNT_MASK 0x0000ffff + + uint32 SerialLed; /* 50 */ + uint32 SerialLedCtrl; /* 54 */ +#define SER_LED_BUSY (1<<3) +#define SER_LED_POLARITY (1<<2) +#define SER_LED_DIV_1 0 +#define SER_LED_DIV_2 1 +#define SER_LED_DIV_4 2 +#define SER_LED_DIV_8 3 +#define SER_LED_DIV_MASK 0x3 +#define SER_LED_DIV_SHIFT 0 + uint32 unused2[4]; /* 58 */ + uint32 DieRevID; /* 68 */ + uint32 DiagMemStatus; /* 6c */ + uint32 DiagSelControl; /* 70 */ + uint32 DiagReadBack; /* 74 */ + uint32 DiagReadBackHi; /* 78 */ + uint32 DiagMiscControl; /* 7c */ +#define EPHY_SA_RESET_N 0x00000300 +#define EPHY_SA_TESTEN 0x00000500 +#define EPHY_SA_CLOCK_RESET 0x0000d900 +} GpioControl; + +#define GPIO ((volatile GpioControl * const) GPIO_BASE) + +/* Number to mask conversion macro used for GPIODir and GPIOio */ +#define GPIO_NUM_MAX 40 +#define GPIO_NUM_TO_MASK(X) ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) ) + +/* +** Spi Controller +*/ + +typedef struct SpiControl { + uint16 spiMsgCtl; /* (0x0) control byte */ +#define FULL_DUPLEX_RW 0 +#define HALF_DUPLEX_W 1 +#define HALF_DUPLEX_R 2 +#define SPI_MSG_TYPE_SHIFT 14 +#define SPI_BYTE_CNT_SHIFT 0 + byte spiMsgData[0x21e]; /* (0x02 - 0x21f) msg data */ + byte unused0[0x1e0]; + byte spiRxDataFifo[0x220]; /* (0x400 - 0x61f) rx data */ + byte unused1[0xe0]; + + uint16 spiCmd; /* (0x700): SPI command */ +#define SPI_CMD_NOOP 0 +#define SPI_CMD_SOFT_RESET 1 +#define SPI_CMD_HARD_RESET 2 +#define SPI_CMD_START_IMMEDIATE 3 + +#define SPI_CMD_COMMAND_SHIFT 0 +#define SPI_CMD_COMMAND_MASK 0x000f + +#define SPI_CMD_DEVICE_ID_SHIFT 4 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 +#define SPI_CMD_ONE_BYTE_SHIFT 11 +#define SPI_CMD_ONE_WIRE_SHIFT 12 +#define SPI_DEV_ID_0 0 +#define SPI_DEV_ID_1 1 +#define SPI_DEV_ID_2 2 +#define SPI_DEV_ID_3 3 + + byte spiIntStatus; /* (0x702): SPI interrupt status */ + byte spiMaskIntStatus; /* (0x703): SPI masked interrupt status */ + + byte spiIntMask; /* (0x704): SPI interrupt mask */ +#define SPI_INTR_CMD_DONE 0x01 +#define SPI_INTR_RX_OVERFLOW 0x02 +#define SPI_INTR_INTR_TX_UNDERFLOW 0x04 +#define SPI_INTR_TX_OVERFLOW 0x08 +#define SPI_INTR_RX_UNDERFLOW 0x10 +#define SPI_INTR_CLEAR_ALL 0x1f + + byte spiStatus; /* (0x705): SPI status */ +#define SPI_RX_EMPTY 0x02 +#define SPI_CMD_BUSY 0x04 +#define SPI_SERIAL_BUSY 0x08 + + byte spiClkCfg; /* (0x706): SPI clock configuration */ +#define SPI_CLK_0_391MHZ 1 +#define SPI_CLK_0_781MHZ 2 /* default */ +#define SPI_CLK_1_563MHZ 3 +#define SPI_CLK_3_125MHZ 4 +#define SPI_CLK_6_250MHZ 5 +#define SPI_CLK_12_50MHZ 6 +#define SPI_CLK_MASK 0x07 +#define SPI_SSOFFTIME_MASK 0x38 +#define SPI_SSOFFTIME_SHIFT 3 +#define SPI_BYTE_SWAP 0x80 + + byte spiFillByte; /* (0x707): SPI fill byte */ + byte unused2; + byte spiMsgTail; /* (0x709): msgtail */ + byte unused3; + byte spiRxTail; /* (0x70B): rxtail */ +} SpiControl; + +#define SPI ((volatile SpiControl * const) SPI_BASE) + + +/* +** Pcm Controller +*/ + +typedef struct PcmControlRegisters +{ + uint32 pcm_ctrl; // 00 offset from PCM_BASE +#define PCM_ENABLE 0x80000000 // PCM block master enable +#define PCM_ENABLE_SHIFT 31 +#define PCM_SLAVE_SEL 0x40000000 // PCM TDM slave mode select (1 - TDM slave, 0 - TDM master) +#define PCM_SLAVE_SEL_SHIFT 30 +#define PCM_CLOCK_INV 0x20000000 // PCM SCLK invert select (1 - invert, 0 - normal) +#define PCM_CLOCK_INV_SHIFT 29 +#define PCM_FS_INVERT 0x10000000 // PCM FS invert select (1 - invert, 0 - normal) +#define PCM_FS_INVERT_SHIFT 28 +#define PCM_FS_FREQ_16_8 0x08000000 // PCM FS 16/8 Khz select (1 - 16Khz, 0 - 8Khz) +#define PCM_FS_FREQ_16_8_SHIFT 27 +#define PCM_FS_LONG 0x04000000 // PCM FS long/short select (1 - long FS, 0 - short FS) +#define PCM_FS_LONG_SHIFT 26 +#define PCM_FS_TRIG 0x02000000 // PCM FS trigger (1 - falling edge, 0 - rising edge trigger) +#define PCM_FS_TRIG_SHIFT 25 +#define PCM_DATA_OFF 0x01000000 // PCM data offset from FS (1 - one clock from FS, 0 - no offset) +#define PCM_DATA_OFF_SHIFT 24 +#define PCM_DATA_16_8 0x00800000 // PCM data word length (1 - 16 bits, 0 - 8 bits) +#define PCM_DATA_16_8_SHIFT 23 +#define PCM_CLOCK_SEL 0x00700000 // PCM SCLK freq select +#define PCM_CLOCK_SEL_SHIFT 20 + // 000 - 8192 Khz + // 001 - 4096 Khz + // 010 - 2048 Khz + // 011 - 1024 Khz + // 100 - 512 Khz + // 101 - 256 Khz + // 110 - 128 Khz + // 111 - reserved +#define PCM_LSB_FIRST 0x00040000 // PCM shift direction (1 - LSBit first, 0 - MSBit first) +#define PCM_LSB_FIRST_SHIFT 18 +#define PCM_LOOPBACK 0x00020000 // PCM diagnostic loobback enable +#define PCM_LOOPBACK_SHIFT 17 +#define PCM_EXTCLK_SEL 0x00010000 // PCM external timing clock select -- Maybe removed in 6368 +#define PCM_EXTCLK_SEL_SHIFT 16 +#define PCM_NTR_ENABLE 0x00008000 // PCM NTR counter enable -- Nayve removed in 6368 +#define PCM_NTR_ENABLE_SHIFT 15 +#define PCM_BITS_PER_FRAME_1024 0x00000400 // 1024 - Max +#define PCM_BITS_PER_FRAME_256 0x00000100 // 256 +#define PCM_BITS_PER_FRAME_8 0x00000008 // 8 - Min + + uint32 pcm_chan_ctrl; // 04 +#define PCM_TX0_EN 0x00000001 // PCM transmit channel 0 enable +#define PCM_TX1_EN 0x00000002 // PCM transmit channel 1 enable +#define PCM_TX2_EN 0x00000004 // PCM transmit channel 2 enable +#define PCM_TX3_EN 0x00000008 // PCM transmit channel 3 enable +#define PCM_TX4_EN 0x00000010 // PCM transmit channel 4 enable +#define PCM_TX5_EN 0x00000020 // PCM transmit channel 5 enable +#define PCM_TX6_EN 0x00000040 // PCM transmit channel 6 enable +#define PCM_TX7_EN 0x00000080 // PCM transmit channel 7 enable +#define PCM_RX0_EN 0x00000100 // PCM receive channel 0 enable +#define PCM_RX1_EN 0x00000200 // PCM receive channel 1 enable +#define PCM_RX2_EN 0x00000400 // PCM receive channel 2 enable +#define PCM_RX3_EN 0x00000800 // PCM receive channel 3 enable +#define PCM_RX4_EN 0x00001000 // PCM receive channel 4 enable +#define PCM_RX5_EN 0x00002000 // PCM receive channel 5 enable +#define PCM_RX6_EN 0x00004000 // PCM receive channel 6 enable +#define PCM_RX7_EN 0x00008000 // PCM receive channel 7 enable +#define PCM_RX_PACKET_SIZE 0x00ff0000 // PCM Rx DMA quasi-packet size +#define PCM_RX_PACKET_SIZE_SHIFT 16 + + uint32 pcm_int_pending; // 08 + uint32 pcm_int_mask; // 0c +#define PCM_TX_UNDERFLOW 0x00000001 // PCM DMA receive overflow +#define PCM_RX_OVERFLOW 0x00000002 // PCM DMA transmit underflow +#define PCM_TDM_FRAME 0x00000004 // PCM frame boundary +#define PCM_RX_IRQ 0x00000008 // IUDMA interrupts +#define PCM_TX_IRQ 0x00000010 + + uint32 pcm_pll_ctrl1; // 10 +#define PCM_PLL_PWRDN 0x80000000 // PLL PWRDN +#define PCM_PLL_PWRDN_CH1 0x40000000 // PLL CH PWRDN +#define PCM_PLL_REFCMP_PWRDN 0x20000000 // PLL REFCMP PWRDN +#define PCM_CLK16_RESET 0x10000000 // 16.382 MHz PCM interface circuitry reset. +#define PCM_PLL_ARESET 0x08000000 // PLL Analog Reset +#define PCM_PLL_DRESET 0x04000000 // PLL Digital Reset + + uint32 pcm_pll_ctrl2; // 14 + uint32 pcm_pll_ctrl3; // 18 + uint32 pcm_pll_ctrl4; // 1c + + uint32 pcm_pll_stat; // 20 +#define PCM_PLL_LOCK 0x00000001 // Asserted when PLL is locked to programmed frequency + + uint32 pcm_ntr_counter; // 24 + + uint32 unused[6]; + +#define PCM_MAX_TIMESLOT_REGS 16 // Number of PCM time slot registers in the table. + // Each register provides the settings for 8 timeslots (4 bits per timeslot) + uint32 pcm_slot_alloc_tbl[PCM_MAX_TIMESLOT_REGS]; +#define PCM_TS_VALID 0x8 // valid marker for TS alloc ram entry +} PcmControlRegisters; + +#define PCM ((volatile PcmControlRegisters * const) PCM_BASE) + +typedef struct PcmIudmaRegisters +{ + uint16 reserved0; + uint16 ctrlConfig; +#define BCM6368_IUDMA_REGS_CTRLCONFIG_MASTER_EN 0x0001 +#define BCM6368_IUDMA_REGS_CTRLCONFIG_FLOWC_CH1_EN 0x0002 +#define BCM6368_IUDMA_REGS_CTRLCONFIG_FLOWC_CH3_EN 0x0004 +#define BCM6368_IUDMA_REGS_CTRLCONFIG_FLOWC_CH5_EN 0x0008 +#define BCM6368_IUDMA_REGS_CTRLCONFIG_FLOWC_CH7_EN 0x0010 + + // Flow control Ch1 + uint16 reserved1; + uint16 ch1_FC_Low_Thr; + + uint16 reserved2; + uint16 ch1_FC_High_Thr; + + uint16 reserved3; + uint16 ch1_Buff_Alloc; + + // Flow control Ch3 + uint16 reserved4; + uint16 ch3_FC_Low_Thr; + + uint16 reserved5; + uint16 ch3_FC_High_Thr; + + uint16 reserved6; + uint16 ch3_Buff_Alloc; + + // Flow control Ch5 + uint16 reserved7; + uint16 ch5_FC_Low_Thr; + + uint16 reserved8; + uint16 ch5_FC_High_Thr; + + uint16 reserved9; + uint16 ch5_Buff_Alloc; + + // Flow control Ch7 + uint16 reserved10; + uint16 ch7_FC_Low_Thr; + + uint16 reserved11; + uint16 ch7_FC_High_Thr; + + uint16 reserved12; + uint16 ch7_Buff_Alloc; + + // Channel resets + uint16 reserved13; + uint16 channel_reset; + + uint16 reserved14; + uint16 channel_debug; + + // Spare register + uint32 dummy1; + + // Interrupt status registers + uint16 reserved15; + uint16 gbl_int_stat; + + // Interrupt mask registers + uint16 reserved16; + uint16 gbl_int_mask; +} PcmIudmaRegisters; + +typedef struct PcmIudmaChannelCtrl +{ + uint16 reserved1; + uint16 config; +#define BCM6368_IUDMA_CONFIG_ENDMA 0x0001 +#define BCM6368_IUDMA_CONFIG_PKTHALT 0x0002 +#define BCM6368_IUDMA_CONFIG_BURSTHALT 0x0004 + + uint16 reserved2; + uint16 intStat; +#define BCM6368_IUDMA_INTSTAT_BDONE 0x0001 +#define BCM6368_IUDMA_INTSTAT_PDONE 0x0002 +#define BCM6368_IUDMA_INTSTAT_NOTVLD 0x0004 +#define BCM6368_IUDMA_INTSTAT_MASK 0x0007 +#define BCM6368_IUDMA_INTSTAT_ALL BCM6368_IUDMA_INTSTAT_MASK + + uint16 reserved3; + uint16 intMask; +#define BCM6368_IUDMA_INTMASK_BDONE 0x0001 +#define BCM6368_IUDMA_INTMASK_PDONE 0x0002 +#define BCM6368_IUDMA_INTMASK_NOTVLD 0x0004 + + uint32 maxBurst; +#define BCM6368_IUDMA_MAXBURST_SIZE 16 /* 32-bit words */ + +} PcmIudmaChannelCtrl; + + +typedef struct PcmIudmaStateRam +{ + uint32 baseDescPointer; /* pointer to first buffer descriptor */ + + uint32 stateBytesDoneRingOffset; /* state info: how manu bytes done and the offset of the + current descritor in process */ +#define BCM6368_IUDMA_STRAM_DESC_RING_OFFSET 0x3fff + + + uint32 flagsLengthStatus; /* Length and status field of the current descriptor */ + + uint32 currentBufferPointer; /* pointer to the current descriptor */ + +} PcmIudmaStateRam; + +#define BCM6368_MAX_PCM_DMA_CHANNELS 2 + +typedef struct PcmIudma +{ + PcmIudmaRegisters regs; // + uint32 reserved1[110]; // + PcmIudmaChannelCtrl ctrl[BCM6368_MAX_PCM_DMA_CHANNELS]; // + uint32 reserved2[120]; // + PcmIudmaStateRam stram[BCM6368_MAX_PCM_DMA_CHANNELS]; // + +} PcmIudma; + +#define PCM_IUDMA ((volatile PcmIudma * const) PCM_DMA_BASE) + + +#define IUDMA_MAX_CHANNELS 32 + +/* +** DMA Channel Configuration (1 .. 32) +*/ +typedef struct DmaChannelCfg { + uint32 cfg; /* (00) assorted configuration */ +#define DMA_ENABLE 0x00000001 /* set to enable channel */ +#define DMA_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ +#define DMA_BURST_HALT 0x00000004 /* idle after finish current memory burst */ + uint32 intStat; /* (04) interrupts control and status */ + uint32 intMask; /* (08) interrupts mask */ +#define DMA_BUFF_DONE 0x00000001 /* buffer done */ +#define DMA_DONE 0x00000002 /* packet xfer complete */ +#define DMA_NO_DESC 0x00000004 /* no valid descriptors */ + uint32 maxBurst; /* (0C) max burst length permitted */ +} DmaChannelCfg; + +/* +** DMA State RAM (1 .. 16) +*/ +typedef struct DmaStateRam { + uint32 baseDescPtr; /* (00) descriptor ring start address */ + uint32 state_data; /* (04) state/bytes done/ring offset */ + uint32 desc_len_status; /* (08) buffer descriptor status and len */ + uint32 desc_base_bufptr; /* (0C) buffer descrpitor current processing */ +} DmaStateRam; + + +/* +** DMA Registers +*/ +typedef struct DmaRegs { + uint32 controller_cfg; /* (00) controller configuration */ +#define DMA_MASTER_EN 0x00000001 +#define DMA_FLOWC_CH1_EN 0x00000002 +#define DMA_FLOWC_CH3_EN 0x00000004 + + // Flow control Ch1 + uint32 flowctl_ch1_thresh_lo; /* 004 */ + uint32 flowctl_ch1_thresh_hi; /* 008 */ + uint32 flowctl_ch1_alloc; /* 00c */ +#define DMA_BUF_ALLOC_FORCE 0x80000000 + + // Flow control Ch3 + uint32 flowctl_ch3_thresh_lo; /* 010 */ + uint32 flowctl_ch3_thresh_hi; /* 014 */ + uint32 flowctl_ch3_alloc; /* 018 */ + + // Flow control Ch5 + uint32 flowctl_ch5_thresh_lo; /* 01C */ + uint32 flowctl_ch5_thresh_hi; /* 020 */ + uint32 flowctl_ch5_alloc; /* 024 */ + + // Flow control Ch7 + uint32 flowctl_ch7_thresh_lo; /* 028 */ + uint32 flowctl_ch7_thresh_hi; /* 02C */ + uint32 flowctl_ch7_alloc; /* 030 */ + + uint32 ctrl_channel_reset; /* 034 */ + uint32 ctrl_channel_debug; /* 038 */ + uint32 reserved1; /* 03C */ + uint32 ctrl_global_interrupt_status; /* 040 */ + uint32 ctrl_global_interrupt_mask; /* 044 */ + + // Unused words + uint8 reserved2[0x200-0x48]; + + // Per channel registers/state ram + DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */ + union { + DmaStateRam s[IUDMA_MAX_CHANNELS]; + uint32 u32[4 * IUDMA_MAX_CHANNELS]; + } stram; /* (400-5FF) state ram */ +} DmaRegs; + +/* +** DMA Buffer +*/ +typedef struct DmaDesc { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ +} DmaDesc; + +/* +** External Bus Interface +*/ +typedef struct EbiChipSelect { + uint32 base; /* base address in upper 24 bits */ +#define EBI_SIZE_8K 0 +#define EBI_SIZE_16K 1 +#define EBI_SIZE_32K 2 +#define EBI_SIZE_64K 3 +#define EBI_SIZE_128K 4 +#define EBI_SIZE_256K 5 +#define EBI_SIZE_512K 6 +#define EBI_SIZE_1M 7 +#define EBI_SIZE_2M 8 +#define EBI_SIZE_4M 9 +#define EBI_SIZE_8M 10 +#define EBI_SIZE_16M 11 +#define EBI_SIZE_32M 12 +#define EBI_SIZE_64M 13 +#define EBI_SIZE_128M 14 +#define EBI_SIZE_256M 15 + uint32 config; +#define EBI_ENABLE 0x00000001 /* .. enable this range */ +#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */ +#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */ +#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */ +#define EBI_WREN 0x00000020 /* enable posted writes */ +#define EBI_POLARITY 0x00000040 /* .. set to invert something, + ** don't know what yet */ +#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */ +#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */ +#define EBI_FIFO 0x00000200 /* .. use fifo */ +#define EBI_RE 0x00000400 /* .. Reverse Endian */ +#define EBI_SETUP_SHIFT 16 +#define EBI_HOLD_SHIFT 20 +#define EBI_SETUP_STATES 0x0f0000 +#define EBI_HOLD_STATES 0xf00000 +} EbiChipSelect; + +typedef struct MpiRegisters { + EbiChipSelect cs[7]; /* size chip select configuration */ +#define EBI_CS0_BASE 0 +#define EBI_CS1_BASE 1 +#define EBI_CS2_BASE 2 +#define EBI_CS3_BASE 3 +#define PCMCIA_COMMON_BASE 4 +#define PCMCIA_ATTRIBUTE_BASE 5 +#define PCMCIA_IO_BASE 6 + uint32 unused0[2]; /* reserved */ + uint32 ebi_control; /* ebi control */ + uint32 unused1[4]; /* reserved */ +#define EBI_ACCESS_TIMEOUT 0x000007FF + uint32 pcmcia_cntl1; /* pcmcia control 1 */ +#define PCCARD_CARD_RESET 0x00040000 +#define CARDBUS_ENABLE 0x00008000 +#define PCMCIA_ENABLE 0x00004000 +#define PCMCIA_GPIO_ENABLE 0x00002000 +#define CARDBUS_IDSEL 0x00001F00 +#define VS2_OEN 0x00000080 +#define VS1_OEN 0x00000040 +#define VS2_OUT 0x00000020 +#define VS1_OUT 0x00000010 +#define VS2_IN 0x00000008 +#define VS1_IN 0x00000004 +#define CD2_IN 0x00000002 +#define CD1_IN 0x00000001 +#define VS_MASK 0x0000000C +#define CD_MASK 0x00000003 + uint32 unused2; /* reserved */ + uint32 pcmcia_cntl2; /* pcmcia control 2 */ +#define PCMCIA_BYTESWAP_DIS 0x00000002 +#define PCMCIA_HALFWORD_EN 0x00000001 +#define RW_ACTIVE_CNT_BIT 2 +#define INACTIVE_CNT_BIT 8 +#define CE_SETUP_CNT_BIT 16 +#define CE_HOLD_CNT_BIT 24 + uint32 unused3[40]; /* reserved */ + + uint32 sp0range; /* PCI to internal system bus address space */ +#define ADDR_SPACE_MASK 0xFFFF0000 + uint32 sp0remap; + uint32 sp0cfg; + uint32 sp1range; + uint32 sp1remap; + uint32 sp1cfg; + + uint32 EndianCfg; + + uint32 l2pcfgctl; /* internal system bus to PCI IO/Cfg control */ +#define DIR_CFG_SEL 0x80000000 /* change from PCI I/O access to PCI config access */ +#define DIR_CFG_USEREG 0x40000000 /* use this register info for PCI configuration access */ +#define DEVICE_NUMBER 0x00007C00 /* device number for the PCI configuration access */ +#define FUNC_NUMBER 0x00000300 /* function number for the PCI configuration access */ +#define REG_NUMBER 0x000000FC /* register number for the PCI configuration access */ +#define CONFIG_TYPE 0x00000003 /* configuration type for the PCI configuration access */ + + uint32 l2pmrange1; /* internal system bus to PCI memory space */ +#define PCI_SIZE_64K 0xFFFF0000 +#define PCI_SIZE_128K 0xFFFE0000 +#define PCI_SIZE_256K 0xFFFC0000 +#define PCI_SIZE_512K 0xFFF80000 +#define PCI_SIZE_1M 0xFFF00000 +#define PCI_SIZE_2M 0xFFE00000 +#define PCI_SIZE_4M 0xFFC00000 +#define PCI_SIZE_8M 0xFF800000 +#define PCI_SIZE_16M 0xFF000000 +#define PCI_SIZE_32M 0xFE000000 + uint32 l2pmbase1; /* kseg0 or kseg1 address & 0x1FFFFFFF */ + uint32 l2pmremap1; +#define CARDBUS_MEM 0x00000004 +#define MEM_WINDOW_EN 0x00000001 + uint32 l2pmrange2; + uint32 l2pmbase2; + uint32 l2pmremap2; + uint32 l2piorange; /* internal system bus to PCI I/O space */ + uint32 l2piobase; + uint32 l2pioremap; + + uint32 pcimodesel; +#define PCI_INT_BUS_RD_PREFETCH 0x000001F0 +#define PCI_BAR2_NOSWAP 0x00000002 /* BAR at offset 0x20 */ +#define PCI_BAR1_NOSWAP 0x00000001 /* BAR at affset 0x1c */ + + uint32 pciintstat; /* PCI interrupt mask/status */ +#define MAILBOX1_SENT 0x08 +#define MAILBOX0_SENT 0x04 +#define MAILBOX1_MSG_RCV 0x02 +#define MAILBOX0_MSG_RCV 0x01 + uint32 locbuscntrl; /* internal system bus control */ +#define DIR_U2P_NOSWAP 0x00000002 +#define EN_PCI_GPIO 0x00000001 + uint32 locintstat; /* internal system bus interrupt mask/status */ +#define CSERR 0x0200 +#define SERR 0x0100 +#define EXT_PCI_INT 0x0080 +#define DIR_FAILED 0x0040 +#define DIR_COMPLETE 0x0020 +#define PCI_CFG 0x0010 + uint32 unused4[7]; + + uint32 mailbox0; + uint32 mailbox1; + + uint32 pcicfgcntrl; /* internal system bus PCI configuration control */ +#define PCI_CFG_REG_WRITE_EN 0x00000080 +#define PCI_CFG_ADDR 0x0000003C + uint32 pcicfgdata; /* internal system bus PCI configuration data */ + + uint32 locch2ctl; /* PCI to interrnal system bus DMA (downstream) local control */ +#define MPI_DMA_HALT 0x00000008 /* idle after finish current memory burst */ +#define MPI_DMA_PKT_HALT 0x00000004 /* idle after an EOP flag is detected */ +#define MPI_DMA_STALL 0x00000002 /* idle after an EOP flag is detected */ +#define MPI_DMA_ENABLE 0x00000001 /* set to enable channel */ + uint32 locch2intStat; +#define MPI_DMA_NO_DESC 0x00000004 /* no valid descriptors */ +#define MPI_DMA_DONE 0x00000002 /* packet xfer complete */ +#define MPI_DMA_BUFF_DONE 0x00000001 /* buffer done */ + uint32 locch2intMask; + uint32 unused5; + uint32 locch2descaddr; + uint32 locch2status1; +#define LOCAL_DESC_STATE 0xE0000000 +#define PCI_DESC_STATE 0x1C000000 +#define BYTE_DONE 0x03FFC000 +#define RING_ADDR 0x00003FFF + uint32 locch2status2; +#define BUFPTR_OFFSET 0x1FFF0000 +#define PCI_MASTER_STATE 0x000000C0 +#define LOC_MASTER_STATE 0x00000038 +#define CONTROL_STATE 0x00000007 + uint32 unused6; + + uint32 locch1Ctl; /*internal system bus to PCI DMA (upstream) local control */ +#define DMA_U2P_LE 0x00000200 /* local bus is little endian */ +#define DMA_U2P_NOSWAP 0x00000100 /* lccal bus is little endian but no data swapped */ + uint32 locch1intstat; + uint32 locch1intmask; + uint32 unused7; + uint32 locch1descaddr; + uint32 locch1status1; + uint32 locch1status2; + uint32 unused8; + + uint32 pcich1ctl; /* internal system bus to PCI DMA PCI control */ + uint32 pcich1intstat; + uint32 pcich1intmask; + uint32 pcich1descaddr; + uint32 pcich1status1; + uint32 pcich1status2; + + uint32 pcich2Ctl; /* PCI to internal system bus DMA PCI control */ + uint32 pcich2intstat; + uint32 pcich2intmask; + uint32 pcich2descaddr; + uint32 pcich2status1; + uint32 pcich2status2; + + uint32 perm_id; /* permanent device and vendor id */ + uint32 perm_rev; /* permanent revision id */ +} MpiRegisters; + +#define MPI ((volatile MpiRegisters * const) MPI_BASE) + +/* PCI configuration address space start offset 0x40 */ +#define BRCM_PCI_CONFIG_TIMER 0x40 +#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK 0x0000FF00 +#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK 0x000000FF +/* +** USB 2.0 Device Registers +*/ +typedef struct UsbRegisters { +#define USBD_CONTROL_APP_DONECSR 0x0001 +#define USBD_CONTROL_APP_RESUME 0x0002 +#define USBD_CONTROL_APP_RXFIFIO_INIT 0x0040 +#define USBD_CONTROL_APP_TXFIFIO_INIT 0x0080 +#define USBD_CONTROL_APP_FIFO_SEL_SHIFT 0x8 +#define USBD_CONTROL_APP_FIFO_INIT_SEL(x) (((x)&0x0f)<<USBD_CONTROL_APP_FIFO_SEL_SHIFT) +#define USBD_CONTROL_APP_AUTO_CSRS 0x2000 +#define USBD_CONTROL_APP_AUTO_INS_ZERO_LEN_PKT 0x4000 +#define EN_TXZLENINS (1<<14) +#define EN_RXZSCFG (1<<12) +#define APPSETUPERRLOCK (1<<5) + uint32 usbd_control ; +#define USBD_STRAPS_APP_SELF_PWR 0x0400 +#define USBD_STRAPS_APP_DEV_DISCON 0x0200 +#define USBD_STRAPS_APP_CSRPRG_SUP 0x0100 +#define USBD_STRAPS_APP_RAM_IF 0x0080 +#define USBD_STRAPS_APP_DEV_RMTWKUP 0x0040 +#define USBD_STRAPS_APP_PHYIF_8BIT 0x0004 +#define USBD_STRAPS_FULL_SPEED 0x0003 +#define USBD_STRAPS_LOW_SPEED 0x0002 +#define USBD_STRAPS_HIGH_SPEED 0x0000 +#define APPUTMIDIR(x) ((x&1)<<3) +#define UNIDIR 0 + uint32 usbd_straps; +#define USB_ENDPOINT_0 0x01 + uint32 usbd_stall; +#define USBD_ENUM_SPEED_SHIFT 12 +#define USBD_ENUM_SPEED 0x3000 +#define UDC20_ALTINTF(x) ((x>>8)&0xf) +#define UDC20_INTF(x) ((x>>4)&0xf) +#define UDC20_CFG(x) ((x>>0)&0xf) + uint32 usbd_status; +#define USBD_LINK (0x1<<10) +#define USBD_SET_CSRS 0x40 +#define USBD_SUSPEND 0x20 +#define USBD_EARLY_SUSPEND 0x10 +#define USBD_SOF 0x08 +#define USBD_ENUMON 0x04 +#define USBD_SETUP 0x02 +#define USBD_USBRESET 0x01 + uint32 usbd_events; + uint32 usbd_events_irq; +#define UPPER(x) (16+x) +#define ENABLE(x) (1<<x) +#define SWP_TXBSY (15) +#define SWP_RXBSY (14) +#define SETUP_ERR (13) +#define APPUDCSTALLCHG (12) +#define BUS_ERR (11) +#define USB_LINK (10) +#define HST_SETCFG (9) +#define HST_SETINTF (8) +#define ERRATIC_ERR (7) +#define SET_CSRS (6) +#define SUSPEND (5) +#define ERLY_SUSPEND (4) +#define SOF (3) +#define ENUM_ON (2) +#define SETUP (1) +#define USB_RESET (0) +#define RISING(x) (0x0<<2*x) +#define FALLING(x) (0x1<<2*x) +#define USBD_IRQCFG_ENUM_ON_FALLING_EDGE 0x00000010 + uint32 usbd_irqcfg_hi ; + uint32 usbd_irqcfg_lo ; +#define USBD_USB_RESET_IRQ 0x00000001 +#define USBD_USB_SETUP_IRQ 0x00000002 // non-standard setup cmd rcvd +#define USBD_USB_ENUM_ON_IRQ 0x00000004 +#define USBD_USB_SOF_IRQ 0x00000008 +#define USBD_USB_EARLY_SUSPEND_IRQ 0x00000010 +#define USBD_USB_SUSPEND_IRQ 0x00000020 // non-standard setup cmd rcvd +#define USBD_USB_SET_CSRS_IRQ 0x00000040 +#define USBD_USB_ERRATIC_ERR_IRQ 0x00000080 +#define USBD_USB_SETCFG_IRQ 0x00000200 +#define USBD_USB_LINK_IRQ 0x00000400 + uint32 usbd_events_irq_mask; + uint32 usbd_swcfg; + uint32 usbd_swtxctl; + uint32 usbd_swrxctl; + uint32 usbd_txfifo_rwptr; + uint32 usbd_rxfifo_rwptr; + uint32 usbd_txfifo_st_rwptr; + uint32 usbd_rxfifo_st_rwptr; + uint32 usbd_txfifo_config ; + uint32 usbd_rxfifo_config ; + uint32 usbd_txfifo_epsize ; + uint32 usbd_rxfifo_epsize ; +#define USBD_EPNUM_CTRL 0x0 +#define USBD_EPNUM_ISO 0x1 +#define USBD_EPNUM_BULK 0x2 +#define USBD_EPNUM_IRQ 0x3 +#define USBD_EPNUM_EPTYPE(x) (((x)&0x3)<<8) +#define USBD_EPNUM_EPDMACHMAP(x) (((x)&0xf)<<0) + uint32 usbd_epnum_typemap ; + uint32 usbd_reserved [0xB] ; + uint32 usbd_csr_setupaddr ; +#define USBD_EPNUM_MASK 0xf +#define USBD_EPNUM(x) ((x&USBD_EPNUM_MASK)<<0) +#define USBD_EPDIR_IN (1<<4) +#define USBD_EPDIR_OUT (0<<4) +#define USBD_EPTYP_CTRL (USBD_EPNUM_CTRL<<5) +#define USBD_EPTYP_ISO (USBD_EPNUM_ISO<<5) +#define USBD_EPTYP_BULK (USBD_EPNUM_BULK<<5) +#define USBD_EPTYP_IRQ (USBD_EPNUM_IRQ<<5) +#define USBD_EPCFG_MASK 0xf +#define USBD_EPCFG(x) ((x&USBD_EPCFG_MASK)<<7) +#define USBD_EPINTF_MASK 0xf +#define USBD_EPINTF(x) ((x&USBD_EPINTF_MASK)<<11) +#define USBD_EPAINTF_MASK 0xf +#define USBD_EPAINTF(x) ((x&USBD_EPAINTF_MASK)<<15) +#define USBD_EPMAXPKT_MSK 0x7ff +#define USBD_EPMAXPKT(x) ((x&USBD_EPMAXPKT_MSK)<<19) +#define USBD_EPISOPID_MASK 0x3 +#define USBD_EPISOPID(x) ((x&USBD_ISOPID_MASK)<<30) + uint32 usbd_csr_ep [5] ; +} UsbRegisters; + +#define USB ((volatile UsbRegisters * const) USB_CTL_BASE) + +typedef struct USBControl { + uint32 BrtControl1; + uint32 BrtControl2; + uint32 BrtStatus1; + uint32 BrtStatus2; + uint32 UTMIControl1; + uint32 TestPortControl; + uint32 PllControl1; + uint32 SwapControl; +#define USB_DEVICE_SEL (1<<6) +#define EHCI_LOGICAL_ADDRESS_EN (1<<5) +#define EHCI_ENDIAN_SWAP (1<<4) +#define EHCI_DATA_SWAP (1<<3) +#define OHCI_LOGICAL_ADDRESS_EN (1<<2) +#define OHCI_ENDIAN_SWAP (1<<1) +#define OHCI_DATA_SWAP (1<<0) + uint32 unused1; + uint32 FrameAdjustValue; + uint32 Setup; +#define USBH_IOC (1<<4) + uint32 MDIO; + uint32 MDIO32; + uint32 USBSimControl; +} USBControl; + +#define USBH ((volatile USBControl * const) USBH_CFG_BASE) + +typedef struct EthSwRegs{ + byte port_traffic_ctrl[9]; /* 0x00 - 0x08 */ + byte reserved1[2]; /* 0x09 - 0x0a */ + byte switch_mode; /* 0x0b */ + unsigned short pause_quanta; /*0x0c */ + byte imp_port_state; /*0x0e */ + byte led_refresh; /* 0x0f */ + unsigned short led_function[2]; /* 0x10 */ + unsigned short led_function_map; /* 0x14 */ + unsigned short led_enable_map; /* 0x16 */ + unsigned short led_mode_map0; /* 0x18 */ + unsigned short led_function_map1; /* 0x1a */ + byte reserved2[5]; /* 0x1b - 0x20 */ + byte port_forward_ctrl; /* 0x21 */ + byte reserved3[2]; /* 0x22 - 0x23 */ + unsigned short protected_port_selection; /* 0x24 */ + unsigned short wan_port_select; /* 0x26 */ + unsigned int pause_capability; /* 0x28 */ + byte reserved4[3]; /* 0x2c - 0x2e */ + byte reserved_multicast_control; /* 0x2f */ + byte reserved5; /* 0x30 */ + byte txq_flush_mode_control; /* 0x31 */ + unsigned short ulf_forward_map; /* 0x32 */ + unsigned short mlf_forward_map; /* 0x34 */ + unsigned short mlf_impc_forward_map; /* 0x36 */ + unsigned short pause_pass_through_for_rx; /* 0x38 */ + unsigned short pause_pass_through_for_tx; /* 0x3a */ + unsigned short disable_learning; /* 0x3c */ + byte reserved6[26]; /* 0x3e - 0x57 */ + byte port_state_override[8]; /* 0x58 - 0x5f */ + byte reserved7[4]; /* 0x60 - 0x63 */ + byte imp_rgmii_ctrl_p4; /* 0x64 */ + byte imp_rgmii_ctrl_p5; /* 0x65 */ + byte reserved8[6]; /* 0x66 - 0x6b */ + byte rgmii_timing_delay_p4; /* 0x6c */ + byte gmii_timing_delay_p5; /* 0x6d */ + byte reserved9[11]; /* 0x6e - 0x78 */ + byte software_reset; /* 0x79 */ + byte reserved13[6]; /* 0x7a - 0x7f */ + byte pause_frame_detection; /* 0x80 */ + byte reserved10[7]; /* 0x81 - 0x87 */ + byte fast_aging_ctrl; /* 0x88 */ + byte fast_aging_port; /* 0x89 */ + byte fast_aging_vid; /* 0x8a */ + byte reserved11[21]; /* 0x8b - 0x9f */ + unsigned int swpkt_ctrl_sar; /*0xa0 */ + unsigned int swpkt_ctrl_usb; /*0xa4 */ + unsigned int iudma_ctrl; /*0xa8 */ + unsigned int rxfilt_ctrl; /*0xac */ + unsigned int mdio_ctrl; /*0xb0 */ + unsigned int mdio_data; /*0xb4 */ + byte reserved12[42]; /* 0xb6 - 0xdf */ + unsigned int sw_mem_test; /*0xe0 */ +} EthSwRegs; + +#define ETHSWREG ((volatile EthSwRegs * const) SWITCH_BASE) + +typedef struct EthSwMIBRegs { + unsigned int TxOctetsLo; + unsigned int TxOctetsHi; + unsigned int TxDropPkts; + unsigned int TxQoSPkts; + unsigned int TxBroadcastPkts; + unsigned int TxMulticastPkts; + unsigned int TxUnicastPkts; + unsigned int TxCol; + unsigned int TxSingleCol; + unsigned int TxMultipleCol; + unsigned int TxDeferredTx; + unsigned int TxLateCol; + unsigned int TxExcessiveCol; + unsigned int TxFrameInDisc; + unsigned int TxPausePkts; + unsigned int TxQoSOctetsLo; + unsigned int TxQoSOctetsHi; + unsigned int RxOctetsLo; + unsigned int RxOctetsHi; + unsigned int RxUndersizePkts; + unsigned int RxPausePkts; + unsigned int Pkts64Octets; + unsigned int Pkts65to127Octets; + unsigned int Pkts128to255Octets; + unsigned int Pkts256to511Octets; + unsigned int Pkts512to1023Octets; + unsigned int Pkts1024to1522Octets; + unsigned int RxOversizePkts; + unsigned int RxJabbers; + unsigned int RxAlignErrs; + unsigned int RxFCSErrs; + unsigned int RxGoodOctetsLo; + unsigned int RxGoodOctetsHi; + unsigned int RxDropPkts; + unsigned int RxUnicastPkts; + unsigned int RxMulticastPkts; + unsigned int RxBroadcastPkts; + unsigned int RxSAChanges; + unsigned int RxFragments; + unsigned int RxExcessSizeDisc; + unsigned int RxSymbolError; + unsigned int RxQoSPkts; + unsigned int RxQoSOctetsLo; + unsigned int RxQoSOctetsHi; + unsigned int Pkts1523to2047; + unsigned int Pkts2048to4095; + unsigned int Pkts4096to8191; + unsigned int Pkts8192to9728; +} EthSwMIBRegs; + +#define ETHSWMIBREG ((volatile EthSwMIBRegs * const) (SWITCH_BASE + 0x2000)) + +/* +** NAND Interrupt Controller Registers +*/ +typedef struct NandIntrCtrlRegs { + uint32 NandInterrupt; +#define NINT_ENABLE_MASK 0xffff0000 +#define NINT_STS_MASK 0x00000fff +#define NINT_ECC_ERROR_CORR 0x00000080 +#define NINT_ECC_ERROR_UNC 0x00000040 +#define NINT_DEV_RBPIN 0x00000020 +#define NINT_CTRL_READY 0x00000010 +#define NINT_PAGE_PGM 0x00000008 +#define NINT_COPY_BACK 0x00000004 +#define NINT_BLOCK_ERASE 0x00000002 +#define NINT_NP_READ 0x00000001 + + uint32 NandBaseAddr0; /* Default address when booting from NAND flash */ + uint32 reserved; + uint32 NandBaseAddr1; /* Secondary base address for NAND flash */ +} NandIntrCtrlRegs; + +#define NAND_INTR ((volatile NandIntrCtrlRegs * const) NAND_INTR_BASE) + +/* +** NAND Controller Registers +*/ +typedef struct NandCtrlRegs { + uint32 NandRevision; /* NAND Revision */ + uint32 NandCmdStart; /* Nand Flash Command Start */ +#define NCMD_MASK 0x0f000000 +#define NCMD_BLK_LOCK_STS 0x0d000000 +#define NCMD_BLK_UNLOCK 0x0c000000 +#define NCMD_BLK_LOCK_DOWN 0x0b000000 +#define NCMD_BLK_LOCK 0x0a000000 +#define NCMD_FLASH_RESET 0x09000000 +#define NCMD_BLOCK_ERASE 0x08000000 +#define NCMD_DEV_ID_READ 0x07000000 +#define NCMD_COPY_BACK 0x06000000 +#define NCMD_PROGRAM_SPARE 0x05000000 +#define NCMD_PROGRAM_PAGE 0x04000000 +#define NCMD_STS_READ 0x03000000 +#define NCMD_SPARE_READ 0x02000000 +#define NCMD_PAGE_READ 0x01000000 + + uint32 NandCmdExtAddr; /* Nand Flash Command Extended Address */ + uint32 NandCmdAddr; /* Nand Flash Command Address */ + uint32 NandCmdEndAddr; /* Nand Flash Command End Address */ + uint32 NandNandBootConfig; /* Nand Flash Boot Config */ +#define NBC_CS_LOCK 0x80000000 +#define NBC_AUTO_DEV_ID_CFG 0x40000000 +#define NBC_WR_PROT_BLK0 0x10000000 + + uint32 NandCsNandXor; /* Nand Flash EBI CS Address XOR with */ + /* 1FC0 Control */ + uint32 NandReserved; + uint32 NandSpareAreaReadOfs0; /* Nand Flash Spare Area Read Bytes 0-3 */ + uint32 NandSpareAreaReadOfs4; /* Nand Flash Spare Area Read Bytes 4-7 */ + uint32 NandSpareAreaReadOfs8; /* Nand Flash Spare Area Read Bytes 8-11 */ + uint32 NandSpareAreaReadOfsC; /* Nand Flash Spare Area Read Bytes 12-15*/ + uint32 NandSpareAreaWriteOfs0; /* Nand Flash Spare Area Write Bytes 0-3 */ + uint32 NandSpareAreaWriteOfs4; /* Nand Flash Spare Area Write Bytes 4-7 */ + uint32 NandSpareAreaWriteOfs8; /* Nand Flash Spare Area Write Bytes 8-11*/ + uint32 NandSpareAreaWriteOfsC; /* Nand Flash Spare Area Write Bytes12-15*/ + uint32 NandAccControl; /* Nand Flash Access Control */ + uint32 NandConfig; /* Nand Flash Config */ +#define NC_CONFIG_LOCK 0x80000000 +#define NC_PG_SIZE_MASK 0x40000000 +#define NC_PG_SIZE_2K 0x40000000 +#define NC_PG_SIZE_512B 0x00000000 +#define NC_BLK_SIZE_MASK 0x30000000 +#define NC_BLK_SIZE_512K 0x30000000 +#define NC_BLK_SIZE_128K 0x10000000 +#define NC_BLK_SIZE_16K 0x00000000 +#define NC_BLK_SIZE_8K 0x20000000 +#define NC_DEV_SIZE_MASK 0x0f000000 +#define NC_DEV_SIZE_SHIFT 24 +#define NC_DEV_WIDTH_MASK 0x00800000 +#define NC_DEV_WIDTH_16 0x00800000 +#define NC_DEV_WIDTH_8 0x00000000 +#define NC_FUL_ADDR_MASK 0x00070000 +#define NC_FUL_ADDR_SHIFT 16 +#define NC_BLK_ADDR_MASK 0x00000700 +#define NC_BLK_ADDR_SHIFT 8 + + uint32 NandTiming1; /* Nand Flash Timing Parameters 1 */ + uint32 NandTiming2; /* Nand Flash Timing Parameters 2 */ + uint32 NandSemaphore; /* Semaphore */ + uint32 NandFlashDeviceId; /* Nand Flash Device ID */ + uint32 NandBlockLockStatus; /* Nand Flash Block Lock Status */ + uint32 NandIntfcStatus; /* Nand Flash Interface Status */ +#define NIS_CTLR_READY 0x80000000 +#define NIS_FLASH_READY 0x40000000 +#define NIS_CACHE_VALID 0x20000000 +#define NIS_SPARE_VALID 0x10000000 +#define NIS_FLASH_STS_MASK 0x000000ff +#define NIS_WRITE_PROTECT 0x00000080 +#define NIS_DEV_READY 0x00000040 +#define NIS_PGM_ERASE_ERROR 0x00000001 + + uint32 NandEccCorrExtAddr; /* ECC Correctable Error Extended Address*/ + uint32 NandEccCorrAddr; /* ECC Correctable Error Address */ + uint32 NandEccUncExtAddr; /* ECC Uncorrectable Error Extended Addr */ + uint32 NandEccUncAddr; /* ECC Uncorrectable Error Address */ + uint32 NandFlashReadExtAddr; /* Flash Read Data Extended Address */ + uint32 NandFlashReadAddr; /* Flash Read Data Address */ + uint32 NandProgramPageExtAddr; /* Page Program Extended Address */ + uint32 NandProgramPageAddr; /* Page Program Address */ + uint32 NandCopyBackExtAddr; /* Copy Back Extended Address */ + uint32 NandCopyBackAddr; /* Copy Back Address */ + uint32 NandBlockEraseExtAddr; /* Block Erase Extended Address */ + uint32 NandBlockEraseAddr; /* Block Erase Address */ + uint32 NandInvReadExtAddr; /* Flash Invalid Data Extended Address */ + uint32 NandInvReadAddr; /* Flash Invalid Data Address */ + uint32 NandBlkWrProtect; /* Block Write Protect Enable and Size */ + /* for EBI_CS0b */ +} NandCtrlRegs; + +#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE) + +#define NAND_CACHE ((volatile uint8 * const) NAND_CACHE_BASE) + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/shared/broadcom/include/bcm963xx/6816_common.h b/shared/broadcom/include/bcm963xx/6816_common.h new file mode 100755 index 0000000..8c8c2ff --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6816_common.h @@ -0,0 +1,351 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6816_common.h */ +/* DATE: 02/01/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6816 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6816_MAP_COMMON_H +#define __BCM6816_MAP_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define NAND_INTR_BASE 0xb0000070 +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define I2C_BASE 0xb0000180 +#define OTP_BASE 0xb0000400 +#define UBUS_STAT_BASE 0xb0000500 +#define SPI_BASE 0xb0000800 /* SPI master controller registers */ +#define HSSPIM_BASE 0xb0001000 +#define MISC_BASE 0xb0001800 +#define NAND_REG_BASE 0xb0002000 /* NAND control registers */ +#define MPI_BASE 0xb00020A0 /* MPI control registers */ +#define PCI_BASE 0xb0002100 /* PCI control registers */ +#define NAND_CACHE_BASE 0xb0002200 +#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10002500 /* USB host registers */ +#define USB_OHCI_BASE 0x10002600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0002700 +#define IPSEC_BASE 0xb0002800 +#define DDR_BASE 0xb0003000 /* Memory control registers */ +#define GPON_BASE 0xb0004000 +#define APM_BASE 0xb0008000 +#define PCM_BASE 0xb0008200 +#define APM_HVG_BASE 0xb0008300 +#define APM_IUDMA_BASE 0xb0008800 +#define BMU_BASE 0xb0009000 /* fff9D000-fff9Dfff */ +#define USB_DMA_BASE 0xb000c000 /* USB 2.0 device DMA regiseters */ +#define GPON_DMA_BASE 0xb000c800 +#define IPSEC_DMA_BASE 0xb000d000 +#define SWITCH_DMA_BASE 0xb000d800 +#define SWITCH_DMA_CONFIG 0xb000da00 +#define SWITCH_DMA_STATE 0xb000dc00 +#define APM_MEM_BASE 0xb0010000 +#define MOCA_MEM_BASE 0xb0d00000 +#define MOCA_IO_BASE 0xb0d80000 +#define SWITCH_BASE 0xb0e00000 +#define PCIE_MEM65K_BASE 0xb0e40000 +#define PCIE_MEM1M_BASE 0xb0f00000 + +/* +##################################################################### +# System PLL Control Register +##################################################################### +*/ + +/* +##################################################################### +# GPIO Control Registers +##################################################################### +*/ +#define GPIO_SWREG_CONFIG 0x1c +#define GPIO_LIN_VREG_ADJ_SHIFT 0x0 +#define GPIO_LIN_VREG_ADJ_MASK (0xf<<GPIO_LIN_VREG_ADJ_SHIFT) +#define GPIO_SW_VREG_SEL_SHIFT 0x8 +#define GPIO_SW_VREG_SEL_MASK (0xf<<GPIO_SW_VREG_SEL_SHIFT) + +/* +##################################################################### +# Miscellaneous Registers +##################################################################### +*/ +#define MISC_MEMC_CONTROL 0x10 +#define MISC_STRAP_BUS 0x14 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 27 + +/* +##################################################################### +# Memory Control Registers +##################################################################### +*/ +#define DDR_CTL_CNFG 0x000 +#define DDR_CTL_CSST 0x004 +#define DDR_CTL_CSEND 0x008 +#define DDR_CTL_ROW00_0 0x010 +#define DDR_CTL_ROW00_1 0x014 +#define DDR_CTL_ROW01_0 0x018 +#define DDR_CTL_ROW01_1 0x01c +#define DDR_CTL_ROW20_0 0x030 +#define DDR_CTL_ROW20_1 0x034 +#define DDR_CTL_ROW21_0 0x038 +#define DDR_CTL_ROW21_1 0x03c +#define DDR_CTL_COL00_0 0x050 +#define DDR_CTL_COL00_1 0x054 +#define DDR_CTL_COL01_0 0x058 +#define DDR_CTL_COL01_1 0x05c +#define DDR_CTL_COL20_0 0x070 +#define DDR_CTL_COL20_1 0x074 +#define DDR_CTL_COL21_0 0x078 +#define DDR_CTL_COL21_1 0x07c +#define DDR_CTL_BNK10 0x090 +#define DDR_CTL_BNK32 0x094 +#define DDR_CTL_DCMD 0x100 +#define DDR_CTL_DMODE_0 0x104 +#define DDR_CTL_DMODE_1 0x108 +#define DDR_CTL_CLKS 0x10c +#define DDR_CTL_ODT 0x110 +#define DDR_CTL_TIM1_0 0x114 +#define DDR_CTL_TIM1_1 0x118 +#define DDR_CTL_TIM2 0x11c +#define DDR_CTL_CTL_CRC 0x120 +#define DDR_CTL_DOUT_CRC 0x124 +#define DDR_CTL_DIN_CRC 0x128 +#define PHY_CONTROL_REGS_REVISION 0x200 +#define PHY_CONTROL_REGS_CLK_PM_CTRL 0x204 +#define PHY_CONTROL_REGS_PLL_STATUS 0x210 +#define PHY_CONTROL_REGS_PLL_CONFIG 0x214 +#define PHY_CONTROL_REGS_PLL_PRE_DIVIDER 0x218 +#define PHY_CONTROL_REGS_PLL_DIVIDER 0x21c +#define PHY_CONTROL_REGS_PLL_CONTROL1 0x220 +#define PHY_CONTROL_REGS_PLL_CONTROL2 0x224 +#define PHY_CONTROL_REGS_PLL_SS_EN 0x228 +#define PHY_CONTROL_REGS_PLL_SS_CFG 0x22c +#define PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE 0x230 +#define PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE 0x234 +#define PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x238 +#define PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL 0x23c +#define PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x240 +#define PHY_BYTE_LANE_0_REVISION 0x300 +#define PHY_BYTE_LANE_0_VDL_CALIBRATE 0x304 +#define PHY_BYTE_LANE_0_VDL_STATUS 0x308 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_0 0x310 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_1 0x314 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_2 0x318 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_3 0x31c +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_4 0x320 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_5 0x324 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_6 0x328 +#define PHY_BYTE_LANE_0_VDL_OVERRIDE_7 0x32c +#define PHY_BYTE_LANE_0_READ_CONTROL 0x330 +#define PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x334 +#define PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x338 +#define PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x33c +#define PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x340 +#define PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE 0x344 +#define PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x348 +#define PHY_BYTE_LANE_1_REVISION 0x400 +#define PHY_BYTE_LANE_1_VDL_CALIBRATE 0x404 +#define PHY_BYTE_LANE_1_VDL_STATUS 0x408 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_0 0x410 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_1 0x414 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_2 0x418 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_3 0x41c +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_4 0x420 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_5 0x424 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_6 0x428 +#define PHY_BYTE_LANE_1_VDL_OVERRIDE_7 0x42c +#define PHY_BYTE_LANE_1_READ_CONTROL 0x430 +#define PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x434 +#define PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x438 +#define PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x43c +#define PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x440 +#define PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE 0x444 +#define PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x448 +#define PHY_BYTE_LANE_2_REVISION 0x500 +#define PHY_BYTE_LANE_2_VDL_CALIBRATE 0x504 +#define PHY_BYTE_LANE_2_VDL_STATUS 0x508 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_0 0x510 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_1 0x514 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_2 0x518 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_3 0x51c +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_4 0x520 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_5 0x524 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_6 0x528 +#define PHY_BYTE_LANE_2_VDL_OVERRIDE_7 0x52c +#define PHY_BYTE_LANE_2_READ_CONTROL 0x530 +#define PHY_BYTE_LANE_2_READ_FIFO_STATUS 0x534 +#define PHY_BYTE_LANE_2_READ_FIFO_CLEAR 0x538 +#define PHY_BYTE_LANE_2_IDLE_PAD_CONTROL 0x53c +#define PHY_BYTE_LANE_2_DRIVE_PAD_CTL 0x540 +#define PHY_BYTE_LANE_2_CLOCK_PAD_DISABLE 0x544 +#define PHY_BYTE_LANE_2_WR_PREAMBLE_MODE 0x548 +#define PHY_BYTE_LANE_3_REVISION 0x600 +#define PHY_BYTE_LANE_3_VDL_CALIBRATE 0x604 +#define PHY_BYTE_LANE_3_VDL_STATUS 0x608 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_0 0x610 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_1 0x614 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_2 0x618 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_3 0x61c +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_4 0x620 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_5 0x624 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_6 0x628 +#define PHY_BYTE_LANE_3_VDL_OVERRIDE_7 0x62c +#define PHY_BYTE_LANE_3_READ_CONTROL 0x630 +#define PHY_BYTE_LANE_3_READ_FIFO_STATUS 0x634 +#define PHY_BYTE_LANE_3_READ_FIFO_CLEAR 0x638 +#define PHY_BYTE_LANE_3_IDLE_PAD_CONTROL 0x63c +#define PHY_BYTE_LANE_3_DRIVE_PAD_CTL 0x640 +#define PHY_BYTE_LANE_3_CLOCK_PAD_DISABLE 0x644 +#define PHY_BYTE_LANE_3_WR_PREAMBLE_MODE 0x648 +#define DDR_CTL_GCFG 0x800 +#define DDR_CTL_LBIST_CFG 0x804 +#define DDR_CTL_LBIST_SEED 0x808 +#define DDR_CTL_ARB 0x80c +#define DDR_CTL_PI_GCF 0x810 +#define DDR_CTL_PI_UBUS_CTL 0x814 +#define DDR_CTL_PI_MIPS_CTL 0x818 +#define DDR_CTL_PI_DSL_MIPS_CTL 0x81c +#define DDR_CTL_PI_DSL_PHY_CTL 0x820 +#define DDR_CTL_PI_UBUS_ST 0x824 +#define DDR_CTL_PI_MIPS_ST 0x828 +#define DDR_CTL_PI_DSL_MIPS_ST 0x82c +#define DDR_CTL_PI_DSL_PHY_ST 0x830 +#define DDR_CTL_PI_UBUS_SMPL 0x834 +#define DDR_CTL_TESTMODE 0x838 +#define DDR_CTL_TEST_CFG1 0x83c +#define DDR_CTL_TEST_PAT 0x840 +#define DDR_CTL_TEST_COUNT 0x844 +#define DDR_CTL_TEST_CURR_COUNT 0x848 +#define DDR_CTL_TEST_ADDR_UPDT 0x84c +#define DDR_CTL_TEST_ADDR 0x850 +#define DDR_CTL_TEST_DATA0 0x854 +#define DDR_CTL_TEST_DATA1 0x858 +#define DDR_CTL_TEST_DATA2 0x85c +#define DDR_CTL_TEST_DATA3 0x860 + +/* +##################################################################### +# MPI Control Registers +##################################################################### +*/ +#define CS0BASE 0x00 +#define CS0CNTL 0x04 + +/* +# CSxBASE settings +# Size in low 4 bits +# Base Address for match in upper 24 bits +# +# TBD - Is it 8K to 256M or 4K to 128M? +# +*/ +#define EBI_SIZE_8K 0 +#define EBI_SIZE_16K 1 +#define EBI_SIZE_32K 2 +#define EBI_SIZE_64K 3 +#define EBI_SIZE_128K 4 +#define EBI_SIZE_256K 5 +#define EBI_SIZE_512K 6 +#define EBI_SIZE_1M 7 +#define EBI_SIZE_2M 8 +#define EBI_SIZE_4M 9 +#define EBI_SIZE_8M 10 +#define EBI_SIZE_16M 11 +#define EBI_SIZE_32M 12 +#define EBI_SIZE_64M 13 +#define EBI_SIZE_128M 14 +#define EBI_SIZE_256M 15 + +/* CSxCNTL settings */ +/* TBD. Verify these definitions on BCM6816 */ +#define EBI_ENABLE 0x00000001 /* .. enable this range */ +#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */ +#define ZEROWT 0x00000000 /* .. 0 WS */ +#define ONEWT 0x00000002 /* .. 1 WS */ +#define TWOWT 0x00000004 /* .. 2 WS */ +#define THREEWT 0x00000006 /* .. 3 WS */ +#define FOURWT 0x00000008 /* .. 4 WS */ +#define FIVEWT 0x0000000a /* .. 5 WS */ +#define SIXWT 0x0000000c /* .. 6 WS */ +#define SEVENWT 0x0000000e /* .. 7 WS */ +#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */ +#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */ +#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */ +#define EBI_FIFO 0x00000200 /* .. enable fifo */ +#define EBI_RE 0x00000400 /* .. Reverse Endian */ + +/* +##################################################################### +# UART Control Registers +##################################################################### +*/ +/* TBD. Verify these definitions on BCM6816 */ +#define UART0CONTROL 0x01 +#define UART0CONFIG 0x02 +#define UART0RXTIMEOUT 0x03 +#define UART0BAUD 0x04 +#define UART0FIFOCFG 0x0a +#define UART0INTMASK 0x10 +#define UART0INTSTAT 0x12 +#define UART0DATA 0x17 + +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + +#define XMITBREAK 0x40 /* Config register */ +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/broadcom/include/bcm963xx/6816_map.h b/shared/broadcom/include/bcm963xx/6816_map.h new file mode 100755 index 0000000..6b93307 --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6816_map.h @@ -0,0 +1,2322 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6816_map.h */ +/* DATE: 05/30/08 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6816 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6816_MAP_H +#define __BCM6816_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" +#include "6816_common.h" +#include "6816_intr.h" + +/* macro to convert logical data addresses to physical */ +/* DMA hardware must see physical address */ +#define LtoP( x ) ( (uint32)x & 0x1fffffff ) +#define PtoL( x ) ( LtoP(x) | 0xa0000000 ) + +typedef struct DDRPhyControl { + uint32 REVISION; /* 0x00 */ + uint32 CLK_PM_CTRL; /* 0x04 */ + uint32 unused0[2]; /* 0x08-0x10 */ + uint32 PLL_STATUS; /* 0x10 */ + uint32 PLL_CONFIG; /* 0x14 */ + uint32 PLL_PRE_DIVIDER; /* 0x18 */ + uint32 PLL_DIVIDER; /* 0x1c */ + uint32 PLL_CONTROL1; /* 0x20 */ + uint32 PLL_CONTROL2; /* 0x24 */ + uint32 PLL_SS_EN; /* 0x28 */ + uint32 PLL_SS_CFG; /* 0x2c */ + uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ + uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ + uint32 IDLE_PAD_CONTROL; /* 0x38 */ + uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_REG_CONTROL; /* 0x44 */ + uint32 unused1[46]; +} DDRPhyControl; + +typedef struct DDRPhyByteLaneControl { + uint32 REVISION; /* 0x00 */ + uint32 VDL_CALIBRATE; /* 0x04 */ + uint32 VDL_STATUS; /* 0x08 */ + uint32 unused; /* 0x0c */ + uint32 VDL_OVERRIDE_0; /* 0x10 */ + uint32 VDL_OVERRIDE_1; /* 0x14 */ + uint32 VDL_OVERRIDE_2; /* 0x18 */ + uint32 VDL_OVERRIDE_3; /* 0x1c */ + uint32 VDL_OVERRIDE_4; /* 0x20 */ + uint32 VDL_OVERRIDE_5; /* 0x24 */ + uint32 VDL_OVERRIDE_6; /* 0x28 */ + uint32 VDL_OVERRIDE_7; /* 0x2c */ + uint32 READ_CONTROL; /* 0x30 */ + uint32 READ_FIFO_STATUS; /* 0x34 */ + uint32 READ_FIFO_CLEAR; /* 0x38 */ + uint32 IDLE_PAD_CONTROL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_PAD_DISABLE; /* 0x44 */ + uint32 WR_PREAMBLE_MODE; /* 0x48 */ + uint32 CLOCK_REG_CONTROL; /* 0x4C */ + uint32 unused0[44]; +} DDRPhyByteLaneControl; + +typedef struct DDRControl { + uint32 CNFG; /* 0x000 */ + uint32 CSST; /* 0x004 */ + uint32 CSEND; /* 0x008 */ + uint32 unused; /* 0x00c */ + uint32 ROW00_0; /* 0x010 */ + uint32 ROW00_1; /* 0x014 */ + uint32 ROW01_0; /* 0x018 */ + uint32 ROW01_1; /* 0x01c */ + uint32 unused0[4]; + uint32 ROW20_0; /* 0x030 */ + uint32 ROW20_1; /* 0x034 */ + uint32 ROW21_0; /* 0x038 */ + uint32 ROW21_1; /* 0x03c */ + uint32 unused1[4]; + uint32 COL00_0; /* 0x050 */ + uint32 COL00_1; /* 0x054 */ + uint32 COL01_0; /* 0x058 */ + uint32 COL01_1; /* 0x05c */ + uint32 unused2[4]; + uint32 COL20_0; /* 0x070 */ + uint32 COL20_1; /* 0x074 */ + uint32 COL21_0; /* 0x078 */ + uint32 COL21_1; /* 0x07c */ + uint32 unused3[4]; + uint32 BNK10; /* 0x090 */ + uint32 BNK32; /* 0x094 */ + uint32 unused4[26]; + uint32 DCMD; /* 0x100 */ +#define DCMD_CS1 (1 << 5) +#define DCMD_CS0 (1 << 4) +#define DCMD_SET_SREF 4 + uint32 DMODE_0; /* 0x104 */ + uint32 DMODE_1; /* 0x108 */ +#define DMODE_1_DRAMSLEEP (1 << 11) + uint32 CLKS; /* 0x10c */ + uint32 ODT; /* 0x110 */ + uint32 TIM1_0; /* 0x114 */ + uint32 TIM1_1; /* 0x118 */ + uint32 TIM2; /* 0x11c */ + uint32 CTL_CRC; /* 0x120 */ + uint32 DOUT_CRC; /* 0x124 */ + uint32 DIN_CRC; /* 0x128 */ + uint32 unused5[53]; + + DDRPhyControl PhyControl; /* 0x200 */ + DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ + DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ + DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ + DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ + uint32 unused6[64]; + + uint32 GCFG; /* 0x800 */ + uint32 LBIST_CFG; /* 0x804 */ + uint32 LBIST_SEED; /* 0x808 */ + uint32 ARB; /* 0x80c */ + uint32 PI_GCF; /* 0x810 */ + uint32 PI_UBUS_CTL; /* 0x814 */ + uint32 PI_MIPS_CTL; /* 0x818 */ + uint32 PI_DSL_MIPS_CTL; /* 0x81c */ + uint32 PI_DSL_PHY_CTL; /* 0x820 */ + uint32 PI_UBUS_ST; /* 0x824 */ + uint32 PI_MIPS_ST; /* 0x828 */ + uint32 PI_DSL_MIPS_ST; /* 0x82c */ + uint32 PI_DSL_PHY_ST; /* 0x830 */ + uint32 PI_UBUS_SMPL; /* 0x834 */ + uint32 TESTMODE; /* 0x838 */ + uint32 TEST_CFG1; /* 0x83c */ + uint32 TEST_PAT; /* 0x840 */ + uint32 TEST_COUNT; /* 0x844 */ + uint32 TEST_CURR_COUNT; /* 0x848 */ + uint32 TEST_ADDR_UPDT; /* 0x84c */ + uint32 TEST_ADDR; /* 0x850 */ + uint32 TEST_DATA0; /* 0x854 */ + uint32 TEST_DATA1; /* 0x858 */ + uint32 TEST_DATA2; /* 0x85c */ + uint32 TEST_DATA3; /* 0x860 */ +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define ACP_A_CLK_EN (1 << 25) +#define ACP_B_CLK_EN (1 << 24) +#define NTP_CLK_EN (1 << 23) +#define PCM_CLK_EN (1 << 22) +#define BMU_CLK_EN (1 << 21) +#define PCIE_CLK_EN (1 << 20) +#define GPON_SER_CLK_EN (1 << 19) +#define IPSEC_CLK_EN (1 << 18) +#define NAND_CLK_EN (1 << 17) +#define DISABLE_GLESS (1 << 16) +#define USBH_CLK_EN (1 << 15) +#define APM_CLK_EN (1 << 14) +#define ROBOSW_CLK_EN (1 << 12) +#define USBD_CLK_EN (1 << 10) +#define SPI_CLK_EN (1 << 9) +#define SWPKT_GPON_CLK_EN (1 << 8) +#define SWPKT_USB_CLK_EN (1 << 7) +#define GPON_CLK_EN (1 << 6) + + uint32 pll_control; /* (08) word 2 */ +#define SOFT_RESET 0x00000001 // 0 + + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_SERDES_DIG (1 << 23) +#define SOFT_RST_SERDES (1 << 22) +#define SOFT_RST_SERDES_MDIO (1 << 21) +#define SOFT_RST_SERDES_PLL (1 << 20) +#define SOFT_RST_SERDES_HW (1 << 19) +#define SOFT_RST_GPON (1 << 18) +#define SOFT_RST_BMU (1 << 17) +#define SOFT_RST_HVG (1 << 16) +#define SOFT_RST_APM (1 << 15) +#define SOFT_RST_ACP (1 << 14) +#define SOFT_RST_PCM (1 << 13) +#define SOFT_RST_USBH (1 << 12) +#define SOFT_RST_USBD (1 << 11) +#define SOFT_RST_SWITCH (1 << 10) +#define SOFT_RST_MOCA_CPU (1 << 9) +#define SOFT_RST_MOCA_SYS (1 << 8) +#define SOFT_RST_MOCA (1 << 7) +#define SOFT_RST_EPHY (1 << 6) +#define SOFT_RST_PCIE (1 << 5) +#define SOFT_RST_IPSEC (1 << 4) +#define SOFT_RST_MPI (1 << 3) +#define SOFT_RST_PCIE_EXT (1 << 2) +#define SOFT_RST_PCIE_CORE (1 << 1) +#define SOFT_RST_SPI (1 << 0) + + uint32 diagControl; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 ExtIrqCfg1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo<thresh + */ + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1) + * if these bits are also enabled to GPIO_o + */ +#define DTREN 0x01 +#define RTSEN 0x02 + + byte unused1; + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to + * detect irq on rising AND falling + * edges for corresponding GPIO_i + * if enabled (edge insensitive) + */ + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense + * 0 for negedge sense if + * not configured for edge + * insensitive (see above) + * Lower 4 bits: Mask to enable change + * detection IRQ for corresponding + * GPIO_i + */ + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits + * have changed (may set IRQ). + * read automatically clears bit + * Lower 4 bits are actual status + */ + + uint16 intMask; /* Same Bit defs for Mask and status */ + uint16 intStatus; +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + + uint16 unused2; + uint16 Data; /* Write to TX, Read from RX */ + /* bits 11:8 are BRK,PAR,FRM errors */ + + uint32 unused3; + uint32 unused4; +} Uart; + +#define UART ((volatile Uart * const) UART_BASE) + +/* +** Gpio Controller +*/ + +typedef struct GpioControl { + uint64 GPIODir; /* 0 */ + uint64 GPIOio; /* 8 */ +#define GPIO_MoCA_OVERLAY_UART_WRITE 39 +#define GPIO_MoCA_OVERLAY_UART_READ 38 + uint32 LEDCtrl; +#define LED_ALL_STROBE 0x0f000000 +#define LED3_STROBE 0x08000000 +#define LED2_STROBE 0x04000000 +#define LED1_STROBE 0x02000000 +#define LED0_STROBE 0x01000000 +#define LED_TEST 0x00010000 +#define DISABLE_LINK_ACT_ALL 0x0000f000 +#define DISABLE_LINK_ACT_3 0x00008000 +#define DISABLE_LINK_ACT_2 0x00004000 +#define DISABLE_LINK_ACT_1 0x00002000 +#define DISABLE_LINK_ACT_0 0x00001000 +#define LED_INTERVAL_SET_MASK 0x00000f00 +#define LED_INTERVAL_SET_1280MS 0x00000700 +#define LED_INTERVAL_SET_640MS 0x00000600 +#define LED_INTERVAL_SET_320MS 0x00000500 +#define LED_INTERVAL_SET_160MS 0x00000400 +#define LED_INTERVAL_SET_80MS 0x00000300 +#define LED_INTERVAL_SET_40MS 0x00000200 +#define LED_INTERVAL_SET_20MS 0x00000100 +#define LED_ON_ALL 0x000000f0 +#define LED_ON_3 0x00000080 +#define LED_ON_2 0x00000040 +#define LED_ON_1 0x00000020 +#define LED_ON_0 0x00000010 +#define LED_ENABLE_ALL 0x0000000f +#define LED_ENABLE_3 0x00000008 +#define LED_ENABLE_2 0x00000004 +#define LED_ENABLE_1 0x00000002 +#define LED_ENABLE_0 0x00000001 + uint32 SpiSlaveCfg; /* 14 */ + uint32 GPIOMode; /* 18 */ +#define GPIO_MODE_SPI_SSN5 (1<<31) +#define GPIO_MODE_SPI_SSN4 (1<<30) +#define GPIO_MODE_SPI_SSN3 (1<<29) +#define GPIO_MODE_SPI_SSN2 (1<<28) +#define GPIO_MODE_EBI_CS3 (1<<27) +#define GPIO_MODE_EBI_CS2 (1<<26) +#define GPIO_MODE_APM_CLK (1<<25) +#define GPIO_MODE_APM_SDIN (1<<24) +#define GPIO_MODE_APM_SDOUT (1<<23) +#define GPIO_MODE_APM_FRAME_SYNC (1<<22) +#define GPIO_MODE_PCI_GNT0 (1<<20) +#define GPIO_MODE_PCI_REQ0 (1<<19) +#define GPIO_MODE_PCI_INTB (1<<18) +#define GPIO_MODE_PCI_GNT1 (1<<17) +#define GPIO_MODE_PCI_REQ1 (1<<16) +#define GPIO_MODE_NTR_PULSE (1<<15) +#define GPIO_MODE_USBD_LED (1<<14) +#define GPIO_MODE_ROBOSW_LED1 (1<<13) +#define GPIO_MODE_ROBOSW_LED0 (1<<12) +#define GPIO_MODE_ROBOSW_LED_CLK (1<<11) +#define GPIO_MODE_ROBOSW_LED_DATA (1<<10) +#define GPIO_MODE_GPON_LED (1<<8) +#define GPIO_MODE_GPHY1_LED (1<<7) +#define GPIO_MODE_GPHY0_LED (1<<6) +#define GPIO_MODE_MOCA_LED (1<<5) +#define GPIO_MODE_SERIAL_LED_CLK (1<<4) +#define GPIO_MODE_SERIAL_LED_DATA (1<<3) +#define GPIO_MODE_SYS_IRQ (1<<2) +#define GPIO_MODE_GPON_TX_APC_FAIL (1<<1) /*Anticipating B0*/ +#define GPIO_MODE_GPON_TX_EN_L (1<<0) + + uint32 VregConfig; /* 1C */ +#define VREG_VSEL1P2_SHIFT 8 +#define VREG_VSEL1P2_MASK (0x0f<<8) +#define VREG_VSEL1P2_MIDDLE 9 + + uint32 AuxLedInterval; /* 20 */ +#define AUX_LED_IN_7 0x80000000 +#define AUX_LED_IN_6 0x40000000 +#define AUX_LED_IN_5 0x20000000 +#define AUX_LED_IN_4 0x10000000 +#define AUX_LED_IN_MASK 0xf0000000 +#define LED_IN_3 0x08000000 +#define LED_IN_2 0x04000000 +#define LED_IN_1 0x02000000 +#define LED_IN_0 0x01000000 +#define AUX_LED_TEST 0x00400000 +#define USE_NEW_INTV 0x00200000 +#define LED7_LNK_ORAND 0x00100000 +#define LED7_LNK_MASK 0x000f0000 +#define LED7_LNK_MASK_SHFT 16 +#define LED7_ACT_MASK 0x0000f000 +#define LED7_ACT_MASK_SHFT 12 +#define AUX_FLASH_INTV 0x00000fc0 +#define AUX_FLASH_INTV_100MS 0x00000140 +#define AUX_FLASH_INTV_SHFT 6 +#define AUX_BLINK_INTV 0x0000003f +#define AUX_BLINK_INTV_60MS 0x00000003 + uint32 AuxLedCtrl; /* 24 */ +#define AUX_HW_DISAB_7 0x80000000 +#define AUX_STROBE_7 0x40000000 +#define AUX_MODE_7 0x30000000 +#define AUX_MODE_SHFT_7 28 +#define AUX_HW_DISAB_6 0x08000000 +#define AUX_STROBE_6 0x04000000 +#define AUX_MODE_6 0x03000000 +#define AUX_MODE_SHFT_6 24 +#define AUX_HW_DISAB_5 0x00800000 +#define AUX_STROBE_5 0x00400000 +#define AUX_MODE_5 0x00300000 +#define AUX_MODE_SHFT_5 20 +#define AUX_HW_DISAB_4 0x00080000 +#define AUX_STROBE_4 0x00040000 +#define AUX_MODE_4 0x00030000 +#define AUX_MODE_SHFT_4 16 +#define AUX_HW_DISAB_3 0x00008000 +#define AUX_STROBE_3 0x00004000 +#define AUX_MODE_3 0x00003000 +#define AUX_MODE_SHFT_3 12 +#define AUX_HW_DISAB_2 0x00000800 +#define AUX_STROBE_2 0x00000400 +#define AUX_MODE_2 0x00000300 +#define AUX_MODE_SHFT_2 8 +#define AUX_HW_DISAB_1 0x00000080 +#define AUX_STROBE_1 0x00000040 +#define AUX_MODE_1 0x00000030 +#define AUX_MODE_SHFT_1 4 +#define AUX_HW_DISAB_0 0x00000008 +#define AUX_STROBE_0 0x00000004 +#define AUX_MODE_0 0x00000003 +#define AUX_MODE_SHFT_0 0 + +#define LED_STEADY_OFF 0x0 +#define LED_FLASH 0x1 +#define LED_BLINK 0x2 +#define LED_STEADY_ON 0x3 + + uint32 TestControl; /* 28 */ + + uint32 OscControl; /* 2C */ + uint32 RoboSWLEDControl; /* 30 */ + uint32 RoboSWLEDLSR; /* 34 */ + uint32 GPIOBaseMode; /* 38 */ +#define EN_GMII2 (1<<17) +#define EN_GMII1 (1<<16) + uint32 RoboswEphyCtrl; /* 3C */ +#define RSW_HW_FWDG_EN (1<<19) +#define RSW_MII_DUMB_FWDG_EN (1<<16) +#define EPHY_RST_4 (1<<9) +#define EPHY_RST_3 (1<<8) +#define EPHY_RST_2 (1<<7) +#define EPHY_RST_1 (1<<6) +#define EPHY_PWR_DOWN_4 (1<<5) +#define EPHY_PWR_DOWN_3 (1<<4) +#define EPHY_PWR_DOWN_2 (1<<3) +#define EPHY_PWR_DOWN_1 (1<<2) + uint32 unused1[2]; /* 40 */ + + uint32 RingOscCtrl0; /* 48 */ +#define RING_OSC_256_CYCLES 8 +#define RING_OSC_512_CYCLES 9 +#define RING_OSC_1024_CYCLES 10 + + uint32 RingOscCtrl1; /* 4C */ +#define RING_OSC_ENABLE_MASK (0x57<<24) +#define RING_OSC_ENABLE_SHIFT 24 +#define RING_OSC_MAX 7 +#define RING_OSC_COUNT_RESET (0x1<<23) +#define RING_OSC_SELECT_MASK (0x7<<20) +#define RING_OSC_SELECT_SHIFT 20 +#define RING_OSC_IRQ (0x1<<18) +#define RING_OSC_COUNTER_OVERFLOW (0x1<<17) +#define RING_OSC_COUNTER_BUSY (0x1<<16) +#define RING_OSC_COUNT_MASK 0x0000ffff + + uint32 SerialLed; /* 50 */ + uint32 SerialLedCtrl; /* 54 */ +#define SER_LED_BUSY (1<<3) +#define SER_LED_POLARITY (1<<2) +#define SER_LED_DIV_1 0 +#define SER_LED_DIV_2 1 +#define SER_LED_DIV_4 2 +#define SER_LED_DIV_8 3 +#define SER_LED_DIV_MASK 0x3 +#define SER_LED_DIV_SHIFT 0 + uint32 SerialLedBlink; /* 58 */ + uint32 SerdesCtl; /* 5c */ +#define SERDES_PCIE_ENABLE 0x00000001 +#define SERDES_PCIE_EXD_ENABLE (1<<15) + uint32 SerdesStatus; /* 60 */ + uint32 unused2; /* 64 */ + uint32 DieRevID; /* 68 */ + uint32 DiagMemStatus; /* 6c */ + uint32 DiagSelControl; /* 70 */ + uint32 DiagReadBack; /* 74 */ + uint32 DiagReadBackHi; /* 78 */ + uint32 DiagMiscControl; /* 7c */ +#define EPHY_SA_RESET_N 0x00000300 +#define EPHY_SA_TESTEN 0x00000500 +#define EPHY_SA_CLOCK_RESET 0x0000d900 +} GpioControl; + +#define GPIO ((volatile GpioControl * const) GPIO_BASE) + +/* Number to mask conversion macro used for GPIODir and GPIOio */ +#define GPIO_NUM_MAX 40 +#define GPIO_NUM_TO_MASK(X) ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) ) + +/* + * I2C Controller. + */ + +typedef struct I2CControl { + uint32 ChipAddress; /* 0x0 */ +#define I2C_CHIP_ADDRESS_MASK 0x000000f7 +#define I2C_CHIP_ADDRESS_SHIFT 0x1 + uint32 DataIn0; /* 0x4 */ + uint32 DataIn1; /* 0x8 */ + uint32 DataIn2; /* 0xc */ + uint32 DataIn3; /* 0x10 */ + uint32 DataIn4; /* 0x14 */ + uint32 DataIn5; /* 0x18 */ + uint32 DataIn6; /* 0x1c */ + uint32 DataIn7; /* 0x20 */ + uint32 CntReg; /* 0x24 */ +#define I2C_CNT_REG1_SHIFT 0x0 +#define I2C_CNT_REG2_SHIFT 0x6 + uint32 CtlReg; /* 0x28 */ +#define I2C_CTL_REG_DTF_MASK 0x00000003 +#define I2C_CTL_REG_DTF_WRITE 0x0 +#define I2C_CTL_REG_DTF_READ 0x1 +#define I2C_CTL_REG_DTF_READ_AND_WRITE 0x2 +#define I2C_CTL_REG_DTF_WRITE_AND_READ 0x3 +#define I2C_CTL_REG_DEGLITCH_DISABLE 0x00000004 +#define I2C_CTL_REG_DELAY_DISABLE 0x00000008 +#define I2C_CTL_REG_SCL_SEL_MASK 0x00000030 +#define I2C_CTL_REG_SCL_CLK_375KHZ 0x00000000 +#define I2C_CTL_REG_SCL_CLK_390KHZ 0x00000010 +#define I2C_CTL_REG_SCL_CLK_187_5KHZ 0x00000020 +#define I2C_CTL_REG_SCL_CLK_200KHZ 0x00000030 +#define I2C_CTL_REG_INT_ENABLE 0x00000040 +#define I2C_CTL_REG_DIV_CLK 0x00000080 + uint32 IICEnable; /* 0x2c */ +#define I2C_IIC_ENABLE 0x00000001 +#define I2C_IIC_INTRP 0x00000002 +#define I2C_IIC_NO_ACK 0x00000004 +#define I2C_IIC_NO_STOP 0x00000010 +#define I2C_IIC_NO_START 0x00000020 + uint32 DataOut0; /* 0x30 */ + uint32 DataOut1; /* 0x34 */ + uint32 DataOut2; /* 0x38 */ + uint32 DataOut3; /* 0x3c */ + uint32 DataOut4; /* 0x40 */ + uint32 DataOut5; /* 0x44 */ + uint32 DataOut6; /* 0x48 */ + uint32 DataOut7; /* 0x4c */ + uint32 CtlHiReg; /* 0x50 */ +#define I2C_CTLHI_REG_WAIT_DISABLE 0x00000001 +#define I2C_CTLHI_REG_IGNORE_ACK 0x00000002 +#define I2C_CTLHI_REG_DATA_REG_SIZE 0x00000040 + uint32 SclParam; /* 0x54 */ +} I2CControl; + +#define I2C ((volatile I2CControl * const) I2C_BASE) + +/* +** Spi Controller +*/ + +typedef struct SpiControl { + uint16 spiMsgCtl; /* (0x0) control byte */ +#define FULL_DUPLEX_RW 0 +#define HALF_DUPLEX_W 1 +#define HALF_DUPLEX_R 2 +#define SPI_MSG_TYPE_SHIFT 14 +#define SPI_BYTE_CNT_SHIFT 0 + byte spiMsgData[0x21e]; /* (0x02 - 0x21f) msg data */ + byte unused0[0x1e0]; + byte spiRxDataFifo[0x220]; /* (0x400 - 0x61f) rx data */ + byte unused1[0xe0]; + + uint16 spiCmd; /* (0x700): SPI command */ +#define SPI_CMD_NOOP 0 +#define SPI_CMD_SOFT_RESET 1 +#define SPI_CMD_HARD_RESET 2 +#define SPI_CMD_START_IMMEDIATE 3 + +#define SPI_CMD_COMMAND_SHIFT 0 +#define SPI_CMD_COMMAND_MASK 0x000f + +#define SPI_CMD_DEVICE_ID_SHIFT 4 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 +#define SPI_CMD_ONE_BYTE_SHIFT 11 +#define SPI_CMD_ONE_WIRE_SHIFT 12 +#define SPI_DEV_ID_0 0 +#define SPI_DEV_ID_1 1 +#define SPI_DEV_ID_2 2 +#define SPI_DEV_ID_3 3 + + byte spiIntStatus; /* (0x702): SPI interrupt status */ + byte spiMaskIntStatus; /* (0x703): SPI masked interrupt status */ + + byte spiIntMask; /* (0x704): SPI interrupt mask */ +#define SPI_INTR_CMD_DONE 0x01 +#define SPI_INTR_RX_OVERFLOW 0x02 +#define SPI_INTR_INTR_TX_UNDERFLOW 0x04 +#define SPI_INTR_TX_OVERFLOW 0x08 +#define SPI_INTR_RX_UNDERFLOW 0x10 +#define SPI_INTR_CLEAR_ALL 0x1f + + byte spiStatus; /* (0x705): SPI status */ +#define SPI_RX_EMPTY 0x02 +#define SPI_CMD_BUSY 0x04 +#define SPI_SERIAL_BUSY 0x08 + + byte spiClkCfg; /* (0x706): SPI clock configuration */ +#define SPI_CLK_0_391MHZ 1 +#define SPI_CLK_0_781MHZ 2 /* default */ +#define SPI_CLK_1_563MHZ 3 +#define SPI_CLK_3_125MHZ 4 +#define SPI_CLK_6_250MHZ 5 +#define SPI_CLK_12_50MHZ 6 +#define SPI_CLK_MASK 0x07 +#define SPI_SSOFFTIME_MASK 0x38 +#define SPI_SSOFFTIME_SHIFT 3 +#define SPI_BYTE_SWAP 0x80 + + byte spiFillByte; /* (0x707): SPI fill byte */ + byte unused2; + byte spiMsgTail; /* (0x709): msgtail */ + byte unused3; + byte spiRxTail; /* (0x70B): rxtail */ +} SpiControl; + + +#define SPI ((volatile SpiControl * const) SPI_BASE) + + +/* +** High-Speed SPI Controller +*/ + +#define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start) +typedef struct HsSpiControl { + + uint32 hs_spiGlobalCtrl; // 0x0000 +#define HS_SPI_MOSI_IDLE (1 << 18) +#define HS_SPI_CLK_STATE_GATED (1 << 17) +#define HS_SPI_CLK_GATE_SSOFF (1 << 16) +#define HS_SPI_PLL_CLK_CTRL (8) +#define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL) +#define HS_SPI_SS_POLARITY (0) +#define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY) + + uint32 hs_spiExtTrigCtrl; // 0x0004 +#define HS_SPI_TRIG_RAW_STATE (24) +#define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE) +#define HS_SPI_TRIG_LATCHED (16) +#define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED) +#define HS_SPI_TRIG_SENSE (8) +#define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE) +#define HS_SPI_TRIG_TYPE (0) +#define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE) +#define HS_SPI_TRIG_TYPE_EDGE (0) +#define HS_SPI_TRIG_TYPE_LEVEL (1) + + uint32 hs_spiIntStatus; // 0x0008 +#define HS_SPI_IRQ_PING1_USER (28) +#define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER) +#define HS_SPI_IRQ_PING0_USER (24) +#define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER) + +#define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQ_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQ_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntStatusMasked; // 0x000C +#define HS_SPI_IRQSM__PING1_USER (28) +#define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER) +#define HS_SPI_IRQSM__PING0_USER (24) +#define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER) + +#define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntMask; // 0x0010 +#define HS_SPI_IRQM_PING1_USER (28) +#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER) +#define HS_SPI_IRQM_PING0_USER (24) +#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER) + +#define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQM_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQM_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0) + +#define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F) + + uint32 hs_spiFlashCtrl; // 0x0014 +#define HS_SPI_FCTRL_MB_ENABLE (1 << 23) +#define HS_SPI_FCTRL_SS_NUM (20) +#define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM) +#define HS_SPI_FCTRL_PROFILE_NUM (16) +#define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM) +#define HS_SPI_FCTRL_DUMMY_BYTES (10) +#define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES (8) +#define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES_2 (0) +#define HS_SPI_FCTRL_ADDR_BYTES_3 (1) +#define HS_SPI_FCTRL_ADDR_BYTES_4 (2) +#define HS_SPI_FCTRL_READ_OPCODE (0) +#define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE) + + uint32 hs_spiFlashAddrBase; // 0x0018 + + char fill0[0x80 - 0x18]; + + uint32 hs_spiPP_0_Cmd; // 0x0080 +#define HS_SPI_PP_SS_NUM (12) +#define HS_SPI_PP_SS_NUM_MASK __mask(14, HS_SPI_PP_SS_NUM) +#define HS_SPI_PP_PROFILE_NUM (8) +#define HS_SPI_PP_PROFILE_NUM_MASK __mask(10, HS_SPI_PP_PROFILE_NUM) + +} HsSpiControl; + +typedef struct HsSpiPingPong { + + uint32 command; +#define HS_SPI_SS_NUM (12) +#define HS_SPI_PROFILE_NUM (8) +#define HS_SPI_TRIGGER_NUM (4) +#define HS_SPI_COMMAND_VALUE (0) + #define HS_SPI_COMMAND_NOOP (0) + #define HS_SPI_COMMAND_START_NOW (1) + #define HS_SPI_COMMAND_START_TRIGGER (2) + #define HS_SPI_COMMAND_HALT (3) + #define HS_SPI_COMMAND_FLUSH (4) + + uint32 status; +#define HS_SPI_ERROR_BYTE_OFFSET (16) +#define HS_SPI_WAIT_FOR_TRIGGER (2) +#define HS_SPI_SOURCE_BUSY (1) +#define HS_SPI_SOURCE_GNT (0) + + uint32 fifo_status; + uint32 control; + +} HsSpiPingPong; + +typedef struct HsSpiProfile { + + uint32 clk_ctrl; +#define HS_SPI_ACCUM_RST_ON_LOOP (15) +#define HS_SPI_SPI_CLK_2X_SEL (14) +#define HS_SPI_FREQ_CTRL_WORD (0) + + uint32 signal_ctrl; +#define HS_SPI_LAUNCH_RISING (1 << 13) +#define HS_SPI_LATCH_RISING (1 << 12) + + uint32 mode_ctrl; +#define HS_SPI_PREPENDBYTE_CNT (24) +#define HS_SPI_MODE_ONE_WIRE (20) +#define HS_SPI_MULTIDATA_WR_SIZE (18) +#define HS_SPI_MULTIDATA_RD_SIZE (16) +#define HS_SPI_MULTIDATA_WR_STRT (12) +#define HS_SPI_MULTIDATA_RD_STRT (8) +#define HS_SPI_FILLBYTE (0) + + uint32 polling_config; + uint32 polling_and_mask; + uint32 polling_compare; + uint32 polling_timeout; + uint32 reserved; + +} HsSpiProfile; + +#define HS_SPI_OP_CODE 13 + #define HS_SPI_OP_SLEEP (0) + #define HS_SPI_OP_READ_WRITE (1) + #define HS_SPI_OP_WRITE (2) + #define HS_SPI_OP_READ (3) + #define HS_SPI_OP_SETIRQ (4) + +#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE) +#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80)) +#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0)) +#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100)) +#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200)) +#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400)) + + +/* +** Periph - Misc Register Set Definitions. +*/ + +typedef struct Misc { + uint32 miscMoCADiv ; /* (0x0) MoCA Ref PLL Div */ +#define MISC_MOCA_DIV_REF_DIV_FB_MASK 0xFF000000 +#define MISC_MOCA_DIV_REF_DIV_FB_SHIFT 24 +#define MISC_MOCA_DIV_REF_OUTDIV_M1_MASK 0x00FF0000 +#define MISC_MOCA_DIV_REF_OUTDIV_M1_SHIFT 16 +#define MISC_MOCA_DIV_REF_OUTDIV_M4_MASK 0x0000FF00 +#define MISC_MOCA_DIV_REF_OUTDIV_M4_SHIFT 8 +#define MISC_MOCA_DIV_REF_OUTDIV_M5_MASK 0x000000FF +#define MISC_MOCA_DIV_REF_OUTDIV_M5_SHIFT 0 + uint32 miscMoCACtl ; /* (0x4) MoCA Ref PLL Ctl */ +#define MISC_MOCA_CTL_REF_OUTCML_LOWCUR_MASK 0x001FC000 +#define MISC_MOCA_CTL_REF_OUTCML_LOWCUR_SHIFT 14 +#define MISC_MOCA_CTL_REF_CLFCNT_MASK 0x00003000 +#define MISC_MOCA_CTL_REF_CLFCNT_SHIFT 12 +#define MISC_MOCA_CTL_REF_QP_ICTRL_MASK 0x00000E00 +#define MISC_MOCA_CTL_REF_QP_ICTRL_SHIFT 9 +#define MISC_MOCA_CTL_REF_VCOBUF_LATCH_ON 0x00000100 +#define MISC_MOCA_CTL_REF_LF_RCNTL_MASK 0x000000E0 +#define MISC_MOCA_CTL_REF_LF_RCNTL_SHIFT 5 +#define MISC_MOCA_CTL_REF_MUX_FBOFF 0x00000010 +#define MISC_MOCA_CTL_REF_MUX_SEL_MASK 0x0000000C +#define MISC_MOCA_CTL_REF_MUX_SEL_SHIFT 2 +#define MISC_MOCA_CTL_REF_REF_CMLBIAS_MASK 0x00000003 +#define MISC_MOCA_CTL_REF_REF_CMLBIAS_SHIFT 0 + uint32 miscMoCAPwr ; /* (0x8) MoCA Ref PLL Pwr */ +#define MISC_MOCA_PWR_REF_DEEP_PWRDN 0x01000000 +#define MISC_MOCA_PWR_REF_OUTDIV_PWRDN_M_MASK 0x00FE0000 +#define MISC_MOCA_PWR_REF_OUTDIV_PWRDN_M_SHIFT 17 +#define MISC_MOCA_PWR_REF_OUTCML_PWRDN_M_MASK 0x0001FC00 +#define MISC_MOCA_PWR_REF_OUTCML_PWRDN_M_SHIFT 10 +#define MISC_MOCA_PWR_REF_OUTCMOS_PWRDN_M_MASK 0x000003F8 +#define MISC_MOCA_PWR_REF_OUTCMOS_PWRDN_M_SHIFT 3 +#define MISC_MOCA_PWR_REF_UGB_PWRDN 0x00000004 +#define MISC_MOCA_PWR_REF_MUX_PWRDN 0x00000002 +#define MISC_MOCA_PWR_REF_VCO_PWRDN 0x00000001 + uint32 miscMoCARst ; /* (0xC) MoCA Ref PLL Rst */ +#define MISC_MOCA_RST_REF_OUTDIV_RESET_M_MASK 0x00000FE0 +#define MISC_MOCA_RST_REF_OUTDIV_RESET_M_SHIFT 5 +#define MISC_MOCA_RST_REF_DIV2RST 0x00000010 +#define MISC_MOCA_RST_REF_MDIV2RST 0x00000008 +#define MISC_MOCA_RST_REF_FBDIVRST 0x00000004 +#define MISC_MOCA_RST_REF_LD_RESET_STRT 0x00000002 +#define MISC_MOCA_RST_REF_VCRST 0x00000001 + uint32 miscMemcControl ; /* (0x10) MEMC Control */ +#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE 0x00000008 +#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE 0x00000004 +#define MISC_MEMC_CONTROL_DDR_TEST_DONE 0x00000002 +#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE 0x00000001 + uint32 miscStrapBus ; /* (0x14) Strap Register */ +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK 0xF8000000 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 27 +#define MISC_STRAP_BUS_HRD_RST_DELAY 0x04000000 +#define MISC_STRAP_BUS_ALT_BFC_EN 0x02000000 +#define MISC_STRAP_BUS_MOCA_STANDALONE_B 0x01000000 +#define MISC_STRAP_BUS_MOCA_CONFIG_RATIO 0x00800000 +#define MISC_STRAP_BUS_IXTAL_ADJ_MASK 0x00600000 +#define MISC_STRAP_BUS_IXTAL_ADJ_SHIFT 21 +#define MISC_STRAP_BUS_BYPASS_XTAL 0x00100000 +#define MISC_STRAP_BUS_TS 0x00080000 +#define MISC_STRAP_BUS_APM_PICO_BOOT_ROM 0x00040000 +#define MISC_STRAP_BUS_TA 0x00020000 +#define MISC_STRAP_BUS_ROBOSW_2_MODE_MASK 0x00018000 +#define MISC_STRAP_BUS_ROBOSW_2_MODE_SHIFT 15 +#define MISC_STRAP_BUS_ROBOSW_1_MODE_MASK 0x00006000 +#define MISC_STRAP_BUS_ROBOSW_1_MODE_SHIFT 13 +#define MISC_STRAP_BUS_BIST_CLRMEM_N 0x00001000 +#define MISC_STRAP_BUS_PLL_MIPS_WAIT_FAST_N 0x00000200 +#define MISC_STRAP_BUS_PLL_USE_LOCK 0x00000100 +#define MISC_STRAP_BUS_PCIE_ROOT_COMPLEX 0x00000080 +#define MISC_STRAP_BUS_LS_SPIM_ENABLED 0x00000040 +#define MISC_STRAP_BUS_USE_SPI_MASTER 0x00000020 +#define MISC_STRAP_BUS_SPI_CLK_FAST 0x00000010 +#define MISC_STRAP_BUS_SPI_BOOT_DELAY 0x00000008 +#define MISC_STRAP_BUS_MIPS_BOOT16 0x00000004 +#define MISC_STRAP_BUS_BOOT_SEL_MASK 0x00000003 +#define MISC_STRAP_BUS_BOOT_SEL_SHIFT 0 +#define MISC_STRAP_BUS_BOOT_PARALLEL 0x03 +#define MISC_STRAP_BUS_BOOT_SERIAL 0x01 +#define MISC_STRAP_BUS_BOOT_NAND 0x02 + uint32 miscStrapOverride ; /* (0x18) Strap Override Reg */ +#define MISC_STRAP_OVERRIDE_INT_MPI_ARB 0x00000008 +#define MISC_STRAP_OVERRIDE_INT_MPI_CLK 0x00000004 +#define MISC_STRAP_OVERRIDE_INT_HOST 0x00000002 +#define MISC_STRAP_OVERRIDE_STRAP_OVERRIDE 0x00000001 + uint32 miscMoCAClkStrapBus ; /* (0x1C) MoCA Clock Strap Reg */ +#define MISC_MOCA_CLK_STRAP_BUS_MDIV_10_OVERRIDE_MASK 0x0000FF00 +#define MISC_MOCA_CLK_STRAP_BUS_MDIV_10_OVERRIDE_SHIFT 8 +#define MISC_MOCA_CLK_STRAP_BUS_MDIV_9_OVERRIDE_MASK 0x000000FF +#define MISC_MOCA_CLK_STRAP_BUS_MDIV_9_OVERRIDE_SHIFT 0 + uint32 miscMoCAClkStrapOverride ; /* (0x20) MoCA Clock Strap Overdide Reg */ +#define MISC_MOCA_CLK_STRAP_OVERRIDE_MOCA_CLK_STRAP_OVERRIDE_CTL 0x00000001 + uint32 miscMoCAGpioOverlayLo ; /* (0x24) MoCA GPIO Overlay bus lo Reg */ + uint32 miscMoCAGpioOverlayHi ; /* (0x28) MoCA GPIO Overlay bus hi Reg */ +#define MISC_MOCA_GPIO_UART 0x000000C0 + uint32 miscDdrPllOutEnCh ; /* (0x2C) DDR PLL Out En Ch Number */ +#define MISC_DDR_PLL_OUTEN_CH_DDR_PLL_OUTEN_CH_MASK 0x000001FF +#define MISC_DDR_PLL_OUTEN_CH_DDR_PLL_OUTEN_CH_SHIFT 0 +#define MISC_DDR_PLL_OUTEN_CH_MOCA_CPU_CLK 0x00000080 +#define MISC_DDR_PLL_OUTEN_CH_MOCA_PHY_CLK 0x00000100 + uint32 miscGpioDiagOverlay ; /* (0x30) GPIO Diag Overlay Control Reg */ +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_EN 0x00000020 +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_MASK 0x0000001F +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_39_32 0x00000010 +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_31_24 0x00000008 +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_23_16 0x00000004 +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_15_8 0x00000002 +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_7_0 0x00000001 + uint32 miscGpioModeCtrlHi ; /* (0x34) GPIO Pin Mode Control Reg Hi */ +} Misc ; + +#define MISC ((volatile Misc * const) MISC_BASE) + +/* +** Pcm Controller +*/ + +typedef struct PcmControlRegisters +{ + uint32 pcm_ctrl; // 00 offset from PCM_BASE +#define PCM_ENABLE 0x80000000 // PCM block master enable +#define PCM_ENABLE_SHIFT 31 +#define PCM_SLAVE_SEL 0x40000000 // PCM TDM slave mode select (1 - TDM slave, 0 - TDM master) +#define PCM_SLAVE_SEL_SHIFT 30 +#define PCM_CLOCK_INV 0x20000000 // PCM SCLK invert select (1 - invert, 0 - normal) +#define PCM_CLOCK_INV_SHIFT 29 +#define PCM_FS_INVERT 0x10000000 // PCM FS invert select (1 - invert, 0 - normal) +#define PCM_FS_INVERT_SHIFT 28 +#define PCM_FS_FREQ_16_8 0x08000000 // PCM FS 16/8 Khz select (1 - 16Khz, 0 - 8Khz) +#define PCM_FS_FREQ_16_8_SHIFT 27 +#define PCM_FS_LONG 0x04000000 // PCM FS long/short select (1 - long FS, 0 - short FS) +#define PCM_FS_LONG_SHIFT 26 +#define PCM_FS_TRIG 0x02000000 // PCM FS trigger (1 - falling edge, 0 - rising edge trigger) +#define PCM_FS_TRIG_SHIFT 25 +#define PCM_DATA_OFF 0x01000000 // PCM data offset from FS (1 - one clock from FS, 0 - no offset) +#define PCM_DATA_OFF_SHIFT 24 +#define PCM_DATA_16_8 0x00800000 // PCM data word length (1 - 16 bits, 0 - 8 bits) +#define PCM_DATA_16_8_SHIFT 23 +#define PCM_CLOCK_SEL 0x00700000 // PCM SCLK freq select +#define PCM_CLOCK_SEL_SHIFT 20 + // 000 - 8192 Khz + // 001 - 4096 Khz + // 010 - 2048 Khz + // 011 - 1024 Khz + // 100 - 512 Khz + // 101 - 256 Khz + // 110 - 128 Khz + // 111 - reserved +#define PCM_LSB_FIRST 0x00040000 // PCM shift direction (1 - LSBit first, 0 - MSBit first) +#define PCM_LSB_FIRST_SHIFT 18 +#define PCM_LOOPBACK 0x00020000 // PCM diagnostic loobback enable +#define PCM_LOOPBACK_SHIFT 17 +#define PCM_EXTCLK_SEL 0x00010000 // PCM external timing clock select -- Maybe removed in 6816 +#define PCM_EXTCLK_SEL_SHIFT 16 +#define PCM_NTR_ENABLE 0x00008000 // PCM NTR counter enable -- Nayve removed in 6816 +#define PCM_NTR_ENABLE_SHIFT 15 +#define PCM_BITS_PER_FRAME_1024 0x00000400 // 1024 - Max +#define PCM_BITS_PER_FRAME_256 0x00000100 // 256 +#define PCM_BITS_PER_FRAME_8 0x00000008 // 8 - Min + + uint32 pcm_chan_ctrl; // 04 +#define PCM_TX0_EN 0x00000001 // PCM transmit channel 0 enable +#define PCM_TX1_EN 0x00000002 // PCM transmit channel 1 enable +#define PCM_TX2_EN 0x00000004 // PCM transmit channel 2 enable +#define PCM_TX3_EN 0x00000008 // PCM transmit channel 3 enable +#define PCM_TX4_EN 0x00000010 // PCM transmit channel 4 enable +#define PCM_TX5_EN 0x00000020 // PCM transmit channel 5 enable +#define PCM_TX6_EN 0x00000040 // PCM transmit channel 6 enable +#define PCM_TX7_EN 0x00000080 // PCM transmit channel 7 enable +#define PCM_RX0_EN 0x00000100 // PCM receive channel 0 enable +#define PCM_RX1_EN 0x00000200 // PCM receive channel 1 enable +#define PCM_RX2_EN 0x00000400 // PCM receive channel 2 enable +#define PCM_RX3_EN 0x00000800 // PCM receive channel 3 enable +#define PCM_RX4_EN 0x00001000 // PCM receive channel 4 enable +#define PCM_RX5_EN 0x00002000 // PCM receive channel 5 enable +#define PCM_RX6_EN 0x00004000 // PCM receive channel 6 enable +#define PCM_RX7_EN 0x00008000 // PCM receive channel 7 enable +#define PCM_RX_PACKET_SIZE 0x00ff0000 // PCM Rx DMA quasi-packet size +#define PCM_RX_PACKET_SIZE_SHIFT 16 + + uint32 pcm_int_pending; // 08 + uint32 pcm_int_mask; // 0c +#define PCM_TX_UNDERFLOW 0x00000001 // PCM DMA receive overflow +#define PCM_RX_OVERFLOW 0x00000002 // PCM DMA transmit underflow +#define PCM_TDM_FRAME 0x00000004 // PCM frame boundary +#define PCM_RX_IRQ 0x00000008 // IUDMA interrupts +#define PCM_TX_IRQ 0x00000010 + +// From apm_core.h in Irvine + uint32 reg_pcm_clk_cntl_0; // (0x210) PCM Clock Control 0 (NCO_FCW_MISC) + uint32 reg_pcm_clk_cntl_1; // (0x214) PCM Clock Control 1 (NCO_SCALE) + uint32 reg_pcm_clk_cntl_2; // (0x218) PCM Clock Control 2 +#define PCM_NCO_SHIFT 0x0000000f +#define PCM_NCO_MUX_CNTL 0x00000030 +#define PCM_NCO_LOAD_MISC 0x00000040 +#define PCM_NCO_SOFT_INIT 0x00000080 +#if 0 // Incorrect for 6816 + uint32 pcm_pll_ctrl1; // 10 +#define PCM_PLL_PWRDN 0x80000000 // PLL PWRDN +#define PCM_PLL_PWRDN_CH1 0x40000000 // PLL CH PWRDN +#define PCM_PLL_REFCMP_PWRDN 0x20000000 // PLL REFCMP PWRDN +#define PCM_CLK16_RESET 0x10000000 // 16.382 MHz PCM interface circuitry reset. +#define PCM_PLL_ARESET 0x08000000 // PLL Analog Reset +#define PCM_PLL_DRESET 0x04000000 // PLL Digital Reset + + uint32 pcm_pll_ctrl2; // 14 + uint32 pcm_pll_ctrl3; // 18 + uint32 pcm_pll_ctrl4; // 1c + + uint32 pcm_pll_stat; // 20 +#define PCM_PLL_LOCK 0x00000001 // Asserted when PLL is locked to programmed frequency + + uint32 pcm_ntr_counter; // 24 +#endif + + uint32 unused[9]; +#define PCM_MAX_TIMESLOT_REGS 16 // Number of PCM time slot registers in the table. + // Each register provides the settings for 8 timeslots (4 bits per timeslot) + uint32 pcm_slot_alloc_tbl[PCM_MAX_TIMESLOT_REGS]; +#define PCM_TS_VALID 0x8 // valid marker for TS alloc ram entry +} PcmControlRegisters; + +#define PCM ((volatile PcmControlRegisters * const) PCM_BASE) + +typedef struct HvgControlRegisters +{ + uint16 reg_hvg_scale_vtip; + uint16 reg_hvg_scale_vhvg; + + uint16 reg_hvg_scale_vloop; + uint16 reg_hvg_scale_vring; + + uint16 reg_hvg_scale_vcal; + uint16 reg_hvg_scale_vinput; + + uint16 reg_hvg_offset_vtip; + uint16 reg_hvg_offset_vhvg; + + uint16 reg_hvg_offset_vloop; + uint16 reg_hvg_offset_vring; + + uint16 reg_hvg_offset_vcal; + uint16 reg_hvg_offset_vinput; + + uint32 reg_hvg_shift; +#define COND_SHIFT_V_HVG 0x0000000f +#define COND_SHIFT_V_TIP 0x000000f0 +#define COND_SHIFT_V_RING 0x00000f00 +#define COND_SHIFT_V_LOOP 0x0000f000 +#define COND_SHIFT_V_INPUT 0x000f0000 +#define COND_SHIFT_CAL 0x00f00000 +#define DIODE_DROP 0x0f000000 +#define HVG_IGNORE_RESET 0x10000000 +#define BG_TRIM_SOURCE 0x20000000 +#define HVG_SOFT_INIT 0x40000000 + + uint32 reg_hvg_turns_ratio; +#define TURNS_RATIO 0x00000ffc +#define RING_RECT_LINE 0xffff0000 + + uint32 reg_hvg_duty_cycle; +#define MAX_DUTY_CYCLE 0x000000ff +#define MIN_DUTY_CYCLE 0x0000ff00 +#define MIN_ON_TIME 0x00ff0000 +#define SHORT_CIRCUIT_THSHLD 0xff000000 + + uint32 reg_hvg_ring; +#define RING_GAIN 0x00000fff +#define RING_OVHD 0x0fff0000 +#define HVG_COMMON_RING_REF 0x80000000 +#define RING_GAIN_SHIFT 0 +#define RING_OVHD_SHIFT 16 +#define HVG_COMMON_RING_REF_SHIFT 31 + + uint32 reg_hvg_off_hook; +#define OFF_HOOK_OVHD 0x000001ff +#define OFF_HOOK_MIN 0x0003fe00 +#define PULSE_START_PHASE 0xff000000 + + uint32 reg_hvg_bg; +#define BG_CTAT 0x0000003f +#define BG_PTAT 0x00003f00 +#define BG_PTAT_SHIFT 8 +#define RING_DELAY 0x001f0000 +#define HVG_SER_TST_INJECT 0x00200000 + + uint32 reg_hvg_reg_3; +#define SCALE_V_BAT 0x00007fff +#define OFFSET_V_BAT 0x0fff8000 +#define SHIFT_V_BAT 0xf0000000 + + uint32 reg_hvg_status1; +#define HVG_OOB_B 0x40000000 +#define HVG_INST_VALID_B 0x20000000 +#define HVG_INST_B 0x1fff0000 +#define HVG_OOB_A 0x00004000 +#define HVG_INST_VALID_A 0x00002000 +#define HVG_INST_A 0x00001fff + + uint32 reg_hvg_status2; +#define TIP_OOB_B 0x40000000 +#define TIP_INST_VALID_B 0x20000000 +#define TIP_INST_B 0x1fff0000 +#define TIP_OOB_A 0x00004000 +#define TIP_INST_VALID_A 0x00002000 +#define TIP_INST_A 0x00001fff + + uint32 reg_hvg_status3; +#define RING_OOB_B 0x40000000 +#define RING_INST_VALID_B 0x20000000 +#define RING_INST_B 0x1fff0000 +#define RING_OOB_A 0x00004000 +#define RING_INST_VALID_A 0x00002000 +#define RING_INST_A 0x00001fff + + uint32 reg_hvg_status4; +#define LOOP_OOB_B 0x40000000 +#define LOOP_INST_VALID_B 0x20000000 +#define LOOP_INST_B 0x1fff0000 +#define LOOP_OOB_A 0x00004000 +#define LOOP_INST_VALID_A 0x00002000 +#define LOOP_INST_A 0x00001fff + + uint32 reg_hvg_status5; +#define INPUT_OOB_B 0x40000000 +#define INPUT_INST_VALID_B 0x20000000 +#define INPUT_INST_B 0x1fff0000 +#define INPUT_OOB_A 0x00004000 +#define INPUT_INST_VALID_A 0x00002000 +#define INPUT_INST_A 0x00001fff + + uint32 reg_hvg_status6; +#define CAL_OOB_B 0x40000000 +#define CAL_OOB_INST_VALID_B 0x20000000 +#define CAL_INST_B 0x1fff0000 +#define CAL_OOB_A 0x00004000 +#define CAL_OOB_INST_VALID_A 0x00002000 +#define CAL_INST_A 0x00001fff + + uint32 reg_hvg_status7; +#define HVG_DUTY_CYCLE_B 0xff000000 +#define HVG_DUTY_CYCLE_A 0x00ff0000 +#define HVG_SHORT_FLAG_B 0x00000800 +#define HVG_SHORT_FLAG_A 0x00000400 +#define HVG_DUTY_CYCLE_LIMITED_B 0x00000200 +#define HVG_DUTY_CYCLE_LIMITED_A 0x00000100 +#define MAX_DIV_OOB_B 0x00000080 +#define MAX_DIV_OOB_A 0x00000040 +#define MAX_MULT_OOB_B 0x00000020 +#define MAX_MULT_OOB_A 0x00000010 +#define ARBITER_ERR_B 0x00000008 +#define ARBITER_ERR_A 0x00000004 +#define AVG_BLOCK_DONE_B 0x00000002 +#define AVG_BLOCK_DONE_A 0x00000001 + + uint32 reg_hvg_status8; +#define HVG_AVG_VALID 0x20000000 +#define HVG_SAT 0x10000000 +#define HVG_WINDOW_SLEW 0x0f000000 +#define HVG_MEAN 0x001fffff + + uint32 reg_hvg_status9; + uint32 reg_hvg_status10; +#define TIP_AVG_VALID 0x20000000 +#define TIP_SAT 0x10000000 +#define TIP_WINDOW_SLEW 0x0f000000 +#define TIP_MEAN 0x001fffff + + uint32 reg_hvg_status11; + uint32 reg_hvg_status12; +#define RING_AVG_VALID 0x20000000 +#define RING_SAT 0x10000000 +#define RING_WINDOW_SLEW 0x0f000000 +#define RING_MEAN 0x001fffff + + uint32 reg_hvg_status13; + uint32 reg_hvg_status14; +#define TP_RG_AVG_VALID 0x20000000 +#define TP_RG_SAT 0x10000000 +#define TP_RG_WINDOW_SLEW 0x0f000000 +#define TP_RG_MEAN 0x001fffff + + uint32 reg_hvg_status15; + uint32 reg_hvg_status16; +#define I_LOOP_AVG_VALID 0x20000000 +#define I_LOOP_SAT 0x10000000 +#define I_LOOP_WINDOW_SLEW 0x0f000000 +#define I_LOOP_MEAN 0x001fffff + + uint32 reg_hvg_status17; + uint32 reg_hvg_status18; +#define INPUT_AVG_VALID 0x20000000 +#define INPUT_SAT 0x10000000 +#define INPUT_WINDOW_SLEW 0x0f000000 +#define INPUT_MEAN 0x001fffff + + uint32 reg_hvg_status19; + uint32 reg_hvg_status20; +#define CAL_AVG_VALID 0x20000000 +#define CAL_SAT 0x10000000 +#define CAL_WINDOW_SLEW 0x0f000000 +#define CAL_MEAN 0x001fffff + + uint32 reg_hvg_status21; + uint32 reg_hvg_status22; + uint32 reg_hvg_status23; + uint32 reg_hvg_status24; + uint32 reg_hvg_status25; + uint32 reg_hvg_status26; + uint32 reg_hvg_status27; + uint32 reg_hvg_status28; + uint32 reg_hvg_status29; + uint32 reg_hvg_status30; + uint32 reg_hvg_status31; + uint32 reg_hvg_status32; + uint32 reg_hvg_status33; + uint32 reg_hvg_status34; + uint32 reg_hvg_status35; + + uint32 hvg_spacer1[16]; + + uint32 reg_hvg_cha_window_ctrl; +#define HVG_WINDOW_SIZE 0x0000000f +#define TIP_WINDOW_SIZE 0x000000f0 +#define RING_WINDOW_SIZE 0x00000f00 +#define LOOP_WINDOW_SIZE 0x0000f000 +#define INPUT_WINDOW_SIZE 0x000f0000 +#define TP_RG_WINDOW_SIZE 0x00f00000 +#define CAL_WINDOW_SIZE 0x0f000000 +#define SLEW_WINDOW_SIZES 0x10000000 +#define NEW_BLK_RQST 0x20000000 + + uint16 reg_hvg_cha_max_hvg_slic; + uint16 reg_hvg_cha_const_volt_goal; + + uint32 reg_hvg_cha_misc; +#define K_PROP 0x0000000f +#define K_INTEG 0x000000f0 +#define SER_TST_OUTPUT_SEL 0x00000700 +#define CONT_OR_BLOCK 0x00000800 +#define HVG_MODE 0x00003000 +#define HVG_MODE_OFFHOOK_TRACKING 0x00001000 +#define HVG_MODE_ONHOOK_FIXED 0x00002000 +#define HVG_SOFT_INIT_0 0x00004000 +#define HVG_RR_SINGLE 0x00008000 + + uint32 reg_hvg_cha_spare; + uint32 hvg_spacer2[28]; + + uint32 reg_hvg_chb_window_ctrl; + + uint16 reg_hvg_chb_max_hvg_slic; + uint16 reg_hvg_chb_const_volt_goal; + + uint32 reg_hvg_chb_misc; + uint32 reg_hvg_chb_spare; + +} HvgControlRegisters; + +#define HVG ((volatile HvgControlRegisters * const) APM_HVG_BASE) + +/***** TBD. This is the BCM6368 definition. Need BCM6816 definition. *****/ +typedef struct PcmIudmaRegisters +{ + uint16 reserved0; + uint16 ctrlConfig; +#define BCM6816_IUDMA_REGS_CTRLCONFIG_MASTER_EN 0x0001 +#define BCM6816_IUDMA_REGS_CTRLCONFIG_FLOWC_CH1_EN 0x0002 +#define BCM6816_IUDMA_REGS_CTRLCONFIG_FLOWC_CH3_EN 0x0004 +#define BCM6816_IUDMA_REGS_CTRLCONFIG_FLOWC_CH5_EN 0x0008 +#define BCM6816_IUDMA_REGS_CTRLCONFIG_FLOWC_CH7_EN 0x0010 + + // Flow control Ch1 + uint16 reserved1; + uint16 ch1_FC_Low_Thr; + + uint16 reserved2; + uint16 ch1_FC_High_Thr; + + uint16 reserved3; + uint16 ch1_Buff_Alloc; + + // Flow control Ch3 + uint16 reserved4; + uint16 ch3_FC_Low_Thr; + + uint16 reserved5; + uint16 ch3_FC_High_Thr; + + uint16 reserved6; + uint16 ch3_Buff_Alloc; + + // Flow control Ch5 + uint16 reserved7; + uint16 ch5_FC_Low_Thr; + + uint16 reserved8; + uint16 ch5_FC_High_Thr; + + uint16 reserved9; + uint16 ch5_Buff_Alloc; + + // Flow control Ch7 + uint16 reserved10; + uint16 ch7_FC_Low_Thr; + + uint16 reserved11; + uint16 ch7_FC_High_Thr; + + uint16 reserved12; + uint16 ch7_Buff_Alloc; + + // Channel resets + uint16 reserved13; + uint16 channel_reset; + + uint16 reserved14; + uint16 channel_debug; + + // Spare register + uint32 dummy1; + + // Interrupt status registers + uint16 reserved15; + uint16 gbl_int_stat; + + // Interrupt mask registers + uint16 reserved16; + uint16 gbl_int_mask; +} PcmIudmaRegisters; + +/***** TBD. This is the BCM6368 definition. Need BCM6816 definition. *****/ +typedef struct PcmIudmaChannelCtrl +{ + uint16 reserved1; + uint16 config; +#define BCM6816_IUDMA_CONFIG_ENDMA 0x0001 +#define BCM6816_IUDMA_CONFIG_PKTHALT 0x0002 +#define BCM6816_IUDMA_CONFIG_BURSTHALT 0x0004 + + uint16 reserved2; + uint16 intStat; +#define BCM6816_IUDMA_INTSTAT_BDONE 0x0001 +#define BCM6816_IUDMA_INTSTAT_PDONE 0x0002 +#define BCM6816_IUDMA_INTSTAT_NOTVLD 0x0004 +#define BCM6816_IUDMA_INTSTAT_MASK 0x0007 +#define BCM6816_IUDMA_INTSTAT_ALL BCM6816_IUDMA_INTSTAT_MASK + + uint16 reserved3; + uint16 intMask; +#define BCM6816_IUDMA_INTMASK_BDONE 0x0001 +#define BCM6816_IUDMA_INTMASK_PDONE 0x0002 +#define BCM6816_IUDMA_INTMASK_NOTVLD 0x0004 + + uint32 maxBurst; +#define BCM6816_IUDMA_MAXBURST_SIZE 16 /* 32-bit words */ + +} PcmIudmaChannelCtrl; + + +typedef struct PcmIudmaStateRam +{ + uint32 baseDescPointer; /* pointer to first buffer descriptor */ + + uint32 stateBytesDoneRingOffset; /* state info: how manu bytes done and the offset of the + current descritor in process */ +#define BCM6816_IUDMA_STRAM_DESC_RING_OFFSET 0x3fff + + + uint32 flagsLengthStatus; /* Length and status field of the current descriptor */ + + uint32 currentBufferPointer; /* pointer to the current descriptor */ + +} PcmIudmaStateRam; + +#define BCM6816_MAX_PCM_DMA_CHANNELS 2 + +typedef struct PcmIudma +{ + PcmIudmaRegisters regs; // + uint32 reserved1[110]; // + PcmIudmaChannelCtrl ctrl[BCM6816_MAX_PCM_DMA_CHANNELS]; // + uint32 reserved2[120]; // + PcmIudmaStateRam stram[BCM6816_MAX_PCM_DMA_CHANNELS]; // + +} PcmIudma; + +#define PCM_IUDMA ((volatile PcmIudma * const) PCM_DMA_BASE) + + +#define IUDMA_MAX_CHANNELS 32 + +/* +** DMA Channel Configuration (1 .. 32) +*/ +typedef struct DmaChannelCfg { + uint32 cfg; /* (00) assorted configuration */ +#define DMA_ENABLE 0x00000001 /* set to enable channel */ +#define DMA_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ +#define DMA_BURST_HALT 0x00000004 /* idle after finish current memory burst */ + uint32 intStat; /* (04) interrupts control and status */ + uint32 intMask; /* (08) interrupts mask */ +#define DMA_BUFF_DONE 0x00000001 /* buffer done */ +#define DMA_DONE 0x00000002 /* packet xfer complete */ +#define DMA_NO_DESC 0x00000004 /* no valid descriptors */ + uint32 maxBurst; /* (0C) max burst length permitted */ +#define DMA_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */ +} DmaChannelCfg; + +/* +** DMA State RAM (1 .. 16) +*/ +typedef struct DmaStateRam { + uint32 baseDescPtr; /* (00) descriptor ring start address */ + uint32 state_data; /* (04) state/bytes done/ring offset */ + uint32 desc_len_status; /* (08) buffer descriptor status and len */ + uint32 desc_base_bufptr; /* (0C) buffer descrpitor current processing */ +} DmaStateRam; + + +/* +** DMA Registers +*/ +typedef struct DmaRegs { + uint32 controller_cfg; /* (00) controller configuration */ +#define DMA_MASTER_EN 0x00000001 +#define DMA_FLOWC_CH1_EN 0x00000002 +#define DMA_FLOWC_CH3_EN 0x00000004 + + // Flow control Ch1 + uint32 flowctl_ch1_thresh_lo; /* 004 */ + uint32 flowctl_ch1_thresh_hi; /* 008 */ + uint32 flowctl_ch1_alloc; /* 00c */ +#define DMA_BUF_ALLOC_FORCE 0x80000000 + + // Flow control Ch3 + uint32 flowctl_ch3_thresh_lo; /* 010 */ + uint32 flowctl_ch3_thresh_hi; /* 014 */ + uint32 flowctl_ch3_alloc; /* 018 */ + + // Flow control Ch5 + uint32 flowctl_ch5_thresh_lo; /* 01C */ + uint32 flowctl_ch5_thresh_hi; /* 020 */ + uint32 flowctl_ch5_alloc; /* 024 */ + + // Flow control Ch7 + uint32 flowctl_ch7_thresh_lo; /* 028 */ + uint32 flowctl_ch7_thresh_hi; /* 02C */ + uint32 flowctl_ch7_alloc; /* 030 */ + + uint32 ctrl_channel_reset; /* 034 */ + uint32 ctrl_channel_debug; /* 038 */ + uint32 reserved1; /* 03C */ + uint32 ctrl_global_interrupt_status; /* 040 */ + uint32 ctrl_global_interrupt_mask; /* 044 */ + + // Unused words + uint8 reserved2[0x200-0x48]; + + // Per channel registers/state ram + DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */ + union { + DmaStateRam s[IUDMA_MAX_CHANNELS]; + uint32 u32[4 * IUDMA_MAX_CHANNELS]; + } stram; /* (400-5FF) state ram */ +} DmaRegs; + +#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE) + +/* +** DMA Buffer +*/ +typedef struct DmaDesc { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ +} DmaDesc; + +/* +** 16 Byte DMA Buffer +*/ +typedef struct { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ + uint32 control; +#define GEM_ID_MASK 0x001F + uint32 reserved; +} DmaDesc16; + +/* +** External Bus Interface +*/ +typedef struct EbiChipSelect { + uint32 base; /* base address in upper 24 bits */ +#define EBI_SIZE_8K 0 +#define EBI_SIZE_16K 1 +#define EBI_SIZE_32K 2 +#define EBI_SIZE_64K 3 +#define EBI_SIZE_128K 4 +#define EBI_SIZE_256K 5 +#define EBI_SIZE_512K 6 +#define EBI_SIZE_1M 7 +#define EBI_SIZE_2M 8 +#define EBI_SIZE_4M 9 +#define EBI_SIZE_8M 10 +#define EBI_SIZE_16M 11 +#define EBI_SIZE_32M 12 +#define EBI_SIZE_64M 13 +#define EBI_SIZE_128M 14 +#define EBI_SIZE_256M 15 + uint32 config; +#define EBI_ENABLE 0x00000001 /* .. enable this range */ +#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */ +#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */ +#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */ +#define EBI_WREN 0x00000020 /* enable posted writes */ +#define EBI_POLARITY 0x00000040 /* .. set to invert something, + ** don't know what yet */ +#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */ +#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */ +#define EBI_FIFO 0x00000200 /* .. use fifo */ +#define EBI_RE 0x00000400 /* .. Reverse Endian */ +#define EBI_SETUP_SHIFT 16 +#define EBI_HOLD_SHIFT 20 +#define EBI_SETUP_STATES 0x0f0000 +#define EBI_HOLD_STATES 0xf00000 +} EbiChipSelect; + +typedef struct MpiRegisters { + EbiChipSelect cs[7]; /* size chip select configuration */ +#define EBI_CS0_BASE 0 +#define EBI_CS1_BASE 1 +#define EBI_CS2_BASE 2 +#define EBI_CS3_BASE 3 +#define EBI_CS4_BASE 4 +#define EBI_CS5_BASE 5 +#define EBI_CS6_BASE 6 + uint32 unused0[2]; /* reserved */ + uint32 ebi_control; /* ebi control */ +#define EBI_ACCESS_TIMEOUT 0x000007FF + uint32 unused1[7]; /* reserved */ + + uint32 sp0range; /* PCI to internal system bus address space */ +#define ADDR_SPACE_MASK 0xFFFF0000 + uint32 sp0remap; + uint32 sp0cfg; + uint32 sp1range; + uint32 sp1remap; + uint32 sp1cfg; + + uint32 EndianCfg; + + uint32 l2pcfgctl; /* internal system bus to PCI IO/Cfg control */ +#define DIR_CFG_SEL 0x80000000 /* change from PCI I/O access to PCI config access */ +#define DIR_CFG_USEREG 0x40000000 /* use this register info for PCI configuration access */ +#define DEVICE_NUMBER 0x00007C00 /* device number for the PCI configuration access */ +#define FUNC_NUMBER 0x00000300 /* function number for the PCI configuration access */ +#define REG_NUMBER 0x000000FC /* register number for the PCI configuration access */ +#define CONFIG_TYPE 0x00000003 /* configuration type for the PCI configuration access */ + + uint32 l2pmrange1; /* internal system bus to PCI memory space */ +#define PCI_SIZE_64K 0xFFFF0000 +#define PCI_SIZE_128K 0xFFFE0000 +#define PCI_SIZE_256K 0xFFFC0000 +#define PCI_SIZE_512K 0xFFF80000 +#define PCI_SIZE_1M 0xFFF00000 +#define PCI_SIZE_2M 0xFFE00000 +#define PCI_SIZE_4M 0xFFC00000 +#define PCI_SIZE_8M 0xFF800000 +#define PCI_SIZE_16M 0xFF000000 +#define PCI_SIZE_32M 0xFE000000 + uint32 l2pmbase1; /* kseg0 or kseg1 address & 0x1FFFFFFF */ + uint32 l2pmremap1; +#define CARDBUS_MEM 0x00000004 +#define MEM_WINDOW_EN 0x00000001 + uint32 l2pmrange2; + uint32 l2pmbase2; + uint32 l2pmremap2; + uint32 l2piorange; /* internal system bus to PCI I/O space */ + uint32 l2piobase; + uint32 l2pioremap; + + uint32 pcimodesel; +#define PCI_INT_BUS_RD_PREFETCH 0x000001F0 +#define PCI_BAR2_NOSWAP 0x00000002 /* BAR at offset 0x20 */ +#define PCI_BAR1_NOSWAP 0x00000001 /* BAR at affset 0x1c */ + + uint32 pciintstat; /* PCI interrupt mask/status */ +#define MAILBOX1_SENT 0x08 +#define MAILBOX0_SENT 0x04 +#define MAILBOX1_MSG_RCV 0x02 +#define MAILBOX0_MSG_RCV 0x01 + uint32 locbuscntrl; /* internal system bus control */ +#define DIR_U2P_NOSWAP 0x00000002 +#define EN_PCI_GPIO 0x00000001 + uint32 locintstat; /* internal system bus interrupt mask/status */ +#define CSERR 0x0200 +#define SERR 0x0100 +#define EXT_PCI_INT 0x0080 +#define DIR_FAILED 0x0040 +#define DIR_COMPLETE 0x0020 +#define PCI_CFG 0x0010 + uint32 unused4[7]; + + uint32 mailbox0; + uint32 mailbox1; + + uint32 pcicfgcntrl; /* internal system bus PCI configuration control */ +#define PCI_CFG_REG_WRITE_EN 0x00000080 +#define PCI_CFG_ADDR 0x0000003C + uint32 pcicfgdata; /* internal system bus PCI configuration data */ + + uint32 locch2ctl; /* PCI to interrnal system bus DMA (downstream) local control */ +#define MPI_DMA_HALT 0x00000008 /* idle after finish current memory burst */ +#define MPI_DMA_PKT_HALT 0x00000004 /* idle after an EOP flag is detected */ +#define MPI_DMA_STALL 0x00000002 /* idle after an EOP flag is detected */ +#define MPI_DMA_ENABLE 0x00000001 /* set to enable channel */ + uint32 locch2intStat; +#define MPI_DMA_NO_DESC 0x00000004 /* no valid descriptors */ +#define MPI_DMA_DONE 0x00000002 /* packet xfer complete */ +#define MPI_DMA_BUFF_DONE 0x00000001 /* buffer done */ + uint32 locch2intMask; + uint32 unused5; + uint32 locch2descaddr; + uint32 locch2status1; +#define LOCAL_DESC_STATE 0xE0000000 +#define PCI_DESC_STATE 0x1C000000 +#define BYTE_DONE 0x03FFC000 +#define RING_ADDR 0x00003FFF + uint32 locch2status2; +#define BUFPTR_OFFSET 0x1FFF0000 +#define PCI_MASTER_STATE 0x000000C0 +#define LOC_MASTER_STATE 0x00000038 +#define CONTROL_STATE 0x00000007 + uint32 unused6; + + uint32 locch1Ctl; /*internal system bus to PCI DMA (upstream) local control */ +#define DMA_U2P_LE 0x00000200 /* local bus is little endian */ +#define DMA_U2P_NOSWAP 0x00000100 /* lccal bus is little endian but no data swapped */ + uint32 locch1intstat; + uint32 locch1intmask; + uint32 unused7; + uint32 locch1descaddr; + uint32 locch1status1; + uint32 locch1status2; + uint32 unused8; + + uint32 pcich1ctl; /* internal system bus to PCI DMA PCI control */ + uint32 pcich1intstat; + uint32 pcich1intmask; + uint32 pcich1descaddr; + uint32 pcich1status1; + uint32 pcich1status2; + + uint32 pcich2Ctl; /* PCI to internal system bus DMA PCI control */ + uint32 pcich2intstat; + uint32 pcich2intmask; + uint32 pcich2descaddr; + uint32 pcich2status1; + uint32 pcich2status2; + + uint32 perm_id; /* permanent device and vendor id */ + uint32 perm_rev; /* permanent revision id */ +} MpiRegisters; + +#define MPI ((volatile MpiRegisters * const) MPI_BASE) + +/* PCI configuration address space start offset 0x40 */ +#define BRCM_PCI_CONFIG_TIMER 0x40 +#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK 0x0000FF00 +#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK 0x000000FF + +/* +** USB 2.0 Device Registers +*/ +typedef struct UsbRegisters { +#define USBD_CONTROL_APP_DONECSR 0x0001 +#define USBD_CONTROL_APP_RESUME 0x0002 +#define USBD_CONTROL_APP_RXFIFIO_INIT 0x0040 +#define USBD_CONTROL_APP_TXFIFIO_INIT 0x0080 +#define USBD_CONTROL_APP_FIFO_SEL_SHIFT 0x8 +#define USBD_CONTROL_APP_FIFO_INIT_SEL(x) (((x)&0x0f)<<USBD_CONTROL_APP_FIFO_SEL_SHIFT) +#define USBD_CONTROL_APP_AUTO_CSRS 0x2000 +#define USBD_CONTROL_APP_AUTO_INS_ZERO_LEN_PKT 0x4000 +#define EN_TXZLENINS (1<<14) +#define EN_RXZSCFG (1<<12) +#define APPSETUPERRLOCK (1<<5) + uint32 usbd_control ; +#define USBD_STRAPS_APP_SELF_PWR 0x0400 +#define USBD_STRAPS_APP_DEV_DISCON 0x0200 +#define USBD_STRAPS_APP_CSRPRG_SUP 0x0100 +#define USBD_STRAPS_APP_RAM_IF 0x0080 +#define USBD_STRAPS_APP_DEV_RMTWKUP 0x0040 +#define USBD_STRAPS_APP_PHYIF_8BIT 0x0004 +#define USBD_STRAPS_FULL_SPEED 0x0003 +#define USBD_STRAPS_LOW_SPEED 0x0002 +#define USBD_STRAPS_HIGH_SPEED 0x0000 +#define APPUTMIDIR(x) ((x&1)<<3) +#define UNIDIR 0 + uint32 usbd_straps; +#define USB_ENDPOINT_0 0x01 + uint32 usbd_stall; +#define USBD_ENUM_SPEED_SHIFT 12 +#define USBD_ENUM_SPEED 0x3000 +#define UDC20_ALTINTF(x) ((x>>8)&0xf) +#define UDC20_INTF(x) ((x>>4)&0xf) +#define UDC20_CFG(x) ((x>>0)&0xf) + uint32 usbd_status; +#define USBD_LINK (0x1<<10) +#define USBD_SET_CSRS 0x40 +#define USBD_SUSPEND 0x20 +#define USBD_EARLY_SUSPEND 0x10 +#define USBD_SOF 0x08 +#define USBD_ENUMON 0x04 +#define USBD_SETUP 0x02 +#define USBD_USBRESET 0x01 + uint32 usbd_events; + uint32 usbd_events_irq; +#define UPPER(x) (16+x) +#define ENABLE(x) (1<<x) +#define SWP_TXBSY (15) +#define SWP_RXBSY (14) +#define SETUP_ERR (13) +#define APPUDCSTALLCHG (12) +#define BUS_ERR (11) +#define USB_LINK (10) +#define HST_SETCFG (9) +#define HST_SETINTF (8) +#define ERRATIC_ERR (7) +#define SET_CSRS (6) +#define SUSPEND (5) +#define ERLY_SUSPEND (4) +#define SOF (3) +#define ENUM_ON (2) +#define SETUP (1) +#define USB_RESET (0) +#define RISING(x) (0x0<<2*x) +#define FALLING(x) (0x1<<2*x) +#define USBD_IRQCFG_ENUM_ON_FALLING_EDGE 0x00000010 + uint32 usbd_irqcfg_hi ; + uint32 usbd_irqcfg_lo ; +#define USBD_USB_RESET_IRQ 0x00000001 +#define USBD_USB_SETUP_IRQ 0x00000002 // non-standard setup cmd rcvd +#define USBD_USB_ENUM_ON_IRQ 0x00000004 +#define USBD_USB_SOF_IRQ 0x00000008 +#define USBD_USB_EARLY_SUSPEND_IRQ 0x00000010 +#define USBD_USB_SUSPEND_IRQ 0x00000020 // non-standard setup cmd rcvd +#define USBD_USB_SET_CSRS_IRQ 0x00000040 +#define USBD_USB_ERRATIC_ERR_IRQ 0x00000080 +#define USBD_USB_SETCFG_IRQ 0x00000200 +#define USBD_USB_LINK_IRQ 0x00000400 + uint32 usbd_events_irq_mask; + uint32 usbd_swcfg; + uint32 usbd_swtxctl; + uint32 usbd_swrxctl; + uint32 usbd_txfifo_rwptr; + uint32 usbd_rxfifo_rwptr; + uint32 usbd_txfifo_st_rwptr; + uint32 usbd_rxfifo_st_rwptr; + uint32 usbd_txfifo_config ; + uint32 usbd_rxfifo_config ; + uint32 usbd_txfifo_epsize ; + uint32 usbd_rxfifo_epsize ; +#define USBD_EPNUM_CTRL 0x0 +#define USBD_EPNUM_ISO 0x1 +#define USBD_EPNUM_BULK 0x2 +#define USBD_EPNUM_IRQ 0x3 +#define USBD_EPNUM_EPTYPE(x) (((x)&0x3)<<8) +#define USBD_EPNUM_EPDMACHMAP(x) (((x)&0xf)<<0) + uint32 usbd_epnum_typemap ; + uint32 usbd_reserved [0xB] ; + uint32 usbd_csr_setupaddr ; +#define USBD_EPNUM_MASK 0xf +#define USBD_EPNUM(x) ((x&USBD_EPNUM_MASK)<<0) +#define USBD_EPDIR_IN (1<<4) +#define USBD_EPDIR_OUT (0<<4) +#define USBD_EPTYP_CTRL (USBD_EPNUM_CTRL<<5) +#define USBD_EPTYP_ISO (USBD_EPNUM_ISO<<5) +#define USBD_EPTYP_BULK (USBD_EPNUM_BULK<<5) +#define USBD_EPTYP_IRQ (USBD_EPNUM_IRQ<<5) +#define USBD_EPCFG_MASK 0xf +#define USBD_EPCFG(x) ((x&USBD_EPCFG_MASK)<<7) +#define USBD_EPINTF_MASK 0xf +#define USBD_EPINTF(x) ((x&USBD_EPINTF_MASK)<<11) +#define USBD_EPAINTF_MASK 0xf +#define USBD_EPAINTF(x) ((x&USBD_EPAINTF_MASK)<<15) +#define USBD_EPMAXPKT_MSK 0x7ff +#define USBD_EPMAXPKT(x) ((x&USBD_EPMAXPKT_MSK)<<19) +#define USBD_EPISOPID_MASK 0x3 +#define USBD_EPISOPID(x) ((x&USBD_ISOPID_MASK)<<30) + uint32 usbd_csr_ep [5] ; +} UsbRegisters; + +#define USB ((volatile UsbRegisters * const) USB_CTL_BASE) + +typedef struct USBControl { + uint32 BrtControl1; + uint32 BrtControl2; + uint32 BrtStatus1; + uint32 BrtStatus2; + uint32 UTMIControl1; + uint32 TestPortControl; + uint32 PllControl1; + uint32 SwapControl; +#define USB_DEVICE_SEL (1<<6) +#define EHCI_LOGICAL_ADDRESS_EN (1<<5) +#define EHCI_ENDIAN_SWAP (1<<4) +#define EHCI_DATA_SWAP (1<<3) +#define OHCI_LOGICAL_ADDRESS_EN (1<<2) +#define OHCI_ENDIAN_SWAP (1<<1) +#define OHCI_DATA_SWAP (1<<0) + uint32 unused1; + uint32 FrameAdjustValue; + uint32 Setup; +#define USBH_IOC (1<<4) + uint32 MDIO; + uint32 MDIO32; + uint32 USBSimControl; +} USBControl; + +#define USBH ((volatile USBControl * const) USBH_CFG_BASE) + +/* +** GPON SERDES Registers +*/ +typedef struct GponSerdesRegs { + uint32 topCfg; + uint32 swReset; + uint32 aeCfg; + uint32 aeStatus; + uint32 phyCfg; + uint32 phyStatus; + uint32 mdioWr; + uint32 mdioRd; + uint32 reserved[2]; + uint32 fifoCfg; + uint32 fifoStatus; + uint32 patternCfg[4]; + uint32 patternStatus[2]; + uint32 laserCfg; +#define GPON_SERDES_LASERMODE_MASK (3<<30) +#define GPON_SERDES_LASERMODE_NORMAL (0<<30) +#define GPON_SERDES_LASERMODE_FORCE_OFF (1<<30) +#define GPON_SERDES_LASERMODE_FORCE_ON (2<<30) + uint32 laserStatus; + uint32 miscCfg; + uint32 miscStatus; + uint32 phDet[5]; +} GponSerdesRegs; + +#define GPON_SERDES ((volatile GponSerdesRegs * const) GPON_SERDES_BASE) + + +/* +** PCI-E +*/ +typedef struct PcieRegs{ + uint32 devVenID; + uint16 command; + uint16 status; + uint32 revIdClassCode; + uint32 headerTypeLatCacheLineSize; + uint32 bar1; + uint32 bar2; + uint32 priSecBusNo; +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK 0x00ff0000 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT 16 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK 0x0000ff00 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT 8 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK 0x000000ff +} PcieRegs; + +typedef struct PcieBlk404Regs{ + uint32 unused; /* 0x404 */ + uint32 config2; /* 0x408 */ +#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK 0x0000000f +#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE 0 + uint32 config3; /* 0x40c */ + uint32 pmDataA; /* 0x410 */ + uint32 pmDataB; /* 0x414 */ +} PcieBlk404Regs; + +typedef struct PcieBlk428Regs{ + uint32 vpdIntf; /* 0x428 */ + uint16 unused_g; /* 0x42c */ + uint16 vpdAddrFlag; /* 0x42e */ + uint32 vpdData; /* 0x430 */ + uint32 idVal1; /* 0x434 */ + uint32 idVal2; /* 0x438 */ + uint32 idVal3; /* 0x43c */ +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK 0xff000000 +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT 24 +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK 0x00ffffff +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT 16 +#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT 8 +}PcieBlk428Regs; + +typedef struct PcieBridgeRegs{ + uint32 bar1Remap; /* 0x0818*/ + uint32 bar2Remap; /* 0x081c*/ + uint32 bridgeOptReg1; /* 0x0820*/ +#define PCIE_BRIDGE_OPT_REG1_EN_RD_BE (1 << 4) +#define PCIE_BRIDGE_OPT_REG1_EN_RD_BE_NOSWAP (1 << 5) + uint32 bridgeOptReg2; /* 0x0824*/ +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK 0xe0000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT 29 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK 0x1f000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT 24 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK 0x00ff0000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT 16 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK 0x00000080 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT 7 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK 0x00000040 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT 6 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK 0x00000020 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT 5 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK 0x00000010 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT 4 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK 0x00000004 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT 2 +#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK 0x0000ff0b +}PcieBridgeRegs; + +typedef struct PcieBlk1000Regs{ + uint32 undisclosed[18]; /*0x1000 - 0x1044*/ + uint32 dlStatus; /* 0x1048 */ +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK 0x00002000 +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT 13 +}PcieBlk1000Regs; + +typedef struct PcieBlk1800Regs{ +#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS 4 + uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS]; +#define REG_POWERDOWN_P1PLL_ENA (1<<12) + uint32 phyErrorAttnVec; + uint32 phyErrorAttnMask; +#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS 3 + uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS]; +#define NUM_PCIE_BLK_1800_PHY_DBG_REGS 11 + uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS]; +} PcieBlk1800Regs; + +#define PCIEH_DEV_OFFSET 0x8000 +#define PCIEH ((volatile uint32 * const) PCIE_BASE) +#define PCIEH_REGS ((volatile PcieCfeType1Regs * const) PCIE_BASE) +#define PCIEH_BLK_404_REGS ((volatile PcieBlk404Regs * const)(PCIE_BASE+0x404)) +#define PCIEH_BLK_428_REGS ((volatile PcieBlk428Regs * const)(PCIE_BASE+0x428)) +#define PCIEH_BRIDGE_REGS ((volatile PcieBridgeRegs * const) (PCIE_BASE+0x818)) +#define PCIEH_BLK_1000_REGS ((volatile PcieBlk1000Regs * const) (PCIE_BASE+0x1000)) +#define PCIEH_BLK_1800_REGS ((volatile PcieBlk1800Regs * const) (PCIE_BASE+0x1800)) + +typedef struct EthSwRegs{ + byte port_traffic_ctrl[9]; /* 0x00 - 0x08 */ + byte reserved1[2]; /* 0x09 - 0x0a */ + byte switch_mode; /* 0x0b */ + unsigned short pause_quanta; /*0x0c */ + byte imp_port_state; /*0x0e */ + byte led_refresh; /* 0x0f */ + unsigned short led_function[2]; /* 0x10 */ + unsigned short led_function_map; /* 0x14 */ + unsigned short led_enable_map; /* 0x16 */ + unsigned short led_mode_map0; /* 0x18 */ + unsigned short led_function_map1; /* 0x1a */ + byte reserved2[5]; /* 0x1b - 0x20 */ + byte port_forward_ctrl; /* 0x21 */ + byte reserved3[2]; /* 0x22 - 0x23 */ + unsigned short protected_port_selection; /* 0x24 */ + unsigned short wan_port_select; /* 0x26 */ + unsigned int pause_capability; /* 0x28 */ + byte reserved4[3]; /* 0x2c - 0x2e */ + byte reserved_multicast_control; /* 0x2f */ + byte reserved5; /* 0x30 */ + byte txq_flush_mode_control; /* 0x31 */ + unsigned short ulf_forward_map; /* 0x32 */ + unsigned short mlf_forward_map; /* 0x34 */ + unsigned short mlf_impc_forward_map; /* 0x36 */ + unsigned short pause_pass_through_for_rx; /* 0x38 */ + unsigned short pause_pass_through_for_tx; /* 0x3a */ + unsigned short disable_learning; /* 0x3c */ + byte reserved6[26]; /* 0x3e - 0x57 */ + byte port_state_override[8]; /* 0x58 - 0x5f */ + byte reserved7[4]; /* 0x60 - 0x63 */ + byte imp_rgmii_ctrl_p4; /* 0x64 */ + byte imp_rgmii_ctrl_p5; /* 0x65 */ + byte reserved8[6]; /* 0x66 - 0x6b */ + byte rgmii_timing_delay_p4; /* 0x6c */ + byte gmii_timing_delay_p5; /* 0x6d */ + byte reserved9[11]; /* 0x6e - 0x78 */ + byte software_reset; /* 0x79 */ + byte reserved13[6]; /* 0x7a - 0x7f */ + byte pause_frame_detection; /* 0x80 */ + byte reserved10[7]; /* 0x81 - 0x87 */ + byte fast_aging_ctrl; /* 0x88 */ + byte fast_aging_port; /* 0x89 */ + byte fast_aging_vid; /* 0x8a */ + byte reserved11[21]; /* 0x8b - 0x9f */ + unsigned int swpkt_ctrl_sar; /*0xa0 */ + unsigned int swpkt_ctrl_usb; /*0xa4 */ + unsigned int iudma_ctrl; /*0xa8 */ + unsigned int rxfilt_ctrl; /*0xac */ + unsigned int mdio_ctrl; /*0xb0 */ + unsigned int mdio_data; /*0xb4 */ + byte reserved12[42]; /* 0xb6 - 0xdf */ + unsigned int sw_mem_test; /*0xe0 */ +} EthSwRegs; + +#define ETHSWREG ((volatile EthSwRegs * const) SWITCH_BASE) + +typedef struct EthSwMIBRegs { + unsigned int TxOctetsLo; + unsigned int TxOctetsHi; + unsigned int TxDropPkts; + unsigned int TxQoSPkts; + unsigned int TxBroadcastPkts; + unsigned int TxMulticastPkts; + unsigned int TxUnicastPkts; + unsigned int TxCol; + unsigned int TxSingleCol; + unsigned int TxMultipleCol; + unsigned int TxDeferredTx; + unsigned int TxLateCol; + unsigned int TxExcessiveCol; + unsigned int TxFrameInDisc; + unsigned int TxPausePkts; + unsigned int TxQoSOctetsLo; + unsigned int TxQoSOctetsHi; + unsigned int RxOctetsLo; + unsigned int RxOctetsHi; + unsigned int RxUndersizePkts; + unsigned int RxPausePkts; + unsigned int Pkts64Octets; + unsigned int Pkts65to127Octets; + unsigned int Pkts128to255Octets; + unsigned int Pkts256to511Octets; + unsigned int Pkts512to1023Octets; + unsigned int Pkts1024to1522Octets; + unsigned int RxOversizePkts; + unsigned int RxJabbers; + unsigned int RxAlignErrs; + unsigned int RxFCSErrs; + unsigned int RxGoodOctetsLo; + unsigned int RxGoodOctetsHi; + unsigned int RxDropPkts; + unsigned int RxUnicastPkts; + unsigned int RxMulticastPkts; + unsigned int RxBroadcastPkts; + unsigned int RxSAChanges; + unsigned int RxFragments; + unsigned int RxExcessSizeDisc; + unsigned int RxSymbolError; + unsigned int RxQoSPkts; + unsigned int RxQoSOctetsLo; + unsigned int RxQoSOctetsHi; + unsigned int Pkts1523to2047; + unsigned int Pkts2048to4095; + unsigned int Pkts4096to8191; + unsigned int Pkts8192to9728; +} EthSwMIBRegs; + +#define ETHSWMIBREG ((volatile EthSwMIBRegs * const) (SWITCH_BASE + 0x2000)) + +/* +** NAND Interrupt Controller Registers +*/ +typedef struct NandIntrCtrlRegs { + uint32 NandInterrupt; +#define NINT_ENABLE_MASK 0xffff0000 +#define NINT_STS_MASK 0x00000fff +#define NINT_ECC_ERROR_CORR 0x00000080 +#define NINT_ECC_ERROR_UNC 0x00000040 +#define NINT_DEV_RBPIN 0x00000020 +#define NINT_CTRL_READY 0x00000010 +#define NINT_PAGE_PGM 0x00000008 +#define NINT_COPY_BACK 0x00000004 +#define NINT_BLOCK_ERASE 0x00000002 +#define NINT_NP_READ 0x00000001 + + uint32 NandBaseAddr0; /* Default address when booting from NAND flash */ + uint32 reserved; + uint32 NandBaseAddr1; /* Secondary base address for NAND flash */ +} NandIntrCtrlRegs; + +#define NAND_INTR ((volatile NandIntrCtrlRegs * const) NAND_INTR_BASE) + +/* +** NAND Controller Registers +*/ +typedef struct NandCtrlRegs { + uint32 NandRevision; /* NAND Revision */ + uint32 NandCmdStart; /* Nand Flash Command Start */ +#define NCMD_MASK 0x0f000000 +#define NCMD_BLK_LOCK_STS 0x0d000000 +#define NCMD_BLK_UNLOCK 0x0c000000 +#define NCMD_BLK_LOCK_DOWN 0x0b000000 +#define NCMD_BLK_LOCK 0x0a000000 +#define NCMD_FLASH_RESET 0x09000000 +#define NCMD_BLOCK_ERASE 0x08000000 +#define NCMD_DEV_ID_READ 0x07000000 +#define NCMD_COPY_BACK 0x06000000 +#define NCMD_PROGRAM_SPARE 0x05000000 +#define NCMD_PROGRAM_PAGE 0x04000000 +#define NCMD_STS_READ 0x03000000 +#define NCMD_SPARE_READ 0x02000000 +#define NCMD_PAGE_READ 0x01000000 + + uint32 NandCmdExtAddr; /* Nand Flash Command Extended Address */ + uint32 NandCmdAddr; /* Nand Flash Command Address */ + uint32 NandCmdEndAddr; /* Nand Flash Command End Address */ + uint32 NandNandBootConfig; /* Nand Flash Boot Config */ +#define NBC_CS_LOCK 0x80000000 +#define NBC_AUTO_DEV_ID_CFG 0x40000000 +#define NBC_WR_PROT_BLK0 0x10000000 + + uint32 NandCsNandXor; /* Nand Flash EBI CS Address XOR with */ + /* 1FC0 Control */ + uint32 NandReserved; + uint32 NandSpareAreaReadOfs0; /* Nand Flash Spare Area Read Bytes 0-3 */ + uint32 NandSpareAreaReadOfs4; /* Nand Flash Spare Area Read Bytes 4-7 */ + uint32 NandSpareAreaReadOfs8; /* Nand Flash Spare Area Read Bytes 8-11 */ + uint32 NandSpareAreaReadOfsC; /* Nand Flash Spare Area Read Bytes 12-15*/ + uint32 NandSpareAreaWriteOfs0; /* Nand Flash Spare Area Write Bytes 0-3 */ + uint32 NandSpareAreaWriteOfs4; /* Nand Flash Spare Area Write Bytes 4-7 */ + uint32 NandSpareAreaWriteOfs8; /* Nand Flash Spare Area Write Bytes 8-11*/ + uint32 NandSpareAreaWriteOfsC; /* Nand Flash Spare Area Write Bytes12-15*/ + uint32 NandAccControl; /* Nand Flash Access Control */ + uint32 NandConfig; /* Nand Flash Config */ +#define NC_CONFIG_LOCK 0x80000000 +#define NC_PG_SIZE_MASK 0x40000000 +#define NC_PG_SIZE_2K 0x40000000 +#define NC_PG_SIZE_512B 0x00000000 +#define NC_BLK_SIZE_MASK 0x30000000 +#define NC_BLK_SIZE_512K 0x30000000 +#define NC_BLK_SIZE_128K 0x10000000 +#define NC_BLK_SIZE_16K 0x00000000 +#define NC_BLK_SIZE_8K 0x20000000 +#define NC_DEV_SIZE_MASK 0x0f000000 +#define NC_DEV_SIZE_SHIFT 24 +#define NC_DEV_WIDTH_MASK 0x00800000 +#define NC_DEV_WIDTH_16 0x00800000 +#define NC_DEV_WIDTH_8 0x00000000 +#define NC_FUL_ADDR_MASK 0x00070000 +#define NC_FUL_ADDR_SHIFT 16 +#define NC_BLK_ADDR_MASK 0x00000700 +#define NC_BLK_ADDR_SHIFT 8 + + uint32 NandTiming1; /* Nand Flash Timing Parameters 1 */ + uint32 NandTiming2; /* Nand Flash Timing Parameters 2 */ + uint32 NandSemaphore; /* Semaphore */ + uint32 NandFlashDeviceId; /* Nand Flash Device ID */ + uint32 NandBlockLockStatus; /* Nand Flash Block Lock Status */ + uint32 NandIntfcStatus; /* Nand Flash Interface Status */ +#define NIS_CTLR_READY 0x80000000 +#define NIS_FLASH_READY 0x40000000 +#define NIS_CACHE_VALID 0x20000000 +#define NIS_SPARE_VALID 0x10000000 +#define NIS_FLASH_STS_MASK 0x000000ff +#define NIS_WRITE_PROTECT 0x00000080 +#define NIS_DEV_READY 0x00000040 +#define NIS_PGM_ERASE_ERROR 0x00000001 + + uint32 NandEccCorrExtAddr; /* ECC Correctable Error Extended Address*/ + uint32 NandEccCorrAddr; /* ECC Correctable Error Address */ + uint32 NandEccUncExtAddr; /* ECC Uncorrectable Error Extended Addr */ + uint32 NandEccUncAddr; /* ECC Uncorrectable Error Address */ + uint32 NandFlashReadExtAddr; /* Flash Read Data Extended Address */ + uint32 NandFlashReadAddr; /* Flash Read Data Address */ + uint32 NandProgramPageExtAddr; /* Page Program Extended Address */ + uint32 NandProgramPageAddr; /* Page Program Address */ + uint32 NandCopyBackExtAddr; /* Copy Back Extended Address */ + uint32 NandCopyBackAddr; /* Copy Back Address */ + uint32 NandBlockEraseExtAddr; /* Block Erase Extended Address */ + uint32 NandBlockEraseAddr; /* Block Erase Address */ + uint32 NandInvReadExtAddr; /* Flash Invalid Data Extended Address */ + uint32 NandInvReadAddr; /* Flash Invalid Data Address */ + uint32 NandBlkWrProtect; /* Block Write Protect Enable and Size */ + /* for EBI_CS0b */ +} NandCtrlRegs; + +#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE) + +#define NAND_CACHE ((volatile uint8 * const) NAND_CACHE_BASE) + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/shared/broadcom/include/bcm963xx/mocablock.h b/shared/broadcom/include/bcm963xx/mocablock.h new file mode 100755 index 0000000..bccb24b --- /dev/null +++ b/shared/broadcom/include/bcm963xx/mocablock.h @@ -0,0 +1,144 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 5300 California Avenue + Irvine, California 92617 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/*************************************************************************** + * File Name : MoCABlock.h + * + * Description: This file contains definitions for the MoCA Block for the + * BCM6816 and the BCM3450 chipset(s). + ***************************************************************************/ + +#if !defined(_MoCABLOCK_H_) +#define _MoCABLOCK_H_ + +/* BCM 96816 related definitions . */ +#define MoCA_INTERRUPT_DISABLE 0x0 +#define MoCA_INTERRUPT_ENABLE 0x1 + +/* Definitions for coreInterrupts from host */ +#define MoCA_HOST_RESP_TO_CORE 0x1 +#define MoCA_HOST_REQ_TO_CORE 0x2 + +/* Definitions for hostInterrupts from core */ +#define MoCA_CORE_RESP_TO_HOST 0x1 +#define MoCA_CORE_REQ_TO_HOST 0x2 +#define MoCA_CORE_ASSERT_TO_HOST 0x4 +#define MoCA_CORE_UNUSED 0xFC +#define MoCA_CORE_DDR_START 0x100 +#define MoCA_CORE_DDR_END 0x200 + +#define MoCA_LED_LINK_ON_ACTIVE_OFF 0x0 +#define MoCA_LED_LINK_OFF_ACTIVE_OFF 0x1 +#define MoCA_LED_LINK_ON_ACTIVE_ON 0x2 +#define MoCA_LED_LINK_OFF_ACTIVE_ON 0x3 /* NW Search and New Node Admission */ +typedef struct _MoCAExtras { + UINT32 host2MoCAIntEn ; + UINT32 host2MoCAIntTrig ; + UINT32 host2MoCAIntStatus ; + UINT32 MoCA2HostIntEn ; + UINT32 MoCA2HostIntTrig ; + UINT32 MoCA2HostIntStatus ; + UINT32 genPurpose0 ; + UINT32 genPurpose1 ; + UINT32 sideBandGmiiFC ; + UINT32 leds ; + UINT32 MoCAStatus ; + UINT32 testMuxSel ; + UINT32 mdCtrl ; + UINT32 mdcDivider ; + UINT32 outRefIntR01 ; + UINT32 outRefIntR02 ; + UINT32 outRefIntR03 ; + UINT32 outRefIntR04 ; + UINT32 outRefIntR05 ; + UINT32 outRefIntSel ; +} MoCAExtras ; + + +typedef struct _MoCAMACRegs { + UINT32 macCtrl ; // 0x00 +#define MoCA_MAC_REGS_MAC_CTRL_MAC_ENABLE 0x00000001 + UINT32 resv1 [7] ; + UINT32 frmHdr ; // 0x20 + UINT32 msduHdr ; // 0x24 + UINT32 resv2 [2] ; + UINT32 macStatus ; // 0x30 + UINT32 macStatusEn ; // 0x34 + UINT32 resv3 [2] ; + UINT32 netTimer ; // 0x40 + UINT32 maxNetTimerCorr ; // 0x44 + UINT32 timerCorrCtrl ; // 0x48 + UINT32 bitParams ; // 0x4c + UINT32 fineCorr ; // 0x50 + UINT32 coarseCorr ; // 0x54 + UINT32 loadTimer1 ; // 0x58 + UINT32 loadTimer2 ; // 0x5c + UINT32 mpiConfigCtrl ; // 0x60 +#define MoCA_MAC_REGS_MPI_CONFIG_CTRL_READ 0x00000001 +#define MoCA_MAC_REGS_MPI_CONFIG_CTRL_WRITE 0x00000002 + UINT32 mpiConfigAddr ; // 0x64 + UINT32 mpiConfigDataW ; // 0x68 + UINT32 mpiConfigDataR ; // 0x6c +} MoCA_MAC_REGST, *PMoCA_MAC_REGST ; + +#define MoCA_BLOCK_BASE MOCA_MEM_BASE +typedef struct MoCABlockT { + + UINT8 dataMem [0x3FFFC] ; + UINT8 resvd [0x61403] ; + MoCAExtras extras ; // 0xb0da1400. + //MoCAHostM2M follows. + //MoCAMoCAM2M follows. +} MoCA_BLOCKT, *PMoCA_BLOCKT ; + +#define MoCA_PHYS_IO_BASE NONCACHE_TO_PHYS(MOCA_IO_BASE) +#define MoCA_BLOCK_MAC_REGS_START (MOCA_IO_BASE+0x400) +#define MoCA_BLOCK_PHY_START MoCA_PHYS_IO_BASE+0x8000 +#define MoCA_BLOCK_PHY_END MoCA_PHYS_IO_BASE+0xA3FF +#define MoCA_BLOCK ((volatile PMoCA_BLOCKT const) MoCA_BLOCK_BASE) +#define MoCA_MAC_REGS ((volatile PMoCA_MAC_REGST const) MoCA_BLOCK_MAC_REGS_START) +#define MoCA_CORE_MEM_BASE MoCA_BLOCK->dataMem +#define MoCA_MAIL_BOX_ADDR_REG MoCA_BLOCK->extras.genPurpose0 +#define MoCA_IQ_SNR_ADDR_REG MoCA_BLOCK->extras.genPurpose1 + +/* BCM 93450 related definitions . */ + +#define BCM3450_I2C_CHIP_ADDRESS 0x70 +typedef struct _Bcm3450Reg { + UINT32 ChipId; /* 0x0 */ + UINT32 ChipRev; /* 0x4 */ + UINT32 Test; /* 0x8 */ + UINT32 SerialCtl; /* 0xc */ + UINT32 StatusRead; /* 0x10 */ + UINT32 LnaCntl; /* 0x14 */ + UINT32 PaCntl; /* 0x18 */ +#define BCM3450_PACNTL_PA_RDEG_SHIFT 11 +#define BCM3450_PACNTL_PA_RDEG_MASK 0x00007800 +#define BCM3450_PACNTL_PA_CURR_CONT_SHIFT 5 +#define BCM3450_PACNTL_PA_CURR_CONT_MASK 0x000007E0 +#define BCM3450_PACNTL_PA_CURR_FOLLOWER_SHIFT 2 +#define BCM3450_PACNTL_PA_CURR_FOLLOWER_MASK 0x0000001C +#define BCM3450_PACNTL_PA_PWRDWN_SHIFT 0 +#define BCM3450_PACNTL_PA_PWRDWN_MASK 0x00000001 +#define BCM3450_PACNTL_OFFSET 0x18 + UINT32 Misc; /* 0x1c */ +#define BCM3452_MISC_BG_PWRDWN_SHIFT 15 +#define BCM3452_MISC_BG_PWRDWN_MASK 0x00008000 +#define BCM3450_MISC_IIC_RESET 0x1 +#define BCM3450_MISC_SERIAL_RESET 0x2 +#define BCM3450_MISC_OFFSET 0x1c +} Bcm3450Reg ; + +#endif /* _MoCABLOCK_H_ */ diff --git a/shared/broadcom/include/bcm963xx/robosw_reg.h b/shared/broadcom/include/bcm963xx/robosw_reg.h new file mode 100755 index 0000000..4fcc0ac --- /dev/null +++ b/shared/broadcom/include/bcm963xx/robosw_reg.h @@ -0,0 +1,169 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ + +#ifndef __ROBOSW_REG_H +#define __ROBOSW_REG_H + +void robosw_init(void); +void robosw_configure_ports(void); +void robosw_check_ports(void); + +// These macros make offset validation vs. data sheet easier. + +#define group(type, name, start_offset, next) type name[(next - start_offset) / sizeof(type)] +#define entry(type, name, start_offset, next) type name + +typedef struct RoboSwitch { + group(byte, PortCtrl, 0x0000, 0x0009); + group(byte, Reserved0009, 0x0009, 0x000b); + entry(byte, SwitchMode, 0x000b, 0x000c); + entry(uint16, PauseQuanta, 0x000c, 0x000e); + entry(byte, ImpOverride, 0x000e, 0x000f); + entry(byte, LedRefresh, 0x000f, 0x0010); + entry(uint16, LedFunc0, 0x0010, 0x0012); + entry(uint16, LedFunc1, 0x0012, 0x0014); + entry(uint16, LedFuncMap, 0x0014, 0x0016); + entry(uint16, LedEnableMap, 0x0016, 0x0018); + entry(uint16, LedMap0, 0x0018, 0x001a); + entry(uint16, LedMap1, 0x001a, 0x001c); + group(byte, Reserved001c, 0x001c, 0x0020); + group(byte, Reserved0020, 0x0020, 0x0021); + entry(byte, ForwardCtrl, 0x0021, 0x0022); + group(byte, Reserved0022, 0x0022, 0x0024); + entry(uint16, ProtSelect, 0x0024, 0x0026); + entry(uint16, WanSelect, 0x0026, 0x0028); + entry(uint32, PauseCap, 0x0028, 0x002c); + group(byte, Reserved002c, 0x002c, 0x002f); + entry(byte, MultiCtrl, 0x002f, 0x0030); + group(byte, Reserved0030, 0x0030, 0x0031); + entry(byte, TxqFlush, 0x0031, 0x0032); + entry(uint16, UniFail, 0x0032, 0x0034); + entry(uint16, MultiFail, 0x0034, 0x0036); + entry(uint16, MlfIpmc, 0x0036, 0x0038); + entry(uint16, PausePassRx, 0x0038, 0x003a); + entry(uint16, PausePassTx, 0x003a, 0x003c); + entry(uint16, DisableLearn, 0x003c, 0x003e); + group(byte, Reserved003e, 0x003e, 0x004a); + entry(uint16, PllTest, 0x004a, 0x004c); + group(byte, Reserved004c, 0x004c, 0x0058); + group(byte, PortOverride, 0x0058, 0x0060); + group(byte, Reserved0061, 0x0060, 0x0064); + entry(byte, ImpRgmiiCtrlP4, 0x0064, 0x0065); + entry(byte, ImpRgmiiCtrlP5, 0x0065, 0x0066); + group(byte, Reserved0066, 0x0066, 0x006c); + entry(byte, ImpRgmiiTimingDelayP4, 0x006c, 0x006d); + entry(byte, ImpRgmiiTimingDelayP5, 0x006d, 0x006e); + group(byte, Reserved006e, 0x006e, 0x0079); + entry(byte, SWResetCtrl, 0x0079, 0x007a); + group(byte, Reserved007a, 0x007a, 0x0090); + entry(uint32, Rxfilt_Ctl, 0x0090, 0x0094); + entry(uint32, Cmf_En_Ctl, 0x0094, 0x0098); + group(byte, Reserved0098, 0x0098, 0x00a0); + entry(uint32, SwpktCtrl0, 0x00a0, 0x00a4); + entry(uint32, SwpktCtrl1, 0x00a4, 0x00a8); + group(byte, Reserved00a8, 0x00a8, 0x00b0); + entry(uint32, MdioCtrl, 0x00b0, 0x00b4); + entry(uint16, MdioData, 0x00b4, 0x00b6); + group(byte, Reserved00b4, 0x00b6, 0x0200); + entry(byte, GlbMgmt, 0x0200, 0x0201); + entry(byte, ChpBoxID, 0x0201, 0x0202); + entry(byte, MngPID, 0x0202, 0x0203); + group(byte, Reserved0203, 0x0203, 0x1100); + entry(uint16, MIICtrl0, 0x1100, 0x1101); + +} RoboSwitch; + +#define SWITCH ((volatile RoboSwitch * const)SWITCH_BASE) +#define PBVLAN_OFFSET 0x3100 +#define PBMAP_MIPS 0x100 +#define SWITCH_PBVLAN ((volatile uint16 * const)(SWITCH_BASE + PBVLAN_OFFSET)) + +#define PortCtrl_Forwarding 0xa0 +#define PortCtrl_Learning 0x80 +#define PortCtrl_Listening 0x60 +#define PortCtrl_Blocking 0x40 +#define PortCtrl_Disable 0x20 +#define PortCtrl_RxUcstEn 0x10 +#define PortCtrl_RxMcstEn 0x08 +#define PortCtrl_RxBcstEn 0x04 +#define PortCtrl_DisableTx 0x02 +#define PortCtrl_DisableRx 0x01 + +#define SwitchMode_FwdgEn 0x02 +#define SwitchMode_ManageMode 0x01 + +#define ImpOverride_Force 0x80 +#define ImpOverride_TxFlow 0x20 +#define ImpOverrode_RxFlow 0x10 +#define ImpOverride_1000Mbs 0x08 +#define ImpOverride_100Mbs 0x04 +#define ImpOverride_10Mbs 0x00 +#define ImpOverride_Fdx 0x02 +#define ImpOverride_Linkup 0x01 + +#define PortOverride_Enable 0x40 +#define PortOverride_TxFlow 0x20 +#define PortOverride_RxFlow 0x10 +#define PortOverride_1000Mbs 0x08 +#define PortOverride_100Mbs 0x04 +#define PortOverride_10Mbs 0x00 +#define PortOverride_Fdx 0x02 +#define PortOverride_Linkup 0x01 + +#define GlbMgmt_EnableImp 0x80 +#define GlbMgmt_IgmpSnooping 0x08 +#define GlbMgmt_ReceiveBpdu 0x02 +#define GlbMgmt_ResetMib 0x01 + +#define MdioCtrl_Write (1 << 31) +#define MdioCtrl_Read (1 << 30) +#define MdioCtrl_Ext (1 << 16) +#define MdioCtrl_ID_Shift 25 +#define MdioCtrl_ID_Mask (0x1f << MdioCtrl_ID_Shift) +#define MdioCtrl_Addr_Shift 20 +#define MdioCtrl_Addr_Mask (0x1f << MdioCtrl_Addr_Shift) + +#define ImpRgmiiCtrl_GMII_En 0x80 +#define ImpRgmiiCtrl_DLL_IQQD 0x04 +#define ImpRgmiiCtrl_DLL_RXC_Bypass 0x02 +#define ImpRgmiiCtrl_Timing_Sel 0x01 + +#define ImpRgmiiTimingDelayDefault 0xF9 + +#if defined (_BCM96328_) +#define EPHY_PORTS 5 +#define PORT_6_PORT_ID 6 +#define PORT_7_PORT_ID 7 +#endif +#if defined (_BCM96362_) +#define EPHY_PORTS 6 +#define PORT_6_PORT_ID 6 +#define PORT_7_PORT_ID 7 +#endif +#if defined (_BCM96368_) +#define EPHY_PORTS 6 +#define USB_PORT_ID 6 +#define SAR_PORT_ID 7 +#endif +#if defined (_BCM96816_) +#define EPHY_PORTS 4 +#define SERDES_PORT_ID 4 +#define MOCA_PORT_ID 5 +#define USB_PORT_ID 6 +#define GPON_PORT_ID 7 +#endif + +#endif diff --git a/shared/broadcom/include/bcm963xx/xtmprocregs.h b/shared/broadcom/include/bcm963xx/xtmprocregs.h new file mode 100755 index 0000000..307ed79 --- /dev/null +++ b/shared/broadcom/include/bcm963xx/xtmprocregs.h @@ -0,0 +1,602 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 5300 California Avenue + Irvine, California 92617 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/*************************************************************************** + * File Name : XtmProcRegs.h + * + * Description: This file contains definitions for the ATM/PTM processor + * registers. + ***************************************************************************/ + +#if !defined(_XTMPROCREGS_H_) +#define _XTMPROCREGS_H_ + +/* Miscellaneous values. */ +#define XP_MAX_PORTS 4 +#define XP_MAX_CONNS 16 +#define XP_MAX_RX_QUEUES 4 +#define XP_MAX_TX_HDRS 8 +#define XP_TX_HDR_WORDS (16 / sizeof(UINT32)) +#define XP_RX_MIB_MATCH_ENTRIES 128 + +/* Circuit types. */ +#define XCT_TRANSPARENT 0x00000001 +#define XCT_AAL0_PKT 0x00000002 +#define XCT_AAL0_CELL 0x00000003 +#define XCT_OAM_F5_SEG 0x00000004 +#define XCT_OAM_F5_E2E 0x00000005 +#define XCT_RM 0x00000006 +#define XCT_AAL5 0x00000007 +#define XCT_ASM_P0 0x00000008 +#define XCT_ASM_P1 0x00000009 +#define XCT_ASM_P2 0x0000000a +#define XCT_ASM_P3 0x0000000b +#define XCT_OAM_F4_SEG 0x0000000c +#define XCT_OAM_F4_E2E 0x0000000d +#define XCT_TEQ 0x0000000e +#define XCT_PTM 0x0000000f + +/* Definitions for ATM ulTxChannelCfg. */ +#define TXCHA_VCID_MASK 0x0000000f +#define TXCHA_VCID_SHIFT 0 +#define TXCHA_CT_MASK 0x000000f0 +#define TXCHA_CT_SHIFT 4 +#define TXCHA_CT_TRANSPARENT (XCT_TRANSPARENT << TXCHA_CT_SHIFT) +#define TXCHA_CT_AAL0_PKT (XCT_AAL0_PKT << TXCHA_CT_SHIFT) +#define TXCHA_CT_AAL0_CELL (XCT_AAL0_CELL << TXCHA_CT_SHIFT) +#define TXCHA_CT_OAM_F5_SEG (XCT_OAM_F5_SEG << TXCHA_CT_SHIFT) +#define TXCHA_CT_OAM_F5_E2E (XCT_OAM_F5_E2E << TXCHA_CT_SHIFT) +#define TXCHA_CT_RM (XCT_RM << TXCHA_CT_SHIFT) +#define TXCHA_CT_AAL5 (XCT_AAL5 << TXCHA_CT_SHIFT) +#define TXCHA_CT_ASM_P0 (XCT_ASM_P0 << TXCHA_CT_SHIFT) +#define TXCHA_CT_ASM_P1 (XCT_ASM_P1 << TXCHA_CT_SHIFT) +#define TXCHA_CT_ASM_P2 (XCT_ASM_P2 << TXCHA_CT_SHIFT) +#define TXCHA_CT_ASM_P3 (XCT_ASM_P3 << TXCHA_CT_SHIFT) +#define TXCHA_CT_OAM_F4_SEG (XCT_OAM_F4_SEG << TXCHA_CT_SHIFT) +#define TXCHA_CT_OAM_F4_E2E (XCT_OAM_F4_E2E << TXCHA_CT_SHIFT) +#define TXCHA_CT_TEQ (XCT_TEQ << TXCHA_CT_SHIFT) +#define TXCHA_CT_PTM (XCT_PTM << TXCHA_CT_SHIFT) +#define TXCHA_CI 0x00000100 +#define TXCHA_CLP 0x00000200 +#define TXCHA_USE_ALT_GFC 0x00000400 +#define TXCHA_ALT_GFC_MASK 0x00007800 +#define TXCHA_ALT_GFC_SHIFT 11 +#define TXCHA_HDR_EN 0x00008000 +#define TXCHA_HDR_IDX_MASK 0x00070000 +#define TXCHA_HDR_IDX_SHIFT 16 +#define TXCHA_FCS_STRIP 0x00080000 + +/* Definitions for PTM ulTxChannelCfg. */ +#define TXCHP_FCS_EN 0x00000001 +#define TXCHP_CRC_EN 0x00000002 +#define TXCHP_HDR_EN 0x00008000 +#define TXCHP_HDR_IDX_MASK 0x00070000 +#define TXCHP_HDR_IDX_SHIFT 16 + +/* Definitions for ulSwitchPktCfg. */ +#define SWP_MAX_PKT_COUNT_MASK 0x00000003 +#define SWP_MAX_PKT_COUNT_SHIFT 0 +#define SWP_MAX_PKT_SIZE_MASK 0x0000007c +#define SWP_MAX_PKT_SIZE_SHIFT 2 +#define SWP_SRC_ID_MASK 0x00000380 +#define SWP_SRC_ID_SHIFT 7 +#define SWP_RX_CHAN_MASK 0x00000c00 +#define SWP_RX_CHAN_SHIFT 10 +#define SWP_TX_CHAN_MASK 0x0000f000 +#define SWP_TX_CHAN_SHIFT 12 +#define SWP_TX_EN 0x00010000 +#define SWP_RX_EN 0x00020000 + +/* Definitions for ulSwitchPktTxCtrl. */ +#define SWP_VCID_VALUE_MASK 0x0000000f +#define SWP_VCID_VALUE_SHIFT 0 +#define SWP_CT_VALUE_MASK 0x000000f0 +#define SWP_CT_VALUE_SHIFT 4 +#define SWP_FSTAT_CFG_VALUE_MASK 0x00000700 +#define SWP_FSTAT_CFG_VALUE_SHIFT 8 +#define SWP_MUX_MODE_VALUE 0x00000800 +#define SWP_VCID_MASK_MASK 0x000f0000 +#define SWP_VCID_MASK_SHIFT 16 +#define SWP_CT_MASK_MASK 0x00f00000 +#define SWP_CT_MASK_SHIFT 20 +#define SWP_FSTAT_CFG_MASK_MASK 0x07000000 +#define SWP_FSTAT_CFG_MASK_SHIFT 24 +#define SWP_MUX_MODE_MASK 0x08000000 + +/* Definitions for ulSwitchPktRxCtrl. */ +#define SWP_MATCH_MASK 0x0000007f +#define SWP_MASK_SHIFT 0 +#define SWP_CRC32 0x00000080 +#define SWP_DEST_PORT_MASK 0x0000ff00 +#define SWP_DEST_PORT_SHIFT 8 +#define SWP_MUX_MATCH_MASK 0x007f0000 +#define SWP_MUX_MATCH_SHIFT 16 +#define SWP_MUX_CRC32 0x00800000 +#define SWP_MUX_DESTPORT_MASK 0xff000000 +#define SWP_MUX_DESTPORT_SHIFT 24 + +/* Definitions for ulPktModCtrl. */ +#define PKTM_RXQ_EN_MASK 0x0000000f +#define PKTM_RXQ_EN_SHIFT 0 +#define PKTM_EN 0x80000000 + +/* Definitions for ulIrqStatus and ulIrqMask. */ +#define INTR_RX_BUF_EMPTY 0x00000001 +#define INTR_TX_BUF_EMPTY 0x00000002 +#define INTR_RX_DMA_NO_DESC_MASK 0x0000003c +#define INTR_RX_DMA_NO_DESC_SHIFT 2 +#define INTR_PTM_FRAG_ERROR 0x00000040 +#define INTR_PKT_BUF_UNDERFLOW 0x00000080 +#define INTR_TX_DMA_UNDERFLOW 0x00000100 +#define INTR_TX_ATM_DC 0x00000200 +#define INTR_BOND_BUF_FULL 0x00000400 +#define INTR_RX_ATM_DC 0x00000800 +#define INTR_MULT_MATCH_ERROR 0x00001000 +#define INTR_PKT_BUF_IRQ_MASK 0x0000e000 +#define INTR_PKT_BUF_IRQ_SHIFT 13 + +/* Definitions for ulTxSarCfg. */ +#define TXSAR_MODE_ATM 0x00000000 +#define TXSAR_MODE_PTM 0x00000001 +#define TXSARA_BOND_EN 0x00000002 +#define TXSARA_SID12_EN 0x00000004 +#define TXSARA_CRC10_INIT 0x00000008 +#define TXSARA_CRC10_EN_MASK 0x000000f0 +#define TXSARA_CRC10_EN_SHIFT 4 +#define TXSARA_BOND_DUAL_LATENCY 0x00000100 +#define TXSAR_USE_ALT_FSTAT 0x00000200 +#define TXSARP_ENET_FCS_INSERT 0x00000400 +#define TXSARP_CRC16_EN 0x00000800 +#define TXSARP_SOF_WHILE_TX 0x00001000 +#define TXSARP_PREEMPT 0x00002000 +#define TXSAR_HDR_INS_OFFSET_MASK 0x0007c000 +#define TXSAR_HDR_INS_OFFSET_SHIFT 14 +#define TXSARP_NUM_Z_BYTES_MASK 0x00780000 +#define TXSARP_NUM_Z_BYTES_SHIFT 19 +#define TXSAR_SW_EN 0x00800000 +#define TXSAR_USE_THRESH 0x01000000 +#define TXSAR_PKT_THRESH_MASK 0x06000000 +#define TXSAR_PKT_THRESH_SHIFT 25 +#define TXSARA_BOND_PORT_DIS_MASK 0x78000000 +#define TXSARA_BOND_PORT_DIS_SHIFT 27 +#define TXSARA_ASM_CRC_DIS 0x80000000 + +/* Definitions for ulTxSchedCfg. */ +#define TXSCH_PORT_EN_MASK 0x0000000f +#define TXSCH_PORT_EN_SHIFT 0 +#define TXSCHA_ALT_SHAPER_MODE 0x00000010 +#define TXSCHP_FAST_SCHED 0x00000020 +#define TXSCH_SHAPER_RESET 0x00000040 +#define TXSCH_SIT_COUNT_EN 0x00000080 +#define TXSCH_SIT_COUNT_VALUE_MASK 0x00ffff00 +#define TXSCH_SIT_COUNT_VALUE_SHIFT 8 +#define TXSCH_SIT_MAX_VALUE (TXSCH_SIT_COUNT_VALUE_MASK >> \ + TXSCH_SIT_COUNT_VALUE_SHIFT) +#define TXSCH_SOFWT_PRIORITY_EN 0x01000000 +#define TXSCH_BASE_COUNT_EN 0x02000000 +#define TXSCH_BASE_COUNT_VALUE_MASK 0x3c000000 +#define TXSCH_BASE_COUNT_VALUE_SHIFT 26 +#define TXSCHP_USE_BIT4_SOF 0x40000000 +#define TXSCH_ALT_MCR_MODE 0x80000000 + +/* Definitions for ulTxOamCfg. */ +#define TXOAM_F4_SEG_VPI_MASK 0x000000ff +#define TXOAM_F4_SEG_VPI_SHIFT 0 +#define TXOAM_F4_E2E_VPI_MASK 0x0000ff00 +#define TXOAM_F4_E2E_VPI_SHIFT 8 +#define TXASM_VCI_MASK 0xffff0000 +#define TXASM_VCI_SHIFT 16 + +/* Definitions for ulTxMpAalCfg. */ +#define TXMP_NUM_GROUPS 4 +#define TXMP_GROUP_SIZE 5 +#define TXMP_GROUP_EN 0x00000001 +#define TXMP_GROUP_SHAPER_MASK 0x0000001e +#define TXMP_GROUP_SHAPER_SHIFT 1 +#define TXSOPWT_COUNT_EN 0x00100000 +#define TXSOPWT_COUNT_VALUE_MASK 0x07e00000 +#define TXSOPWT_COUNT_VALUE_SHIFT 21 + +/* Definitions for ulTxUtopiaCfg. */ +#define TXUTO_PORT_EN_MASK 0x0000000f +#define TXUTO_PORT_EN_SHIFT 0 +#define TXUTO_MODE_INT_EXT_MASK 0x00000030 +#define TXUTO_MODE_ALL_INT 0x00000000 +#define TXUTO_MODE_ALL_EXT 0x00000010 +#define TXUTO_MODE_INT_EXT 0x00000020 +#define TXUTO_CELL_FIFO_DEPTH_2 0x00000000 +#define TXUTO_CELL_FIFO_DEPTH_1 0x00000040 +#define TXUTO_NEG_EDGE 0x00000080 +#define TXUTO_LEVEL_1 0x00000100 + +/* Definitions for ulTxLineRateTimer. */ +#define TXLRT_EN 0x00000001 +#define TXLRT_COUNT_VALUE_MASK 0x0001fffe +#define TXLRT_COUNT_VALUE_SHIFT 1 +#define TXLRT_MAX_VALUE (TXLRT_COUNT_VALUE_MASK >> \ + TXLRT_COUNT_VALUE_SHIFT) +#define TXLRT_IDLE_CELL_INS_MASK 0xf0000000 +#define TXLRT_IDLE_CELL_INS_SHIFT 28 + +/* Definitions for ulRxAtmCfg. */ +#define RX_PORT_EN 0x00000001 +#define RX_DOE_MASK 0x000001fe +#define RX_DOE_SHIFT 1 +#define RX_DOE_GFC_ERROR 0x00000002 +#define RX_DOE_CRC_ERROR 0x00000004 +#define RX_DOE_CT_ERROR 0x00000008 +#define RX_DOE_CAM_LOOKUP_ERROR 0x00000010 +#define RX_DOE_IDLE_CELL 0x00000020 +#define RX_DOE_PTI_ERROR 0x00000040 +#define RX_DOE_HEC_ERROR 0x00000080 +#define RX_DOE_PORT_NOT_ENABLED_ERROR 0x00000100 +#define RXA_HEC_CRC_IGNORE 0x00000200 +#define RXA_GFC_ERROR_IGNORE 0x00000400 +#define RX_PORT_MASK 0x00001800 +#define RX_PORT_MASK_SHIFT 11 +#define RXP_RX_FLOW_DISABLED 0x00004000 +#define RXA_VCI_MASK 0x00008000 +#define RXA_VC_BIT_MASK 0xffff0000 +#define RXA_BONDING_VP_MASK 0x00ff0000 + +/* Definitions for ulRxSarCfg. */ +#define RXSAR_MODE_ATM 0x00000000 +#define RXSAR_MODE_PTM 0x00000001 +#define RXSAR_MODE_MASK 0x00000001 +#define RXSARA_BOND_EN 0x00000002 +#define RXSARA_SID12_EN 0x00000004 +#define RXSARA_CRC10_INIT 0x00000008 +#define RXSARA_CRC10_EN_MASK 0x000000f0 +#define RXSARA_CRC10_EN_SHIFT 4 +#define RXSARA_BOND_DUAL_LATENCY 0x00000100 +#define RXSARA_BOND_CELL_COUNT_MASK 0x07ff0000 +#define RXSARA_BOND_CELL_COUNT_SHIFT 16 +#define RXSARA_BOND_TIMER_MODE 0x08000000 +#define RXSARA_BOND_BUF_MODE_MASK 0x70000000 +#define RXSARA_BOND_BUF_MODE_SHIFT 29 +#define RXSARA_BOND_BUF_MODE_MASK 0x70000000 +#define RXSARA_ASM_CRC_DIS 0x80000000 + +/* Definitions for ulRxOamCfg. */ +#define RXOAM_F4_SEG_VPI_MASK 0x000000ff +#define RXOAM_F4_SEG_VPI_SHIFT 0 +#define RXOAM_F4_E2E_VPI_MASK 0x0000ff00 +#define RXOAM_F4_E2E_VPI_SHIFT 8 +#define RXASM_VCI_MASK 0xffff0000 +#define RXASM_VCI_SHIFT 16 + +/* Definitions for ulRxUtopiaCfg. */ +#define RXUTO_PORT_EN_MASK 0x0000000f +#define RXUTO_PORT_EN_SHIFT 0 +#define RXUTO_TEQ_PORT_MASK 0x00000070 +#define RXUTO_TEQ_PORT_SHIFT 4 +#define RXUTO_NEG_EDGE 0x00000080 +#define RXUTO_LEVEL_1 0x00000100 +#define RXUTO_INTERNAL_BUF0_EN 0x00000200 +#define RXUTO_EXTERNAL_BUF1_EN 0x00000400 + +/* Definitions for ulRxAalCfg. */ +#define RXAALA_AAL5_SW_TRAILER_EN 0x00000001 +#define RXAALA_AAL0_CRC_CHECK 0x00000002 +#define RXAALP_CRC32_EN 0x00000004 +#define RXAALP_CELL_LENGTH_MASK 0x000000f0 +#define RXAALP_CELL_LENGTH_SHIFT 4 + +/* Definitions for ulLedCtrl. */ +#define SAR_LED_EN 0x00000001 +#define SAR_LED_MODE_MASK 0x00000006 +#define SAR_LED_MODE_SHIFT 1 +#define SAR_LED_MODE_LINK_ONLY 0x00000000 +#define SAR_LED_MODE_CELL_ACTIVITY 0x00000002 +#define SAR_LED_MODE_MELODY_LINK 0x00000004 +#define SAR_LED_MODE_LINK_CELL_ACTIVITY 0x00000006 +#define SAR_LED_LINK 0x00000010 +#define SAR_LED_SPEED_MASK 0x00000060 +#define SAR_LED_SPEED_SHIFT 5 +#define SAR_LED_SPEED_30MS 0x00000000 +#define SAR_LED_SPEED_50MS 0x00000020 +#define SAR_LED_SPEED_125MS 0x00000040 +#define SAR_LED_SPEED_250MS 0x00000060 +#define SAR_LED_INTERNAL 0x00000080 + +/* Definitions for ulTxVpiVciTable. */ +#define TXTBL_VCI_MASK 0x0000ffff +#define TXTBL_VCI_SHIFT 0 +#define TXTBL_VPI_MASK 0x00ff0000 +#define TXTBL_VPI_SHIFT 16 + +/* Definitions for ulRxVpiVciCam - CAM side. */ +#define RXCAM_PORT_MASK 0x00000003 +#define RXCAM_PORT_SHIFT 0 +#define RXCAMP_PTM_PRI_LOW 0x00000000 +#define RXCAMP_PTM_PRI_HIGH 0x00000004 +#define RXCAM_TEQ_CELL 0x00000008 +#define RXCAMA_VCI_MASK 0x000ffff0 +#define RXCAMA_VCI_SHIFT 4 +#define RXCAMA_VPI_MASK 0x0ff00000 +#define RXCAMA_VPI_SHIFT 20 +#define RXCAM_VALID 0x10000000 + +/* Definitions for ulRxVpiVciCam - RAM side. */ +#define RXCAM_CT_MASK 0x0000000f +#define RXCAM_CT_SHIFT 0 +#define RXCAM_CT_TRANSPARENT (XCT_TRANSPARENT << RXCAM_CT_SHIFT) +#define RXCAM_CT_AAL0_PKT (XCT_AAL0_PKT << RXCAM_CT_SHIFT) +#define RXCAM_CT_AAL0_CELL (XCT_AAL0_CELL << RXCAM_CT_SHIFT) +#define RXCAM_CT_AAL5 (XCT_AAL5 << RXCAM_CT_SHIFT) +#define RXCAM_CT_TEQ (XCT_TEQ << RXCAM_CT_SHIFT) +#define RXCAM_CT_PTM (XCT_PTM << RXCAM_CT_SHIFT) +#define RXCAM_VCID_MASK 0x000001f0 +#define RXCAM_VCID_SHIFT 4 +#define RXCAM_STRIP_BYTE_MASK 0x00003e00 +#define RXCAM_STRIP_BYTE_SHIFT 9 +#define RXCAM_STRIP_EN 0x00004000 +#define RXCAMA_ASM_CELL 0x00080000 +#define RXCAMA_CRC10_EN 0x00100000 + +/* Definitions for ulSstCtrl. */ +#define SST_EN 0x00000001 +#define SST_MP_GROUP_MASK 0x00000006 +#define SST_MP_GROUP_SHIFT 1 +#define SST_PTM_PREEMPT 0x00000010 +#define SST_PORT_MASK 0x00000060 +#define SST_PORT_SHIFT 5 +#define SST_ALG_MASK 0x00000380 +#define SST_ALG_SHIFT 7 +#define SST_ALG_UBR_NO_PCR 0x00000000 +#define SST_ALG_UBR_PCR 0x00000080 +#define SST_ALG_MBR 0x00000100 +#define SST_ALG_VBR_1 0x00000180 +#define SST_ALG_CBR 0x00000200 +#define SST_SUB_PRIORITY_MASK 0x00001c00 +#define SST_SUB_PRIORITY_SHIFT 10 +#define SST_SUPER_PRIORITY 0x00002000 +#define SST_MP_EN 0x00004000 +#define SST_MCR_EN 0x00008000 +#define SST_RATE_MCR_MASK 0xffff0000 +#define SST_RATE_MCR_SHIFT 16 + +/* Definitions for ulSstPcrScr. */ +#define SST_RATE_PCR_MASK 0x0000ffff +#define SST_RATE_PCR_SHIFT 0 +#define SST_RATE_SCR_MASK 0xffff0000 +#define SST_RATE_SCR_SHIFT 16 + +/* Definitions for ulSstBt. */ +#define SST_RATE_BT_MASK 0x00ffffff +#define SST_RATE_BT_SHIFT 0 +#define SST_ALG_WEIGHT_MASK 0x03000000 +#define SST_ALG_WEIGHT_SHIFT 24 +#define SST_ALG_DISABLED 0x00000000 +#define SST_ALG_CWRR 0x01000000 +#define SST_ALG_PWRR 0x02000000 +#define SST_ALG_WFQ 0x03000000 +#define SST_WEIGHT_VALUE_MASK 0xfc000000 +#define SST_WEIGHT_VALUE_SHIFT 26 + +/* Definitions for ulSstBucketCnt. */ +#define SST_BP_PCR_MASK 0x0000ffff +#define SST_BP_PCR_SHIFT 0 +#define SST_BM_MCR_MASK 0xffff0000 +#define SST_BM_MCR_SHIFT 16 + +/* Definitions for ulRxPktBufCfg. */ +#define PBCFG_LENGTH_MASK 0x0000ffff +#define PBCFG_LENGTH_SHIFT 0 +#define PBCFG_FPM_EMPTY 0x02000000 +#define PBCFG_LD_PTRS 0x04000000 +#define PBCFG_ALLOCATE_LAST 0x08000000 +#define PBCFG_KEEP_ERROR_PKTS 0x10000000 +#define PBCFG_FPM_ENABLE 0x20000000 +#define PBCFG_INIT_REQ 0x40000000 +#define PBCFG_S_RESET 0x80000000 + +/* Definitions for ulRxPktBufThreshold. */ +#define PBTHRESH_MAX_COUNT_MASK 0x000000ff +#define PBTHRESH_MAX_COUNT_SHIFT 0 +#define PBTHRESH_NO_BUF_DELAY_MASK 0xffff0000 +#define PBTHRESH_NO_BUF_DELAY_SHIFT 16 + +/* Definitions for ulRxPktBufVcid. */ +#define PBVCID_WAIT_EN_MASK 0x0000ffff +#define PBVCID_WAIT_EN_SHIFT 0 + +/* Definitions for ulRxPktBufMem. */ +#define PBMEM_ADDR_MASK 0x0000ffff +#define PBMEM_ADDR_SHIFT 0 +#define PBMEM_BS_B_MASK 0x00ff0000 +#define PBMEM_BS_B_SHIFT 16 +#define PBMEM_READ_WRITE_B 0x40000000 +#define PBMEM_GO_BUSY 0x80000000 + +/* Definitions for ulRxPktBufPtr. */ +#define PBPTR_BUF_STOP_MASK 0x0000ffff +#define PBPTR_BUF_STOP_SHIFT 0 +#define PBPTR_BUF_START_MASK 0xffff0000 +#define PBPTR_BUF_START_SHIFT 16 + +/* Definitions for ulRxPktBufSize. */ +#define PBSIZE_THRESHOLD_MASK 0x0000ffff +#define PBSIZE_THRESHOLD_SHIFT 0 +#define PBSIZE_MASK 0xffff0000 +#define PBSIZE_SHIFT 16 + +/* Definitions for ulRxPktBufFifoStart[2]. */ +#define PBSTART_0_MASK 0x0000ffff +#define PBSTART_0_SHIFT 0 +#define PBSTART_1_MASK 0xffff0000 +#define PBSTART_1_SHIFT 16 + +/* Definitions for ulRxPktBufFifoStop[2]. */ +#define PBSTOP_0_MASK 0x0000ffff +#define PBSTOP_0_SHIFT 0 +#define PBSTOP_1_MASK 0xffff0000 +#define PBSTOP_1_SHIFT 16 + +/* Definitions for ulRxPktBufFifoDelay[2]. */ +#define PBDELAY_0_MASK 0x0000ffff +#define PBDELAY_0_SHIFT 0 +#define PBDELAY_1_MASK 0xffff0000 +#define PBDELAY_1_SHIFT 16 + +/* Definitions for ulRxPktBufQueueStatus. */ +#define PBQS_NUM_NO_BUFS_MASK 0x0000ffff +#define PBQS_NUM_NO_BUFS_SHIFT 0 +#define PBQS_NUM_QUEUE_FULL_MASK 0xffff0000 +#define PBQS_NUM_QUEUE_FULL_SHIFT 16 + +/* Definitions for ulRxPktBufErrorStatus. */ +#define PBERR_NUM_ERROR_FRAGS_MASK 0x0000ffff +#define PBERR_NUM_ERROR_FRAGS_SHIFT 0 +#define PBERR_NUM_ERROR_PKTS_MASK 0xffff0000 +#define PBERR_NUM_ERROR_PKTS_SHIFT 16 + +/* Definitions for ulRxPktBufTR. */ +#define PBTR_LD_T_PTR_MASK 0x0000ffff +#define PBTR_LD_T_PTR_SHIFT 0 +#define PBTR_LD_H_PTR_MASK 0xffff0000 +#define PBTR_LD_H_PTR_SHIFT 16 + +/* Definitions for ulRxPktBufFPM. */ +#define PBFPM_FRAME_BUF_MASK 0x0000ffff +#define PBFPM_FRAME_BUF_SHIFT 0 +#define PBFPM_LOAD_COUNT_MASK 0xffff0000 +#define PBFPM_LOAD_COUNT_SHIFT 16 + +/* Definitions for ulRxPktBufMibCtrl. */ +#define PBMIB_TOGGLE 0x40000000 +#define PBMIB_CLEAR 0x80000000 + +/* Definitions for ulRxPktBufMibMatch. */ +#define PBMIB_MATCH_MASK 0x0000007f + +/* Definitions for ulTxHdrInsert. */ +#define TXHDR_COUNT_MASK 0x0000001f +#define TXHDR_COUNT_SHIFT 0 +#define TXHDR_OFFSET_MASK 0x00ff0000 +#define TXHDR_OFFSET_SHIFT 16 + +/* Definitions for ulTxRxPortOamCellCnt. */ +#define OAM_TX_CELL_COUNT_MASK 0x0000ffff +#define OAM_TX_CELL_COUNT_SHIFT 0 +#define OAM_RX_CELL_COUNT_MASK 0xffff0000 +#define OAM_RX_CELL_COUNT_SHIFT 16 + +/* Definitions for ulTxRxPortAsmCellCnt. */ +#define ASM_TX_CELL_COUNT_MASK 0x0000ffff +#define ASM_TX_CELL_COUNT_SHIFT 0 +#define ASM_RX_CELL_COUNT_MASK 0xffff0000 +#define ASM_RX_CELL_COUNT_SHIFT 16 + +/* Definitions for ulRxPortErrorPktCellCnt. */ +#define ERROR_RX_CELL_COUNT_MASK 0x0000ffff +#define ERROR_RX_CELL_COUNT_SHIFT 0 +#define ERROR_RX_PKT_COUNT_MASK 0xffff0000 +#define ERROR_RX_PKT_COUNT_SHIFT 16 + + +#if defined(CONFIG_BCM96368) +#define XTM_PROCESSOR_BASE 0xb0001800 +#elif defined(CONFIG_BCM96328) || defined(CONFIG_BCM96362) +#define XTM_PROCESSOR_BASE 0xb0007800 +#endif +typedef struct XtmProcessorRegisters +{ + UINT32 ulTxChannelCfg[XP_MAX_CONNS]; /* 0000 */ + UINT32 ulSwitchPktCfg; /* 0040 */ + UINT32 ulSwitchPktTxCtrl; /* 0044 */ + UINT32 ulSwitchPktRxCtrl; /* 0048 */ + UINT32 ulPktModCtrl; /* 004c */ + UINT32 ulIrqStatus; /* 0050 */ + UINT32 ulIrqMask; /* 0054 */ + UINT32 ulReserved1[2]; /* 0058 */ + UINT32 ulTxSarCfg; /* 0060 */ + UINT32 ulTxSchedCfg; /* 0064 */ + UINT32 ulTxOamCfg; /* 0068 */ + UINT32 ulTxAtmStatus; /* 006c */ + UINT32 ulTxAalStatus; /* 0070 */ + UINT32 ulTxMpAalCfg; /* 0074 */ + UINT32 ulTxUtopiaCfg; /* 0078 */ + UINT32 ulTxLineRateTimer; /* 007c */ + UINT32 ulRxAtmCfg[XP_MAX_PORTS]; /* 0080 */ + UINT32 ulRxSarCfg; /* 0090 */ + UINT32 ulRxOamCfg; /* 0094 */ + UINT32 ulRxAtmStatus; /* 0098 */ + UINT32 ulRxUtopiaCfg; /* 009c */ + UINT32 ulRxAalCfg; /* 00a0 */ + UINT32 ulRxAalMaxSdu; /* 00a4 */ + UINT32 ulRxAalStatus; /* 00a8 */ + UINT32 ulLedCtrl; /* 00ac */ + UINT32 ulReserved2[20]; /* 00b0 */ + UINT32 ulTxVpiVciTable[XP_MAX_CONNS]; /* 0100 */ + UINT32 ulRxVpiVciCam[XP_MAX_CONNS * 2]; /* 0140 */ + UINT32 ulReserved3[16]; /* 01c0 */ + UINT32 ulSstCtrl[XP_MAX_CONNS]; /* 0200 */ + UINT32 ulSstPcrScr[XP_MAX_CONNS]; /* 0240 */ + UINT32 ulSstBt[XP_MAX_CONNS]; /* 0280 */ + UINT32 ulSstBucketCnt[XP_MAX_CONNS]; /* 02c0 */ + UINT32 ulRxPktBufCfg; /* 0300 */ + UINT32 ulRxPktBufThreshold; /* 0304 */ + UINT32 ulRxPktBufVcid; /* 0308 */ + UINT32 ulRxPktBufMem; /* 030c */ + UINT32 ulRxPktBufData[2]; /* 0310 */ + UINT32 ulRxPktBufPtr; /* 0318 */ + UINT32 ulRxPktBufSize; /* 031c */ + UINT32 ulRxPktBufFifoStart[2]; /* 0320 */ + UINT32 ulRxPktBufFifoStop[2]; /* 0328 */ + UINT32 ulRxPktBufFifoDelay[2]; /* 0330 */ + UINT32 ulRxPktBufQueueStatus; /* 0338 */ + UINT32 ulRxPktBufErrorStatus; /* 033c */ + UINT32 ulRxPktBufTR; /* 0340 */ + UINT32 ulRxPktBufFPM; /* 0344 */ + UINT32 ulRxPktBufMibCtrl; /* 0348 */ + UINT32 ulRxPktBufMibMatch; /* 034c */ + UINT32 ulRxPktBufMibRxOctet; /* 0350 */ + UINT32 ulRxPktBufMibRxPkt; /* 0354 */ + UINT32 ulReserved4[106]; /* 0358 */ + UINT32 ulTxHdrInsert[XP_MAX_TX_HDRS]; /* 0500 */ + UINT32 ulReserved5[24]; /* 0520 */ + UINT32 ulTxHdrValues[XP_MAX_TX_HDRS][XP_TX_HDR_WORDS]; /* 0580 */ + UINT32 ulTxPortPktOctCnt[XP_MAX_PORTS]; /* 0600 */ + UINT32 ulRxPortPktOctCnt[XP_MAX_PORTS]; /* 0610 */ + UINT32 ulTxPortPktCnt[XP_MAX_PORTS]; /* 0620 */ + UINT32 ulRxPortPktCnt[XP_MAX_PORTS]; /* 0630 */ + UINT32 ulTxRxPortOamCellCnt[XP_MAX_PORTS]; /* 0640 */ + UINT32 ulTxRxPortAsmCellCnt[XP_MAX_PORTS]; /* 0650 */ + UINT32 ulRxPortErrorPktCellCnt[XP_MAX_PORTS]; /* 0660 */ + UINT32 ulBondInputCellCnt; /* 0670 */ + UINT32 ulBondOutputCellCnt; /* 0674 */ + UINT32 ulReserved6[1]; /* 0678 */ + UINT32 ulMibCtrl; /* 067c */ + UINT32 ulTxVcPktOctCnt[XP_MAX_CONNS]; /* 0680 */ +} XTM_PROCESSOR_REGISTERS, *PXTM_PROCESSOR_REGISTERS; + +#define XP_REGS ((volatile PXTM_PROCESSOR_REGISTERS const) XTM_PROCESSOR_BASE) + +/* Definitions from pktCmfHw.h. TBD. Use commoon header file. */ +#ifndef PKTCMF_OFFSET_ENGINE_SAR +#define PKTCMF_OFFSET_ENGINE_SAR 0xB0002000 +#endif +#define PKTCMF_OFFSET_RXFILT 0x00001B00 +#define RXFILT_REG_MATCH0_DEF_ID 0x0000000C /* 7b/VCID 03..00 */ +#define RXFILT_REG_MATCH1_DEF_ID 0x00000010 /* 7b/VCID 07..04 */ +#define RXFILT_REG_MATCH2_DEF_ID 0x00000014 /* 7b/VCID 11..08 */ +#define RXFILT_REG_MATCH3_DEF_ID 0x00000018 /* 7b/VCID 15..12 */ + +#define RXFILT_REG_VCID0_QID 0x00000004 /* 2b/VCID 15..00 */ +#define RXFILT_REG_VCID1_QID 0x00000008 /* 2b VCID= 16 */ + +#endif /* _XTMPROCREGS_H_ */ + diff --git a/shared/opensource/boardparms/bcm963xx/Makefile b/shared/opensource/boardparms/bcm963xx/Makefile new file mode 100755 index 0000000..8d2573c --- /dev/null +++ b/shared/opensource/boardparms/bcm963xx/Makefile @@ -0,0 +1,16 @@ + +ifeq ($(CONFIG_MIPS_BRCM),y) + +# Linux +obj-y += boardparms.o + +ifneq ($(strip $(VOXXXLOAD)),) +obj-y += boardparms_voice.o +endif + +EXTRA_CFLAGS += -DCONFIG_BCM9$(BRCM_CHIP) -I$(INC_BRCMSHARED_PUB_PATH)/$(BRCM_BOARD) +-include $(TOPDIR)/Rules.make + +endif + + diff --git a/shared/opensource/boardparms/bcm963xx/boardparms.c b/shared/opensource/boardparms/bcm963xx/boardparms.c new file mode 100755 index 0000000..23ab3ef --- /dev/null +++ b/shared/opensource/boardparms/bcm963xx/boardparms.c @@ -0,0 +1,3712 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/************************************************************************** +* File Name : boardparms.c +* +* Description: This file contains the implementation for the BCM63xx board +* parameter access functions. +* +* Updates : 07/14/2003 Created. +***************************************************************************/ + +/* Includes. */ +#include "boardparms.h" +#include "boardparms_voice.h" + +/* Typedefs */ +typedef struct boardparameters +{ + char szBoardId[BP_BOARD_ID_LEN]; /* board id string */ + unsigned short usGPIOOverlay; /* enabled interfaces */ + + unsigned short usGpioRj11InnerPair; /* GPIO pin or not defined */ + unsigned short usGpioRj11OuterPair; /* GPIO pin or not defined */ + unsigned short usGpioUartRts; /* GPIO pin or not defined */ + unsigned short usGpioUartCts; /* GPIO pin or not defined */ + + unsigned short usGpioLedAdsl; /* GPIO pin or not defined */ + unsigned short usGpioLedAdslFail; /* GPIO pin or not defined */ + unsigned short usGpioSecLedAdsl; /* GPIO pin or not defined */ + unsigned short usGpioSecLedAdslFail; /* GPIO pin or not defined */ + unsigned short usGpioLedSesWireless; /* GPIO pin or not defined */ + unsigned short usGpioLedHpna; /* GPIO pin or not defined */ + unsigned short usGpioLedWanData; /* GPIO pin or not defined */ + unsigned short usGpioLedWanError; /* GPIO pin or not defined */ + unsigned short usGpioLedBlPowerOn; /* GPIO pin or not defined */ + unsigned short usGpioLedBlStop; /* GPIO pin or not defined */ + unsigned short usGpioFpgaReset; /* GPIO pin or not defined */ + unsigned short usGpioLedGpon; /* GPIO pin or not defined */ + unsigned short usGpioLedGponFail; /* GPIO pin or not defined */ + + unsigned short usGpioLedMoCA; /* GPIO pin or not defined */ + unsigned short usGpioLedMoCAFail; /* GPIO pin or not defined */ + + unsigned short usExtIntrResetToDefault; /* ext intr or not defined */ + unsigned short usExtIntrSesBtnWireless; /* ext intr or not defined */ + unsigned short usExtIntrHpna; /* ext intr or not defined */ + + unsigned short usCsHpna; /* HPNA chip select or not defined */ + + unsigned short usAntInUseWireless; /* antenna in use or not defined */ + unsigned short usWirelessFlags; /* WLAN flags */ + + ETHERNET_MAC_INFO EnetMacInfos[BP_MAX_ENET_MACS]; + VOIP_DSP_INFO VoIPDspInfo[BP_MAX_VOIP_DSP]; + unsigned short usGpioWirelessPowerDown; /* WLAN_PD control or not defined */ + unsigned long ulAfeIds[2]; /* DSL AFE Ids */ + unsigned short usGpioExtAFEReset; /* GPIO pin or not defined */ + unsigned short usGpioExtAFELDPwr; /* GPIO pin or not defined */ + unsigned short usGpioExtAFELDMode; /* GPIO pin or not defined */ +} BOARD_PARAMETERS, *PBOARD_PARAMETERS; + +#define SW_INFO_DEFAULT(n) { \ + (0x00000001 << (n)) - 1, /* port_map */ \ +{0, 0, 0, 0, 0, 0, 0, 0} /* phy_id */ \ +} + +/* Variables */ +#if defined(_BCM96362_) || defined(CONFIG_BCM96362) + +static BOARD_PARAMETERS g_bcm96362advnx = +{ + "96362ADVNX", /* szBoardId */ + (BP_OVERLAY_USB_LED | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_SERIAL_LEDS | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_SERIAL_GPIO_14_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_SERIAL_GPIO_15_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_1_AL, /* usGpioLedWanData */ + BP_SERIAL_GPIO_10_AL, /* usGpioLedWanError */ + BP_SERIAL_GPIO_12_AL, /* usGpioLedBlPowerOn */ + BP_SERIAL_GPIO_13_AL, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + BP_WLAN_EXCLUDE_ONBOARD, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x1f, {0x01, 0x02, 0x03, 0x04, 0x18, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_SERIAL_GPIO_8_AL, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_SERIAL_GPIO_9_AL, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6301 | BP_AFE_FE_ANNEXA | BP_AFE_FE_AVMODE_ADSL | BP_AFE_FE_REV_6301_REV_5_1_1, /* ulAfeIds */ + BP_AFE_DEFAULT}, + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96362advngr = +{ + "96362ADVNgr", /* szBoardId */ + (BP_OVERLAY_USB_LED | + BP_OVERLAY_SPI_EXT_CS | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_SERIAL_LEDS | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_SERIAL_GPIO_14_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_SERIAL_GPIO_15_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_1_AL, /* usGpioLedWanData */ + BP_SERIAL_GPIO_10_AL, /* usGpioLedWanError */ + BP_SERIAL_GPIO_12_AL, /* usGpioLedBlPowerOn */ + BP_SERIAL_GPIO_13_AL, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + BP_WLAN_EXCLUDE_ONBOARD, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x3f, {0x01, 0x02, 0x03, 0x04, 0x18, 0x19, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_SERIAL_GPIO_8_AL, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_SERIAL_GPIO_9_AL, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6301 | BP_AFE_FE_ANNEXA | BP_AFE_FE_AVMODE_ADSL | BP_AFE_FE_REV_6301_REV_5_1_1, /* ulAfeIds */ + BP_AFE_DEFAULT}, + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96362advngr2 = +{ + "96362ADVNgr2", /* szBoardId */ + (BP_OVERLAY_USB_LED | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_SERIAL_LEDS | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_SERIAL_GPIO_14_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_SERIAL_GPIO_15_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_1_AL, /* usGpioLedWanData */ + BP_SERIAL_GPIO_10_AL, /* usGpioLedWanError */ + BP_SERIAL_GPIO_12_AL, /* usGpioLedBlPowerOn */ + BP_SERIAL_GPIO_13_AL, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + BP_WLAN_EXCLUDE_ONBOARD, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x1f, {0x01, 0x02, 0x03, 0x04, 0x18, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_SERIAL_GPIO_8_AL, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_SERIAL_GPIO_9_AL, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_SERIAL_GPIO_11_AL, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6302 | BP_AFE_FE_ANNEXA | BP_AFE_FE_AVMODE_ADSL | BP_AFE_FE_REV_6302_REV_5_2_2, /* ulAfeIds */ + BP_AFE_DEFAULT}, + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static PBOARD_PARAMETERS g_BoardParms[] = {&g_bcm96362advnx, &g_bcm96362advngr, &g_bcm96362advngr2, 0}; +#endif + +#if defined(_BCM96368_) || defined(CONFIG_BCM96368) + +static BOARD_PARAMETERS g_bcm96368vvw = +{ + "96368VVW", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_GPIO_24_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_33_AH, /* usGpioLedWanError */ + BP_GPIO_0_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_1_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x0f, {0x01, 0x02, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_GPIO_25_AL, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_GPIO_26_AL, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_GPIO_27_AL, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_ISIL1556 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_ISIL_REV1, + BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368vvwb = +{ + "96368VVWB", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_GPIO_24_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_33_AH, /* usGpioLedWanError */ + BP_GPIO_0_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_1_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x0f, {0x01, 0x02, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_GPIO_25_AL, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_GPIO_26_AL, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_GPIO_27_AL, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_ISIL1556 | BP_AFE_FE_ANNEXB| BP_AFE_FE_REV_ISIL_REV1, + BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368ntr = +{ + "96368NTR", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_33_AH, /* usGpioLedWanError */ + BP_GPIO_0_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_1_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + BP_NOT_DEFINED, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x0f, {0x01, 0x02, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_GPIO_25_AL, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_GPIO_26_AL, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_GPIO_27_AL, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_DEFAULT, /* ulAfeIds */ + BP_AFE_DEFAULT}, + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368sv2 = +{ + "96368SV2", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_33_AH, /* usGpioLedWanError */ + BP_GPIO_30_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_31_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_NOT_DEFINED, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x3f, {0x01, 0x02, 0x03, 0x04, 0x12, 0x11, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_GPIO_25_AL, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_GPIO_26_AL, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_GPIO_27_AL, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_ISIL1556 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_ISIL_REV1, + BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368mvwg = +{ + "96368MVWG", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_GPIO_22_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_31_AH, /* usGpioLedWanError */ + BP_GPIO_22_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_24_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x36, {0x00, 0x02, 0x03, 0x00, 0x12, 0x11, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6302 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_6302_REV1, + BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368mvwgb = +{ + "96368MVWGB", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_GPIO_22_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_31_AH, /* usGpioLedWanError */ + BP_GPIO_22_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_24_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x36, {0x00, 0x02, 0x03, 0x00, 0x12, 0x11, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6302 | BP_AFE_FE_ANNEXB| BP_AFE_FE_REV_6302_REV1, + BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368mvwgj = +{ + "96368MVWGJ", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_GPIO_22_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_31_AH, /* usGpioLedWanError */ + BP_GPIO_22_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_24_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x36, {0x00, 0x02, 0x03, 0x00, 0x12, 0x11, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6302 | BP_AFE_FE_ANNEXJ | BP_AFE_FE_REV_6302_REV1, + BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368mbg = +{ + "96368MBG", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_31_AH, /* usGpioLedWanError */ + BP_GPIO_22_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_24_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + BP_NOT_DEFINED, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x0f, {0x01, 0x02, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6302 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_6302_REV1, + BP_AFE_CHIP_6306 | BP_AFE_LD_ISIL1556 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_ISIL_REV1}, /* ulAfeIds */ + BP_GPIO_35_AL, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368mbg6b = +{ + "96368MBG6b", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_31_AH, /* usGpioLedWanError */ + BP_GPIO_22_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_24_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + BP_NOT_DEFINED, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x0f, {0x01, 0x02, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_6306 | BP_AFE_LD_ISIL1556 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_ISIL_REV1, /* ulAfeIds */ + BP_AFE_DEFAULT}, + BP_GPIO_35_AL, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368mbg6302 = +{ + "96368MBG6302", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_31_AH, /* usGpioLedWanError */ + BP_GPIO_22_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_24_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + BP_NOT_DEFINED, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x0f, {0x01, 0x02, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6302 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_6302_REV1, + BP_AFE_CHIP_6306 | BP_AFE_LD_6302 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_6302_REV1}, /* ulAfeIds */ + BP_GPIO_35_AL, /* usGpioExtAFEReset */ + BP_GPIO_37_AH, /* usGpioExtAFELDPwr */ + BP_GPIO_36_AH /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368mng = +{ + "96368MNG", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_31_AH, /* usGpioLedWanError */ + BP_GPIO_22_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_24_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + BP_NOT_DEFINED, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x20, {0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00}}}, /* sw */ + {BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_SPI_SSB_1, /* usConfigType */ + {0x0f, {0x00, 0x01, 0x02, 0x03, 0x00, 0x00, 0x00, 0x00}}}}, /* sw */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_6306 | BP_AFE_LD_ISIL1556 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_ISIL_REV1, + BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_GPIO_37_AL, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96367avng = +{ + "96367AVNG", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_GPIO_23_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_NOT_DEFINED, /* usGpioLedWanData */ + BP_GPIO_31_AH, /* usGpioLedWanError */ + BP_GPIO_22_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_24_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x2f, {0x01, 0x02, 0x03, 0x04, 0x00, 0x11, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6302 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_6302_REV1, + BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368mvngr = +{ + "96368MVNgr", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_SPI_EXT_CS | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_GPIO_23_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AH, /* usGpioLedWanData */ + BP_GPIO_3_AH, /* usGpioLedWanError */ + BP_GPIO_22_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_24_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x0f, {0x01, 0x02, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6302 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_6302_REV1, + BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96368mvngrP2 = +{ + "96368MVNgrP2", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_PHY | + BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_INET_LED | + BP_OVERLAY_USB_DEVICE), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_2_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_GPIO_23_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_5_AL, /* usGpioLedWanData */ + BP_GPIO_3_AL, /* usGpioLedWanError */ + BP_GPIO_22_AL, /* usGpioLedBlPowerOn */ + BP_GPIO_24_AL, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_0, /* usExtIntrResetToDefault */ + BP_EXT_INTR_1, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x0f, {0x01, 0x02, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6302 | BP_AFE_FE_ANNEXA | BP_AFE_FE_REV_6302_REV1, + BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static PBOARD_PARAMETERS g_BoardParms[] = +{&g_bcm96368vvw, &g_bcm96368mvwg, &g_bcm96368sv2, &g_bcm96368mbg, +&g_bcm96368ntr, &g_bcm96368mbg6b, &g_bcm96368vvwb, &g_bcm96368mvwgb, +&g_bcm96368mng, &g_bcm96368mbg6302, &g_bcm96368mvwgj, &g_bcm96367avng, +&g_bcm96368mvngr, &g_bcm96368mvngrP2, 0}; +#endif + +#if defined(_BCM96816_) || defined(CONFIG_BCM96816) + +static BOARD_PARAMETERS g_bcm96816sv = +{ + "96816SV", /* szBoardId */ + (BP_OVERLAY_PCI | + BP_OVERLAY_GPHY_LED_0 | + BP_OVERLAY_GPHY_LED_1 | + BP_OVERLAY_MOCA_LED ), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_NOT_DEFINED, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_NOT_DEFINED, /* usGpioLedWanData */ + BP_NOT_DEFINED, /* usGpioLedWanError */ + BP_GPIO_3_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_4_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_GPIO_8_AH, /* usGpioLedGpon */ + BP_GPIO_16_AH, /* usGpioLedGponFail */ + BP_GPIO_5_AH, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_NOT_DEFINED, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0xbf, {0x00, 0x01, 0x14, 0x12, 0x18, 0xff, 0x00, 0xff}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_NO_DSP}, /* ucDspType */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_DEFAULT, BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96816pvwm = +{ + "96816PVWM", /* szBoardId */ + (BP_OVERLAY_GPHY_LED_0 | + BP_OVERLAY_GPHY_LED_1 | + BP_OVERLAY_MOCA_LED), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_NOT_DEFINED, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_NOT_DEFINED, /* usGpioLedWanData */ + BP_NOT_DEFINED, /* usGpioLedWanError */ + BP_GPIO_3_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_4_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_GPIO_8_AH, /* usGpioLedGpon */ + BP_GPIO_2_AH, /* usGpioLedGponFail */ + BP_GPIO_5_AH, /* usGpioLedMoCA */ + BP_GPIO_37_AH, /* usGpioLedMoCAFail */ + + BP_NOT_DEFINED, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0xaf, {0x00, 0x01, 0x11, 0x12, 0x00, 0xff, 0x00, 0xff}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_NOT_DEFINED, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_NOT_DEFINED, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_DEFAULT, /* ulAfeIds */ + BP_AFE_DEFAULT}, + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96829rg = +{ + "96829RG", /* szBoardId */ + (BP_OVERLAY_GPHY_LED_0 | + BP_OVERLAY_GPHY_LED_1 | + BP_OVERLAY_MOCA_LED), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_NOT_DEFINED, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_NOT_DEFINED, /* usGpioLedWanData */ + BP_NOT_DEFINED, /* usGpioLedWanError */ + BP_GPIO_3_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_4_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_GPIO_5_AL, /* usGpioLedMoCA */ + BP_GPIO_37_AH, /* usGpioLedMoCAFail */ + + BP_NOT_DEFINED, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0xaf, {0x00, 0x01, 0x11, 0x12, 0x00, 0xff, 0x00, 0xff}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_NO_DSP}, /* ucDspType */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_DEFAULT, BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96816p2og = +{ + "96816P2OG", /* szBoardId */ + (BP_OVERLAY_GPHY_LED_0 | + BP_OVERLAY_GPHY_LED_1 | + BP_OVERLAY_PCI | + BP_OVERLAY_MOCA_LED), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_NOT_DEFINED, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_NOT_DEFINED, /* usGpioLedWanData */ + BP_NOT_DEFINED, /* usGpioLedWanError */ + BP_NOT_DEFINED, /* usGpioLedBlPowerOn */ + BP_NOT_DEFINED, /* usGpioLedBlStop */ + BP_GPIO_2_AH, /* usGpioFpgaReset */ + BP_GPIO_8_AH, /* usGpioLedGpon */ + BP_GPIO_16_AH, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_NOT_DEFINED, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0xaf, {0x00, 0x01, 0x11, 0xff, 0x00, 0xff, 0x00, 0xff}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_NO_DSP}, /* ucDspType */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_DEFAULT, BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96812pg = +{ + "96812PG" , /* szBoardId */ + (BP_OVERLAY_GPHY_LED_0 | + BP_OVERLAY_GPHY_LED_1), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_NOT_DEFINED, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_NOT_DEFINED, /* usGpioLedWanData */ + BP_NOT_DEFINED, /* usGpioLedWanError */ + BP_GPIO_3_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_4_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_GPIO_8_AH, /* usGpioLedGpon */ + BP_GPIO_2_AH, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_NOT_DEFINED, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0xaf, {0x00, 0x01, 0x11, 0x12, 0x00, 0xff, 0x00, 0xff}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_NO_DSP}, /* ucDspType */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_DEFAULT, BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96819bhr = +{ + "96819BHR", /* szBoardId */ + (BP_OVERLAY_GPHY_LED_0 | + BP_OVERLAY_GPHY_LED_1 | + BP_OVERLAY_MOCA_LED), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_NOT_DEFINED, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_NOT_DEFINED, /* usGpioLedWanData */ + BP_NOT_DEFINED, /* usGpioLedWanError */ + BP_GPIO_3_AH, /* usGpioLedBlPowerOn */ + BP_GPIO_4_AH, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_GPIO_5_AL, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_EXT_INTR_3, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_NOT_DEFINED, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x3f, {0x00, 0x01, 0x14, 0x12, 0xA1, 0xff, 0x00, 0xff}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_NO_DSP}, /* ucDspType */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_DEFAULT, BP_AFE_DEFAULT}, /* ulAfeIds */ + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED, /* usGpioExtAFELDMode */ +}; + +static PBOARD_PARAMETERS g_BoardParms[] = {&g_bcm96816sv, &g_bcm96816pvwm, &g_bcm96829rg, &g_bcm96816p2og, &g_bcm96812pg, &g_bcm96819bhr, 0}; +#endif + +#if defined(_BCM96328_) || defined(CONFIG_BCM96328) +static BOARD_PARAMETERS g_bcm96328avng = +{ + "96328avng", /* szBoardId */ + (BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_3_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_GPIO_9_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + // **** Set to BP_GPIO_0_AL when WanData LED is connected to GPIO11 + BP_GPIO_0_AL, /* usGpioLedWanData */ + BP_GPIO_2_AL, /* usGpioLedWanError */ + BP_GPIO_4_AL, /* usGpioLedBlPowerOn */ + BP_GPIO_8_AL, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_NOT_DEFINED, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x1f, {0x01, 0x02, 0x03, 0x04, 0x18, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_GPIO_6_AL, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_GPIO_7_AL, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_GPIO_5_AL, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6301 | BP_AFE_FE_ANNEXA | BP_AFE_FE_AVMODE_ADSL | BP_AFE_FE_REV_6301_REV_5_1_1, /* ulAfeIds */ + BP_AFE_DEFAULT}, + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96328avngrP1 = +{ + "96328avngrP1", /* szBoardId */ + (BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_SERIAL_LEDS), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_SERIAL_GPIO_10_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_SERIAL_GPIO_11_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_SERIAL_GPIO_1_AL, /* usGpioLedWanData */ + BP_SERIAL_GPIO_13_AL, /* usGpioLedWanError */ + BP_SERIAL_GPIO_8_AL, /* usGpioLedBlPowerOn */ + BP_SERIAL_GPIO_15_AL, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_NOT_DEFINED, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x1f, {0x01, 0x02, 0x03, 0x04, 0x18, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_SERIAL_GPIO_12_AL, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_SERIAL_GPIO_14_AL, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6301 | BP_AFE_FE_ANNEXA | BP_AFE_FE_AVMODE_ADSL | BP_AFE_FE_REV_6301_REV_5_1_1, /* ulAfeIds */ + BP_AFE_DEFAULT}, + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm96328avngr = +{ + "96328avngr", /* szBoardId */ + (BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 | + BP_OVERLAY_SERIAL_LEDS), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_SERIAL_GPIO_10_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_SERIAL_GPIO_11_AL, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_GPIO_1_AL, /* usGpioLedWanData */ + BP_SERIAL_GPIO_13_AL, /* usGpioLedWanError */ + BP_SERIAL_GPIO_8_AL, /* usGpioLedBlPowerOn */ + BP_SERIAL_GPIO_15_AL, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_NOT_DEFINED, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x1f, {0x01, 0x02, 0x03, 0x04, 0x18, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_MIPS, /* ucDspType */ + 0, /* ucDspAddress */ + BP_NOT_DEFINED, /* usGpioLedVoip */ + BP_SERIAL_GPIO_12_AL, /* usGpioVoip1Led */ + BP_NOT_DEFINED, /* usGpioVoip1LedFail */ + BP_SERIAL_GPIO_14_AL, /* usGpioVoip2Led */ + BP_NOT_DEFINED, /* usGpioVoip2LedFail */ + BP_NOT_DEFINED, /* usGpioPotsLed */ + BP_NOT_DEFINED}, /* usGpioDectLed */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6301 | BP_AFE_FE_ANNEXA | BP_AFE_FE_AVMODE_ADSL | BP_AFE_FE_REV_6301_REV_5_1_1, /* ulAfeIds */ + BP_AFE_DEFAULT}, + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static BOARD_PARAMETERS g_bcm963281TAN = +{ + "963281TAN", /* szBoardId */ + + (BP_OVERLAY_EPHY_LED_0 | + BP_OVERLAY_EPHY_LED_1 | + BP_OVERLAY_EPHY_LED_2 | + BP_OVERLAY_EPHY_LED_3 ), /* usGPIOOverlay */ + + BP_NOT_DEFINED, /* usGpioRj11InnerPair */ + BP_NOT_DEFINED, /* usGpioRj11OuterPair */ + BP_NOT_DEFINED, /* usGpioUartRts */ + BP_NOT_DEFINED, /* usGpioUartCts */ + + BP_GPIO_20_AL, /* usGpioLedAdsl */ + BP_NOT_DEFINED, /* usGpioLedAdslFail */ + BP_NOT_DEFINED, /* usGpioSecLedAdsl */ + BP_NOT_DEFINED, /* usGpioSecLedAdslFail */ + BP_NOT_DEFINED, /* usGpioLedSesWireless */ + BP_NOT_DEFINED, /* usGpioLedHpna */ + BP_NOT_DEFINED, /* usGpioLedWanData */ + BP_NOT_DEFINED, /* usGpioLedWanError */ + BP_NOT_DEFINED, /* usGpioLedBlPowerOn */ + BP_NOT_DEFINED, /* usGpioLedBlStop */ + BP_NOT_DEFINED, /* usGpioFpgaReset */ + BP_NOT_DEFINED, /* usGpioLedGpon */ + BP_NOT_DEFINED, /* usGpioLedGponFail */ + BP_NOT_DEFINED, /* usGpioLedMoCA */ + BP_NOT_DEFINED, /* usGpioLedMoCAFail */ + + BP_NOT_DEFINED, /* usExtIntrResetToDefault */ + BP_NOT_DEFINED, /* usExtIntrSesBtnWireless */ + BP_NOT_DEFINED, /* usExtIntrHpna */ + + BP_NOT_DEFINED, /* usCsHpna */ + + BP_WLAN_ANT_MAIN, /* usAntInUseWireless */ + 0, /* WLAN flags */ + + {{BP_ENET_EXTERNAL_SWITCH, /* ucPhyType */ + 0x0, /* ucPhyAddress */ + BP_NOT_DEFINED, /* usGpioLedPhyLinkSpeed */ + BP_ENET_CONFIG_MMAP, /* usConfigType */ + {0x0f, {0x01, 0x02, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00}}}, /* sw */ + {BP_ENET_NO_PHY}}, /* ucPhyType */ + {{BP_VOIP_NO_DSP}, /* ucDspType */ + {BP_VOIP_NO_DSP}}, /* ucDspType */ + BP_NOT_DEFINED, /* usGpioWirelessPowerDown */ + {BP_AFE_CHIP_INT | BP_AFE_LD_6301 | BP_AFE_FE_ANNEXA | BP_AFE_FE_AVMODE_ADSL | BP_AFE_FE_REV_6301_REV_5_1_1, /* ulAfeIds */ + BP_AFE_DEFAULT}, + BP_NOT_DEFINED, /* usGpioExtAFEReset */ + BP_NOT_DEFINED, /* usGpioExtAFELDPwr */ + BP_NOT_DEFINED /* usGpioExtAFELDMode */ +}; + +static PBOARD_PARAMETERS g_BoardParms[] = {&g_bcm96328avng, &g_bcm96328avngrP1, &g_bcm96328avngr, &g_bcm963281TAN, 0}; +#endif + +static PBOARD_PARAMETERS g_pCurrentBp = 0; + +/************************************************************************** +* Name : bpstrcmp +* +* Description: String compare for this file so it does not depend on an OS. +* (Linux kernel and CFE share this source file.) +* +* Parameters : [IN] dest - destination string +* [IN] src - source string +* +* Returns : -1 - dest < src, 1 - dest > src, 0 dest == src +***************************************************************************/ +int bpstrcmp(const char *dest,const char *src) +{ + while (*src && *dest) + { + if (*dest < *src) return -1; + if (*dest > *src) return 1; + dest++; + src++; + } + + if (*dest && !*src) return 1; + if (!*dest && *src) return -1; + return 0; +} /* bpstrcmp */ + +/************************************************************************** +* Name : BpGetVoipDspConfig +* +* Description: Gets the DSP configuration from the board parameter +* structure for a given DSP index. +* +* Parameters : [IN] dspNum - DSP index (number) +* +* Returns : Pointer to DSP configuration block if found/valid, NULL +* otherwise. +***************************************************************************/ +VOIP_DSP_INFO *BpGetVoipDspConfig( unsigned char dspNum ) +{ + VOIP_DSP_INFO *pDspConfig = 0; + int i; + + if( g_pCurrentBp ) + { + for( i = 0 ; i < BP_MAX_VOIP_DSP ; i++ ) + { + if( g_pCurrentBp->VoIPDspInfo[i].ucDspType != BP_VOIP_NO_DSP && + g_pCurrentBp->VoIPDspInfo[i].ucDspAddress == dspNum ) + { + pDspConfig = &g_pCurrentBp->VoIPDspInfo[i]; + break; + } + } + } + + return pDspConfig; +} + + +/************************************************************************** +* Name : BpSetBoardId +* +* Description: This function find the BOARD_PARAMETERS structure for the +* specified board id string and assigns it to a global, static +* variable. +* +* Parameters : [IN] pszBoardId - Board id string that is saved into NVRAM. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_FOUND - Error, board id input string does not +* have a board parameters configuration record. +***************************************************************************/ +int BpSetBoardId( char *pszBoardId ) +{ + int nRet = BP_BOARD_ID_NOT_FOUND; + PBOARD_PARAMETERS *ppBp; + + for( ppBp = g_BoardParms; *ppBp; ppBp++ ) + { + if( !bpstrcmp((*ppBp)->szBoardId, pszBoardId) ) + { + g_pCurrentBp = *ppBp; + nRet = BP_SUCCESS; + break; + } + } + + return( nRet ); +} /* BpSetBoardId */ + +/************************************************************************** +* Name : BpGetBoardId +* +* Description: This function returns the current board id strings. +* +* Parameters : [OUT] pszBoardIds - Address of a buffer that the board id +* string is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +***************************************************************************/ + +int BpGetBoardId( char *pszBoardId ) +{ + int i; + + if (g_pCurrentBp == 0) + return -1; + + for (i = 0; i < BP_BOARD_ID_LEN; i++) + pszBoardId[i] = g_pCurrentBp->szBoardId[i]; + + return 0; +} + +/************************************************************************** +* Name : BpGetBoardIds +* +* Description: This function returns all of the supported board id strings. +* +* Parameters : [OUT] pszBoardIds - Address of a buffer that the board id +* strings are returned in. Each id starts at BP_BOARD_ID_LEN +* boundary. +* [IN] nBoardIdsSize - Number of BP_BOARD_ID_LEN elements that +* were allocated in pszBoardIds. +* +* Returns : Number of board id strings returned. +***************************************************************************/ +int BpGetBoardIds( char *pszBoardIds, int nBoardIdsSize ) +{ + PBOARD_PARAMETERS *ppBp; + int i; + char *src; + char *dest; + + for( i = 0, ppBp = g_BoardParms; *ppBp && nBoardIdsSize; + i++, ppBp++, nBoardIdsSize--, pszBoardIds += BP_BOARD_ID_LEN ) + { + dest = pszBoardIds; + src = (*ppBp)->szBoardId; + while( *src ) + *dest++ = *src++; + *dest = '\0'; + } + + return( i ); +} /* BpGetBoardIds */ + +/************************************************************************** +* Name : BpGetGPIOverlays +* +* Description: This function GPIO overlay configuration +* +* Parameters : [OUT] pusValue - Address of short word that interfaces in use. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetGPIOverlays( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGPIOOverlay; + + if( g_pCurrentBp->usGPIOOverlay != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetGPIOverlays */ + +/************************************************************************** +* Name : BpGetEthernetMacInfo +* +* Description: This function returns all of the supported board id strings. +* +* Parameters : [OUT] pEnetInfos - Address of an array of ETHERNET_MAC_INFO +* buffers. +* [IN] nNumEnetInfos - Number of ETHERNET_MAC_INFO elements that +* are pointed to by pEnetInfos. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +***************************************************************************/ +int BpGetEthernetMacInfo( PETHERNET_MAC_INFO pEnetInfos, int nNumEnetInfos ) +{ + int i, nRet; + + if( g_pCurrentBp ) + { + for( i = 0; i < nNumEnetInfos; i++, pEnetInfos++ ) + { + if( i < BP_MAX_ENET_MACS ) + { + unsigned char *src = (unsigned char *) + &g_pCurrentBp->EnetMacInfos[i]; + unsigned char *dest = (unsigned char *) pEnetInfos; + int len = sizeof(ETHERNET_MAC_INFO); + while( len-- ) + *dest++ = *src++; + } + else + pEnetInfos->ucPhyType = BP_ENET_NO_PHY; + } + + nRet = BP_SUCCESS; + } + else + { + for( i = 0; i < nNumEnetInfos; i++, pEnetInfos++ ) + pEnetInfos->ucPhyType = BP_ENET_NO_PHY; + + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetEthernetMacInfo */ + +/************************************************************************** +* Name : BpGetRj11InnerOuterPairGpios +* +* Description: This function returns the GPIO pin assignments for changing +* between the RJ11 inner pair and RJ11 outer pair. +* +* Parameters : [OUT] pusInner - Address of short word that the RJ11 inner pair +* GPIO pin is returned in. +* [OUT] pusOuter - Address of short word that the RJ11 outer pair +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, values are returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetRj11InnerOuterPairGpios( unsigned short *pusInner, + unsigned short *pusOuter ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusInner = g_pCurrentBp->usGpioRj11InnerPair; + *pusOuter = g_pCurrentBp->usGpioRj11OuterPair; + + if( g_pCurrentBp->usGpioRj11InnerPair != BP_NOT_DEFINED && + g_pCurrentBp->usGpioRj11OuterPair != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusInner = *pusOuter = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetRj11InnerOuterPairGpios */ + +/************************************************************************** +* Name : BpGetUartRtsCtsGpios +* +* Description: This function returns the GPIO pin assignments for RTS and CTS +* UART signals. +* +* Parameters : [OUT] pusRts - Address of short word that the UART RTS GPIO +* pin is returned in. +* [OUT] pusCts - Address of short word that the UART CTS GPIO +* pin is returned in. +* +* Returns : BP_SUCCESS - Success, values are returned. +* BP_BOARD_ID_NOT_SET - Error, board id input string does not +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetRtsCtsUartGpios( unsigned short *pusRts, unsigned short *pusCts ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusRts = g_pCurrentBp->usGpioUartRts; + *pusCts = g_pCurrentBp->usGpioUartCts; + + if( g_pCurrentBp->usGpioUartRts != BP_NOT_DEFINED && + g_pCurrentBp->usGpioUartCts != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusRts = *pusCts = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetUartRtsCtsGpios */ + +/************************************************************************** +* Name : BpGetAdslLedGpio +* +* Description: This function returns the GPIO pin assignment for the ADSL +* LED. +* +* Parameters : [OUT] pusValue - Address of short word that the ADSL LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetAdslLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedAdsl; + + if( g_pCurrentBp->usGpioLedAdsl != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetAdslLedGpio */ + +/************************************************************************** +* Name : BpGetAdslFailLedGpio +* +* Description: This function returns the GPIO pin assignment for the ADSL +* LED that is used when there is a DSL connection failure. +* +* Parameters : [OUT] pusValue - Address of short word that the ADSL LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetAdslFailLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedAdslFail; + + if( g_pCurrentBp->usGpioLedAdslFail != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetAdslFailLedGpio */ + +/************************************************************************** +* Name : BpGetSecAdslLedGpio +* +* Description: This function returns the GPIO pin assignment for the ADSL +* LED of the Secondary line, applicable more for bonding. +* +* Parameters : [OUT] pusValue - Address of short word that the ADSL LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetSecAdslLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioSecLedAdsl; + + if( g_pCurrentBp->usGpioSecLedAdsl != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetSecAdslLedGpio */ + +/************************************************************************** +* Name : BpGetSecAdslFailLedGpio +* +* Description: This function returns the GPIO pin assignment for the ADSL +* LED of the Secondary ADSL line, that is used when there is +* a DSL connection failure. +* +* Parameters : [OUT] pusValue - Address of short word that the ADSL LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetSecAdslFailLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioSecLedAdslFail; + + if( g_pCurrentBp->usGpioSecLedAdslFail != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetSecAdslFailLedGpio */ + +/************************************************************************** +* Name : BpGetWirelessAntInUse +* +* Description: This function returns the antennas in use for wireless +* +* Parameters : [OUT] pusValue - Address of short word that the Wireless Antenna +* is in use. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetWirelessAntInUse( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usAntInUseWireless; + + if( g_pCurrentBp->usAntInUseWireless != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetWirelessAntInUse */ + +/************************************************************************** +* Name : BpGetWirelessFlags +* +* Description: This function returns optional control flags for wireless +* +* Parameters : [OUT] pusValue - Address of short word control flags +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetWirelessFlags( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usWirelessFlags; + + if( g_pCurrentBp->usWirelessFlags != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetWirelessAntInUse */ + +/************************************************************************** +* Name : BpGetWirelessSesExtIntr +* +* Description: This function returns the external interrupt number for the +* Wireless Ses Button. +* +* Parameters : [OUT] pusValue - Address of short word that the Wireless Ses +* external interrup is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetWirelessSesExtIntr( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usExtIntrSesBtnWireless; + + if( g_pCurrentBp->usExtIntrSesBtnWireless != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); + +} /* BpGetWirelessSesExtIntr */ + +/************************************************************************** +* Name : BpGetWirelessSesLedGpio +* +* Description: This function returns the GPIO pin assignment for the Wireless +* Ses Led. +* +* Parameters : [OUT] pusValue - Address of short word that the Wireless Ses +* Led GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetWirelessSesLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedSesWireless; + + if( g_pCurrentBp->usGpioLedSesWireless != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); + +} /* BpGetWirelessSesLedGpio */ + +/* this data structure could be moved to boardparams structure in the future */ +/* does not require to rebuild cfe here if more srom entries are needed */ +static WLAN_SROM_PATCH_INFO wlanPaInfo[]={ +#if defined(_BCM96362_) || defined(CONFIG_BCM96362) + /* this is the patch to srom map for 96362ADVNX */ + {"96362ADVNX", 0x6362, 220, + {{"boardrev", 65, 0x1100}, + {"fem2g", 87, 0x0319}, + {"ittmaxp2ga0", 96, 0x2058}, + {"pa2gw0a0", 97, 0xfe6f}, + {"pa2gw1a0", 98, 0x1785}, + {"pa2gw2a0", 99, 0xfa21}, + {"ittmaxp2ga1", 112, 0x2058}, + {"pa2gw0a0", 113, 0xfe77}, + {"pa2gw1a0", 114, 0x17e0}, + {"pa2gw2a0", 115, 0xfa16}, + {"ofdm2gpo0", 161, 0x5555}, + {"ofdm2gpo1", 162, 0x5555}, + {"mcs2gpo0", 169, 0x5555}, + {"mcs2gpo1", 170, 0x5555}, + {"mcs2gpo2", 171, 0x5555}, + {"mcs2gpo3", 172, 0x5555}, + {"mcs2gpo4", 173, 0x3333}, + {"mcs2gpo5", 174, 0x3333}, + {"mcs2gpo6", 175, 0x3333}, + {"mcs2gpo7", 176, 0x3333}, + {"", 0, 0}}}, + /* this is the patch to srom map for 6362SDVNgr2 */ + {"96362ADVNgr2", 0x6362, 220, + {{"ittmaxp2ga0", 96, 0x2048}, + {"pa2gw0a0", 97, 0xfeff}, + {"pa2gw1a0", 98, 0x160e}, + {"pa2gw2a0", 99, 0xfabf}, + {"ittmaxp2ga1", 112, 0x2048}, + {"pa2gw0a0", 113, 0xff13}, + {"pa2gw1a0", 114, 0x161e}, + {"pa2gw2a0", 115, 0xfacc}, + {"mcs2gpo0", 169, 0x2222}, + {"mcs2gpo1", 170, 0x2222}, + {"mcs2gpo2", 171, 0x2222}, + {"mcs2gpo3", 172, 0x2222}, + {"mcs2gpo4", 173, 0x4444}, + {"mcs2gpo5", 174, 0x4444}, + {"mcs2gpo6", 175, 0x4444}, + {"mcs2gpo7", 176, 0x4444}, + {"", 0, 0}}}, +#endif +#if 0 //defined(_BCM96328_) || defined(CONFIG_BCM96328) + {"963281TAN", 0xa8d9, 220, + {{"pa2gw0a0", 97, 0xfed9}, + {"pa2gw1a0", 98, 0x15c7}, + {"pa2gw2a0", 99, 0xfaee}, + {"pa2gw0a0", 113, 0xfed7}, + {"pa2gw1a0", 114, 0x1540}, + {"pa2gw2a0", 115, 0xfafc}, + {"", 0, 0}}}, +#endif + {"", 0, 0, {{"", 0, 0}}}, /* last entry*/ +}; + +/************************************************************************** +* Name : BpUpdateWirelessSromMap +* +* Description: This function patch wireless PA values +* +* Parameters : [IN] unsigned short chipID +* [IN/OUT] unsigned short* pBase - base of srom map +* [IN/OUT] int size - size of srom map +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpUpdateWirelessSromMap(unsigned short chipID, unsigned short* pBase, int sizeInWords) +{ + int nRet = BP_BOARD_ID_NOT_FOUND; + int i = 0; + int j = 0; + + if(chipID == 0 || pBase == 0 || sizeInWords <= 0 ) + return nRet; + + i = 0; + while ( wlanPaInfo[i].szboardId[0] != 0 ) { + /* check boardId */ + if ( !bpstrcmp(g_pCurrentBp->szBoardId, wlanPaInfo[i].szboardId) ) { + /* check chipId */ + if ( (wlanPaInfo[i].usWirelessChipId == chipID) && (wlanPaInfo[i].usNeededSize <= sizeInWords) ){ + /* valid , patch entry */ + while ( wlanPaInfo[i].entries[j].name[0] ) { + pBase[wlanPaInfo[i].entries[j].wordOffset] = wlanPaInfo[i].entries[j].value; + j++; + } + nRet = BP_SUCCESS; + goto srom_update_done; + } + } + i++; + } + +srom_update_done: + + return( nRet ); + +} /* BpUpdateWirelessSromMap */ + + +static WLAN_PCI_PATCH_INFO wlanPciInfo[]={ +#if defined(_BCM96362_) || defined(CONFIG_BCM96362) + /* this is the patch to boardtype(boardid) for internal PA */ + {"96362ADVNX", 0x435f14e4, 64, + {{"subpciids", 11, 0x53614e4}, + {"", 0, 0}}}, +#endif + {"", 0, 0, {{"", 0, 0}}}, /* last entry*/ +}; + +/************************************************************************** +* Name : BpUpdateWirelessPciConfig +* +* Description: This function patch wireless PCI Config Header +* This is not functional critial/necessary but for dvt database maintenance +* +* Parameters : [IN] unsigned int pciID +* [IN/OUT] unsigned int* pBase - base of pci config header +* [IN/OUT] int sizeInDWords - size of pci config header +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpUpdateWirelessPciConfig (unsigned long pciID, unsigned long* pBase, int sizeInDWords) +{ + int nRet = BP_BOARD_ID_NOT_FOUND; + int i = 0; + int j = 0; + + if(pciID == 0 || pBase == 0 || sizeInDWords <= 0 ) + return nRet; + + i = 0; + while ( wlanPciInfo[i].szboardId[0] != 0 ) { + /* check boardId */ + if ( !bpstrcmp(g_pCurrentBp->szBoardId, wlanPciInfo[i].szboardId) ) { + /* check pciId */ + if ( (wlanPciInfo[i].usWirelessPciId == pciID) && (wlanPciInfo[i].usNeededSize <= sizeInDWords) ){ + /* valid , patch entry */ + while ( wlanPciInfo[i].entries[j].name[0] ) { + pBase[wlanPciInfo[i].entries[j].dwordOffset] = wlanPciInfo[i].entries[j].value; + j++; + } + nRet = BP_SUCCESS; + goto pciconfig_update_done; + } + } + i++; + } + +pciconfig_update_done: + + return( nRet ); + +} + +/************************************************************************** +* Name : BpGetHpnaLedGpio +* +* Description: This function returns the GPIO pin assignment for the HPNA +* LED. +* +* Parameters : [OUT] pusValue - Address of short word that the HPNA LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetHpnaLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedHpna; + + if( g_pCurrentBp->usGpioLedHpna != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetHpnaLedGpio */ + +/************************************************************************** +* Name : BpGetWanDataLedGpio +* +* Description: This function returns the GPIO pin assignment for the WAN Data +* LED. +* +* Parameters : [OUT] pusValue - Address of short word that the WAN Data LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetWanDataLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedWanData; + + if( g_pCurrentBp->usGpioLedWanData != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetWanDataLedGpio */ + +/************************************************************************** +* Name : BpGetWanErrorLedGpio +* +* Description: This function returns the GPIO pin assignment for the WAN +* LED that is used when there is a WAN connection failure. +* +* Parameters : [OUT] pusValue - Address of short word that the WAN LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetWanErrorLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedWanError; + + if( g_pCurrentBp->usGpioLedWanError != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetWanErrorLedGpio */ + +/************************************************************************** +* Name : BpGetBootloaderPowerOnLedGpio +* +* Description: This function returns the GPIO pin assignment for the power +* on LED that is set by the bootloader. +* +* Parameters : [OUT] pusValue - Address of short word that the alarm LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetBootloaderPowerOnLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedBlPowerOn; + + if( g_pCurrentBp->usGpioLedBlPowerOn != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetBootloaderPowerOn */ + +/************************************************************************** +* Name : BpGetBootloaderStopLedGpio +* +* Description: This function returns the GPIO pin assignment for the break +* into bootloader LED that is set by the bootloader. +* +* Parameters : [OUT] pusValue - Address of short word that the break into +* bootloader LED GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetBootloaderStopLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedBlStop; + + if( g_pCurrentBp->usGpioLedBlStop != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetBootloaderStopLedGpio */ + +/************************************************************************** +* Name : BpGetVoipLedGpio +* +* Description: This function returns the GPIO pin assignment for the VOIP +* LED. +* +* Parameters : [OUT] pusValue - Address of short word that the VOIP LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +* +* Note : The VoIP structure would allow for having one LED per DSP +* however, the board initialization function assumes only one +* LED per functionality (ie one LED for VoIP). Therefore in +* order to keep this tidy and simple we do not make usage of the +* one-LED-per-DSP function. Instead, we assume that the LED for +* VoIP is unique and associated with DSP 0 (always present on +* any VoIP platform). If changing this to a LED-per-DSP function +* then one need to update the board initialization driver in +* bcmdrivers\opensource\char\board\bcm963xx\impl1 +***************************************************************************/ +int BpGetVoipLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + VOIP_DSP_INFO *pDspInfo = BpGetVoipDspConfig( 0 ); + + if( pDspInfo ) + { + *pusValue = pDspInfo->usGpioLedVoip; + + if( *pusValue != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_FOUND; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetVoipLedGpio */ + +/************************************************************************** +* Name : BpGetVoip1LedGpio +* +* Description: This function returns the GPIO pin assignment for the VoIP1. +* LED which is used when FXS0 is active +* Parameters : [OUT] pusValue - Address of short word that the VoIP1 +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetVoip1LedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + VOIP_DSP_INFO *pDspInfo = &g_pCurrentBp->VoIPDspInfo[0]; + + if( pDspInfo->ucDspType != BP_VOIP_NO_DSP) + { + *pusValue = pDspInfo->usGpioVoip1Led; + + if( pDspInfo->usGpioVoip1Led != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetVoip1LedGpio */ + +/************************************************************************** +* Name : BpGetVoip1FailLedGpio +* +* Description: This function returns the GPIO pin assignment for the VoIP1 +* Fail LED which is used when there's an error with FXS0 +* Parameters : [OUT] pusValue - Address of short word that the VoIP1 +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetVoip1FailLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + VOIP_DSP_INFO *pDspInfo = &g_pCurrentBp->VoIPDspInfo[0]; + + if( pDspInfo->ucDspType != BP_VOIP_NO_DSP) + { + *pusValue = pDspInfo->usGpioVoip1LedFail; + + if( pDspInfo->usGpioVoip1LedFail != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetVoip1FailLedGpio */ + +/************************************************************************** +* Name : BpGetVoip2LedGpio +* +* Description: This function returns the GPIO pin assignment for the VoIP2. +* LED which is used when FXS1 is active +* Parameters : [OUT] pusValue - Address of short word that the VoIP2 +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetVoip2LedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + VOIP_DSP_INFO *pDspInfo = &g_pCurrentBp->VoIPDspInfo[0]; + + if( pDspInfo->ucDspType != BP_VOIP_NO_DSP) + { + *pusValue = pDspInfo->usGpioVoip2Led; + + if( pDspInfo->usGpioVoip2Led != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetVoip2LedGpio */ + +/************************************************************************** +* Name : BpGetVoip2FailLedGpio +* +* Description: This function returns the GPIO pin assignment for the VoIP2 +* Fail LED which is used when there's an error with FXS1 +* Parameters : [OUT] pusValue - Address of short word that the VoIP2 +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetVoip2FailLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + VOIP_DSP_INFO *pDspInfo = &g_pCurrentBp->VoIPDspInfo[0]; + + if( pDspInfo->ucDspType != BP_VOIP_NO_DSP) + { + *pusValue = pDspInfo->usGpioVoip2LedFail; + + if( pDspInfo->usGpioVoip2LedFail != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetVoip2FailLedGpio */ + +/************************************************************************** +* Name : BpGetPotsLedGpio +* +* Description: This function returns the GPIO pin assignment for the POTS1. +* LED which is used when DAA is active +* Parameters : [OUT] pusValue - Address of short word that the POTS11 +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetPotsLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + VOIP_DSP_INFO *pDspInfo = &g_pCurrentBp->VoIPDspInfo[0]; + + if( pDspInfo->ucDspType != BP_VOIP_NO_DSP) + { + *pusValue = pDspInfo->usGpioPotsLed; + + if( pDspInfo->usGpioPotsLed != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetPotsLedGpio */ + +/************************************************************************** +* Name : BpGetDectLedGpio +* +* Description: This function returns the GPIO pin assignment for the DECT. +* LED which is used when DECT is active +* Parameters : [OUT] pusValue - Address of short word that the DECT +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetDectLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + VOIP_DSP_INFO *pDspInfo = &g_pCurrentBp->VoIPDspInfo[0]; + + if( pDspInfo->ucDspType != BP_VOIP_NO_DSP) + { + *pusValue = pDspInfo->usGpioDectLed; + + if( pDspInfo->usGpioDectLed != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetDectLedGpio */ + +/************************************************************************** +* Name : BpGetFpgaResetGpio +* +* Description: This function returns the GPIO pin assignment for the FPGA +* Reset signal. +* +* Parameters : [OUT] pusValue - Address of short word that the FPGA Reset +* signal GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetFpgaResetGpio( unsigned short *pusValue ) { + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioFpgaReset; + + if( g_pCurrentBp->usGpioFpgaReset != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); + +} /*BpGetFpgaResetGpio*/ + +/************************************************************************** +* Name : BpGetGponLedGpio +* +* Description: This function returns the GPIO pin assignment for the GPON +* LED. +* +* Parameters : [OUT] pusValue - Address of short word that the GPON LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetGponLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedGpon; + + if( g_pCurrentBp->usGpioLedGpon != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetGponLedGpio */ + +/************************************************************************** +* Name : BpGetGponFailLedGpio +* +* Description: This function returns the GPIO pin assignment for the GPON +* LED that is used when there is a GPON connection failure. +* +* Parameters : [OUT] pusValue - Address of short word that the GPON LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetGponFailLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedGponFail; + + if( g_pCurrentBp->usGpioLedGponFail != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetGponFailLedGpio */ + + +/************************************************************************** +* Name : BpGetMoCALedGpio +* +* Description: This function returns the GPIO pin assignment for the MoCA +* LED. +* +* Parameters : [OUT] pusValue - Address of short word that the MoCA LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetMoCALedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedMoCA; + + if( g_pCurrentBp->usGpioLedMoCA != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetMoCALedGpio */ + +/************************************************************************** +* Name : BpGetMoCAFailLedGpio +* +* Description: This function returns the GPIO pin assignment for the MoCA +* LED that is used when there is a MoCA connection failure. +* +* Parameters : [OUT] pusValue - Address of short word that the MoCA LED +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetMoCAFailLedGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioLedMoCAFail; + + if( g_pCurrentBp->usGpioLedMoCAFail != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetMoCAFailLedGpio */ + +/************************************************************************** +* Name : BpGetHpnaExtIntr +* +* Description: This function returns the HPNA external interrupt number. +* +* Parameters : [OUT] pulValue - Address of short word that the HPNA +* external interrupt number is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetHpnaExtIntr( unsigned long *pulValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pulValue = g_pCurrentBp->usExtIntrHpna; + + if( g_pCurrentBp->usExtIntrHpna != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pulValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetHpnaExtIntr */ + +/************************************************************************** +* Name : BpGetHpnaChipSelect +* +* Description: This function returns the HPNA chip select number. +* +* Parameters : [OUT] pulValue - Address of short word that the HPNA +* chip select number is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetHpnaChipSelect( unsigned long *pulValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pulValue = g_pCurrentBp->usCsHpna; + + if( g_pCurrentBp->usCsHpna != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pulValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetHpnaChipSelect */ + +/************************************************************************** +* Name : BpGetResetToDefaultExtIntr +* +* Description: This function returns the external interrupt number for the +* reset to default button. +* +* Parameters : [OUT] pusValue - Address of short word that reset to default +* external interrupt is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetResetToDefaultExtIntr( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usExtIntrResetToDefault; + + if( g_pCurrentBp->usExtIntrResetToDefault != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); + +} /* BpGetResetToDefaultExtIntr */ + +/************************************************************************** +* Name : BpGetWirelessPowerDownGpio +* +* Description: This function returns the GPIO pin assignment for WLAN_PD +* +* +* Parameters : [OUT] pusValue - Address of short word that the WLAN_PD +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - At least one return value is not defined +* for the board. +***************************************************************************/ +int BpGetWirelessPowerDownGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioWirelessPowerDown; + + if( g_pCurrentBp->usGpioWirelessPowerDown != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* usGpioWirelessPowerDown */ + +/************************************************************************** +* Name : BpGetDslPhyAfeIds +* +* Description: This function returns the DSL PHY AFE ids for primary and +* secondary PHYs. +* +* Parameters : [OUT] pulValues-Address of an array of two long words where +* AFE Id for the primary and secondary PHYs are returned. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET-Error, BpSetBoardId hasn't been called. +* BP_VALUE_NOT_DEFINED - No defined AFE Ids. +**************************************************************************/ +int BpGetDslPhyAfeIds( unsigned long *pulValues ) +{ + int nRet; + + if( g_pCurrentBp ) + { + pulValues[0] = g_pCurrentBp->ulAfeIds[0]; + pulValues[1] = g_pCurrentBp->ulAfeIds[1]; + nRet = BP_SUCCESS; + } + else + { + pulValues[0] = BP_AFE_DEFAULT; + pulValues[1] = BP_AFE_DEFAULT; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetDslPhyAfeIds */ + +/************************************************************************** +* Name : BpGetExtAFEResetGpio +* +* Description: This function returns the GPIO pin assignment for resetting the external AFE chip +* +* +* Parameters : [OUT] pusValue - Address of short word that the ExtAFEReset +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - Not defined +***************************************************************************/ +int BpGetExtAFEResetGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioExtAFEReset; + + if( g_pCurrentBp->usGpioExtAFEReset != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetExtAFEResetGpio */ + +/************************************************************************** +* Name : BpGetExtAFELDModeGpio +* +* Description: This function returns the GPIO pin assignment for setting LD Mode to ADSL/VDSL +* +* +* Parameters : [OUT] pusValue - Address of short word that the usGpioExtAFELDMode +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - Not defined +***************************************************************************/ +int BpGetExtAFELDModeGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioExtAFELDMode; + + if( g_pCurrentBp->usGpioExtAFELDMode != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetExtAFELDModeGpio */ + +/************************************************************************** +* Name : BpGetExtAFELDPwrGpio +* +* Description: This function returns the GPIO pin assignment for turning on/off the external AFE LD +* +* +* Parameters : [OUT] pusValue - Address of short word that the usGpioExtAFELDPwr +* GPIO pin is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - Not defined +***************************************************************************/ +int BpGetExtAFELDPwrGpio( unsigned short *pusValue ) +{ + int nRet; + + if( g_pCurrentBp ) + { + *pusValue = g_pCurrentBp->usGpioExtAFELDPwr; + + if( g_pCurrentBp->usGpioExtAFELDPwr != BP_NOT_DEFINED ) + { + nRet = BP_SUCCESS; + } + else + { + nRet = BP_VALUE_NOT_DEFINED; + } + } + else + { + *pusValue = BP_NOT_DEFINED; + nRet = BP_BOARD_ID_NOT_SET; + } + + return( nRet ); +} /* BpGetExtAFELDPwrGpio */ + + +/************************************************************************** +* Name : BpGet6829PortInfo +* +* Description: This function checks the ENET MAC info to see if a 6829 +* is connected +* +* Parameters : [OUT] portInfo6829 - 0 if 6829 is not present +* - 6829 port information otherwise +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_SET - Error, BpSetBoardId has not been called. +* BP_VALUE_NOT_DEFINED - Not defined +***************************************************************************/ +int BpGet6829PortInfo( unsigned char *portInfo6829 ) +{ + ETHERNET_MAC_INFO enetMacInfo; + ETHERNET_SW_INFO *pSwInfo; + int retVal; + int i; + + *portInfo6829 = 0; + retVal = BpGetEthernetMacInfo( &enetMacInfo, 1 ); + if ( BP_SUCCESS == retVal ) + { + pSwInfo = &enetMacInfo.sw; + for (i = 0; i < BP_MAX_SWITCH_PORTS; i++) + { + if ( (pSwInfo->phy_id[i] != 0xFF) && + (pSwInfo->phy_id[i] & 0x80) ) + { + *portInfo6829 = pSwInfo->phy_id[i]; + retVal = BP_SUCCESS; + break; + } + } + } + + return retVal; + +} + diff --git a/shared/opensource/boardparms/bcm963xx/boardparms_voice.c b/shared/opensource/boardparms/bcm963xx/boardparms_voice.c new file mode 100755 index 0000000..72161cd --- /dev/null +++ b/shared/opensource/boardparms/bcm963xx/boardparms_voice.c @@ -0,0 +1,8804 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/************************************************************************** +* File Name : boardparms_voice.c +* +* Description: This file contains the implementation for the BCM63xx board +* parameter voice access functions. +* +***************************************************************************/ + +/* ---- Include Files ---------------------------------------------------- */ + +#include "boardparms_voice.h" + +/* ---- Public Variables ------------------------------------------------- */ + +/* ---- Private Constants and Types -------------------------------------- */ + +/* Always end the device list in VOICE_BOARD_PARMS with this macro */ +#define BP_NULL_DEVICE_MACRO \ +{ \ + BP_VD_NONE, \ + { 0, BP_NOT_DEFINED }, \ + 0, \ + BP_NOT_DEFINED, \ + { \ + { BP_VOICE_CHANNEL_INACTIVE, BP_VCTYPE_NONE, BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, BP_VOICE_CHANNEL_NARROWBAND, BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, BP_VOICE_CHANNEL_ENDIAN_BIG, BP_TIMESLOT_INVALID, BP_TIMESLOT_INVALID }, \ + { BP_VOICE_CHANNEL_INACTIVE, BP_VCTYPE_NONE, BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, BP_VOICE_CHANNEL_NARROWBAND, BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, BP_VOICE_CHANNEL_ENDIAN_BIG, BP_TIMESLOT_INVALID, BP_TIMESLOT_INVALID }, \ + } \ +} + +#define BP_NULL_CHANNEL_MACRO \ +{ BP_VOICE_CHANNEL_INACTIVE, \ + BP_VCTYPE_NONE, \ + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, \ + BP_VOICE_CHANNEL_NARROWBAND, \ + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, \ + BP_VOICE_CHANNEL_ENDIAN_BIG, \ + BP_TIMESLOT_INVALID, \ + BP_TIMESLOT_INVALID \ +}, + + +#if defined(_BCM96328_) || defined(CONFIG_BCM96328) + +VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88276 = +{ + VOICECFG_LE88276_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88276, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_31_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI3226 = +{ + VOICECFG_SI3226_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_SILABS_3226, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_31_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890 = +{ + VOICECFG_VE890_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_30_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_31_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI3217X = +{ + VOICECFG_SI3217X_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_30_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_31_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88506 = +{ + VOICECFG_LE88506_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88506, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_31_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI32267 = +{ + VOICECFG_6328AVNG_SI32267_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_SILABS_32267, + + /* SPI control */ + { + /* SPI dev id */ + 6, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_31_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( BP_FLAG_ISI_SUPPORT ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88276_NTR = +{ + VOICECFG_6328AVNG_LE88276_NTR_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88276, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890HV_Partial = +{ + VOICECFG_6328AVNG_VE890HV_PARTIAL_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89336, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 0, /* This setting is specific to Zarlink reference card Le71HR8923G for shared 1 reset line. */ + + /* Reset pin */ + BP_GPIO_30_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_31_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890HV = +{ + VOICECFG_6328AVNG_VE890HV_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89136, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89336, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 0, /* This setting is specific to Zarlink reference card Le71HR8923G for shared 1 reset line. */ + + /* Reset pin */ + BP_GPIO_30_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_31_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96328AVNGR_SI32176 = +{ + VOICECFG_6328AVNGR_SI32176_STR, /* szBoardId */ + 1, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96328AVNGR_LE89116 = +{ + VOICECFG_6328AVNGR_LE89116_STR, /* szBoardId */ + 1, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96328AVNGR_SI3217X = +{ + VOICECFG_6328AVNGR_SI3217X_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 0, /* Reset line shared to one line only for AVNGR board */ + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +static PVOICE_BOARD_PARMS g_VoiceBoardParms[] = +{ + &voiceBoard_96328AVNG_LE88276, + &voiceBoard_96328AVNG_SI3226, + &voiceBoard_96328AVNG_VE890, + &voiceBoard_96328AVNG_SI3217X, + &voiceBoard_96328AVNG_LE88506, +#ifdef SI32267ENABLE + &voiceBoard_96328AVNG_SI32267, +#endif + &voiceBoard_96328AVNG_LE88276_NTR, + &voiceBoard_96328AVNG_VE890HV_Partial, + &voiceBoard_96328AVNG_VE890HV, + + &voiceBoard_96328AVNGR_SI32176, + &voiceBoard_96328AVNGR_LE89116, + &voiceBoard_96328AVNGR_SI3217X, + 0 +}; + + +#endif + +#if defined(_BCM96362_) || defined(CONFIG_BCM96362) + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_NOSLIC = +{ + VOICECFG_6362ADVNGP5_NOSLIC_STR, /* szBoardId */ + 0, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_VE890 = +{ + VOICECFG_6362ADVNGP5_VE890_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_0_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice3 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_10_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE89116 = +{ + VOICECFG_6362ADVNGP5_LE89116_STR, /* szBoardId */ + 1, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_0_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_10_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE89316 = +{ + VOICECFG_6362ADVNGP5_LE89316_STR, /* szBoardId */ + 1, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_10_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI3217X = +{ + VOICECFG_6362ADVNGP5_SI3217X_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_0_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 32176 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice3 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_10_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI32176 = +{ + VOICECFG_6362ADVNGP5_SI32176_STR, /* szBoardId */ + 1, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_0_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_10_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI32178 = +{ + VOICECFG_6362ADVNGP5_SI32178_STR, /* szBoardId */ + 1, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_10_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE88276 = +{ + VOICECFG_6362ADVNGP5_LE88276_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88276, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_0_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_10_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI3226 = +{ + VOICECFG_6362ADVNGP5_SI3226_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_3226, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_0_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_10_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE88506 = +{ + VOICECFG_6362ADVNGP5_LE88506_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_6_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88506, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_0_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_10_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3217X = +{ + VOICECFG_6362ADVNGR_SI3217X_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice3 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32176 = +{ + VOICECFG_6362ADVNGR_SI32176_STR, /* szBoardId */ + 1, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32178 = +{ + VOICECFG_6362ADVNGR_SI32178_STR, /* szBoardId */ + 1, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3217X_NOFXO = +{ + VOICECFG_6362ADVNGR_SI3217X_NOFXO_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 32176 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice3 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890 = +{ + VOICECFG_6362ADVNGR_VE890_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 4, + 4 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice3 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 5, + 5 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 6, + 6 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE89116 = +{ + VOICECFG_6362ADVNGR_LE89116_STR, /* szBoardId */ + 1, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 4, + 4 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE89316 = +{ + VOICECFG_6362ADVNGR_LE89316_STR, /* szBoardId */ + 1, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 4, + 4 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 5, + 5 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE88506 = +{ + VOICECFG_6362ADVNGR_LE88506_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88506, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE88276 = +{ + VOICECFG_6362ADVNGR_LE88276_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88276, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3226 = +{ + VOICECFG_6362ADVNGR_SI3226_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_3226, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32261 = +{ + VOICECFG_6362ADVNGR_SI32261_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32261, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32267 = +{ + VOICECFG_6362ADVNGR_SI32267_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32267, + + /* SPI control */ + { + /* SPI dev id */ + 3, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( BP_FLAG_ISI_SUPPORT ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890HVP = +{ + VOICECFG_6362ADVNGR_VE890HV_PARTIAL_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 4, + 4 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice3 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89336, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 0, /* This setting is specific to Zarlink reference card Le71HR8923G for shared 1 reset line. */ + + /* Reset pin */ + BP_GPIO_28_AL, /* This setting is specific to Zarlink reference card Le71HR8923G for shared 1 reset line. */ + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 5, + 5 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 6, + 6 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890HV = +{ + VOICECFG_6362ADVNGR_VE890HV_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89136, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 4, + 4 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice3 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89336, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 5, + 5 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 6, + 6 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_SI3217X = +{ + VOICECFG_6362ADVNGR2_SI3217X_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice3 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_44_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_VE890 = +{ + VOICECFG_6362ADVNGR2_VE890_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 4, + 4 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice3 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_31_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 5, + 5 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 6, + 6 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_44_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_LE88506 = +{ + VOICECFG_6362ADVNGR2_LE88506_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88506, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_44_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_LE88276 = +{ + VOICECFG_6362ADVNGR2_LE88276_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88276, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_44_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_SI3226 = +{ + VOICECFG_6362ADVNGR2_SI3226_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 4, /* numDectLines */ + 1, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_29_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_3226, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_28_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_44_AH, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +static PVOICE_BOARD_PARMS g_VoiceBoardParms[] = +{ + &voiceBoard_96362ADVNGP5_NOSLIC, +// &voiceBoard_96362ADVNGP5_VE890, +// &voiceBoard_96362ADVNGP5_LE89116, +// &voiceBoard_96362ADVNGP5_LE89316, +// &voiceBoard_96362ADVNGP5_SI3217X, +// &voiceBoard_96362ADVNGP5_SI32176, +// &voiceBoard_96362ADVNGP5_SI32178, +// &voiceBoard_96362ADVNGP5_LE88276, +// &voiceBoard_96362ADVNGP5_SI3226, +// &voiceBoard_96362ADVNGP5_LE88506, + &voiceBoard_96362ADVNgr_SI3217X, + &voiceBoard_96362ADVNgr_SI32176, + &voiceBoard_96362ADVNgr_SI32178, + &voiceBoard_96362ADVNgr_SI3217X_NOFXO, + &voiceBoard_96362ADVNgr_VE890, + &voiceBoard_96362ADVNgr_LE89116, + &voiceBoard_96362ADVNgr_LE89316, + &voiceBoard_96362ADVNgr_LE88506, + &voiceBoard_96362ADVNgr_LE88276, + &voiceBoard_96362ADVNgr_SI3226, +#ifdef SI32261ENABLE + &voiceBoard_96362ADVNgr_SI32261, +#endif +#ifdef SI32267ENABLE + &voiceBoard_96362ADVNgr_SI32267, +#endif + &voiceBoard_96362ADVNgr_VE890HVP, + &voiceBoard_96362ADVNgr_VE890HV, + &voiceBoard_96362ADVNGR2_SI3217X, + &voiceBoard_96362ADVNGR2_VE890, + &voiceBoard_96362ADVNGR2_LE88506, + &voiceBoard_96362ADVNGR2_LE88276, + &voiceBoard_96362ADVNGR2_SI3226, + 0 +}; + +#endif + +#if defined(_BCM96368_) || defined(CONFIG_BCM96368) + +VOICE_BOARD_PARMS voiceBoard_96368MVWG = +{ + VOICECFG_6368MVWG_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 2, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_10_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 4, + 4 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 3, + /* SPI GPIO */ + BP_GPIO_29_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 0, + + /* Reset pin */ + BP_GPIO_10_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 5, + 5 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 6, + 6 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_GPIO_3_AH, BP_GPIO_13_AH } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MBG_VE890 = +{ + VOICECFG_6368MBG_VE890_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + +{ + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_3_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MBG_LE89116 = +{ + VOICECFG_6368MBG_LE89116_STR, /* szBoardId */ + 1, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_3_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MBG_LE89316 = +{ + VOICECFG_6368MBG_LE89316_STR, /* szBoardId */ + 1, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MBG_SI3217X = +{ + VOICECFG_6368MBG_SI3217X_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_3_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MBG_SI32176 = +{ + VOICECFG_6368MBG_SI32176_STR, /* szBoardId */ + 1, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_3_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MBG_SI32178 = +{ + VOICECFG_6368MBG_SI32178_STR, /* szBoardId */ + 1, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1}, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MBG_LE88276 = +{ + VOICECFG_6368MBG_LE88276_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88276, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_3_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MBG_LE88506 = +{ + VOICECFG_6368MBG_LE88506_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88506, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_3_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MBG_SI3226 = +{ + VOICECFG_6368MBG_SI3226_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_SILABS_3226, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_3_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3217X = +{ + VOICECFG_6368MVNGR_SI3217X_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_17_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI32176 = +{ + VOICECFG_6368MVNGR_SI32176_STR, /* szBoardId */ + 1, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI32178 = +{ + VOICECFG_6368MVNGR_SI32178_STR, /* szBoardId */ + 1, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_17_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3217X_NOFXO = +{ + VOICECFG_6368MVNGR_SI3217X_NOFXO_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_SILABS_32176, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_SILABS_32178, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_17_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890 = +{ + VOICECFG_6368MVNGR_VE890_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_17_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE89116 = +{ + VOICECFG_6368MVNGR_LE89116_STR, /* szBoardId */ + 1, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE89316 = +{ + VOICECFG_6368MVNGR_LE89316_STR, /* szBoardId */ + 1, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89316, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_17_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE88506 = +{ + VOICECFG_6368MVNGR_LE88506_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88506, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE88276 = +{ + VOICECFG_6368MVNGR_LE88276_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88276, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3226 = +{ + VOICECFG_6368MVNGR_SI3226_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_SILABS_3226, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890HV_Partial = +{ + VOICECFG_6368MVNGR_VE890HV_PARTIAL_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89116, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89336, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 0, /* This setting is specific to Zarlink reference card Le71HR8923G for shared 1 reset line. */ + + /* Reset pin */ + BP_GPIO_16_AL, /* This setting is specific to Zarlink reference card Le71HR8923G for shared 1 reset line. */ + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890HV = +{ + VOICECFG_6368MVNGR_VE890HV_STR, /* szBoardId */ + 2, /* numFxsLines */ + 1, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_IDECT1, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID + }, + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_DECT, + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_WIDEBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice1 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89136, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_16_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* There is no second channel on 89116 so mark it as inactive */ + { BP_VOICE_CHANNEL_INACTIVE, + BP_VCTYPE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_TIMESLOT_INVALID, + BP_TIMESLOT_INVALID}, + } + }, + + /* voiceDevice2 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_89336, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_17_AL, + + /* Channel description */ + { + /* Channel 0 on device 0 */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_DAA, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 2, + 2 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + +static PVOICE_BOARD_PARMS g_VoiceBoardParms[] = +{ + &voiceBoard_96368MVWG, + &voiceBoard_96368MBG_LE88276, + &voiceBoard_96368MBG_LE88506, + &voiceBoard_96368MBG_VE890, + &voiceBoard_96368MBG_LE89116, + &voiceBoard_96368MBG_LE89316, + &voiceBoard_96368MBG_SI3217X, + &voiceBoard_96368MBG_SI32176, + &voiceBoard_96368MBG_SI32178, + &voiceBoard_96368MBG_SI3226, + &voiceBoard_96368MVNgr_SI3217X, + &voiceBoard_96368MVNgr_SI32176, + &voiceBoard_96368MVNgr_SI32178, + &voiceBoard_96368MVNgr_SI3217X_NOFXO, + &voiceBoard_96368MVNgr_VE890, +// &voiceBoard_96368MVNgr_LE89116, /* Temporarily remove */ +// &voiceBoard_96368MVNgr_LE89316, /* Temporarily remove */ + &voiceBoard_96368MVNgr_VE890HV_Partial, + &voiceBoard_96368MVNgr_VE890HV, + &voiceBoard_96368MVNgr_LE88506, + &voiceBoard_96368MVNgr_LE88276, + &voiceBoard_96368MVNgr_SI3226, + 0 +}; + +#endif + +#if defined(_BCM96816_) || defined(CONFIG_BCM96816) + +VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE9530 = +{ + VOICECFG_LE9530_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_9530, + + /* SPI control */ + { + /* SPI dev id */ + 0, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 0, + + /* Reset pin */ + BP_NOT_DEFINED, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( BP_FLAG_DSP_APMHAL_ENABLE ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE88276 = +{ + VOICECFG_LE88276_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88276, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96816PVWM_SI3226 = +{ + VOICECFG_SI3226_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_SILABS_3226, + + /* SPI control */ + { + /* SPI dev id */ + 2, + /* SPI GPIO */ + BP_GPIO_28_AL, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + +VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE88506 = +{ + VOICECFG_LE88506_STR, /* szBoardId */ + 2, /* numFxsLines */ + 0, /* numFxoLines */ + 0, /* numDectLines */ + 0, /* numFailoverRelayPins */ + + { + /* voiceDevice0 parameters */ + { + /* Device type */ + BP_VD_ZARLINK_88506, + + /* SPI control */ + { + /* SPI dev id */ + 1, + /* SPI GPIO */ + BP_NOT_DEFINED, + }, + + /* Reset required (1 for yes, 0 for no) */ + 1, + + /* Reset pin */ + BP_GPIO_14_AL, + + /* Channel description */ + { + /* Channel 0 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 0, + 0 + }, + /* Channel 1 on device */ + { BP_VOICE_CHANNEL_ACTIVE, + BP_VCTYPE_SLIC, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_ENDIAN_BIG, + 1, + 1 + }, + } + }, + + /* Always end the device list with BP_NULL_DEVICE_MACRO */ + BP_NULL_DEVICE_MACRO, + }, + + /* Relay control pins */ + { { BP_NOT_DEFINED, BP_NOT_DEFINED } }, + + /* DECT UART control pins */ + { BP_NOT_DEFINED, BP_NOT_DEFINED }, + + /* General-purpose flags */ + ( 0 ) + +}; + + + +static PVOICE_BOARD_PARMS g_VoiceBoardParms[] = +{ &voiceBoard_96816PVWM_LE88276, + &voiceBoard_96816PVWM_SI3226, + &voiceBoard_96816PVWM_LE88506, + &voiceBoard_96816PVWM_LE9530, + 0 +}; + +#endif + + +static PVOICE_BOARD_PARMS g_pCurrentVoiceBp = 0; + +static void bpmemcpy( void* dstptr, const void* srcptr, int size ); +static void bpmemcpy( void* dstptr, const void* srcptr, int size ) +{ + char* dstp = dstptr; + const char* srcp = srcptr; + int i; + for( i=0; i < size; i++ ) + { + *dstp++ = *srcp++; + } +} + +int BpGetVoiceParms( char* pszBoardId, VOICE_BOARD_PARMS* voiceParms ) +{ + int nRet = BP_BOARD_ID_NOT_FOUND; + PVOICE_BOARD_PARMS *ppBp; + + for( ppBp = g_VoiceBoardParms; *ppBp; ppBp++ ) + { + if( !bpstrcmp((*ppBp)->szBoardId, pszBoardId) ) + { + g_pCurrentVoiceBp = *ppBp; + bpmemcpy( voiceParms, g_pCurrentVoiceBp, sizeof(VOICE_BOARD_PARMS) ); + nRet = BP_SUCCESS; + break; + } + } + + return( nRet ); +} + + +/************************************************************************** +* Name : BpSetVoiceBoardId +* +* Description: This function find the BOARD_PARAMETERS structure for the +* specified board id string and assigns it to a global, static +* variable. +* +* Parameters : [IN] pszBoardId - Board id string that is saved into NVRAM. +* +* Returns : BP_SUCCESS - Success, value is returned. +* BP_BOARD_ID_NOT_FOUND - Error, board id input string does not +* have a board parameters configuration record. +***************************************************************************/ +int BpSetVoiceBoardId( char *pszBoardId ) +{ + int nRet = BP_BOARD_ID_NOT_FOUND; + PVOICE_BOARD_PARMS *ppBp; + + for( ppBp = g_VoiceBoardParms; *ppBp; ppBp++ ) + { + if( !bpstrcmp((*ppBp)->szBoardId, pszBoardId) ) + { + g_pCurrentVoiceBp = *ppBp; + nRet = BP_SUCCESS; + break; + } + } + + return( nRet ); +} /* BpSetVoiceBoardId */ + + +/************************************************************************** +* Name : BpGetVoiceBoardId +* +* Description: This function returns the current board id strings. +* +* Parameters : [OUT] pszBoardIds - Address of a buffer that the board id +* string is returned in. +* +* Returns : BP_SUCCESS - Success, value is returned. +***************************************************************************/ + +int BpGetVoiceBoardId( char *pszBoardId ) +{ + int i; + + if (g_pCurrentVoiceBp == 0) + return -1; + + for (i = 0; i < BP_BOARD_ID_LEN; i++) + pszBoardId[i] = g_pCurrentVoiceBp->szBoardId[i]; + + return 0; +} + + +/************************************************************************** +* Name : BpGetVoiceBoardIds +* +* Description: This function returns all of the supported voice board id strings. +* +* Parameters : [OUT] pszBoardIds - Address of a buffer that the board id +* strings are returned in. Each id starts at BP_BOARD_ID_LEN +* boundary. +* [IN] nBoardIdsSize - Number of BP_BOARD_ID_LEN elements that +* were allocated in pszBoardIds. +* +* Returns : Number of board id strings returned. +***************************************************************************/ +int BpGetVoiceBoardIds( char *pszBoardIds, int nBoardIdsSize ) +{ + PVOICE_BOARD_PARMS *ppBp; + int i; + char *src; + char *dest; + + for( i = 0, ppBp = g_VoiceBoardParms; *ppBp && nBoardIdsSize; + i++, ppBp++, nBoardIdsSize--, pszBoardIds += BP_BOARD_ID_LEN ) + { + dest = pszBoardIds; + src = (*ppBp)->szBoardId; + while( *src ) + *dest++ = *src++; + *dest = '\0'; + } + + return( i ); +} /* BpGetVoiceBoardIds */ diff --git a/shared/opensource/flash/Makefile b/shared/opensource/flash/Makefile new file mode 100755 index 0000000..b7a9812 --- /dev/null +++ b/shared/opensource/flash/Makefile @@ -0,0 +1,41 @@ + +ifeq ($(CONFIG_MIPS_BRCM),y) + +# Linux + +obj-y += flash_api.o flash_common.o + +ifeq ($(strip $(BRCM_CHIP)),6368) +INC_CFI_FLASH_DRIVER=1 +INC_SPI_FLASH_DRIVER=1 +endif +ifeq ($(strip $(BRCM_CHIP)),6816) +INC_CFI_FLASH_DRIVER=1 +INC_SPI_FLASH_DRIVER=1 +endif +ifeq ($(strip $(BRCM_CHIP)),6362) +INC_CFI_FLASH_DRIVER=0 +INC_SPI_FLASH_DRIVER=1 +endif +ifeq ($(strip $(BRCM_CHIP)),6328) +INC_CFI_FLASH_DRIVER=0 +INC_SPI_FLASH_DRIVER=1 +endif + +ifeq ($(strip $(INC_CFI_FLASH_DRIVER)),1) +obj-y += cfiflash.o +endif +ifeq ($(strip $(INC_SPI_FLASH_DRIVER)),1) +obj-y += spiflash.o +endif + +EXTRA_CFLAGS += -DCONFIG_BCM9$(BRCM_CHIP) -I$(INC_BRCMDRIVER_PUB_PATH)/$(BRCM_BOARD) -I$(INC_BRCMSHARED_PUB_PATH)/$(BRCM_BOARD) -DINC_CFI_FLASH_DRIVER=$(INC_CFI_FLASH_DRIVER) -DINC_SPI_FLASH_DRIVER=$(INC_SPI_FLASH_DRIVER) + +endif + + + + + + + diff --git a/shared/opensource/flash/cfiflash.c b/shared/opensource/flash/cfiflash.c new file mode 100755 index 0000000..efd08de --- /dev/null +++ b/shared/opensource/flash/cfiflash.c @@ -0,0 +1,1112 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/** Includes. */ +#ifdef _CFE_ +#include "lib_types.h" +#include "lib_printf.h" +#include "lib_string.h" +#include "cfe_timer.h" +#include "bcm_map.h" +#define CFI_USLEEP(x) cfe_usleep(x) +#define printk printf +#else // linux +#include <linux/version.h> +#include <linux/init.h> +#include <linux/param.h> +#include <linux/sched.h> +#include <linux/timer.h> +#include <linux/interrupt.h> +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) +#include <linux/semaphore.h> +#else +#include <asm/semaphore.h> +#endif +#include <asm/delay.h> +#include <bcm_map_part.h> +#define CFI_USLEEP(x) udelay(x) +#endif + +#include "bcmtypes.h" +#include "bcm_hwdefs.h" +#include "flash_api.h" + +/** Defines. **/ +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _CFE_ +static DECLARE_MUTEX(cfi_flash_lock); +#define CF_FLASH_SCHED_BYTES 512 +static int cfi_flash_sched = 0; /* voluntary schedule() disabled by default */ +#endif + +#define MAXSECTORS 1024 /* maximum number of sectors supported */ + +/* Standard Boolean declarations */ +#define TRUE 1 +#define FALSE 0 + +/* Define different type of flash */ +#define FLASH_UNDEFINED 0 +#define FLASH_AMD 1 +#define FLASH_INTEL 2 +#define FLASH_SST 3 + +/* Command codes for the flash_command routine */ +#define FLASH_RESET 0 /* reset to read mode */ +#define FLASH_READ_ID 1 /* read device ID */ +#define FLASH_CFIQUERY 2 /* CFI query */ +#define FLASH_UB 3 /* go into unlock bypass mode */ +#define FLASH_PROG 4 /* program a unsigned short */ +#define FLASH_UBRESET 5 /* reset to read mode from unlock bypass mode */ +#define FLASH_SERASE 6 /* sector erase */ +#define FLASH_WRITE_BUF 7 /* write to buffer */ + +/* Return codes from flash_status */ +#define STATUS_READY 0 /* ready for action */ +#define STATUS_TIMEOUT 1 /* operation timed out */ + +/* A list of AMD compatible device ID's - add others as needed */ +#define ID_AM29DL800T 0x224A +#define ID_AM29DL800B 0x22CB +#define ID_AM29LV800T 0x22DA +#define ID_AM29LV800B 0x225B +#define ID_AM29LV400B 0x22BA +#define ID_AM29LV200BT 0x223B + +#define ID_AM29LV160B 0x2249 +#define ID_AM29LV160T 0x22C4 + +#define ID_AM29LV320T 0x22F6 +#define ID_MX29LV320AT 0x22A7 +#define ID_AM29LV320B 0x22F9 +#define ID_MX29LV320AB 0x22A8 +#define ID_MX29LV640BT 0x22C9 + +#define ID_AM29LV320M 0x227E +#define ID_AM29LV320MB 0x2200 +#define ID_AM29LV320MT 0x2201 + +#define ID_SST39VF200A 0x2789 +#define ID_SST39VF400A 0x2780 +#define ID_SST39VF800A 0x2781 +#define ID_SST39VF1601 0x234B +#define ID_SST39VF3201 0x235B +#define ID_SST39VF6401 0x236B + +/* A list of Intel compatible device ID's - add others as needed */ +#define ID_I28F160C3T 0x88C2 +#define ID_I28F160C3B 0x88C3 +#define ID_I28F320C3T 0x88C4 +#define ID_I28F320C3B 0x88C5 +#define ID_I28F640J3 0x8916 + +#define ID_M29W640FB 0x22FD + +#define CFI_FLASH_DEVICES \ + {{ID_AM29DL800T, "AM29DL800T"}, \ + {ID_AM29DL800B, "AM29DL800B"}, \ + {ID_AM29LV800T, "AM29LV800T"}, \ + {ID_AM29LV800B, "AM29LV800B"}, \ + {ID_AM29LV400B, "AM29LV400B"}, \ + {ID_AM29LV200BT, "AM29LV200BT"}, \ + {ID_AM29LV160B, "AM29LV160B"}, \ + {ID_AM29LV160T, "AM29LV160T"}, \ + {ID_AM29LV320T, "AM29LV320T"}, \ + {ID_MX29LV320AT, "MX29LV320AT"}, \ + {ID_AM29LV320B, "AM29LV320B"}, \ + {ID_MX29LV320AB, "MX29LV320AB"}, \ + {ID_AM29LV320M, "AM29LV320M"}, \ + {ID_AM29LV320MB, "AM29LV320MB"}, \ + {ID_AM29LV320MT, "AM29LV320MT"}, \ + {ID_MX29LV640BT, "MX29LV640BT"}, \ + {ID_SST39VF200A, "SST39VF200A"}, \ + {ID_SST39VF400A, "SST39VF400A"}, \ + {ID_SST39VF800A, "SST39VF800A"}, \ + {ID_SST39VF1601, "SST39VF1601"}, \ + {ID_SST39VF3201, "SST39VF3201"}, \ + {ID_SST39VF6401, "SST39VF6401"}, \ + {ID_I28F160C3T, "I28F160C3T"}, \ + {ID_I28F160C3B, "I28F160C3B"}, \ + {ID_I28F320C3T, "I28F320C3T"}, \ + {ID_I28F320C3B, "I28F320C3B"}, \ + {ID_I28F640J3, "I28F640J3"}, \ + {ID_M29W640FB, "STM29W640FB"}, \ + {0, ""} \ + } + +/** Structs. **/ +/* A structure for identifying a flash part. There is one for each + * of the flash part definitions. We need to keep track of the + * sector organization, the address register used, and the size + * of the sectors. + */ +struct flashinfo { + char *name; /* "Am29DL800T", etc. */ + unsigned long addr; /* physical address, once translated */ + int areg; /* Can be set to zero for all parts */ + int nsect; /* # of sectors -- 19 in LV, 22 in DL */ + int bank1start; /* first sector # in bank 1 */ + int bank2start; /* first sector # in bank 2, if DL part */ + struct { + long size; /* # of bytes in this sector */ + long base; /* offset from beginning of device */ + int bank; /* 1 or 2 for DL; 1 for LV */ + } sec[MAXSECTORS]; /* per-sector info */ + int write_buffer_size; /* max size of multi byte write */ +}; + +/* + * This structure holds all CFI query information as defined + * in the JEDEC standard. All information up to + * primary_extended_query is standard among all manufactures + * with CFI enabled devices. + */ + +struct cfi_query { + int num_erase_blocks; /* Number of sector defs. */ + long device_size; /* Device size in bytes */ + struct { + unsigned long sector_size; /* byte size of sector */ + int num_sectors; /* Num sectors of this size */ + } erase_block[8]; /* Max of 256, but 8 is good */ + int write_buffer_size; /* max size of multi byte write */ +}; + +struct flash_name_from_id { + unsigned short fnfi_id; + char fnfi_name[30]; +}; + + +/** Prototypes. **/ +int cfi_flash_init(flash_device_info_t **flash_info); +static int cfi_flash_sector_erase_int(unsigned short sector); +static int cfi_flash_read_buf(unsigned short sector, int offset, + unsigned char *buffer, int numbytes); +static int cfi_flash_write_buf(unsigned short sector, int offset, + unsigned char *buffer, int numbytes); +static int cfi_flash_get_numsectors(void); +static int cfi_flash_get_sector_size(unsigned short sector); +static unsigned char *cfi_flash_get_memptr(unsigned short sector); +static int cfi_flash_get_blk(int addr); +static int cfi_flash_get_total_size(void); +static void cfi_flash_command(int command, unsigned short sector, int offset, + unsigned short data, unsigned short *); +static int cfi_flash_write(unsigned short sector, int offset, unsigned char *buf, + int nbytes); +static int cfi_flash_write_to_buffer(unsigned short sector, unsigned char *buf); +static int cfi_flash_wait(unsigned short sector, int offset,unsigned short data); +static unsigned short cfi_flash_get_device_id(void); +static int cfi_flash_get_cfi(struct cfi_query *query, unsigned short *cfi_struct, + int flashFamily); +static int cfi_memcmp_sched(unsigned char *s1, unsigned char *s2, int nbytes); + +/** Variables. **/ +static flash_device_info_t flash_cfi_dev = + { + 0xffff, + FLASH_IFC_PARALLEL, + "", + cfi_flash_sector_erase_int, + cfi_flash_read_buf, + cfi_flash_write_buf, + cfi_flash_get_numsectors, + cfi_flash_get_sector_size, + cfi_flash_get_memptr, + cfi_flash_get_blk, + cfi_flash_get_total_size + }; + +/*********************************************************************/ +/* 'meminfo' should be a pointer, but most C compilers will not */ +/* allocate static storage for a pointer without calling */ +/* non-portable functions such as 'new'. We also want to avoid */ +/* the overhead of passing this pointer for every driver call. */ +/* Systems with limited heap space will need to do this. */ +/*********************************************************************/ +static struct flashinfo meminfo; /* Flash information structure */ +static int flashFamily = FLASH_UNDEFINED; +static int totalSize = 0; +static struct cfi_query query; + +static unsigned short cfi_data_struct_29W160[] = { + 0x0020, 0x0049, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0x0051, 0x0052, 0x0059, 0x0002, 0x0000, 0x0040, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0027, 0x0036, 0x0000, 0x0000, 0x0004, + 0x0000, 0x000a, 0x0000, 0x0004, 0x0000, 0x0003, 0x0000, 0x0015, + 0x0002, 0x0000, 0x0000, 0x0000, 0x0004, 0x0000, 0x0000, 0x0040, + 0x0000, 0x0001, 0x0000, 0x0020, 0x0000, 0x0000, 0x0000, 0x0080, + 0x0000, 0x001e, 0x0000, 0x0000, 0x0001, 0xffff, 0xffff, 0xffff, + 0x0050, 0x0052, 0x0049, 0x0031, 0x0030, 0x0000, 0x0002, 0x0001, + 0x0001, 0x0004, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0x0002, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0x0888, 0x252b, 0x8c84, 0x7dbc, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff +}; + +static UINT16 cfi_data_struct_29W200[] = { + 0x0020, 0x0049, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0x0051, 0x0052, 0x0059, 0x0002, 0x0000, 0x0040, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0027, 0x0036, 0x0000, 0x0000, 0x0004, + 0x0000, 0x000a, 0x0000, 0x0004, 0x0000, 0x0003, 0x0000, 0x0015, + 0x0002, 0x0000, 0x0000, 0x0000, 0x0004, 0x0000, 0x0000, 0x0040, + 0x0000, 0x0001, 0x0000, 0x0020, 0x0000, 0x0000, 0x0000, 0x0080, + 0x0000, 0x0002, 0x0000, 0x0000, 0x0001, 0xffff, 0xffff, 0xffff, + 0x0050, 0x0052, 0x0049, 0x0031, 0x0030, 0x0000, 0x0002, 0x0001, + 0x0001, 0x0004, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0x0002, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0x0888, 0x252b, 0x8c84, 0x7dbc, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff +}; + +static UINT16 cfi_data_struct_26LV800B[] = { + 0x0020, 0x0049, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0x0051, 0x0052, 0x0059, 0x0002, 0x0000, 0x0040, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0027, 0x0036, 0x0000, 0x0000, 0x0004, + 0x0000, 0x000a, 0x0000, 0x0004, 0x0000, 0x0003, 0x0000, 0x0015, + 0x0002, 0x0000, 0x0000, 0x0000, 0x0004, 0x0000, 0x0000, 0x0040, + 0x0000, 0x0001, 0x0000, 0x0020, 0x0000, 0x0000, 0x0000, 0x0080, + 0x0000, 0x000e, 0x0000, 0x0000, 0x0001, 0xffff, 0xffff, 0xffff, + 0x0050, 0x0052, 0x0049, 0x0031, 0x0030, 0x0000, 0x0002, 0x0001, + 0x0001, 0x0004, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0x0002, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0x0888, 0x252b, 0x8c84, 0x7dbc, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff +}; + +static struct flash_name_from_id fnfi[] = CFI_FLASH_DEVICES; + +/*********************************************************************/ +/* Init_flash is used to build a sector table from the information */ +/* provided through the CFI query. This information is translated */ +/* from erase_block information to base:offset information for each */ +/* individual sector. This information is then stored in the meminfo */ +/* structure, and used throughout the driver to access sector */ +/* information. */ +/* */ +/* This is more efficient than deriving the sector base:offset */ +/* information every time the memory map switches (since on the */ +/* development platform can only map 64k at a time). If the entire */ +/* flash memory array can be mapped in, then the addition static */ +/* allocation for the meminfo structure can be eliminated, but the */ +/* drivers will have to be re-written. */ +/* */ +/* The meminfo struct occupies 653 bytes of heap space, depending */ +/* on the value of the define MAXSECTORS. Adjust to suit */ +/* application */ +/*********************************************************************/ +int cfi_flash_init(flash_device_info_t **flash_info) +{ + struct flash_name_from_id *fnfi_ptr; + int i=0, j=0, count=0; + int basecount=0L; + unsigned short device_id; + int flipCFIGeometry = FALSE; + + *flash_info = &flash_cfi_dev; + + /* First, assume + * a single 8k sector for sector 0. This is to allow + * the system to perform memory mapping to the device, + * even though the actual physical layout is unknown. + * Once mapped in, the CFI query will produce all + * relevant information. + */ + meminfo.addr = 0L; + meminfo.areg = 0; + meminfo.nsect = 1; + meminfo.bank1start = 0; + meminfo.bank2start = 0; + + meminfo.sec[0].size = 8192; + meminfo.sec[0].base = 0x00000; + meminfo.sec[0].bank = 1; + + cfi_flash_command(FLASH_RESET, 0, 0, 0, NULL); + + flash_cfi_dev.flash_device_id = device_id = cfi_flash_get_device_id(); + flash_cfi_dev.flash_device_name[0] = '\0'; + switch (device_id) { + case ID_I28F160C3B: + case ID_I28F320C3B: + case ID_I28F160C3T: + case ID_I28F320C3T: + case ID_I28F640J3: + flashFamily = FLASH_INTEL; + break; + case ID_AM29DL800B: + case ID_AM29LV800B: + case ID_AM29LV400B: + case ID_AM29LV160B: + case ID_AM29LV320B: + case ID_MX29LV320AB: + case ID_AM29LV320MB: + case ID_AM29DL800T: + case ID_AM29LV800T: + case ID_AM29LV160T: + case ID_AM29LV320T: + case ID_MX29LV320AT: + case ID_AM29LV320MT: + case ID_AM29LV200BT: + case ID_MX29LV640BT: + case ID_M29W640FB: + flashFamily = FLASH_AMD; + break; + case ID_SST39VF200A: + case ID_SST39VF400A: + case ID_SST39VF800A: + case ID_SST39VF1601: + case ID_SST39VF3201: + case ID_SST39VF6401: + flashFamily = FLASH_SST; + break; + default: + return FLASH_API_ERROR; + } + + if (cfi_flash_get_cfi(&query, 0, flashFamily) == -1) { + switch(device_id) { + case ID_AM29LV160T: + case ID_AM29LV160B: + cfi_flash_get_cfi(&query, cfi_data_struct_29W160, flashFamily); + break; + case ID_AM29LV200BT: + cfi_flash_get_cfi(&query, cfi_data_struct_29W200, flashFamily); + break; + case ID_AM29LV800B: + cfi_flash_get_cfi(&query, cfi_data_struct_26LV800B, flashFamily); + strcpy( flash_cfi_dev.flash_device_name, "MX26LV800B" ); + break; + default: + return FLASH_API_ERROR; + } + } + + // need to determine if it top or bottom boot here + switch (device_id) + { + case ID_AM29DL800B: + case ID_AM29LV800B: + case ID_AM29LV400B: + case ID_AM29LV160B: + case ID_AM29LV320B: + case ID_MX29LV320AB: + case ID_AM29LV320MB: + case ID_I28F160C3B: + case ID_I28F320C3B: + case ID_I28F640J3: + case ID_I28F160C3T: + case ID_I28F320C3T: + case ID_SST39VF3201: + case ID_SST39VF6401: + case ID_SST39VF200A: + case ID_SST39VF400A: + case ID_SST39VF800A: + case ID_M29W640FB: + flipCFIGeometry = FALSE; + break; + case ID_AM29DL800T: + case ID_AM29LV800T: + case ID_AM29LV160T: + case ID_AM29LV320T: + case ID_MX29LV320AT: + case ID_AM29LV320MT: + case ID_AM29LV200BT: + case ID_SST39VF1601: + case ID_MX29LV640BT: + flipCFIGeometry = TRUE; + break; + default: + return FLASH_API_ERROR; + } + + count=0;basecount=0L; + + if (!flipCFIGeometry) + { + + for (i=0; i<query.num_erase_blocks && basecount < query.device_size; i++) { + for(j=0; j<query.erase_block[i].num_sectors; j++) { + meminfo.sec[count].size = (int) query.erase_block[i].sector_size; + meminfo.sec[count].base = (int) basecount; + basecount += (int) query.erase_block[i].sector_size; + count++; + } + } + } + else + { + for (i = (query.num_erase_blocks - 1); i >= 0 && basecount < query.device_size; i--) { + for(j=0; j<query.erase_block[i].num_sectors; j++) { + meminfo.sec[count].size = (int) query.erase_block[i].sector_size; + meminfo.sec[count].base = (int) basecount; + basecount += (int) query.erase_block[i].sector_size; + count++; + } + } + } + + meminfo.nsect = count; + totalSize = meminfo.sec[count-1].base + meminfo.sec[count-1].size; + + if( flash_cfi_dev.flash_device_name[0] == '\0' ) { + for( fnfi_ptr = fnfi; fnfi_ptr->fnfi_id != 0; fnfi_ptr++ ) { + if( fnfi_ptr->fnfi_id == device_id ) { + strcpy( flash_cfi_dev.flash_device_name, fnfi_ptr->fnfi_name ); + break; + } + } + } + + meminfo.write_buffer_size = query.write_buffer_size; + + return (FLASH_API_OK); +} + +/*********************************************************************/ +/* Flash_sector_erase_int() is identical to flash_sector_erase(), */ +/* except it will wait until the erase is completed before returning */ +/* control to the calling function. This can be used in cases which */ +/* require the program to hold until a sector is erased, without */ +/* adding the wait check external to this function. */ +/*********************************************************************/ +static int cfi_flash_sector_erase_int(unsigned short sector) +{ + int i; + +#ifndef _CFE_ + down(&cfi_flash_lock); +#endif + + for( i = 0; i < 3; i++ ) { + cfi_flash_command(FLASH_SERASE, sector, 0, 0, NULL); + if (cfi_flash_wait(sector, 0, 0xffff) == STATUS_READY) + break; + } + +#ifndef _CFE_ + up(&cfi_flash_lock); +#endif + + return(FLASH_API_OK); +} + +/*********************************************************************/ +/* flash_read_buf() reads buffer of data from the specified */ +/* offset from the sector parameter. */ +/*********************************************************************/ +static int cfi_flash_read_buf(unsigned short sector, int offset, + unsigned char *buffer, int numbytes) +{ + unsigned char *fwp; +#ifndef _CFE_ + unsigned int bytes_read = CF_FLASH_SCHED_BYTES; + + down(&cfi_flash_lock); +#endif + + fwp = (unsigned char *) cfi_flash_get_memptr(sector); + + while (numbytes) { + *buffer++ = *(fwp + offset); + numbytes--; + fwp++; +#ifndef _CFE_ + if (!in_interrupt()) { + /* Voluntary schedule() if task tagged as need_sched or 512 bytes read */ + /* Must force need_resched or else schedule() is in-effective */ + if ( cfi_flash_sched ) { + if ( (need_resched()) || (bytes_read >= CF_FLASH_SCHED_BYTES) ) { + bytes_read=0; + set_tsk_need_resched(current); /* fake need_resched() to force schedule() */ + schedule(); + } + else + bytes_read++; + } + } +#endif + } + +#ifndef _CFE_ + up(&cfi_flash_lock); +#endif + + return (FLASH_API_OK); +} + +/*********************************************************************/ +/* cfi_memcmp_sched: invokes memcmp with schedule() invocations */ +/*********************************************************************/ +static int cfi_memcmp_sched(unsigned char *s1, unsigned char *s2, int nb) +{ +#ifndef _CFE_ + const unsigned int sched_chunk = 4 * 1024; + size_t nbytes; + int ret = 0; + + while ( nb > 0 ) + { + if (!in_interrupt()) { + set_tsk_need_resched(current); + schedule(); + } + + nbytes = (nb > sched_chunk) ? sched_chunk : nb; + + if ( (ret = memcmp( s1, s2, nbytes )) != 0 ) + break; + + s1 += sched_chunk; + s2 += sched_chunk; + nb -= sched_chunk; + } + + return ret; +#else + return memcmp( s1, s2, nb ); +#endif +} + +/*********************************************************************/ +/* flash_write_buf() utilizes */ +/* the unlock bypass mode of the flash device. This can remove */ +/* significant overhead from the bulk programming operation, and */ +/* when programming bulk data a sizeable performance increase can be */ +/* observed. */ +/*********************************************************************/ +static int cfi_flash_write_buf(unsigned short sector, int offset, + unsigned char *buffer, int numbytes) +{ + int ret = FLASH_API_ERROR; + int i; + unsigned char *p = cfi_flash_get_memptr(sector) + offset; + int write_buf_method = 0; + + if( meminfo.write_buffer_size != 0 && offset == 0 && + (ID_M29W640FB != cfi_flash_get_device_id()) && + numbytes == cfi_flash_get_sector_size(sector) ) + { + write_buf_method = 1; + } + + /* After writing the flash block, compare the contents to the source + * buffer. Try to write the sector successfully up to three times. + */ + for( i = 0; i < 3; i++ ) { + if( write_buf_method ) + ret = cfi_flash_write_to_buffer(sector, buffer); + else + ret = cfi_flash_write(sector, offset, buffer, numbytes); + if( !cfi_memcmp_sched( p, buffer, numbytes ) ) + break; + /* Erase and try again */ + cfi_flash_sector_erase_int(sector); + ret = FLASH_API_ERROR; + } + + if( ret == FLASH_API_ERROR ) + printk( "Flash write error. Verify failed\n" ); + + return( ret ); +} + +/*********************************************************************/ +/* Usefull funtion to return the number of sectors in the device. */ +/* Can be used for functions which need to loop among all the */ +/* sectors, or wish to know the number of the last sector. */ +/*********************************************************************/ +static int cfi_flash_get_numsectors(void) +{ + return meminfo.nsect; +} + +/*********************************************************************/ +/* flash_get_sector_size() is provided for cases in which the size */ +/* of a sector is required by a host application. The sector size */ +/* (in bytes) is returned in the data location pointed to by the */ +/* 'size' parameter. */ +/*********************************************************************/ +static int cfi_flash_get_sector_size(unsigned short sector) +{ + return meminfo.sec[sector].size; +} + +/*********************************************************************/ +/* The purpose of flash_get_memptr() is to return a memory pointer */ +/* which points to the beginning of memory space allocated for the */ +/* flash. All function pointers are then referenced from this */ +/* pointer. */ +/* */ +/* Different systems will implement this in different ways: */ +/* possibilities include: */ +/* - A direct memory pointer */ +/* - A pointer to a memory map */ +/* - A pointer to a hardware port from which the linear */ +/* address is translated */ +/* - Output of an MMU function / service */ +/* */ +/* Also note that this function expects the pointer to a specific */ +/* sector of the device. This can be provided by dereferencing */ +/* the pointer from a translated offset of the sector from a */ +/* global base pointer (e.g. flashptr = base_pointer + sector_offset)*/ +/* */ +/* Important: Many AMD flash devices need both bank and or sector */ +/* address bits to be correctly set (bank address bits are A18-A16, */ +/* and sector address bits are A18-A12, or A12-A15). Flash parts */ +/* which do not need these bits will ignore them, so it is safe to */ +/* assume that every part will require these bits to be set. */ +/*********************************************************************/ +static unsigned char *cfi_flash_get_memptr(unsigned short sector) +{ + unsigned char *memptr = (unsigned char*) + (FLASH_BASE + meminfo.sec[sector].base); + + return (memptr); +} + +/*********************************************************************/ +/* The purpose of flash_get_blk() is to return a the block number */ +/* for a given memory address. */ +/*********************************************************************/ +static int cfi_flash_get_blk(int addr) +{ + int blk_start, i; + int last_blk = cfi_flash_get_numsectors(); + int relative_addr = addr - (int) FLASH_BASE; + + for(blk_start=0, i=0; i < relative_addr && blk_start < last_blk; blk_start++) + i += cfi_flash_get_sector_size(blk_start); + + if( i > relative_addr ) + { + blk_start--; // last blk, dec by 1 + } + else + if( blk_start == last_blk ) + { + printk("Address is too big.\n"); + blk_start = -1; + } + + return( blk_start ); +} + +/************************************************************************/ +/* The purpose of flash_get_total_size() is to return the total size of */ +/* the flash */ +/************************************************************************/ +static int cfi_flash_get_total_size(void) +{ + return totalSize; +} + +/*********************************************************************/ +/* Flash_command() is the main driver function. It performs */ +/* every possible command available to AMD B revision */ +/* flash parts. Note that this command is not used directly, but */ +/* rather called through the API wrapper functions provided below. */ +/*********************************************************************/ +static void cfi_flash_command(int command, unsigned short sector, int offset, + unsigned short data, unsigned short *dataptr) +{ + volatile unsigned short *flashptr; + volatile unsigned short *flashbase; + unsigned short i, len; + + flashptr = (unsigned short *) cfi_flash_get_memptr(sector); + flashbase = (unsigned short *) cfi_flash_get_memptr(0); + + switch (flashFamily) { + case FLASH_UNDEFINED: + /* These commands should work for AMD, Intel and SST flashes */ + switch (command) { + case FLASH_RESET: + flashptr[0] = 0xF0; + flashptr[0] = 0xFF; + break; + case FLASH_READ_ID: + flashptr[0x5555] = 0xAA; /* unlock 1 */ + flashptr[0x2AAA] = 0x55; /* unlock 2 */ + flashptr[0x5555] = 0x90; + break; + case FLASH_CFIQUERY: + flashbase[0x5555] = 0xAA; /* unlock 1 */ + flashbase[0x2AAA] = 0x55; /* unlock 2 */ + flashbase[0x5555] = 0x90; + break; + default: + break; + } + break; + case FLASH_AMD: + switch (command) { + case FLASH_RESET: + flashptr[0] = 0xF0; + break; + case FLASH_READ_ID: + flashptr[0x555] = 0xAA; /* unlock 1 */ + flashptr[0x2AA] = 0x55; /* unlock 2 */ + flashptr[0x555] = 0x90; + break; + case FLASH_CFIQUERY: + flashptr[0x55] = 0x98; + break; + case FLASH_UB: + flashptr[0x555] = 0xAA; /* unlock 1 */ + flashptr[0x2AA] = 0x55; /* unlock 2 */ + flashptr[0x555] = 0x20; + break; + case FLASH_PROG: + flashptr[0] = 0xA0; + flashptr[offset/2] = data; + break; + case FLASH_UBRESET: + flashptr[0] = 0x90; + flashptr[0] = 0x00; + break; + case FLASH_SERASE: + flashptr[0x555] = 0xAA; /* unlock 1 */ + flashptr[0x2AA] = 0x55; /* unlock 2 */ + flashptr[0x555] = 0x80; + flashptr[0x555] = 0xAA; + flashptr[0x2AA] = 0x55; + flashptr[0] = 0x30; + break; + case FLASH_WRITE_BUF: + flashptr[0x555] = 0xAA; /* unlock 1 */ + flashptr[0x2AA] = 0x55; /* unlock 2 */ + flashptr[0] = 0x25; + offset /= 2; + len = data / 2; /* data is bytes to program */ + flashptr[0] = len - 1; + for( i = 0; i < len; i++ ) + flashptr[offset + i] = *dataptr++; + flashptr[0] = 0x29; + break; + default: + break; + } + break; + case FLASH_INTEL: + switch (command) { + case FLASH_RESET: + flashptr[0] = 0xFF; + break; + case FLASH_READ_ID: + flashptr[0] = 0x90; + break; + case FLASH_CFIQUERY: + flashptr[0] = 0x98; + break; + case FLASH_PROG: + flashptr[0] = 0x40; + flashptr[offset/2] = data; + break; + case FLASH_SERASE: + flashptr[0] = 0x60; + flashptr[0] = 0xD0; + flashptr[0] = 0x20; + flashptr[0] = 0xD0; + break; + default: + break; + } + break; + case FLASH_SST: + switch (command) { + case FLASH_RESET: + flashbase[0x5555] = 0xAA; /* unlock 1 */ + flashbase[0x2AAA] = 0x55; /* unlock 2 */ + flashbase[0x5555] = 0xf0; + break; + case FLASH_READ_ID: + flashbase[0x5555] = 0xAA; /* unlock 1 */ + flashbase[0x2AAA] = 0x55; /* unlock 2 */ + flashbase[0x5555] = 0x90; + break; + case FLASH_CFIQUERY: + flashbase[0x5555] = 0xAA; /* unlock 1 */ + flashbase[0x2AAA] = 0x55; /* unlock 2 */ + flashbase[0x5555] = 0x98; + break; + case FLASH_UB: + break; + case FLASH_PROG: + flashbase[0x5555] = 0xAA; /* unlock 1 */ + flashbase[0x2AAA] = 0x55; /* unlock 2 */ + flashbase[0x5555] = 0xa0; + flashptr[offset/2] = data; + break; + case FLASH_UBRESET: + break; + case FLASH_SERASE: + flashbase[0x5555] = 0xAA; /* unlock 1 */ + flashbase[0x2AAA] = 0x55; /* unlock 2 */ + flashbase[0x5555] = 0x80; + flashbase[0x5555] = 0xAA; + flashbase[0x2AAA] = 0x55; + flashptr[0] = 0x30; + break; + default: + break; + } + break; + default: + break; + } +} + +/*********************************************************************/ +/* flash_write extends the functionality of flash_program() by */ +/* providing an faster way to program multiple data words, without */ +/* needing the function overhead of looping algorithms which */ +/* program word by word. This function utilizes fast pointers */ +/* to quickly loop through bulk data. */ +/*********************************************************************/ +static int cfi_flash_write(unsigned short sector, int offset, unsigned char *buf, + int nbytes) +{ + unsigned short *src; + src = (unsigned short *)buf; + +#ifndef _CFE_ + down(&cfi_flash_lock); +#endif + + if ((nbytes | offset) & 1) { +#ifndef _CFE_ + up(&cfi_flash_lock); +#endif + return FLASH_API_ERROR; + } + + cfi_flash_command(FLASH_UB, 0, 0, 0, NULL); + while (nbytes > 0) { + cfi_flash_command(FLASH_PROG, sector, offset, *src, NULL); + if (cfi_flash_wait(sector, offset, *src) != STATUS_READY) + break; + offset +=2; + nbytes -=2; + src++; + } + cfi_flash_command(FLASH_UBRESET, 0, 0, 0, NULL); + +#ifndef _CFE_ + up(&cfi_flash_lock); +#endif + + return (unsigned char*)src - buf; +} + +/*********************************************************************/ +/* flash_write_to_buffer */ +/*********************************************************************/ +static int cfi_flash_write_to_buffer(unsigned short sector, unsigned char *buf) +{ + int nbytes = cfi_flash_get_sector_size(sector); + int offset; + +#ifndef _CFE_ + down(&cfi_flash_lock); +#endif + + for( offset = 0; offset < nbytes; offset += meminfo.write_buffer_size ) { + cfi_flash_command(FLASH_WRITE_BUF, sector, offset, (unsigned short) + meminfo.write_buffer_size, (unsigned short *) &buf[offset]); + if (cfi_flash_wait(sector, 0, 0) != STATUS_READY) + break; + } + +#ifndef _CFE_ + up(&cfi_flash_lock); +#endif + + return offset; +} + +/*********************************************************************/ +/* flash_wait utilizes the DQ6, DQ5, and DQ2 polling algorithms */ +/* described in the flash data book. It can quickly ascertain the */ +/* operational status of the flash device, and return an */ +/* appropriate status code (defined in flash.h) */ +/*********************************************************************/ +static int cfi_flash_wait(unsigned short sector, int offset, unsigned short data) +{ + volatile unsigned short *flashptr; /* flash window */ + unsigned short d1; + + flashptr = (unsigned short *) cfi_flash_get_memptr(sector); + + if (flashFamily == FLASH_AMD || flashFamily == FLASH_SST) { + do { +#ifndef _CFE_ + if (!in_interrupt()) { + set_tsk_need_resched(current); /* fake need_resched() to force schedule() */ + schedule(); + } +#endif + d1 = *flashptr; /* read data */ + d1 ^= *flashptr; /* read it again and see what toggled */ + if (d1 == 0) /* no toggles, nothing's happening */ + return STATUS_READY; + } while (!(d1 & 0x20)); + + d1 = *flashptr; /* read data */ + d1 ^= *flashptr; /* read it again and see what toggled */ + + if (d1 != 0) { + cfi_flash_command(FLASH_RESET, 0, 0, 0, NULL); + return STATUS_TIMEOUT; + } + } else if (flashFamily == FLASH_INTEL) { + flashptr[0] = 0x70; + /* Wait for completion */ + + do { +#ifndef _CFE_ + if (!in_interrupt()) { + set_tsk_need_resched(current); /* fake need_resched() to force schedule() */ + schedule(); + } +#endif + } while (!(*flashptr & 0x80)); + if (*flashptr & 0x30) { + flashptr[0] = 0x50; + cfi_flash_command(FLASH_RESET, 0, 0, 0, NULL); + return STATUS_TIMEOUT; + } + flashptr[0] = 0x50; + cfi_flash_command(FLASH_RESET, 0, 0, 0, NULL); + } + + return STATUS_READY; +} + +/*********************************************************************/ +/* flash_get_device_id() will perform an autoselect sequence on the */ +/* flash device, and return the device id of the component. */ +/* This function automatically resets to read mode. */ +/*********************************************************************/ +static unsigned short cfi_flash_get_device_id(void) +{ + volatile unsigned short *fwp; /* flash window */ + unsigned short answer; + + fwp = (unsigned short *) cfi_flash_get_memptr(0); + + cfi_flash_command(FLASH_READ_ID, 0, 0, 0, NULL); + answer = *(fwp + 1); + if (answer == ID_AM29LV320M) { + answer = *(fwp + 0xe); + answer = *(fwp + 0xf); + } + + cfi_flash_command(FLASH_RESET, 0, 0, 0, NULL); + return( (unsigned short) answer ); +} + +/*********************************************************************/ +/* flash_get_cfi() is the main CFI workhorse function. Due to it's */ +/* complexity and size it need only be called once upon */ +/* initializing the flash system. Once it is called, all operations */ +/* are performed by looking at the meminfo structure. */ +/* All possible care was made to make this algorithm as efficient as */ +/* possible. 90% of all operations are memory reads, and all */ +/* calculations are done using bit-shifts when possible */ +/*********************************************************************/ +static int cfi_flash_get_cfi(struct cfi_query *query, unsigned short *cfi_struct, + int flashFamily) +{ + volatile unsigned short *fwp; /* flash window */ + int i=0, temp=0; + + cfi_flash_command(FLASH_CFIQUERY, 0, 0, 0, NULL); + + if (cfi_struct == 0) + fwp = (unsigned short *) cfi_flash_get_memptr(0); + else + fwp = cfi_struct; + + /* Initial house-cleaning */ + for(i=0; i < 8; i++) { + query->erase_block[i].sector_size = 0; + query->erase_block[i].num_sectors = 0; + } + + /* If not 'QRY', then we dont have a CFI enabled device in the socket */ + if( fwp[0x10] != 'Q' && + fwp[0x11] != 'R' && + fwp[0x12] != 'Y') { + cfi_flash_command(FLASH_RESET, 0, 0, 0, NULL); + return(FLASH_API_ERROR); + } + + temp = fwp[0x27]; + query->device_size = (int) (((int)1) << temp); + + query->num_erase_blocks = fwp[0x2C]; + if(flashFamily == FLASH_SST) + query->num_erase_blocks = 1; + + for(i=0; i < query->num_erase_blocks; i++) { + query->erase_block[i].num_sectors = + fwp[(0x2D+(4*i))] + (fwp[0x2E + (4*i)] << 8); + query->erase_block[i].num_sectors++; + query->erase_block[i].sector_size = + 256 * (256 * fwp[(0x30+(4*i))] + fwp[(0x2F+(4*i))]); + } + + /* TBD. Add support for other flash families. */ + if(flashFamily == FLASH_AMD) + query->write_buffer_size = (1 << fwp[0x2a]); + else + query->write_buffer_size = 0; + + cfi_flash_command(FLASH_RESET, 0, 0, 0, NULL); + return(FLASH_API_OK); +} + +#ifndef _CFE_ +static int __init cfi_flash_sched_init(void) { + cfi_flash_sched = 1; /* voluntary schedule() enabled */ + return 0; +} +late_initcall(cfi_flash_sched_init); +#endif diff --git a/shared/opensource/flash/flash_api.c b/shared/opensource/flash/flash_api.c new file mode 100755 index 0000000..5b0ca76 --- /dev/null +++ b/shared/opensource/flash/flash_api.c @@ -0,0 +1,350 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/*************************************************************************** + * File Name : flash_api.c + * + * Description: This file contains the implementation of the wrapper functions + * for the flash device interface. + ***************************************************************************/ + +/** Includes. */ +#ifdef _CFE_ +#include "lib_types.h" +#include "lib_printf.h" +#include "lib_string.h" +#include "bcm_map.h" +#define printk printf +#else // Linux +#include <linux/kernel.h> +#include "bcm_map_part.h" +#endif + +#include "bcmtypes.h" +#include "bcm_hwdefs.h" +#include "flash_api.h" + +/** Externs. **/ +#if !defined(INC_CFI_FLASH_DRIVER) +#define INC_CFI_FLASH_DRIVER 0 +#endif + +#if !defined(INC_SPI_FLASH_DRIVER) +#define INC_SPI_FLASH_DRIVER 0 +#endif + +#if !defined(INC_NAND_FLASH_DRIVER) +#define INC_NAND_FLASH_DRIVER 0 +#endif + +#if !defined(INC_SPI_PROG_NAND) +#define INC_SPI_PROG_NAND 0 +#endif + +#if (INC_CFI_FLASH_DRIVER==1) +extern int cfi_flash_init(flash_device_info_t **flash_info); +#else +#define cfi_flash_init(x) FLASH_API_ERROR +#endif + +#if (INC_SPI_FLASH_DRIVER==1) +extern int spi_flash_init(flash_device_info_t **flash_info); +#else +#define spi_flash_init(x) FLASH_API_ERROR +#endif + +#if (INC_NAND_FLASH_DRIVER==1) || (INC_SPI_PROG_NAND==1) +extern int nand_flash_init(flash_device_info_t **flash_info); +#else +#define nand_flash_init(x) FLASH_API_ERROR +#endif + +/** Variables. **/ +static flash_device_info_t *g_flash_info = NULL; +#if (INC_SPI_PROG_NAND==1) +static flash_device_info_t *g_nand_flash_info = NULL; +static flash_device_info_t *g_spi_flash_info = NULL; +#endif + +/*************************************************************************** + * Function Name: display_flash_info + * Description : Displays information about the flash part. + * Returns : None. + ***************************************************************************/ +static void display_flash_info(int ret, flash_device_info_t *flash_info) +{ + switch (flash_info->flash_type) { + case FLASH_IFC_PARALLEL: + printk( "Parallel flash device"); + break; + + case FLASH_IFC_SPI: + printk( "Serial flash device"); + break; + + case FLASH_IFC_HS_SPI: + printk( "HS Serial flash device"); + break; + + case FLASH_IFC_NAND: + printk( "NAND flash device"); + break; + } + + if( ret == FLASH_API_OK ) { + printk(": name %s, id 0x%4.4x", + flash_info->flash_device_name, flash_info->flash_device_id); +#if (INC_SPI_PROG_NAND==1) + printk(" block %dKB", flash_info->fn_flash_get_sector_size(0) / 1024); + printk(" size %dKB", (*flash_info->fn_flash_get_total_size) () / 1024); +#else + if (flash_info->flash_type == FLASH_IFC_NAND) + printk(" block %dKB", flash_get_sector_size(0) / 1024); + printk(" size %dKB", flash_get_total_size() / 1024); +#endif + printk("\n"); + } + else { + printk( " id %4.4x is not supported.\n", flash_info->flash_device_id ); + } +} /* display_flash_info */ + +/*************************************************************************** + * Function Name: flash_init + * Description : Initialize flash part. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +int flash_init(void) +{ + int type = FLASH_IFC_UNKNOWN; + int ret = FLASH_API_ERROR; +#if (INC_SPI_PROG_NAND==1) + int ret_nand = FLASH_API_ERROR; +#endif + + /* If available, use bootstrap to decide which flash to use */ +#if defined(_BCM96816_) || defined(CONFIG_BCM96816) || defined(_BCM96368_) || defined(CONFIG_BCM96368) + unsigned int bootsel; +#if defined(_BCM96816_) || defined(CONFIG_BCM96816) + bootsel = MISC->miscStrapBus; +#elif defined(_BCM96368_) || defined(CONFIG_BCM96368) + bootsel = GPIO->StrapBus; +#endif + switch ((bootsel & MISC_STRAP_BUS_BOOT_SEL_MASK)>>MISC_STRAP_BUS_BOOT_SEL_SHIFT) { + case MISC_STRAP_BUS_BOOT_PARALLEL: + type = FLASH_IFC_PARALLEL; + break; + + case MISC_STRAP_BUS_BOOT_SERIAL: + type = FLASH_IFC_SPI; + break; + + case MISC_STRAP_BUS_BOOT_NAND: + type = FLASH_IFC_NAND; + break; + + } +#elif defined(_BCM96362_) || defined(CONFIG_BCM96362) || defined(_BCM96328_) || defined(CONFIG_BCM96328) + if( ((MISC->miscStrapBus & MISC_STRAP_BUS_BOOT_SEL_MASK) >> + MISC_STRAP_BUS_BOOT_SEL_SHIFT) == MISC_STRAP_BUS_BOOT_SERIAL ) + type = FLASH_IFC_SPI; + else + type = FLASH_IFC_NAND; +#endif + + switch (type) { + case FLASH_IFC_PARALLEL: + ret = cfi_flash_init( &g_flash_info ); + break; + + case FLASH_IFC_SPI: + ret = spi_flash_init( &g_flash_info ); +#if (INC_SPI_PROG_NAND==1) + ret_nand = nand_flash_init( &g_nand_flash_info ); +#endif + + break; + + case FLASH_IFC_NAND: + ret = nand_flash_init( &g_flash_info ); + break; + + case FLASH_IFC_UNKNOWN: + /* Try to detect flash chips, give priority to parallel flash */ + /* Our reference design has both, and we usually use parallel. */ + ret = cfi_flash_init( &g_flash_info ); + if (ret != FLASH_API_OK) { + ret = spi_flash_init( &g_flash_info ); + } + break; + } + + if (g_flash_info != NULL) { + display_flash_info(ret, g_flash_info); +#if (INC_SPI_PROG_NAND==1) + display_flash_info(ret_nand, g_nand_flash_info ); +#endif + } + else { + printk( "BCM Flash API. Flash device is not found.\n" ); + } + + return( ret ); +} /* flash_init */ + +/*************************************************************************** + * Function Name: flash_sector_erase_int + * Description : Erase the specfied flash sector. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +int flash_sector_erase_int(unsigned short sector) +{ + return( (g_flash_info) + ? (*g_flash_info->fn_flash_sector_erase_int) (sector) + : FLASH_API_ERROR ); +} /* flash_sector_erase_int */ + +/*************************************************************************** + * Function Name: flash_read_buf + * Description : Reads from flash memory. + * Returns : number of bytes read or FLASH_API_ERROR + ***************************************************************************/ +int flash_read_buf(unsigned short sector, int offset, unsigned char *buffer, + int numbytes) +{ + return( (g_flash_info) + ? (*g_flash_info->fn_flash_read_buf) (sector, offset, buffer, numbytes) + : FLASH_API_ERROR ); +} /* flash_read_buf */ + +/*************************************************************************** + * Function Name: flash_write_buf + * Description : Writes to flash memory. + * Returns : number of bytes written or FLASH_API_ERROR + ***************************************************************************/ +int flash_write_buf(unsigned short sector, int offset, unsigned char *buffer, + int numbytes) +{ + return( (g_flash_info) + ? (*g_flash_info->fn_flash_write_buf) (sector, offset, buffer, numbytes) + : FLASH_API_ERROR ); +} /* flash_write_buf */ + +/*************************************************************************** + * Function Name: flash_get_numsectors + * Description : Returns the number of sectors in the flash device. + * Returns : Number of sectors in the flash device. + ***************************************************************************/ +int flash_get_numsectors(void) +{ + return( (g_flash_info) + ? (*g_flash_info->fn_flash_get_numsectors) () + : FLASH_API_ERROR ); +} /* flash_get_numsectors */ + +/*************************************************************************** + * Function Name: flash_get_sector_size + * Description : Returns the number of bytes in the specfied flash sector. + * Returns : Number of bytes in the specfied flash sector. + ***************************************************************************/ +int flash_get_sector_size(unsigned short sector) +{ + return( (g_flash_info) + ? (*g_flash_info->fn_flash_get_sector_size) (sector) + : FLASH_API_ERROR ); +} /* flash_get_sector_size */ + +/*************************************************************************** + * Function Name: flash_get_memptr + * Description : Returns the base MIPS memory address for the specfied flash + * sector. + * Returns : Base MIPS memory address for the specfied flash sector. + ***************************************************************************/ +unsigned char *flash_get_memptr(unsigned short sector) +{ + return( (g_flash_info) + ? (*g_flash_info->fn_flash_get_memptr) (sector) + : NULL ); +} /* flash_get_memptr */ + +/*************************************************************************** + * Function Name: flash_get_blk + * Description : Returns the flash sector for the specfied MIPS address. + * Returns : Flash sector for the specfied MIPS address. + ***************************************************************************/ +int flash_get_blk(int addr) +{ + return( (g_flash_info) + ? (*g_flash_info->fn_flash_get_blk) (addr) + : FLASH_API_ERROR ); +} /* flash_get_blk */ + +/*************************************************************************** + * Function Name: flash_get_total_size + * Description : Returns the number of bytes in the flash device. + * Returns : Number of bytes in the flash device. + ***************************************************************************/ +int flash_get_total_size(void) +{ + return( (g_flash_info) + ? (*g_flash_info->fn_flash_get_total_size) () + : FLASH_API_ERROR ); +} /* flash_get_total_size */ + +/*************************************************************************** + * Function Name: flash_get_flash_type + * Description : Returns type of the flash memory. + * Returns : Type of the flash memory. + ***************************************************************************/ +int flash_get_flash_type(void) +{ + return( (g_flash_info) + ? (g_flash_info->flash_type) + : FLASH_API_ERROR ); +} /* flash_get_flash_type */ + +#if (INC_SPI_PROG_NAND==1) +/*************************************************************************** + * Function Name: flash_change_flash_type + * Description : change type of the flash memory. + * Returns : none + ***************************************************************************/ +void flash_change_flash_type(int type) +{ + + if (type == FLASH_IFC_NAND) + { + if (g_spi_flash_info == NULL) + g_spi_flash_info = g_flash_info; + g_flash_info = g_nand_flash_info; + } + else + { + if (g_spi_flash_info != NULL) + g_flash_info = g_spi_flash_info; + } +} /* flash_change_flash_type */ + +#endif + diff --git a/shared/opensource/flash/flash_common.c b/shared/opensource/flash/flash_common.c new file mode 100755 index 0000000..0d4a75d --- /dev/null +++ b/shared/opensource/flash/flash_common.c @@ -0,0 +1,280 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/*!\file flash_common.c + * \brief This file contains NOR flash related functions used by both + * CFE and kernel. + * + */ + +/** Includes. */ +#ifdef _CFE_ +#include "lib_types.h" +#include "lib_printf.h" +#include "lib_string.h" +#include "bcm_map.h" +#define printk printf +#else // Linux +#include <linux/kernel.h> +#include "bcm_map_part.h" +#endif + +#include "bcmtypes.h" +#include "bcm_hwdefs.h" +#include "flash_api.h" +#include "flash_common.h" + +// #define DEBUG_FLASH + +void flash_init_info(const NVRAM_DATA *nvRam, FLASH_ADDR_INFO *fInfo) +{ + int i = 0; + int totalBlks = 0; + int totalSize = 0; + int psiStartAddr = 0; + int spStartAddr = 0; + int usedBlkSize = 0; + int needBytes = 0; + + if (flash_get_flash_type() == FLASH_IFC_NAND) + { + /* When using NAND flash disable Bcm_flash */ + totalSize = 0; + } + else { + totalBlks = flash_get_numsectors(); + totalSize = flash_get_total_size(); + printk("Total Flash size: %dK with %d sectors\n", totalSize/1024, totalBlks); + } + + if (totalSize <= FLASH_LENGTH_BOOT_ROM) { + /* NAND flash settings. NAND flash does not use raw flash partitioins + * to store psi, backup psi, scratch pad and syslog. These data items + * are stored as files on a JFFS2 file system. + */ + if ((nvRam->ulPsiSize != -1) && (nvRam->ulPsiSize != 0)) + fInfo->flash_persistent_length = nvRam->ulPsiSize * ONEK; + else + fInfo->flash_persistent_length = DEFAULT_PSI_SIZE * ONEK; + + fInfo->flash_persistent_start_blk = 0; + fInfo->flash_rootfs_start_offset = 0; + fInfo->flash_scratch_pad_length = SP_MAX_LEN; + fInfo->flash_syslog_length = nvRam->ulSyslogSize * 1024; + + /* This is a boolean field for NAND flash. */ + fInfo->flash_backup_psi_number_blk = nvRam->backupPsi; + return; + } + + /* + * calculate mandatory primary PSI size and set its fInfo parameters. + */ + if ((nvRam->ulPsiSize != -1) && (nvRam->ulPsiSize != 0)) + fInfo->flash_persistent_length = nvRam->ulPsiSize * ONEK; + else + fInfo->flash_persistent_length = DEFAULT_PSI_SIZE * ONEK; + + psiStartAddr = totalSize - fInfo->flash_persistent_length; + fInfo->flash_persistent_start_blk = flash_get_blk(FLASH_BASE+psiStartAddr); + fInfo->flash_persistent_number_blk = totalBlks - fInfo->flash_persistent_start_blk; + + usedBlkSize = 0; + for (i = fInfo->flash_persistent_start_blk; + i < (fInfo->flash_persistent_start_blk + fInfo->flash_persistent_number_blk); i++) + { + usedBlkSize += flash_get_sector_size((unsigned short) i); + } + fInfo->flash_persistent_blk_offset = usedBlkSize - fInfo->flash_persistent_length; + fInfo->flash_meta_start_blk = fInfo->flash_persistent_start_blk; + + /* + * Next is the optional scratch pad, which is on top of the primary PSI. + * Old code allowed scratch pad to share a sector with primary PSI. + * That is retained for backward compatibility. (Although depending on your + * NOR flash sector sizes, they may still be in different sectors.) + * If you have a new deployment, consider forcing separate sectors. + */ + if ((fInfo->flash_persistent_blk_offset > 0) && + (fInfo->flash_persistent_blk_offset < SP_MAX_LEN)) + { + /* + * there is some room left in the first persistent sector, but it is + * not big enough for the scratch pad. (Use this line unconditionally + * if you want to guarentee scratch pad and primary PSI are on different + * sectors.) + */ + spStartAddr = psiStartAddr - fInfo->flash_persistent_blk_offset - SP_MAX_LEN; + } + else + { + /* either the primary PSI starts on a sector boundary, or there is + * enough room at the top of the first sector for the scratch pad. */ + spStartAddr = psiStartAddr - SP_MAX_LEN ; + } + + fInfo->flash_scratch_pad_start_blk = flash_get_blk(FLASH_BASE+spStartAddr); + fInfo->flash_scratch_pad_length = SP_MAX_LEN; + + if (fInfo->flash_persistent_start_blk == fInfo->flash_scratch_pad_start_blk) // share blk + { +#if 0 /* do not used scratch pad unless it's in its own sector */ + printk("Scratch pad is not used for this flash part.\n"); + fInfo->flash_scratch_pad_length = 0; // no sp +#else /* allow scratch pad to share a sector with another section such as PSI */ + fInfo->flash_scratch_pad_number_blk = 1; + fInfo->flash_scratch_pad_blk_offset = fInfo->flash_persistent_blk_offset - fInfo->flash_scratch_pad_length; +#endif + } + else // on different blk + { + fInfo->flash_scratch_pad_number_blk = fInfo->flash_persistent_start_blk - fInfo->flash_scratch_pad_start_blk; + // find out the offset in the start_blk + usedBlkSize = 0; + for (i = fInfo->flash_scratch_pad_start_blk; + i < (fInfo->flash_scratch_pad_start_blk + fInfo->flash_scratch_pad_number_blk); i++) + usedBlkSize += flash_get_sector_size((unsigned short) i); + fInfo->flash_scratch_pad_blk_offset = usedBlkSize - fInfo->flash_scratch_pad_length; + } + + if (fInfo->flash_scratch_pad_length > 0) { + + fInfo->flash_meta_start_blk = fInfo->flash_scratch_pad_start_blk; + } + + /* + * Next is the optional backup PSI. + */ + if (nvRam->backupPsi == 0x01) + { + needBytes = fInfo->flash_persistent_length; + i = fInfo->flash_meta_start_blk; + while (needBytes > 0) + { + i--; + needBytes -= flash_get_sector_size((unsigned short) i); + } + fInfo->flash_backup_psi_start_blk = i; + /* calclate how many blocks we actually consumed */ + needBytes = fInfo->flash_persistent_length; + fInfo->flash_backup_psi_number_blk = 0; + while (needBytes > 0) + { + needBytes -= flash_get_sector_size((unsigned short) i); + i++; + fInfo->flash_backup_psi_number_blk++; + } + + fInfo->flash_meta_start_blk = fInfo->flash_backup_psi_start_blk; + } + else + { + fInfo->flash_backup_psi_number_blk = 0; + } + + /* + * Next is the optional persistent syslog. + */ + if (nvRam->ulSyslogSize != 0 && nvRam->ulSyslogSize != -1) + { + fInfo->flash_syslog_length = nvRam->ulSyslogSize * 1024; + needBytes = fInfo->flash_syslog_length; + i = fInfo->flash_meta_start_blk; + while (needBytes > 0) + { + i--; + needBytes -= flash_get_sector_size((unsigned short) i); + } + fInfo->flash_syslog_start_blk = i; + /* calclate how many blocks we actually consumed */ + needBytes = fInfo->flash_syslog_length; + fInfo->flash_syslog_number_blk = 0; + while (needBytes > 0) + { + needBytes -= flash_get_sector_size((unsigned short) i); + i++; + fInfo->flash_syslog_number_blk++; + } + + fInfo->flash_meta_start_blk = fInfo->flash_syslog_start_blk; + } + else + { + fInfo->flash_syslog_length = 0; + fInfo->flash_syslog_number_blk = 0; + } + +#ifdef DEBUG_FLASH_TOO_MUCH + /* dump sizes of all sectors in flash */ + for (i=0; i<totalBlks; i++) + printk("blk %03d: %d\n", i, flash_get_sector_size((unsigned short) i)); +#endif + +#if defined(DEBUG_FLASH) + printk("FLASH_BASE =0x%08x\n\n", (unsigned int)FLASH_BASE); + + printk("fInfo->flash_rootfs_start_offset =0x%08x\n\n", (unsigned int)fInfo->flash_rootfs_start_offset); + + printk("fInfo->flash_meta_start_blk = %d\n\n", fInfo->flash_meta_start_blk); + + printk("fInfo->flash_syslog_start_blk = %d\n", fInfo->flash_syslog_start_blk); + printk("fInfo->flash_syslog_number_blk = %d\n", fInfo->flash_syslog_number_blk); + printk("fInfo->flash_syslog_length=0x%x\n\n", (unsigned int)fInfo->flash_syslog_length); + + printk("fInfo->flash_backup_psi_start_blk = %d\n", fInfo->flash_backup_psi_start_blk); + printk("fInfo->flash_backup_psi_number_blk = %d\n\n", fInfo->flash_backup_psi_number_blk); + + printk("sp startAddr = %x\n", (unsigned int) (FLASH_BASE+spStartAddr)); + printk("fInfo->flash_scratch_pad_start_blk = %d\n", fInfo->flash_scratch_pad_start_blk); + printk("fInfo->flash_scratch_pad_number_blk = %d\n", fInfo->flash_scratch_pad_number_blk); + printk("fInfo->flash_scratch_pad_length = 0x%x\n", fInfo->flash_scratch_pad_length); + printk("fInfo->flash_scratch_pad_blk_offset = 0x%x\n\n", (unsigned int)fInfo->flash_scratch_pad_blk_offset); + + printk("psi startAddr = %x\n", (unsigned int) (FLASH_BASE+psiStartAddr)); + printk("fInfo->flash_persistent_start_blk = %d\n", fInfo->flash_persistent_start_blk); + printk("fInfo->flash_persistent_number_blk = %d\n", fInfo->flash_persistent_number_blk); + printk("fInfo->flash_persistent_length=0x%x\n", (unsigned int)fInfo->flash_persistent_length); + printk("fInfo->flash_persistent_blk_offset = 0x%x\n\n", (unsigned int)fInfo->flash_persistent_blk_offset); +#endif +} + +unsigned int flash_get_reserved_bytes_at_end(const FLASH_ADDR_INFO *fInfo) +{ + unsigned int reserved=0; + int i = fInfo->flash_meta_start_blk; + int totalBlks = flash_get_numsectors(); + + while (i < totalBlks) + { + reserved += flash_get_sector_size((unsigned short) i); + i++; + } + +#if defined(DEBUG_FLASH) + printk("reserved at bottom=%dKB\n", reserved/1024); +#endif + + return reserved; +} + diff --git a/shared/opensource/flash/nandflash.c b/shared/opensource/flash/nandflash.c new file mode 100755 index 0000000..b90ad7b --- /dev/null +++ b/shared/opensource/flash/nandflash.c @@ -0,0 +1,1260 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/*************************************************************************** + * File Name : nandflash.c + * + * Description: This file implements the Broadcom DSL defined flash api for + * for NAND flash parts. + ***************************************************************************/ + +/** Includes. **/ + +#include "lib_types.h" +#include "lib_printf.h" +#include "lib_string.h" +#include "lib_malloc.h" +#include "bcm_map.h" +#include "bcmtypes.h" +#include "bcm_hwdefs.h" +#include "flash_api.h" +#include "jffs2.h" +#if defined(CFG_RAMAPP) && (INC_SPI_FLASH_DRIVER==1) +#include "cfe_timer.h" +#endif + +/* for debugging in jtag */ +#if !defined(CFG_RAMAPP) +#define static +#endif + + +/** Defines. **/ + +#define NR_OOB_SCAN_PAGES 4 +#define SPARE_MAX_SIZE 64 +#define PAGE_MAX_SIZE 2048 +#define CTRLR_SPARE_SIZE 16 +#define CTRLR_CACHE_SIZE 512 + +/* Flash manufacturers. */ +#define FLASHTYPE_SAMSUNG 0xec +#define FLASHTYPE_ST 0x20 +#define FLASHTYPE_MICRON 0x2c + +/* Samsung flash parts. */ +#define SAMSUNG_K9F5608U0A 0x55 + +/* ST flash parts. */ +#define ST_NAND512W3A2CN6 0x76 +#define ST_NAND01GW3B2CN6 0xf1 + +/* Micron flash parts. */ +#define MICRON_MT29F1G08AAC 0xf1 + +/* Flash id to name mapping. */ +#define NAND_MAKE_ID(A,B) \ + (((unsigned short) (A) << 8) | ((unsigned short) B & 0xff)) + +#define NAND_FLASH_DEVICES \ + {{NAND_MAKE_ID(FLASHTYPE_SAMSUNG,SAMSUNG_K9F5608U0A),"Samsung K9F5608U0"}, \ + {NAND_MAKE_ID(FLASHTYPE_ST,ST_NAND512W3A2CN6),"ST NAND512W3A2CN6"}, \ + {NAND_MAKE_ID(FLASHTYPE_ST,ST_NAND01GW3B2CN6),"ST NAND01GW3B2CN6"}, \ + {NAND_MAKE_ID(FLASHTYPE_MICRON,MICRON_MT29F1G08AAC),"Micron MT29F1G08AAC"},\ + {0,""} \ + } + +/* One byte for small page NAND flash parts. */ +#define SPARE_SP_BI_INDEX_1 5 +#define SPARE_SP_BI_INDEX_2 5 + +/* Two bytes for small page NAND flash parts. */ +#define SPARE_LP_BI_INDEX_1 0 +#define SPARE_LP_BI_INDEX_2 1 + +#define SPARE_BI_MARKER 0 +#define SPARE_BI_ECC_MASK \ + {0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0} + +#define JFFS2_CLEANMARKER {JFFS2_MAGIC_BITMASK, \ + JFFS2_NODETYPE_CLEANMARKER, 0x0000, 0x0008} + +#undef DEBUG_NAND +#if defined(DEBUG_NAND) && defined(CFG_RAMAPP) +#define DBG_PRINTF printf +#else +#define DBG_PRINTF(...) +#endif + + +/** Externs. **/ + +extern void board_setleds(unsigned long); + + +/** Structs. **/ + +typedef struct CfeNandChip +{ + char *chip_name; + unsigned long chip_device_id; + unsigned long chip_base; + unsigned long chip_total_size; + unsigned long chip_block_size; + unsigned long chip_page_size; + unsigned long chip_spare_size; + unsigned char *chip_spare_mask; + unsigned long chip_bi_index_1; + unsigned long chip_bi_index_2; +} CFE_NAND_CHIP, *PCFE_NAND_CHIP; + +struct flash_name_from_id +{ + unsigned short fnfi_id; + char fnfi_name[30]; +}; + + +#if defined(CFG_RAMAPP) +/** Prototypes for CFE RAM. **/ +int nand_flash_init(flash_device_info_t **flash_info); +int mpinand_flash_init(flash_device_info_t **flash_info); +static void nand_init_cleanmarker(PCFE_NAND_CHIP pchip); +static void nand_read_cfg(PCFE_NAND_CHIP pchip); +static int nand_is_blk_cleanmarker(PCFE_NAND_CHIP pchip, + unsigned long start_addr, int write_if_not); +static int nand_initialize_spare_area(PCFE_NAND_CHIP pchip); +static void nand_mark_bad_blk(PCFE_NAND_CHIP pchip, unsigned long page_addr); +static int nand_flash_sector_erase_int(unsigned short blk); +static int nand_flash_read_buf(unsigned short blk, int offset, + unsigned char *buffer, int len); +static int nand_flash_write_buf(unsigned short blk, int offset, + unsigned char *buffer, int numbytes); +static int nand_flash_get_numsectors(void); +static int nand_flash_get_sector_size(unsigned short sector); +static unsigned char *nand_flash_get_memptr(unsigned short sector); +static int nand_flash_get_blk(int addr); +static int nand_flash_get_total_size(void); +static int nandflash_wait_status(unsigned long status_mask); +static int nandflash_read_spare_area(PCFE_NAND_CHIP pchip, + unsigned long page_addr, unsigned char *buffer, int len); +static int nandflash_write_spare_area(PCFE_NAND_CHIP pchip, + unsigned long page_addr, unsigned char *buffer, int len); +static int nandflash_read_page(PCFE_NAND_CHIP pchip, + unsigned long start_addr, unsigned char *buffer, int len); +static int nandflash_write_page(PCFE_NAND_CHIP pchip, unsigned long start_addr, + unsigned char *buffer, int len); +static int nandflash_block_erase(PCFE_NAND_CHIP pchip, unsigned long blk_addr); +#else +/** Prototypes for CFE ROM. **/ +void rom_nand_flash_init(void); +static int nand_is_blk_cleanmarker(PCFE_NAND_CHIP pchip, + unsigned long start_addr, int write_if_not); +static void nand_read_cfg(PCFE_NAND_CHIP pchip); +int nand_flash_get_sector_size(unsigned short sector); +int nand_flash_get_numsectors(void); +static int nandflash_wait_status(unsigned long status_mask); +static int nandflash_read_spare_area(PCFE_NAND_CHIP pchip, + unsigned long page_addr, unsigned char *buffer, int len); +static int nandflash_read_page(PCFE_NAND_CHIP pchip, unsigned long start_addr, + unsigned char *buffer, int len); +int nand_flash_read_buf(unsigned short blk, int offset, + unsigned char *buffer, int len); +static inline void nandflash_copy_from_cache(unsigned char *buffer, + int offset, int numbytes); +static inline void nandflash_copy_from_spare(unsigned char *buffer, + int numbytes); +static int nandflash_wait_status(unsigned long status_mask); +static inline int nandflash_wait_cmd(void); +static inline int nandflash_wait_device(void); +static inline int nandflash_wait_cache(void); +static inline int nandflash_wait_spare(void); +static int nandflash_check_ecc(void); +#endif + + +#if defined(CFG_RAMAPP) +/** Variables for CFE RAM. **/ +CFE_NAND_CHIP g_chip = {NULL,0,0,0,0,0,0}; +static unsigned char g_spare_mask[] = SPARE_BI_ECC_MASK; +static unsigned char g_spare_cleanmarker[SPARE_MAX_SIZE]; + +static flash_device_info_t flash_nand_dev = + { + 0xffff, + FLASH_IFC_NAND, + "", + nand_flash_sector_erase_int, + nand_flash_read_buf, + nand_flash_write_buf, + nand_flash_get_numsectors, + nand_flash_get_sector_size, + nand_flash_get_memptr, + nand_flash_get_blk, + nand_flash_get_total_size + }; + +#else +/** Variables for CFE ROM. **/ +CFE_NAND_CHIP g_chip; +static unsigned char g_spare_mask[] = SPARE_BI_ECC_MASK; +#endif + + +#if defined(CFG_RAMAPP) +/*************************************************************************** + * Function Name: nand_flash_init + * Description : Initialize flash part. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +int nand_flash_init(flash_device_info_t **flash_info) +{ + static int initialized = 0; + int ret = FLASH_API_OK; + + if( initialized == 0 ) + { + PCFE_NAND_CHIP pchip = &g_chip; + static struct flash_name_from_id fnfi[] = NAND_FLASH_DEVICES; + struct flash_name_from_id *fnfi_ptr; + + DBG_PRINTF(">> nand_flash_init - entry\n"); + + /* Enable NAND data on MII ports. */ +#if !defined(_BCM96328_) + PERF->blkEnables |= NAND_CLK_EN; +#endif +#if defined(_BCM96362_) && (INC_SPI_FLASH_DRIVER==1) + GPIO->GPIOBaseMode |= NAND_GPIO_OVERRIDE; +#endif + NAND->NandNandBootConfig = NBC_AUTO_DEV_ID_CFG | 2; +#if (INC_SPI_FLASH_DRIVER==1) + cfe_usleep(1000); +#endif + /* Read the NAND flash chip id. Only use the most signficant 16 bits.*/ + pchip->chip_device_id = NAND->NandFlashDeviceId >> 16; + flash_nand_dev.flash_device_id = pchip->chip_device_id; + + for( fnfi_ptr = fnfi; fnfi_ptr->fnfi_id != 0; fnfi_ptr++ ) + { + if( fnfi_ptr->fnfi_id == pchip->chip_device_id ) + { + strcpy(flash_nand_dev.flash_device_name, fnfi_ptr->fnfi_name); + break; + } + } + + /* If NAND chip is not in the list of NAND chips, the correct + * configuration maybe still have been set by the NAND controller. + */ + if( flash_nand_dev.flash_device_name[0] == '\0' ) + strcpy(flash_nand_dev.flash_device_name, "<not identified>"); + + *flash_info = &flash_nand_dev; + + NAND->NandCsNandXor = 0; + pchip->chip_base = 0; + nand_read_cfg(pchip); + nand_init_cleanmarker(pchip); + + /* If the first block's spare area is not a JFFS2 cleanmarker, + * initialize all block's spare area to a cleanmarker. + */ + if( !nand_is_blk_cleanmarker(pchip, 0, 0) ) + ret = nand_initialize_spare_area(pchip); + + DBG_PRINTF(">> nand_flash_init - return %d\n", ret); + + initialized = 1; + } + else + *flash_info = &flash_nand_dev; + + return( ret ); +} /* nand_flash_init */ + +/*************************************************************************** + * Function Name: nand_init_cleanmarker + * Description : Initializes the JFFS2 clean marker buffer. + * Returns : None. + ***************************************************************************/ +static void nand_init_cleanmarker(PCFE_NAND_CHIP pchip) +{ + unsigned short cleanmarker[] = JFFS2_CLEANMARKER; + unsigned char *pcm = (unsigned char *) cleanmarker; + int i, j; + + /* Skip spare area offsets reserved for ECC bytes. */ + for( i = 0, j = 0; i < pchip->chip_spare_size; i++ ) + { + if( pchip->chip_spare_mask[i] == 0 && j < sizeof(cleanmarker)) + g_spare_cleanmarker[i] = pcm[j++]; + else + g_spare_cleanmarker[i] = 0xff; + } +} /* nand_init_cleanmarker */ + +#else +/*************************************************************************** + * Function Name: rom_nand_flash_init + * Description : Initialize flash part just enough to read blocks. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +void rom_nand_flash_init(void) +{ + PCFE_NAND_CHIP pchip = &g_chip; + + /* Enable NAND data on MII ports. */ +#if !defined(_BCM96328_) + PERF->blkEnables |= NAND_CLK_EN; +#endif + NAND->NandNandBootConfig = NBC_AUTO_DEV_ID_CFG | 2; + + pchip->chip_base = 0; + + /* Read the chip id. Only use the most signficant 16 bits. */ + pchip->chip_device_id = NAND->NandFlashDeviceId >> 16; + + if( pchip->chip_device_id > 0 && pchip->chip_device_id < 0xffff ) + nand_read_cfg(pchip); + else + board_setleds(0x4d494532); +} /* nand_flash_init */ +#endif + +/*************************************************************************** + * Function Name: nand_read_cfg + * Description : Reads and stores the chip configuration. + * Returns : None. + ***************************************************************************/ +static void nand_read_cfg(PCFE_NAND_CHIP pchip) +{ + /* Read chip configuration. */ + unsigned long cfg = NAND->NandConfig; + + pchip->chip_total_size = + (4 * (1 << ((cfg & NC_DEV_SIZE_MASK) >> NC_DEV_SIZE_SHIFT))) << 20; + + switch( (cfg & NC_BLK_SIZE_MASK) ) + { + case NC_BLK_SIZE_512K: + pchip->chip_block_size = 512 * 1024; + break; + + case NC_BLK_SIZE_128K: + pchip->chip_block_size = 128 * 1024; + break; + + case NC_BLK_SIZE_16K: + pchip->chip_block_size = 16 * 1024; + break; + + case NC_BLK_SIZE_8K: + pchip->chip_block_size = 8 * 1024; + break; + } + + if( (cfg & NC_PG_SIZE_MASK) == NC_PG_SIZE_512B ) + { + pchip->chip_page_size = 512; + pchip->chip_bi_index_1 = SPARE_SP_BI_INDEX_1; + pchip->chip_bi_index_2 = SPARE_SP_BI_INDEX_2; + } + else + { + pchip->chip_page_size = 2048; + pchip->chip_bi_index_1 = SPARE_LP_BI_INDEX_1; + pchip->chip_bi_index_2 = SPARE_LP_BI_INDEX_2; + } + + pchip->chip_spare_mask = g_spare_mask; + pchip->chip_spare_mask[pchip->chip_bi_index_1] = 1; + pchip->chip_spare_mask[pchip->chip_bi_index_2] = 1; + + pchip->chip_spare_size = pchip->chip_page_size >> 5; + + DBG_PRINTF(">> nand_read_cfg - size=%luMB, block=%luKB, page=%luB, " + "spare=%lu\n", pchip->chip_total_size / (1024 * 1024), + pchip->chip_block_size / 1024, pchip->chip_page_size, + pchip->chip_spare_size); +} /* nand_read_cfg */ + +/*************************************************************************** + * Function Name: nand_is_blk_cleanmarker + * Description : Compares a buffer to see if it a JFFS2 cleanmarker. + * Returns : 1 - is cleanmarker, 0 - is not cleanmarker + ***************************************************************************/ +static int nand_is_blk_cleanmarker(PCFE_NAND_CHIP pchip, + unsigned long start_addr, int write_if_not) +{ + unsigned short cleanmarker[] = JFFS2_CLEANMARKER; + unsigned char *pcm = (unsigned char *) cleanmarker; + unsigned char spare[SPARE_MAX_SIZE], comparebuf[SPARE_MAX_SIZE]; + unsigned long i, j; + int ret = 0; + + if( nandflash_read_spare_area( pchip, start_addr, spare, + pchip->chip_spare_size) == FLASH_API_OK ) + { + /* Skip spare offsets that are reserved for the ECC. Make spare data + * bytes contiguous in the spare buffer. + */ + for( i = 0, j = 0; i < pchip->chip_spare_size; i++ ) + if( pchip->chip_spare_mask[i] == 0 ) + comparebuf[j++] = spare[i]; + + /* Compare spare area data to the JFFS2 cleanmarker. */ + for( i = 0, ret = 1; i < sizeof(cleanmarker) && ret == 1; i++ ) + if( comparebuf[i] != pcm[i]) + ret = 0; + } + +#if defined(CFG_RAMAPP) + if( ret == 0 && spare[pchip->chip_bi_index_1] != SPARE_BI_MARKER && + spare[pchip->chip_bi_index_2] != SPARE_BI_MARKER && write_if_not ) + { + /* The spare area is not a clean marker but the block is not bad. + * Write a clean marker to this block. (Assumes the block is erased.) + */ + if( nandflash_write_spare_area(pchip, start_addr, (unsigned char *) + g_spare_cleanmarker, pchip->chip_spare_size) == FLASH_API_OK ) + { + ret = nand_is_blk_cleanmarker(pchip, start_addr, 0); + } + } +#endif + + return( ret ); +} /* nand_is_blk_cleanmarker */ + +#if defined(CFG_RAMAPP) +/*************************************************************************** + * Function Name: nand_initialize_spare_area + * Description : Initializes the spare area of the first page of each block + * to a cleanmarker. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +static int nand_initialize_spare_area(PCFE_NAND_CHIP pchip) +{ + unsigned char spare[SPARE_MAX_SIZE]; + unsigned long i; + int ret; + + DBG_PRINTF(">> nand_initialize_spare_area - entry\n"); + + for( i = 0; i < pchip->chip_total_size; i += pchip->chip_block_size ) + { + /* Read the current spare area. */ + ret = nandflash_read_spare_area(pchip,0,spare,pchip->chip_spare_size); + if(ret == FLASH_API_OK + /*&& spare[pchip->chip_bi_index_1] != SPARE_BI_MARKER*/ + /*&& spare[pchip->chip_bi_index_2] != SPARE_BI_MARKER*/) + { + if( nandflash_block_erase(pchip, i) == FLASH_API_OK ) + { + nandflash_write_spare_area(pchip, i, (unsigned char *) + g_spare_cleanmarker, pchip->chip_spare_size); + } + } + } + + return( FLASH_API_OK ); +} /* nand_initialize_spare_area */ + + +/*************************************************************************** + * Function Name: nand_mark_bad_blk + * Description : Marks the specified block as bad by writing 0xFFs to the + * spare area and updating the in memory bad block table. + * Returns : None. + ***************************************************************************/ +static void nand_mark_bad_blk(PCFE_NAND_CHIP pchip, unsigned long page_addr) +{ + static int marking_bad_blk = 0; + + unsigned char spare[SPARE_MAX_SIZE]; + + if( marking_bad_blk == 0 ) + { + marking_bad_blk = 1; + DBG_PRINTF(">> nand_mark_bad_blk - addr=0x%8.8lx, block=0x%8.8lx\n", + page_addr, page_addr / pchip->chip_block_size); + + nandflash_block_erase(pchip, page_addr); + memset(spare, 0xff, pchip->chip_spare_size); + spare[pchip->chip_bi_index_1] = SPARE_BI_MARKER; + spare[pchip->chip_bi_index_2] = SPARE_BI_MARKER; + nandflash_write_spare_area(pchip,page_addr,spare,pchip->chip_spare_size); + marking_bad_blk = 0; + } +} /* nand_mark_bad_blk */ + + +/*************************************************************************** + * Function Name: nand_flash_sector_erase_int + * Description : Erase the specfied flash sector. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +static int nand_flash_sector_erase_int(unsigned short blk) +{ + int ret = FLASH_API_OK; + PCFE_NAND_CHIP pchip = &g_chip; + + if( blk == NAND_REINIT_FLASH ) + nand_initialize_spare_area(pchip); + else + { + unsigned long page_addr = blk * pchip->chip_block_size; + + /* Only erase the block if the spare area is a JFFS2 cleanmarker. + * Assume that the only the CFE boot loader only touches JFFS2 blocks. + * This check prevents the Linux NAND MTD driver bad block block table + * from being erased. The NAND_REINIT_FLASH option unconditionally + * erases all NAND flash blocks. + */ + if( nand_is_blk_cleanmarker(pchip, page_addr, 0) ) + { + ret = nandflash_block_erase(pchip, page_addr); + nandflash_write_spare_area(pchip, page_addr, g_spare_cleanmarker, + pchip->chip_spare_size); + } + + DBG_PRINTF(">> nand_flash_sector_erase_int - blk=0x%8.8lx, ret=%d\n", + blk, ret); + } + + return( ret ); +} /* nand_flash_sector_erase_int */ +#endif + +/*************************************************************************** + * Function Name: nand_flash_read_buf + * Description : Reads from flash memory. + * Returns : number of bytes read or FLASH_API_ERROR + ***************************************************************************/ +#if defined(CFG_RAMAPP) +static +#endif +int nand_flash_read_buf(unsigned short blk, int offset, unsigned char *buffer, + int len) +{ + int ret = len; + PCFE_NAND_CHIP pchip = &g_chip; + UINT32 start_addr; + UINT32 blk_addr; + UINT32 blk_offset; + UINT32 size; + + DBG_PRINTF(">> nand_flash_read_buf - 1 blk=0x%8.8lx, offset=%d, len=%lu\n", + blk, offset, len); + + start_addr = (blk * pchip->chip_block_size) + offset; + blk_addr = start_addr & ~(pchip->chip_block_size - 1); + blk_offset = start_addr - blk_addr; + size = pchip->chip_block_size - blk_offset; + + if(size > len) + size = len; + + do + { + if(nandflash_read_page(pchip,start_addr,buffer,size) != FLASH_API_OK) + { + ret = FLASH_API_ERROR; + break; + } + + len -= size; + if( len ) + { + blk++; + + DBG_PRINTF(">> nand_flash_read_buf - 2 blk=0x%8.8lx, len=%lu\n", + blk, len); + + start_addr = blk * pchip->chip_block_size; + buffer += size; + if(len > pchip->chip_block_size) + size = pchip->chip_block_size; + else + size = len; + } + } while(len); + + DBG_PRINTF(">> nand_flash_read_buf - ret=%d\n", ret); + + return( ret ) ; +} /* nand_flash_read_buf */ + +#if defined(CFG_RAMAPP) +/*************************************************************************** + * Function Name: nand_flash_write_buf + * Description : Writes to flash memory. + * Returns : number of bytes written or FLASH_API_ERROR + ***************************************************************************/ +static int nand_flash_write_buf(unsigned short blk, int offset, + unsigned char *buffer, int len) +{ + int ret = len; + PCFE_NAND_CHIP pchip = &g_chip; + UINT32 start_addr; + UINT32 blk_addr; + UINT32 blk_offset; + UINT32 size; + + DBG_PRINTF(">> nand_flash_write_buf - 1 blk=0x%8.8lx, offset=%d, len=%d\n", + blk, offset, len); + + start_addr = (blk * pchip->chip_block_size) + offset; + blk_addr = start_addr & ~(pchip->chip_block_size - 1); + blk_offset = start_addr - blk_addr; + size = pchip->chip_block_size - blk_offset; + + if(size > len) + size = len; + + do + { + if(nandflash_write_page(pchip,start_addr,buffer,size) != FLASH_API_OK) + { + ret = ret - len; + break; + } + else + { + len -= size; + if( len ) + { + blk++; + + DBG_PRINTF(">> nand_flash_write_buf- 2 blk=0x%8.8lx, len=%d\n", + blk, len); + + offset = 0; + start_addr = blk * pchip->chip_block_size; + buffer += size; + if(len > pchip->chip_block_size) + size = pchip->chip_block_size; + else + size = len; + } + } + } while(len); + + DBG_PRINTF(">> nand_flash_write_buf - ret=%d\n", ret); + + return( ret ) ; +} /* nand_flash_write_buf */ + +/*************************************************************************** + * Function Name: nand_flash_get_memptr + * Description : Returns the base MIPS memory address for the specfied flash + * sector. + * Returns : Base MIPS memory address for the specfied flash sector. + ***************************************************************************/ +static unsigned char *nand_flash_get_memptr(unsigned short sector) +{ + /* Bad things will happen if this pointer is referenced. But it can + * be used for pointer arithmetic to deterine sizes. + */ + return((unsigned char *) (FLASH_BASE + (sector * g_chip.chip_block_size))); +} /* nand_flash_get_memptr */ + +/*************************************************************************** + * Function Name: nand_flash_get_blk + * Description : Returns the flash sector for the specfied MIPS address. + * Returns : Flash sector for the specfied MIPS address. + ***************************************************************************/ +static int nand_flash_get_blk(int addr) +{ + return( (addr - FLASH_BASE) / g_chip.chip_block_size ); +} /* nand_flash_get_blk */ + +/*************************************************************************** + * Function Name: nand_flash_get_total_size + * Description : Returns the number of bytes in the "CFE Linux code" + * partition. + * Returns : Number of bytes + ***************************************************************************/ +static int nand_flash_get_total_size(void) +{ + return(g_chip.chip_total_size); +} /* nand_flash_get_total_size */ +#endif + +/*************************************************************************** + * Function Name: nand_flash_get_sector_size + * Description : Returns the number of bytes in the specfied flash sector. + * Returns : Number of bytes in the specfied flash sector. + ***************************************************************************/ +#if defined(CFG_RAMAPP) +static +#endif +int nand_flash_get_sector_size(unsigned short sector) +{ + return(g_chip.chip_block_size); +} /* nand_flash_get_sector_size */ + +/*************************************************************************** + * Function Name: nand_flash_get_numsectors + * Description : Returns the number of blocks in the "CFE Linux code" + * partition. + * Returns : Number of blocks + ***************************************************************************/ +#if defined(CFG_RAMAPP) +static +#endif +int nand_flash_get_numsectors(void) +{ + return(g_chip.chip_total_size / g_chip.chip_block_size); +} /* nand_flash_get_numsectors */ + + +/*************************************************************************** + * NAND Flash Implementation Functions + ***************************************************************************/ + +/*************************************************************************** + * Function Name: nandflash_copy_from_cache + * Description : Copies data from the chip NAND cache to a local memory + * buffer. + * Returns : None. + ***************************************************************************/ +static inline void nandflash_copy_from_cache(unsigned char *buffer, + int offset, int numbytes) +{ + unsigned char *cache = (unsigned char *) NAND_CACHE; + + /* XXX memcpy will only work for 32-bit aligned data */ + memcpy(buffer, &cache[offset], numbytes); +} /* nandflash_copy_from_cache */ + +/*************************************************************************** + * Function Name: nandflash_copy_from_spare + * Description : Copies data from the chip NAND spare registers to a local + * memory buffer. + * Returns : None. + ***************************************************************************/ +static inline void nandflash_copy_from_spare(unsigned char *buffer, + int numbytes) +{ + unsigned long *spare_area = (unsigned long *) &NAND->NandSpareAreaReadOfs0; + + /* XXX memcpy will only work for 32-bit aligned data */ + memcpy(buffer, spare_area, numbytes); +} /* nandflash_copy_from_spare */ + +#if defined(CFG_RAMAPP) +/*************************************************************************** + * Function Name: nandflash_copy_to_cache + * Description : Copies data from a local memory buffer to the the chip NAND + * cache. + * Returns : None. + ***************************************************************************/ +static inline void nandflash_copy_to_cache(unsigned char *buffer, int offset, + int numbytes) +{ + unsigned char *cache = (unsigned char *) NAND_CACHE; + unsigned long i; + + for( i = 0; i < numbytes; i += sizeof(long) ) + *(unsigned long *) &cache[i] = + ((unsigned long) buffer[i + 0] << 24) | + ((unsigned long) buffer[i + 1] << 16) | + ((unsigned long) buffer[i + 2] << 8) | + ((unsigned long) buffer[i + 3] << 0); +} /* nandflash_copy_to_cache */ + +/*************************************************************************** + * Function Name: nandflash_copy_to_spare + * Description : Copies data from a local memory buffer to the the chip NAND + * spare registers. + * Returns : None. + ***************************************************************************/ +static inline void nandflash_copy_to_spare(unsigned char *buffer,int numbytes) +{ + unsigned long *spare_area = (unsigned long *) &NAND->NandSpareAreaWriteOfs0; + unsigned long *pbuff = (unsigned long *)buffer; + int i; + + for(i=0; i< numbytes / sizeof(unsigned long); ++i) + spare_area[i] = pbuff[i]; +} /* nandflash_copy_to_spare */ +#endif + +/*************************************************************************** + * Function Name: nandflash_wait_status + * Description : Polls the NAND status register waiting for a condition. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +static int nandflash_wait_status(unsigned long status_mask) +{ + + const unsigned long nand_poll_max = 1000000; + unsigned long data; + unsigned long poll_count = 0; + int ret = FLASH_API_OK; + + do + { + data = NAND->NandIntfcStatus; + } while(!(status_mask & data) && (++poll_count < nand_poll_max)); + + if(poll_count >= nand_poll_max) + { + printf("Status wait timeout: nandsts=0x%8.8lx mask=0x%8.8lx, count=" + "%lu\n", NAND->NandIntfcStatus, status_mask, poll_count); + ret = FLASH_API_ERROR; + } + + return( ret ); +} /* nandflash_wait_status */ + +static inline int nandflash_wait_cmd(void) +{ + return nandflash_wait_status(NIS_CTLR_READY); +} /* nandflash_wait_cmd */ + +static inline int nandflash_wait_device(void) +{ + return nandflash_wait_status(NIS_FLASH_READY); +} /* nandflash_wait_device */ + +static inline int nandflash_wait_cache(void) +{ + return nandflash_wait_status(NIS_CACHE_VALID); +} /* nandflash_wait_cache */ + +static inline int nandflash_wait_spare(void) +{ + return nandflash_wait_status(NIS_SPARE_VALID); +} /* nandflash_wait_spare */ + +#if defined(CFG_RAMAPP) +/*************************************************************************** + * Function Name: nandflash_check_ecc + * Description : Reads ECC status. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +static int nandflash_check_ecc(void) +{ + int ret = FLASH_API_OK; + UINT32 intrCtrl; + UINT32 accessCtrl; + + /* read interrupt status */ + intrCtrl = NAND_INTR->NandInterrupt; + accessCtrl = NAND->NandAccControl; + + + if( (intrCtrl & NINT_ECC_ERROR_UNC) != 0 ) + { + printf("Uncorrectable ECC Error detected: addr=0x%8.8lx, intrCtrl=0x" + "%08X, accessCtrl=0x%08X\n", NAND->NandEccUncAddr, (UINT)intrCtrl, + (UINT)accessCtrl); + ret = FLASH_API_ERROR; + } + + if( (intrCtrl & NINT_ECC_ERROR_CORR) != 0 ) + { + printf("Correctable ECC Error detected: addr=0x%8.8lx, intrCtrl=0x" + "%08X, accessCtrl=0x%08X\n", NAND->NandEccCorrAddr, (UINT)intrCtrl, + (UINT)accessCtrl); + } + + return( ret ); +} +#else +static int nandflash_check_ecc(void) +{ + return( FLASH_API_OK ); +} +#endif + +/*************************************************************************** + * Function Name: nandflash_read_spare_area + * Description : Reads the spare area for the specified page. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +static int nandflash_read_spare_area(PCFE_NAND_CHIP pchip, + unsigned long page_addr, unsigned char *buffer, int len) +{ + int ret = FLASH_API_ERROR; + + if( len >= pchip->chip_spare_size ) + { + UINT32 steps = pchip->chip_spare_size / CTRLR_SPARE_SIZE; + UINT32 i; + + for( i = 0; i < steps; i++ ) + { + NAND->NandCmdAddr = pchip->chip_base + page_addr + + (i * CTRLR_CACHE_SIZE); + NAND->NandCmdExtAddr = 0; + NAND->NandCmdStart = NCMD_SPARE_READ; + + if( (ret = nandflash_wait_cmd()) == FLASH_API_OK ) + { + /* wait until data is available in the spare area registers */ + if( (ret = nandflash_wait_spare()) == FLASH_API_OK ) + nandflash_copy_from_spare(buffer + (i * CTRLR_SPARE_SIZE), + CTRLR_SPARE_SIZE); + else + break; + } + else + break; + } + } + + return ret; +} /* nandflash_read_spare_area */ + +#if defined(CFG_RAMAPP) +/*************************************************************************** + * Function Name: nandflash_write_spare_area + * Description : Reads the spare area for the specified page. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +static int nandflash_write_spare_area(PCFE_NAND_CHIP pchip, + unsigned long page_addr, unsigned char *buffer, int len) +{ + int ret = FLASH_API_OK; + unsigned char spare[SPARE_MAX_SIZE]; + + if( len <= pchip->chip_spare_size ) + { + UINT32 steps = pchip->chip_spare_size / CTRLR_SPARE_SIZE; + UINT32 i; + + memset(spare, 0xff, pchip->chip_spare_size); + memcpy(spare, buffer, len); + + for( i = 0; i < steps; i++ ) + { + NAND->NandCmdAddr = pchip->chip_base + page_addr + + (i * CTRLR_CACHE_SIZE); + NAND->NandCmdExtAddr = 0; + + nandflash_copy_to_spare(spare + (i * CTRLR_SPARE_SIZE), + CTRLR_SPARE_SIZE); + + NAND->NandCmdStart = NCMD_PROGRAM_SPARE; + if( (ret = nandflash_wait_cmd()) == FLASH_API_OK ) + { + unsigned long sts = NAND->NandIntfcStatus; + + if( (sts & NIS_PGM_ERASE_ERROR) != 0 ) + { + printf("Error writing to spare area, sts=0x%8.8lx\n", sts); + nand_mark_bad_blk(pchip, page_addr); + ret = FLASH_API_ERROR; + } + } + } + } + else + ret = FLASH_API_ERROR; + + /* Reset spare area to default value. */ + memset(spare, 0xff, CTRLR_SPARE_SIZE); + nandflash_copy_to_spare(spare, CTRLR_SPARE_SIZE); + + return( ret ); +} /* nandflash_write_spare_area */ +#endif + +/*************************************************************************** + * Function Name: nandflash_read_page + * Description : Reads up to a NAND block of pages into the specified buffer. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +static int nandflash_read_page(PCFE_NAND_CHIP pchip, unsigned long start_addr, + unsigned char *buffer, int len) +{ + int ret = FLASH_API_ERROR; + + if( len <= pchip->chip_block_size ) + { + UINT32 page_addr = start_addr & ~(pchip->chip_page_size - 1); + UINT32 page_offset = start_addr - page_addr; + UINT32 size = pchip->chip_page_size - page_offset; + UINT32 index = 0; + + /* Verify that the spare area contains a JFFS2 cleanmarker. */ + if( nand_is_blk_cleanmarker(pchip, page_addr, 0) ) + { + UINT32 i; + + if(size > len) + size = len; + + do + { + for( i = 0, ret = FLASH_API_OK; i < pchip->chip_page_size && + ret == FLASH_API_OK; i += CTRLR_CACHE_SIZE) + { + /* clear interrupts, so we can check later for ECC errors */ + NAND_INTR->NandInterrupt = NINT_STS_MASK; + + /* send command */ + NAND->NandCmdAddr = pchip->chip_base + page_addr + i; + NAND->NandCmdExtAddr = 0; + NAND->NandCmdStart = NCMD_PAGE_READ; + + if( (ret = nandflash_wait_cmd()) == FLASH_API_OK ) + { + /* wait until data is available in the cache */ + if( (ret = nandflash_wait_cache()) == FLASH_API_OK ) + { + /* TBD. get return status for ECC errors and + * process them. + */ + nandflash_check_ecc(); /* check for ECC errors */ + } + + if( ret == FLASH_API_OK ) + { + if( i < size ) + { + UINT32 copy_size = + (i + CTRLR_CACHE_SIZE <= size) + ? CTRLR_CACHE_SIZE : size - i; + + nandflash_copy_from_cache(&buffer[index + i], + page_offset, copy_size); + } + } + else + { + /* TBD. Do something. */ + } + } + } + + if(ret != FLASH_API_OK) + break; + + page_offset = 0; + page_addr += pchip->chip_page_size; + index += size; + len -= size; + if(len > pchip->chip_page_size) + size = pchip->chip_page_size; + else + size = len; + } while(len); + } + else + { + DBG_PRINTF("nandflash_read_page: cleanmarker not found at 0x%8.8lx\n", + page_addr); + } + } + + return( ret ) ; +} /* nandflash_read_page */ + +#if defined(CFG_RAMAPP) +/*************************************************************************** + * Function Name: nandflash_write_page + * Description : Writes up to a NAND block of pages from the specified buffer. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +static int nandflash_write_page(PCFE_NAND_CHIP pchip, unsigned long start_addr, + unsigned char *buffer, int len) +{ + int ret = FLASH_API_ERROR; + + if( len <= pchip->chip_block_size ) + { + unsigned char xfer_buf[CTRLR_CACHE_SIZE]; + UINT32 page_addr = start_addr & ~(pchip->chip_page_size - 1); + UINT32 page_offset = start_addr - page_addr; + UINT32 size = pchip->chip_page_size - page_offset; + UINT32 index = 0; + + /* Verify that the spare area contains a JFFS2 cleanmarker. */ + if( nand_is_blk_cleanmarker(pchip, page_addr, 1) ) + { + UINT32 steps = pchip->chip_page_size / CTRLR_CACHE_SIZE; + UINT32 i, xfer_ofs, xfer_size; + + if(size > len) + size = len; + + do + { + for( i = 0, xfer_ofs = 0, xfer_size = 0, ret = FLASH_API_OK; + i < steps && ret==FLASH_API_OK; i++) + { + memset(xfer_buf, 0xff, sizeof(xfer_buf)); + + if(size - xfer_ofs > CTRLR_CACHE_SIZE) + xfer_size = CTRLR_CACHE_SIZE; + else + xfer_size = size - xfer_ofs; + + if( xfer_size ) + memcpy(xfer_buf + page_offset, buffer + index + + xfer_ofs, xfer_size); + + xfer_ofs += xfer_size; + + NAND->NandCmdAddr = pchip->chip_base + page_addr + + (i * CTRLR_CACHE_SIZE); + NAND->NandCmdExtAddr = 0; + + nandflash_copy_to_cache(xfer_buf, 0, CTRLR_CACHE_SIZE); + + NAND->NandCmdStart = NCMD_PROGRAM_PAGE; + if( (ret = nandflash_wait_cmd()) == FLASH_API_OK ) + { + unsigned long sts = NAND->NandIntfcStatus; + + if( (sts & NIS_PGM_ERASE_ERROR) != 0 ) + { + printf("Error writing to block, sts=0x%8.8lx\n", sts); + nand_mark_bad_blk(pchip, + start_addr & ~(pchip->chip_page_size - 1)); + ret = FLASH_API_ERROR; + } + } + } + + if(ret != FLASH_API_OK) + break; + + page_offset = 0; + page_addr += pchip->chip_page_size; + index += size; + len -= size; + if(len > pchip->chip_page_size) + size = pchip->chip_page_size; + else + size = len; + } while(len); + } + else + DBG_PRINTF("nandflash_write_page: cleanmarker not found at 0x%8.8lx\n", + page_addr); + } + + return( ret ); +} /* nandflash_write_page */ + +/*************************************************************************** + * Function Name: nandflash_block_erase + * Description : Erases a block. + * Returns : FLASH_API_OK or FLASH_API_ERROR + ***************************************************************************/ +static int nandflash_block_erase(PCFE_NAND_CHIP pchip, unsigned long blk_addr ) +{ + + int ret = FLASH_API_OK; + + /* send command */ + NAND->NandCmdAddr = pchip->chip_base + blk_addr; + NAND->NandCmdExtAddr = 0; + NAND->NandCmdStart = NCMD_BLOCK_ERASE; + if( (ret = nandflash_wait_cmd()) == FLASH_API_OK ) + { + unsigned long sts = NAND->NandIntfcStatus; + + if( (sts & NIS_PGM_ERASE_ERROR) != 0 ) + { + printf("Error erasing block 0x%8.8lx, sts=0x%8.8lx\n", + blk_addr, sts); + nand_mark_bad_blk(pchip, blk_addr); + ret = FLASH_API_ERROR; + } + } + + DBG_PRINTF(">> nandflash_block_erase - addr=0x%8.8lx, ret=%d\n", blk_addr, + ret); + + return( ret ); +} /* nandflash_block_erase */ + +void dump_spare(void); +void dump_spare(void) +{ + PCFE_NAND_CHIP pchip = &g_chip; + unsigned char spare[SPARE_MAX_SIZE]; + unsigned long i; + + for( i = 0; i < pchip->chip_total_size; i += pchip->chip_block_size ) + { + if( nandflash_read_spare_area(pchip, i, spare, + pchip->chip_spare_size) == FLASH_API_OK ) + { + printf("%8.8lx: %8.8lx %8.8lx %8.8lx %8.8lx\n", i, + *(unsigned long *) &spare[0], *(unsigned long *) &spare[4], + *(unsigned long *) &spare[8], *(unsigned long *) &spare[12]); + if( pchip->chip_spare_size == SPARE_MAX_SIZE ) + { + printf("%8.8lx: %8.8lx %8.8lx %8.8lx %8.8lx\n", i, + *(unsigned long *)&spare[16],*(unsigned long *)&spare[20], + *(unsigned long *)&spare[24],*(unsigned long *)&spare[28]); + printf("%8.8lx: %8.8lx %8.8lx %8.8lx %8.8lx\n", i, + *(unsigned long *)&spare[32],*(unsigned long *)&spare[36], + *(unsigned long *)&spare[40],*(unsigned long *)&spare[44]); + printf("%8.8lx: %8.8lx %8.8lx %8.8lx %8.8lx\n", i, + *(unsigned long *)&spare[48],*(unsigned long *)&spare[52], + *(unsigned long *)&spare[56],*(unsigned long *)&spare[60]); + } + } + else + printf("Error reading spare 0x%8.8lx\n", i); + } +} + +int read_spare_data(int blk, unsigned char *buf, int bufsize); +int read_spare_data(int blk, unsigned char *buf, int bufsize) +{ + PCFE_NAND_CHIP pchip = &g_chip; + unsigned char spare[SPARE_MAX_SIZE]; + unsigned long page_addr = blk * pchip->chip_block_size; + unsigned long i, j; + int ret; + + if( (ret = nandflash_read_spare_area( pchip, page_addr, spare, + pchip->chip_spare_size)) == FLASH_API_OK ) + { + /* Skip spare offsets that are reserved for the ECC. Make spare data + * bytes contiguous in the spare buffer. + */ + for( i = 0, j = 0; i < pchip->chip_spare_size; i++ ) + if( pchip->chip_spare_mask[i] == 0 && j < bufsize ) + buf[j++] = spare[i]; + } + + return(ret); +} + +#endif + diff --git a/shared/opensource/flash/spiflash.c b/shared/opensource/flash/spiflash.c new file mode 100755 index 0000000..38f4648 --- /dev/null +++ b/shared/opensource/flash/spiflash.c @@ -0,0 +1,969 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/** Includes. **/ +#ifdef _CFE_ +#include "lib_types.h" +#include "lib_printf.h" +#include "lib_string.h" +#include "bcm_map.h" +#define printk printf +#else // linux +#include <linux/version.h> +#include <linux/param.h> +#include <linux/sched.h> +#include <linux/timer.h> +#include <linux/kernel.h> +#include <linux/interrupt.h> +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) +#include <linux/semaphore.h> +#endif +#include <linux/hardirq.h> + +#include <bcm_map_part.h> +#endif + +#include "bcmtypes.h" +#include "bcm_hwdefs.h" +#include "flash_api.h" +#include "bcmSpiRes.h" + + +/** Defines. **/ +#define OSL_DELAY(X) \ + do { { int i; for( i = 0; i < (X) * 500; i++ ) ; } } while(0) + +#define MAX_RETRY 3 + +#ifndef NULL +#define NULL 0 +#endif + +#define MAXSECTORS 8192 /* maximum number of sectors supported */ + +#define FLASH_PAGE_256 256 +#define SECTOR_SIZE_4K (4 * 1024) +#define SECTOR_SIZE_64K (64 * 1024) + +/* Standard Boolean declarations */ +#define TRUE 1 +#define FALSE 0 + +/* Command codes for the flash_command routine */ +#define FLASH_WRST 0x01 /* write status register */ +#define FLASH_PROG 0x02 /* program data into memory array */ +#define FLASH_READ 0x03 /* read data from memory array */ +#define FLASH_WRDI 0x04 /* reset write enable latch */ +#define FLASH_RDSR 0x05 /* read status register */ +#define FLASH_WREN 0x06 /* set write enable latch */ +#define FLASH_READ_FAST 0x0B /* read data from memory array */ +#define FLASH_SERASE 0x20 /* erase one sector in memory array */ +#define FLASH_BERASE 0xD8 /* erase one block in memory array */ +#define FLASH_RDID 0x9F /* read manufacturer and product id */ +#define FLASH_EN4B 0xB7 /* Enable 4 byte address mode */ + +/* RDSR return status bit definition */ +#define SR_WPEN 0x80 +#define SR_BP3 0x20 +#define SR_BP2 0x10 +#define SR_BP1 0x08 +#define SR_BP0 0x04 +#define SR_WEN 0x02 +#define SR_RDY 0x01 + +/* Return codes from flash_status */ +#define STATUS_READY 0 /* ready for action */ +#define STATUS_BUSY 1 /* operation in progress */ +#define STATUS_TIMEOUT 2 /* operation timed out */ +#define STATUS_ERROR 3 /* unclassified but unhappy status */ + +/* Define different type of flash */ +#define FLASH_UNDEFINED 0 +#define FLASH_SPAN 2 + +/* SST's manufacturer ID */ +#define SSTPART 0xBF +/* A list of SST device IDs */ +#define ID_SST25VF016 0x41 +#define ID_SST25VF032 0x4A +#define ID_SST25VF064 0x4B + +/* SPANSION manufacturer IDs */ +#define SPANPART 0x01 +/* SPANSION device ID's */ +#define ID_SPAN25FL016 0x14 +#define ID_SPAN25FL032 0x15 +#define ID_SPAN25FL064 0x16 +#define ID_SPAN25FL128 0x18 + +/* EON manufacturer ID */ +#define EONPART 0x1C +/* NUMONYX manufacturer ID */ +#define NUMONYXPART 0x20 +/* AMIC manufacturer ID */ +#define AMICPART 0x37 +/* Macronix manufacturer ID */ +#define MACRONIXPART 0xC2 +/* Winbond's manufacturer ID */ +#define WBPART 0xEF + +/* JEDEC device IDs */ +#define ID_M25P16 0x15 +#define ID_M25P32 0x16 +#define ID_M25P64 0x17 +#define ID_M25P128 0x18 +#define ID_M25P256 0x19 + +#define SPI_MAKE_ID(A,B) \ + (((unsigned short) (A) << 8) | ((unsigned short) B & 0xff)) + +#define SPI_FLASH_DEVICES \ + {{SPI_MAKE_ID(SSTPART, ID_SST25VF016), "SST25VF016"}, \ + {SPI_MAKE_ID(SSTPART, ID_SST25VF032), "SST25VF032"}, \ + {SPI_MAKE_ID(SSTPART, ID_SST25VF064), "SST25VF064"}, \ + {SPI_MAKE_ID(SPANPART, ID_SPAN25FL016), "S25FL016"}, \ + {SPI_MAKE_ID(SPANPART, ID_SPAN25FL032), "S25FL032"}, \ + {SPI_MAKE_ID(SPANPART, ID_SPAN25FL064), "S25FL064"}, \ + {SPI_MAKE_ID(SPANPART, ID_SPAN25FL128), "S25FL128"}, \ + {SPI_MAKE_ID(WBPART, ID_M25P16), "ID_W25X16"}, \ + {SPI_MAKE_ID(WBPART, ID_M25P32), "ID_W25X32"}, \ + {SPI_MAKE_ID(WBPART, ID_M25P64), "ID_W25X64"}, \ + {SPI_MAKE_ID(WBPART, ID_M25P128), "ID_W25X128"}, \ + {SPI_MAKE_ID(EONPART, ID_M25P16), "EN25P16"}, \ + {SPI_MAKE_ID(EONPART, ID_M25P32), "EN25P32"}, \ + {SPI_MAKE_ID(EONPART, ID_M25P64), "EN25P64"}, \ + {SPI_MAKE_ID(EONPART, ID_M25P128), "EN25P128"}, \ + {SPI_MAKE_ID(AMICPART, ID_M25P16), "A25L016"}, \ + {SPI_MAKE_ID(AMICPART, ID_M25P32), "A25L032"}, \ + {SPI_MAKE_ID(NUMONYXPART, ID_M25P16), "NMNXM25P16"}, \ + {SPI_MAKE_ID(NUMONYXPART, ID_M25P32), "NMNXM25P32"}, \ + {SPI_MAKE_ID(NUMONYXPART, ID_M25P64), "NMNXM25P64"}, \ + {SPI_MAKE_ID(NUMONYXPART, ID_M25P128), "NMNXM25P128"}, \ + {SPI_MAKE_ID(MACRONIXPART, ID_M25P16), "MX25L16"}, \ + {SPI_MAKE_ID(MACRONIXPART, ID_M25P32), "MX25L32"}, \ + {SPI_MAKE_ID(MACRONIXPART, ID_M25P64), "MX25L64"}, \ + {SPI_MAKE_ID(MACRONIXPART, ID_M25P128), "MX25L128"}, \ + {SPI_MAKE_ID(MACRONIXPART, ID_M25P256), "MX25L256"}, \ + {0,""} \ + } + +/** Structs. **/ +/* A structure for identifying a flash part. There is one for each + * of the flash part definitions. We need to keep track of the + * sector organization, the address register used, and the size + * of the sectors. + */ +struct flashinfo { + char *name; /* "AT25F512", etc. */ + unsigned long addr; /* physical address, once translated */ + int nsect; /* # of sectors */ + struct { + long size; /* # of bytes in this sector */ + long base; /* offset from beginning of device */ + } sec[MAXSECTORS]; /* per-sector info */ +}; + +struct flash_name_from_id { + unsigned short fnfi_id; + char fnfi_name[30]; +}; + + +/** Prototypes. **/ +static int my_spi_read( unsigned char *msg_buf, int prependcnt, int nbytes ); +static int my_spi_write( unsigned char *msg_buf, int nbytes ); + +int spi_flash_init(flash_device_info_t **flash_info); +static int spi_flash_sector_erase_int(unsigned short sector); +static int spi_flash_reset(void); +static int spi_flash_read_buf(unsigned short sector, int offset, + unsigned char *buffer, int nbytes); +static int spi_flash_ub(unsigned short sector); +static int spi_flash_write(unsigned short sector, int offset, + unsigned char *buffer, int nbytes); +static int spi_flash_write_buf(unsigned short sector, int offset, + unsigned char *buffer, int nbytes); +static int spi_flash_get_numsectors(void); +static int spi_flash_get_sector_size(unsigned short sector); +static unsigned char *spi_get_flash_memptr(unsigned short sector); +static unsigned char *spi_flash_get_memptr(unsigned short sector); +static int spi_flash_status(void); +static unsigned short spi_flash_get_device_id(unsigned short sector); +static int spi_flash_get_blk(int addr); +static int spi_flash_get_total_size(void); +static int spi_flash_en4b(void); + +/** Variables. **/ +static flash_device_info_t flash_spi_dev = + { + 0xffff, + FLASH_IFC_SPI, + "", + spi_flash_sector_erase_int, + spi_flash_read_buf, + spi_flash_write_buf, + spi_flash_get_numsectors, + spi_flash_get_sector_size, + spi_flash_get_memptr, + spi_flash_get_blk, + spi_flash_get_total_size + }; + +static struct flash_name_from_id fnfi[] = SPI_FLASH_DEVICES; + +/* the controller will handle operati0ns that are greater than the FIFO size + code that relies on READ_BUF_LEN_MAX, READ_BUF_LEN_MIN or spi_max_op_len + could be changed */ +#define READ_BUF_LEN_MAX 544 /* largest of the maximum transaction sizes for SPI */ +#define READ_BUF_LEN_MIN 60 /* smallest of the maximum transaction sizes for SPI */ +/* this is the slave ID of the SPI flash for use with the SPI controller */ +#define SPI_FLASH_SLAVE_DEV_ID 0 +/* clock defines for the flash */ +#define SPI_FLASH_DEF_CLOCK 781000 + +/* default to smallest transaction size - updated later */ +static int spi_max_op_len = READ_BUF_LEN_MIN; +static int fastRead = TRUE; +static int flash_page_size = FLASH_PAGE_256; + +/* default to legacy controller - updated later */ +static int spi_flash_clock = SPI_FLASH_DEF_CLOCK; +static int spi_flash_busnum = LEG_SPI_BUS_NUM; + +#ifndef _CFE_ +static DECLARE_MUTEX(spi_flash_lock); +static bool bSpiFlashSlaveRes = FALSE; +#endif + +static struct flashinfo meminfo; /* Flash information structure */ +static int totalSize = 0; +static int addr32 = FALSE; + +static int my_spi_read(unsigned char *msg_buf, int prependcnt, int nbytes) +{ + int status; + +#ifndef _CFE_ + if ( FALSE == bSpiFlashSlaveRes ) +#endif + { + status = BcmSpi_Read(msg_buf, prependcnt, nbytes, spi_flash_busnum, SPI_FLASH_SLAVE_DEV_ID, spi_flash_clock); + } +#ifndef _CFE_ + else + { + /* the Linux SPI framework provides a non blocking mechanism for SPI transfers. While waiting for a spi + transaction to complete the kernel will look to see if another process can run. This scheduling + can only occur if kernel preemption is active. The SPI flash interfaces can be run when kernel + preemption is enabled or disabled. When kernel preemption is disabled we cannot use the framework */ + if ( in_atomic() ) + status = BcmSpi_Read(msg_buf, prependcnt, nbytes, spi_flash_busnum, SPI_FLASH_SLAVE_DEV_ID, spi_flash_clock); + else + status = BcmSpiSyncTrans(NULL, msg_buf, prependcnt, nbytes, spi_flash_busnum, SPI_FLASH_SLAVE_DEV_ID); + } +#endif + + return status; +} + +static int my_spi_write(unsigned char *msg_buf, int nbytes) +{ + int status; + +#ifndef _CFE_ + if ( FALSE == bSpiFlashSlaveRes ) +#endif + { + status = BcmSpi_Write(msg_buf, nbytes, spi_flash_busnum, SPI_FLASH_SLAVE_DEV_ID, spi_flash_clock); + } +#ifndef _CFE_ + else + { + /* the Linux SPI framework provides a non blocking mechanism for SPI transfers. While waiting for a spi + transaction to complete the kernel will look to see if another process can run. This scheduling + can only occur if kernel preemtion is active. The SPI flash interfaces can be run when kernel + preemption is enabled or disabled. When kernel preemption is disabled we cannot use the framework */ + if ( in_atomic() ) + status = BcmSpi_Write(msg_buf, nbytes, spi_flash_busnum, SPI_FLASH_SLAVE_DEV_ID, spi_flash_clock); + else + status = BcmSpiSyncTrans(msg_buf, NULL, 0, nbytes, spi_flash_busnum, SPI_FLASH_SLAVE_DEV_ID); + } +#endif + return status; +} + + +/*********************************************************************/ +/* Init_flash is used to build a sector table. This information is */ +/* translated from erase_block information to base:offset information*/ +/* for each individual sector. This information is then stored */ +/* in the meminfo structure, and used throughout the driver to access*/ +/* sector information. */ +/* */ +/* This is more efficient than deriving the sector base:offset */ +/* information every time the memory map switches (since on the */ +/* development platform can only map 64k at a time). If the entire */ +/* flash memory array can be mapped in, then the addition static */ +/* allocation for the meminfo structure can be eliminated, but the */ +/* drivers will have to be re-written. */ +/* */ +/* The meminfo struct occupies 44 bytes of heap space, depending */ +/* on the value of the define MAXSECTORS. Adjust to suit */ +/* application */ +/*********************************************************************/ + +int spi_flash_init(flash_device_info_t **flash_info) +{ + struct flash_name_from_id *fnfi_ptr; + int i=0, count=0; + int basecount=0L; + unsigned short device_id; + int sectorsize = 0; + int numsector = 0; + +#if defined(_BCM96816_) || defined(CONFIG_BCM96816) + uint32 miscStrapBus = MISC->miscStrapBus; + + if ( miscStrapBus & MISC_STRAP_BUS_LS_SPIM_ENABLED ) + { + spi_flash_busnum = LEG_SPI_BUS_NUM; + if ( miscStrapBus & MISC_STRAP_BUS_SPI_CLK_FAST ) + { + spi_flash_clock = 20000000; + } + else + { + spi_flash_clock = 781000; + } + } + else + { + spi_flash_busnum = HS_SPI_BUS_NUM; + if ( miscStrapBus & MISC_STRAP_BUS_SPI_CLK_FAST ) + { + spi_flash_clock = 40000000; + } + else + { + spi_flash_clock = 20000000; + } + } +#endif +#if defined(_BCM96328_) || defined(CONFIG_BCM96328) || defined(_BCM96362_) || defined(CONFIG_BCM96362) + spi_flash_busnum = HS_SPI_BUS_NUM; + spi_flash_clock = 40000000; +#endif +#if defined(_BCM96368_) || defined(CONFIG_BCM96368) + uint32 miscStrapBus = GPIO->StrapBus; + + if ( miscStrapBus & (1 << 6) ) + spi_flash_clock = 20000000; + else + spi_flash_clock = 781000; +#endif + + /* retrieve the maximum read/write transaction length from the SPI controller */ + spi_max_op_len = BcmSpi_GetMaxRWSize( spi_flash_busnum ); + + if (HS_SPI_BUS_NUM == spi_flash_busnum) + flash_spi_dev.flash_type = FLASH_IFC_HS_SPI; + + *flash_info = &flash_spi_dev; + +#if 0 + /* + * in case of flash corrupt, the following steps can erase the flash + * 1. jumper USE_SPI_SLAVE to make SPI in slave mode + * 2. start up JTAG debuger and remove the USE_SPI_SLAVE jumper + * 3. run the following code to erase the flash + */ + flash_sector_erase_int(0); + flash_sector_erase_int(1); + printk("flash_init: erase all sectors\n"); + return FLASH_API_OK; +#endif + + flash_spi_dev.flash_device_id = device_id = spi_flash_get_device_id(0); + + switch( device_id >> 8 ) { + case SSTPART: + sectorsize = SECTOR_SIZE_4K; + switch ((unsigned char)(device_id & 0x00ff)) { + case ID_SST25VF016: + numsector = 512; + break; + case ID_SST25VF032: + numsector = 1024; + break; + case ID_SST25VF064: + numsector = 2048; + break; + } + break; + + case SPANPART: + sectorsize = SECTOR_SIZE_64K; + switch ((unsigned short)(device_id & 0x00ff)) { + case ID_SPAN25FL016: + numsector = 32; + break; + case ID_SPAN25FL032: + numsector = 64; + break; + case ID_SPAN25FL064: + numsector = 128; + break; + case ID_SPAN25FL128: + numsector = 256; + break; + } + break; + + case EONPART: + sectorsize = SECTOR_SIZE_64K; + switch ((unsigned short)(device_id & 0x00ff)) { + case ID_M25P16: + numsector = 32; + break; + case ID_M25P32: + numsector = 64; + break; + case ID_M25P64: + numsector = 128; + break; + case ID_M25P128: + numsector = 256; + break; + } + break; + + case NUMONYXPART: + case MACRONIXPART: + case WBPART: + case AMICPART: + sectorsize = SECTOR_SIZE_4K; + switch ((unsigned short)(device_id & 0x00ff)) { + case ID_M25P16: + numsector = 512; + break; + case ID_M25P32: + numsector = 1024; + break; + case ID_M25P64: + numsector = 2048; + break; + case ID_M25P128: + numsector = 4096; + break; + case ID_M25P256: + addr32 = TRUE; + numsector = 8192; + break; + } + break; + + default: + meminfo.addr = 0L; + meminfo.nsect = 1; + meminfo.sec[0].size = SECTOR_SIZE_4K; + meminfo.sec[0].base = 0x00000; + return FLASH_API_ERROR; + } + + if ( addr32 ) { + /* Enable 4 byte mode */ + spi_flash_en4b(); + } + + meminfo.addr = 0L; + meminfo.nsect = numsector; + for (i = 0; i < numsector; i++) { + meminfo.sec[i].size = sectorsize; + meminfo.sec[i].base = basecount; + basecount += meminfo.sec[i].size; + count++; + } + totalSize = meminfo.sec[count-1].base + meminfo.sec[count-1].size; + + for( fnfi_ptr = fnfi; fnfi_ptr->fnfi_id != 0; fnfi_ptr++ ) { + if( fnfi_ptr->fnfi_id == device_id ) { + strcpy( flash_spi_dev.flash_device_name, fnfi_ptr->fnfi_name ); + break; + } + } + + if ( fastRead ) + BcmSpi_SetFlashCtrl(FLASH_READ_FAST, 1, 1, spi_flash_busnum, SPI_FLASH_SLAVE_DEV_ID); + else + BcmSpi_SetFlashCtrl(FLASH_READ, 1, 0, spi_flash_busnum, SPI_FLASH_SLAVE_DEV_ID); + + return (FLASH_API_OK); +} + +/*********************************************************************/ +/* Flash_sector_erase_int() wait until the erase is completed before */ +/* returning control to the calling function. This can be used in */ +/* cases which require the program to hold until a sector is erased, */ +/* without adding the wait check external to this function. */ +/*********************************************************************/ + +static int spi_flash_sector_erase_int(unsigned short sector) +{ + unsigned char buf[6]; + unsigned int cmd_length; + unsigned int addr; + +#ifndef _CFE_ + down(&spi_flash_lock); +#endif + + /* set device to write enabled */ + spi_flash_ub(sector); + + /* erase the sector */ + addr = (unsigned int) spi_get_flash_memptr(sector); + + cmd_length = 0; + if (meminfo.sec[sector].size == SECTOR_SIZE_4K) + buf[cmd_length++] = FLASH_SERASE; + else + buf[cmd_length++] = FLASH_BERASE; + + if ( addr32 ) + buf[cmd_length++] = (unsigned char)((addr & 0xff000000) >> 24); + buf[cmd_length++] = (unsigned char)((addr & 0x00ff0000) >> 16); + buf[cmd_length++] = (unsigned char)((addr & 0x0000ff00) >> 8); + buf[cmd_length++] = (unsigned char)(addr & 0x000000ff); + + /* check device is ready */ + if (my_spi_write(buf, cmd_length) == SPI_STATUS_OK) { + while (spi_flash_status() != STATUS_READY); + } + + spi_flash_reset(); + +#ifndef _CFE_ + up(&spi_flash_lock); +#endif + + return(FLASH_API_OK); +} + +/*********************************************************************/ +/* flash_reset() will reset the flash device to reading array data. */ +/* It is good practice to call this function after autoselect */ +/* sequences had been performed. */ +/*********************************************************************/ + +static int spi_flash_en4b(void) +{ + unsigned char buf[4]; + + /* set device to write disabled */ + buf[0] = FLASH_EN4B; + my_spi_write(buf, 1); + while (spi_flash_status() != STATUS_READY); + + return(FLASH_API_OK); +} + +/*********************************************************************/ +/* flash_reset() will reset the flash device to reading array data. */ +/* It is good practice to call this function after autoselect */ +/* sequences had been performed. */ +/*********************************************************************/ + +static int spi_flash_reset(void) +{ + unsigned char buf[4]; + + /* set device to write disabled */ + buf[0] = FLASH_WRDI; + my_spi_write(buf, 1); + while (spi_flash_status() != STATUS_READY); + + return(FLASH_API_OK); +} + +/*********************************************************************/ +/* flash_read_buf() reads buffer of data from the specified */ +/* offset from the sector parameter. */ +/*********************************************************************/ + +static int spi_flash_read_buf(unsigned short sector, int offset, + unsigned char *buffer, int nbytes) +{ + unsigned char buf[READ_BUF_LEN_MAX]; + unsigned int cmd_length; + unsigned int addr; + int maxread; + +#ifndef _CFE_ + down(&spi_flash_lock); +#endif + + addr = (unsigned int) spi_get_flash_memptr(sector); + addr += offset; + + while (nbytes > 0) { + maxread = (nbytes < spi_max_op_len) ? nbytes : spi_max_op_len; + + cmd_length = 0; + if ( fastRead ) + buf[cmd_length++] = FLASH_READ_FAST; + else + buf[cmd_length++] = FLASH_READ; + if ( addr32 ) + buf[cmd_length++] = (unsigned char)((addr & 0xff000000) >> 24); + buf[cmd_length++] = (unsigned char)((addr & 0x00ff0000) >> 16); + buf[cmd_length++] = (unsigned char)((addr & 0x0000ff00) >> 8); + buf[cmd_length++] = (unsigned char)(addr & 0x000000ff); + + /* Send dummy byte for Fast Read */ + if ( fastRead ) + buf[cmd_length++] = (unsigned char)0xff; + + my_spi_read(buf, cmd_length, maxread); + + while (spi_flash_status() != STATUS_READY); + + memcpy(buffer, buf, maxread); + buffer += maxread; + nbytes -= maxread; + addr += maxread; + } + +#ifndef _CFE_ + up(&spi_flash_lock); +#endif + + return (FLASH_API_OK); +} + +/*********************************************************************/ +/* flash_ub() places the flash into unlock bypass mode. This */ +/* is REQUIRED to be called before any of the other unlock bypass */ +/* commands will become valid (most will be ignored without first */ +/* calling this function. */ +/*********************************************************************/ + +static int spi_flash_ub(unsigned short sector) +{ + unsigned char buf[4]; + + do { + buf[0] = FLASH_RDSR; + if (my_spi_read(buf, 1, 1) == SPI_STATUS_OK) { + while (spi_flash_status() != STATUS_READY); + if (buf[0] & (SR_BP3|SR_BP2|SR_BP1|SR_BP0)) { + /* Sector is write protected. Unprotect it */ + buf[0] = FLASH_WREN; + if (my_spi_write(buf, 1) == SPI_STATUS_OK) { + buf[0] = FLASH_WRST; + buf[1] = 0; + if (my_spi_write(buf, 2) == SPI_STATUS_OK) + while (spi_flash_status() != STATUS_READY); + } + } + else { + break; + } + } + else { + break; + } + } while (1); + + /* set device to write enabled */ + buf[0] = FLASH_WREN; + + /* check device is ready */ + if (my_spi_write(buf, 1) == SPI_STATUS_OK) { + while (spi_flash_status() != STATUS_READY); + do { + buf[0] = FLASH_RDSR; + if (my_spi_read(buf, 1, 1) == SPI_STATUS_OK) { + while (spi_flash_status() != STATUS_READY); + if (buf[0] & SR_WEN) { + break; + } + } + else { + break; + } + } while (1); + } + + return(FLASH_API_OK); +} + +/*********************************************************************/ +/* flash_write_buf() utilizes */ +/* the unlock bypass mode of the flash device. This can remove */ +/* significant overhead from the bulk programming operation, and */ +/* when programming bulk data a sizeable performance increase can be */ +/* observed. */ +/*********************************************************************/ + +static int spi_flash_write(unsigned short sector, int offset, + unsigned char *buffer, int nbytes) +{ + unsigned char buf[FLASH_PAGE_256 + 6]; + unsigned int cmd_length; + unsigned int addr; + int maxwrite; + int pagelimit; + int bytes_written = 0; + +#ifndef _CFE_ + down(&spi_flash_lock); +#endif + + addr = (unsigned int) spi_get_flash_memptr(sector); + addr += offset; + + while (nbytes > 0) { + spi_flash_ub(sector); /* enable write */ + + cmd_length = 0; + buf[cmd_length++] = FLASH_PROG; + if ( addr32 ) + buf[cmd_length++] = (unsigned char)((addr & 0xff000000) >> 24); + buf[cmd_length++] = (unsigned char)((addr & 0x00ff0000) >> 16); + buf[cmd_length++] = (unsigned char)((addr & 0x0000ff00) >> 8); + buf[cmd_length++] = (unsigned char)(addr & 0x000000ff); + + /* set length to the smaller of controller limit (spi_max_op_len) or nbytes + spi_max_op_len considers both controllers */ + maxwrite = (nbytes < (spi_max_op_len - cmd_length)) ? nbytes : (spi_max_op_len - cmd_length); + /* maxwrite is limit to page boundary */ + pagelimit = flash_page_size - (addr & (flash_page_size - 1)); + maxwrite = (maxwrite < pagelimit) ? maxwrite : pagelimit; + + memcpy(&buf[cmd_length], buffer, maxwrite); + my_spi_write(buf, maxwrite + cmd_length); + + while (spi_flash_status() != STATUS_READY); + + buffer += maxwrite; + nbytes -= maxwrite; + addr += maxwrite; + bytes_written += maxwrite; + } + + spi_flash_reset(); + +#ifndef _CFE_ + up(&spi_flash_lock); +#endif + + return( bytes_written ); +} + +/*********************************************************************/ +/* flash_write_buf() utilizes */ +/* the unlock bypass mode of the flash device. This can remove */ +/* significant overhead from the bulk programming operation, and */ +/* when programming bulk data a sizeable performance increase can be */ +/* observed. */ +/*********************************************************************/ +static int spi_flash_write_buf(unsigned short sector, int offset, + unsigned char *buffer, int nbytes) +{ + int ret; + + ret = spi_flash_write(sector, offset, buffer, nbytes); + + if( ret == FLASH_API_ERROR ) + printk( "Flash write error. Verify failed\n" ); + + return( ret ); +} + +/*********************************************************************/ +/* Usefull funtion to return the number of sectors in the device. */ +/* Can be used for functions which need to loop among all the */ +/* sectors, or wish to know the number of the last sector. */ +/*********************************************************************/ + +static int spi_flash_get_numsectors(void) +{ + return meminfo.nsect; +} + +/*********************************************************************/ +/* flash_get_sector_size() is provided for cases in which the size */ +/* of a sector is required by a host application. The sector size */ +/* (in bytes) is returned in the data location pointed to by the */ +/* 'size' parameter. */ +/*********************************************************************/ + +static int spi_flash_get_sector_size(unsigned short sector) +{ + return meminfo.sec[sector].size; +} + +/*********************************************************************/ +/* The purpose of get_flash_memptr() is to return a memory pointer */ +/* which points to the beginning of memory space allocated for the */ +/* flash. All function pointers are then referenced from this */ +/* pointer. */ +/* */ +/* Different systems will implement this in different ways: */ +/* possibilities include: */ +/* - A direct memory pointer */ +/* - A pointer to a memory map */ +/* - A pointer to a hardware port from which the linear */ +/* address is translated */ +/* - Output of an MMU function / service */ +/* */ +/* Also note that this function expects the pointer to a specific */ +/* sector of the device. This can be provided by dereferencing */ +/* the pointer from a translated offset of the sector from a */ +/* global base pointer (e.g. flashptr = base_pointer + sector_offset)*/ +/* */ +/* Important: Many AMD flash devices need both bank and or sector */ +/* address bits to be correctly set (bank address bits are A18-A16, */ +/* and sector address bits are A18-A12, or A12-A15). Flash parts */ +/* which do not need these bits will ignore them, so it is safe to */ +/* assume that every part will require these bits to be set. */ +/*********************************************************************/ + +static unsigned char *spi_get_flash_memptr(unsigned short sector) +{ + unsigned char *memptr = (unsigned char*) + (FLASH_BASE + meminfo.sec[sector].base); + + return (memptr); +} + +static unsigned char *spi_flash_get_memptr(unsigned short sector) +{ + return( spi_get_flash_memptr(sector) ); +} + +/*********************************************************************/ +/* Flash_status return an appropriate status code */ +/*********************************************************************/ + +static int spi_flash_status(void) +{ + unsigned char buf[4]; + int retry = 10; + + /* check device is ready */ + do { + buf[0] = FLASH_RDSR; + if (my_spi_read(buf, 1, 1) == SPI_STATUS_OK) { + if (!(buf[0] & SR_RDY)) { + return STATUS_READY; + } + } else { + return STATUS_ERROR; + } + OSL_DELAY(10); + } while (retry--); + + return STATUS_TIMEOUT; +} + +/*********************************************************************/ +/* flash_get_device_id() return the device id of the component. */ +/*********************************************************************/ + +static unsigned short spi_flash_get_device_id(unsigned short sector) +{ + unsigned char buf[4]; + + buf[0] = FLASH_RDID; + my_spi_read(buf, 1, 3); + while (spi_flash_status() != STATUS_READY); + buf[1] = buf[2]; + + /* return manufacturer code and device code */ + return( *(unsigned short *)&buf[0] ); +} + +/*********************************************************************/ +/* The purpose of flash_get_blk() is to return a the block number */ +/* for a given memory address. */ +/*********************************************************************/ + +static int spi_flash_get_blk(int addr) +{ + int blk_start, i; + int last_blk = spi_flash_get_numsectors(); + int relative_addr = addr - (int) FLASH_BASE; + + for(blk_start=0, i=0; i < relative_addr && blk_start < last_blk; blk_start++) + i += spi_flash_get_sector_size(blk_start); + + if( (unsigned int)i > (unsigned int)relative_addr ) { + blk_start--; // last blk, dec by 1 + } else { + if( blk_start == last_blk ) + { + printk("Address is too big.\n"); + blk_start = -1; + } + } + + return( blk_start ); +} + +/************************************************************************/ +/* The purpose of flash_get_total_size() is to return the total size of */ +/* the flash */ +/************************************************************************/ +static int spi_flash_get_total_size(void) +{ + return totalSize; +} + + +#ifndef _CFE_ +static int __init BcmSpiflash_init(void) +{ + int flashType; + + /* If serial flash is present then register the device. Otherwise do nothing */ + flashType = flash_get_flash_type(); + if ((FLASH_IFC_SPI == flashType) || (FLASH_IFC_HS_SPI == flashType)) + { + /* register the device */ + BcmSpiReserveSlave(spi_flash_busnum, SPI_FLASH_SLAVE_DEV_ID, spi_flash_clock); + bSpiFlashSlaveRes = TRUE; + } + + return 0; +} +module_init(BcmSpiflash_init); + +static void __exit BcmSpiflash_exit(void) +{ + bSpiFlashSlaveRes = FALSE; +} +module_exit(BcmSpiflash_exit); +#endif + diff --git a/shared/opensource/include/bcm963xx/6328_cpu.h b/shared/opensource/include/bcm963xx/6328_cpu.h new file mode 100755 index 0000000..8dfef4c --- /dev/null +++ b/shared/opensource/include/bcm963xx/6328_cpu.h @@ -0,0 +1,150 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM6328_CPU_H +#define __BCM6328_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* +#************************************************************************ +#* Coprocessor 0 Register Names +#************************************************************************ +*/ +#define C0_BCM_CONFIG $22 + +/* +# Select 1 +# Bit 31: unused +# Bits 30:25 MMU Size (Num TLB entries-1) +# Bits 24:22 ICache sets/way (2^n * 64) +# Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache +# Bits 18:16 ICache Associativity (n+1) way +# Bits 15:13 DCache sets/way (2^n * 64) +# Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache +# Bits 9:7 DCache Associativity (n+1) way +# Bits 6:4 unused +# Bit 3: 1=At least 1 watch register +# Bit 2: 1=MIPS16 code compression implemented +# Bit 1: 1=EJTAG implemented +# Bit 0: 1=FPU implemented +*/ +#define CP0_CFG_ISMSK (0x7 << 22) +#define CP0_CFG_ISSHF 22 +#define CP0_CFG_ILMSK (0x7 << 19) +#define CP0_CFG_ILSHF 19 +#define CP0_CFG_IAMSK (0x7 << 16) +#define CP0_CFG_IASHF 16 +#define CP0_CFG_DSMSK (0x7 << 13) +#define CP0_CFG_DSSHF 13 +#define CP0_CFG_DLMSK (0x7 << 10) +#define CP0_CFG_DLSHF 10 +#define CP0_CFG_DAMSK (0x7 << 7) +#define CP0_CFG_DASHF 7 + +/* +#************************************************************************ +#* Coprocessor 0 Broadcom Config Register Bits +#************************************************************************ +*/ +#define CP0_BCM_CFG_ICSHEN (0x1 << 31) +#define CP0_BCM_CFG_DCSHEN (0x1 << 30) +#define CP0_BCM_CFG_BTHD (0x1 << 21) +#define CP0_BCM_CFG_CLF (0x1 << 20) +#define CP0_BCM_CFG_NBK (0x1 << 17) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Interrupt Register +#************************************************************************ +*/ +#define CP0_CMT_XIR_4 (0x1 << 31) +#define CP0_CMT_XIR_3 (0x1 << 30) +#define CP0_CMT_XIR_2 (0x1 << 29) +#define CP0_CMT_XIR_1 (0x1 << 28) +#define CP0_CMT_XIR_0 (0x1 << 27) +#define CP0_CMT_SIR_1 (0x1 << 16) +#define CP0_CMT_SIR_0 (0x1 << 15) +#define CP0_CMT_NMIR_TP1 (0x1 << 1) +#define CP0_CMT_NMIR_TP0 (0x1 << 0) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Control Register +#************************************************************************ +*/ +#define CP0_CMT_DSU_TP1 (0x1 << 30) +#define CP0_CMT_TPS_SHFT 16 +#define CP0_CMT_TPS_MASK (0xF << CP0_CMT_TPS_SHFT) +#define CP0_CMT_PRIO_TP1 (0x1 << 5) +#define CP0_CMT_PRIO_TP0 (0x1 << 4) +#define CP0_CMT_RSTSE (0x1 << 0) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Local Register +#************************************************************************ +*/ +#define CP0_CMT_TPID (0x1 << 31) + +/* +#************************************************************************ +#* MIPS Registers +#************************************************************************ +*/ + +#define MIPS_BASE_BOOT 0xbfa00000 +#define MIPS_BASE 0xff400000 + +#define MIPS_RAC_CR0 0x00 // RAC Configuration Register +#define MIPS_RAC_CR1 0x08 // RAC Configuration Register 1 +#define RAC_FLH (1 << 8) +#define RAC_DPF (1 << 6) +#define RAC_NCH (1 << 5) +#define RAC_C_INV (1 << 4) +#define RAC_PF_D (1 << 3) +#define RAC_PF_I (1 << 2) +#define RAC_D (1 << 1) +#define RAC_I (1 << 0) + +#define MIPS_RAC_ARR 0x04 // RAC Address Range Register +#define RAC_UPB_SHFT 16 +#define RAC_LWB_SHFT 0 + +#define MIPS_LMB_CR 0x1C // LMB Control Register +#define LMB_EN (1 << 0) + +#define MIPS_SBR 0x20 // System Base Register + +#define MIPS_TP0_ALT_BV 0x30000 +#define MIPS_TP1_ALT_BV 0x38000 +#define ENABLE_ALT_BV (1 << 19) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/opensource/include/bcm963xx/6328_intr.h b/shared/opensource/include/bcm963xx/6328_intr.h new file mode 100755 index 0000000..e4197d1 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6328_intr.h @@ -0,0 +1,120 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __6328_INTR_H +#define __6328_INTR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#define INTERRUPT_ID_SOFTWARE_0 0 +#define INTERRUPT_ID_SOFTWARE_1 1 + +/*=====================================================================*/ +/* BCM6328 Timer Interrupt Level Assignments */ +/*=====================================================================*/ +#define MIPS_TIMER_INT 7 + +/*=====================================================================*/ +/* Peripheral ISR Table Offset */ +/*=====================================================================*/ +#define INTERNAL_ISR_TABLE_OFFSET 8 +#define INTERNAL_HIGH_ISR_TABLE_OFFSET (INTERNAL_ISR_TABLE_OFFSET + 32) + +/*=====================================================================*/ +/* Logical Peripheral Interrupt IDs */ +/*=====================================================================*/ + +#define INTERRUPT_ID_NAND (INTERNAL_ISR_TABLE_OFFSET + 0) +#define INTERRUPT_ID_PCM (INTERNAL_ISR_TABLE_OFFSET + 1) +#define INTERRUPT_ID_PCM_DMA_0 (INTERNAL_ISR_TABLE_OFFSET + 2) +#define INTERRUPT_ID_PCM_DMA_1 (INTERNAL_ISR_TABLE_OFFSET + 3) +#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 4) +#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 5) +#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 6) +#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 7) +#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 8) +#define INTERRUPT_ID_USB_ISO_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 9) +#define INTERRUPT_ID_USB_ISO_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 10) +#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 11) +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 12) +#define INTERRUPT_ID_EPHY_ENERGY_0_N (INTERNAL_ISR_TABLE_OFFSET + 13) +#define INTERRUPT_ID_EPHY_ENERGY_1_N (INTERNAL_ISR_TABLE_OFFSET + 14) +#define INTERRUPT_ID_EPHY_ENERGY_2_N (INTERNAL_ISR_TABLE_OFFSET + 15) +#define INTERRUPT_ID_EPHY_ENERGY_3_N (INTERNAL_ISR_TABLE_OFFSET + 16) +#define INTERRUPT_ID_EPHY_ENERGY_0 (INTERNAL_ISR_TABLE_OFFSET + 17) +#define INTERRUPT_ID_EPHY_ENERGY_1 (INTERNAL_ISR_TABLE_OFFSET + 18) +#define INTERRUPT_ID_EPHY_ENERGY_2 (INTERNAL_ISR_TABLE_OFFSET + 19) +#define INTERRUPT_ID_EPHY_ENERGY_3 (INTERNAL_ISR_TABLE_OFFSET + 20) +#define INTERRUPT_ID_XDSL (INTERNAL_ISR_TABLE_OFFSET + 21) +#define INTERRUPT_ID_PCIE_EP (INTERNAL_ISR_TABLE_OFFSET + 22) +#define INTERRUPT_ID_PCIE_RC (INTERNAL_ISR_TABLE_OFFSET + 23) +#define INTERRUPT_ID_EXTERNAL_0 (INTERNAL_ISR_TABLE_OFFSET + 24) +#define INTERRUPT_ID_EXTERNAL_1 (INTERNAL_ISR_TABLE_OFFSET + 25) +#define INTERRUPT_ID_EXTERNAL_2 (INTERNAL_ISR_TABLE_OFFSET + 26) +#define INTERRUPT_ID_EXTERNAL_3 (INTERNAL_ISR_TABLE_OFFSET + 27) +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 28) +#define INTERRUPT_ID_HS_SPIM (INTERNAL_ISR_TABLE_OFFSET + 29) +#define INTERRUPT_ID_WAKE_ON_IRQ (INTERNAL_ISR_TABLE_OFFSET + 30) +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 31) +#define INTERRUPT_ID_ENETSW_RX_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 0) +#define INTERRUPT_ID_ENETSW_RX_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 1) +#define INTERRUPT_ID_ENETSW_RX_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 2) +#define INTERRUPT_ID_ENETSW_RX_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 3) +#define INTERRUPT_ID_UART1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 7) +#define INTERRUPT_ID_ENETSW_SYS (INTERNAL_HIGH_ISR_TABLE_OFFSET + 8) +#define INTERRUPT_ID_USBH (INTERNAL_HIGH_ISR_TABLE_OFFSET + 9) +#define INTERRUPT_ID_USBH20 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 10) +#define INTERRUPT_ID_ATM_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 11) +#define INTERRUPT_ID_ATM_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 12) +#define INTERRUPT_ID_ATM_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 13) +#define INTERRUPT_ID_ATM_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 14) +#define INTERRUPT_ID_ATM_DMA_4 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 15) +#define INTERRUPT_ID_ATM_DMA_5 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 16) +#define INTERRUPT_ID_ATM_DMA_6 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 17) +#define INTERRUPT_ID_ATM_DMA_7 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 18) +#define INTERRUPT_ID_ATM_DMA_8 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 19) +#define INTERRUPT_ID_ATM_DMA_9 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 20) +#define INTERRUPT_ID_ATM_DMA_10 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 21) +#define INTERRUPT_ID_ATM_DMA_11 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 22) +#define INTERRUPT_ID_ATM_DMA_12 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 23) +#define INTERRUPT_ID_ATM_DMA_13 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 24) +#define INTERRUPT_ID_ATM_DMA_14 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 25) +#define INTERRUPT_ID_ATM_DMA_15 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 26) +#define INTERRUPT_ID_ATM_DMA_16 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 27) +#define INTERRUPT_ID_ATM_DMA_17 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 28) +#define INTERRUPT_ID_ATM_DMA_18 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 29) +#define INTERRUPT_ID_ATM_DMA_19 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 30) +#define INTERRUPT_ID_SAR (INTERNAL_HIGH_ISR_TABLE_OFFSET + 31) + +#define INTERRUPT_ID_LAST INTERRUPT_ID_SAR + +#ifdef __cplusplus + } +#endif + +#endif /* __BCM6328_H */ + + diff --git a/shared/opensource/include/bcm963xx/6328_map_part.h b/shared/opensource/include/bcm963xx/6328_map_part.h new file mode 100755 index 0000000..be199a5 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6328_map_part.h @@ -0,0 +1,1325 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM6328_MAP_H +#define __BCM6328_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 /* NAND registers */ +#define NAND_CACHE_BASE 0xb0000400 +#define LED_BASE 0xb0000800 /* LED control registers */ +#define HSSPIM_BASE 0xb0001000 /* High-Speed SPI registers */ +#define MISC_BASE 0xb0001800 /* Miscellaneous Registers */ +#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10002500 /* USB host registers */ +#define USB_OHCI_BASE 0x10002600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0002700 +#define DDR_BASE 0xb0003000 /* Memory control registers */ +#define SAR_DMA_BASE 0xb000b800 /* ATM SAR DMA control registers */ +#define PCIE_BASE 0xb0e40000 + +typedef struct DDRPhyControl { + uint32 REVISION; /* 0x00 */ + uint32 CLK_PM_CTRL; /* 0x04 */ + uint32 unused0[2]; /* 0x08-0x10 */ + uint32 PLL_STATUS; /* 0x10 */ + uint32 PLL_CONFIG; /* 0x14 */ + uint32 PLL_PRE_DIVIDER; /* 0x18 */ + uint32 PLL_DIVIDER; /* 0x1c */ + uint32 PLL_CONTROL1; /* 0x20 */ + uint32 PLL_CONTROL2; /* 0x24 */ + uint32 PLL_SS_EN; /* 0x28 */ + uint32 PLL_SS_CFG; /* 0x2c */ + uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ + uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ + uint32 IDLE_PAD_CONTROL; /* 0x38 */ + uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_REG_CONTROL; /* 0x44 */ + uint32 unused1[46]; +} DDRPhyControl; + +typedef struct DDRPhyByteLaneControl { + uint32 REVISION; /* 0x00 */ + uint32 VDL_CALIBRATE; /* 0x04 */ + uint32 VDL_STATUS; /* 0x08 */ + uint32 unused; /* 0x0c */ + uint32 VDL_OVERRIDE_0; /* 0x10 */ + uint32 VDL_OVERRIDE_1; /* 0x14 */ + uint32 VDL_OVERRIDE_2; /* 0x18 */ + uint32 VDL_OVERRIDE_3; /* 0x1c */ + uint32 VDL_OVERRIDE_4; /* 0x20 */ + uint32 VDL_OVERRIDE_5; /* 0x24 */ + uint32 VDL_OVERRIDE_6; /* 0x28 */ + uint32 VDL_OVERRIDE_7; /* 0x2c */ + uint32 READ_CONTROL; /* 0x30 */ + uint32 READ_FIFO_STATUS; /* 0x34 */ + uint32 READ_FIFO_CLEAR; /* 0x38 */ + uint32 IDLE_PAD_CONTROL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_PAD_DISABLE; /* 0x44 */ + uint32 WR_PREAMBLE_MODE; /* 0x48 */ + uint32 CLOCK_REG_CONTROL; /* 0x4C */ + uint32 unused0[44]; +} DDRPhyByteLaneControl; + +typedef struct DDRControl { + uint32 CNFG; /* 0x000 */ + uint32 CSST; /* 0x004 */ + uint32 CSEND; /* 0x008 */ + uint32 unused; /* 0x00c */ + uint32 ROW00_0; /* 0x010 */ + uint32 ROW00_1; /* 0x014 */ + uint32 ROW01_0; /* 0x018 */ + uint32 ROW01_1; /* 0x01c */ + uint32 unused0[4]; + uint32 ROW20_0; /* 0x030 */ + uint32 ROW20_1; /* 0x034 */ + uint32 ROW21_0; /* 0x038 */ + uint32 ROW21_1; /* 0x03c */ + uint32 unused1[4]; + uint32 COL00_0; /* 0x050 */ + uint32 COL00_1; /* 0x054 */ + uint32 COL01_0; /* 0x058 */ + uint32 COL01_1; /* 0x05c */ + uint32 unused2[4]; + uint32 COL20_0; /* 0x070 */ + uint32 COL20_1; /* 0x074 */ + uint32 COL21_0; /* 0x078 */ + uint32 COL21_1; /* 0x07c */ + uint32 unused3[4]; + uint32 BNK10; /* 0x090 */ + uint32 BNK32; /* 0x094 */ + uint32 unused4[26]; + uint32 DCMD; /* 0x100 */ +#define DCMD_CS1 (1 << 5) +#define DCMD_CS0 (1 << 4) +#define DCMD_SET_SREF 4 + uint32 DMODE_0; /* 0x104 */ + uint32 DMODE_1; /* 0x108 */ +#define DMODE_1_DRAMSLEEP (1 << 11) + uint32 CLKS; /* 0x10c */ + uint32 ODT; /* 0x110 */ + uint32 TIM1_0; /* 0x114 */ + uint32 TIM1_1; /* 0x118 */ + uint32 TIM2; /* 0x11c */ + uint32 CTL_CRC; /* 0x120 */ + uint32 DOUT_CRC; /* 0x124 */ + uint32 DIN_CRC; /* 0x128 */ + uint32 unused5[53]; + + DDRPhyControl PhyControl; /* 0x200 */ + DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ + DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ + DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ + DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ + uint32 unused6[64]; + + uint32 GCFG; /* 0x800 */ + uint32 LBIST_CFG; /* 0x804 */ + uint32 LBIST_SEED; /* 0x808 */ + uint32 ARB; /* 0x80c */ + uint32 PI_GCF; /* 0x810 */ + uint32 PI_UBUS_CTL; /* 0x814 */ + uint32 PI_MIPS_CTL; /* 0x818 */ + uint32 PI_DSL_MIPS_CTL; /* 0x81c */ + uint32 PI_DSL_PHY_CTL; /* 0x820 */ + uint32 PI_UBUS_ST; /* 0x824 */ + uint32 PI_MIPS_ST; /* 0x828 */ + uint32 PI_DSL_MIPS_ST; /* 0x82c */ + uint32 PI_DSL_PHY_ST; /* 0x830 */ + uint32 PI_UBUS_SMPL; /* 0x834 */ + uint32 TESTMODE; /* 0x838 */ + uint32 TEST_CFG1; /* 0x83c */ + uint32 TEST_PAT; /* 0x840 */ + uint32 TEST_COUNT; /* 0x844 */ + uint32 TEST_CURR_COUNT; /* 0x848 */ + uint32 TEST_ADDR_UPDT; /* 0x84c */ + uint32 TEST_ADDR; /* 0x850 */ + uint32 TEST_DATA0; /* 0x854 */ + uint32 TEST_DATA1; /* 0x858 */ + uint32 TEST_DATA2; /* 0x85c */ + uint32 TEST_DATA3; /* 0x860 */ +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define ROBOSW_CLK_EN (1 << 11) +#define PCIE_CLK_EN (1 << 10) +#define HS_SPI_CLK_EN (1 << 9) +#define USBH_CLK_EN (1 << 8) +#define USBD_CLK_EN (1 << 7) +#define PCM_CLK_EN (1 << 6) +#define SAR_CLK_EN (1 << 5) +#define MIPS_CLK_EN (1 << 4) +#define ADSL_CLK_EN (1 << 3) +#define ADSL_AFE_EN (1 << 2) +#define ADSL_QPROC_EN (1 << 1) +#define PHYMIPS_CLK_EN (1 << 0) + + uint32 unused0; /* (08) word 2 */ + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_PCIE_HARD (1 << 10) +#define SOFT_RST_PCIE_EXT (1 << 9) +#define SOFT_RST_PCIE (1 << 8) +#define SOFT_RST_PCIE_CORE (1 << 7) +#define SOFT_RST_PCM (1 << 6) +#define SOFT_RST_USBH (1 << 5) +#define SOFT_RST_USBD (1 << 4) +#define SOFT_RST_SWITCH (1 << 3) +#define SOFT_RST_SAR (1 << 2) +#define SOFT_RST_EPHY (1 << 1) +#define SOFT_RST_SPI (1 << 0) + + uint32 diagControl; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 unused1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 // 0 +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo<thresh + */ + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1) + * if these bits are also enabled to GPIO_o + */ +#define DTREN 0x01 +#define RTSEN 0x02 + + byte unused1; + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to + * detect irq on rising AND falling + * edges for corresponding GPIO_i + * if enabled (edge insensitive) + */ + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense + * 0 for negedge sense if + * not configured for edge + * insensitive (see above) + * Lower 4 bits: Mask to enable change + * detection IRQ for corresponding + * GPIO_i + */ + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits + * have changed (may set IRQ). + * read automatically clears bit + * Lower 4 bits are actual status + */ + + uint16 intMask; /* Same Bit defs for Mask and status */ + uint16 intStatus; +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + + uint16 unused2; + uint16 Data; /* Write to TX, Read from RX */ + /* bits 11:8 are BRK,PAR,FRM errors */ + + uint32 unused3; + uint32 unused4; +} Uart; + +#define UART ((volatile Uart * const) UART_BASE) + +/* +** Gpio Controller +*/ + +#pragma pack(push, 4) +typedef struct GpioControl { + uint32 GPIODirHi; /* 0 */ + uint32 GPIODir; /* 4 */ + uint32 GPIOioHi; /* 8 */ + uint32 GPIOio; /* C */ + uint32 unused0; /* 10 */ + uint32 SpiSlaveCfg; /* 14 */ + uint32 GPIOMode; /* 18 */ + uint64 PinMuxSel; /* 1C */ +#define SERIAL_LED_DATA 6 +#define SERIAL_LED_CLK 7 +#define INET_ACT_LED 11 +#define EPHY0_SPD_LED 17 +#define EPHY1_SPD_LED 18 +#define EPHY2_SPD_LED 19 +#define EPHY3_SPD_LED 20 +#define EPHY0_ACT_LED 25 +#define EPHY1_ACT_LED 26 +#define EPHY2_ACT_LED 27 +#define EPHY3_ACT_LED 28 + +#define PINMUX_SERIAL_LED_DATA ((uint64)2 << (SERIAL_LED_DATA << 1)) +#define PINMUX_SERIAL_LED_CLK ((uint64)2 << (SERIAL_LED_CLK << 1)) +#define PINMUX_INET_ACT_LED ((uint64)1 << (INET_ACT_LED << 1)) +#define PINMUX_EPHY0_ACT_LED ((uint64)1 << (EPHY0_ACT_LED << 1)) +#define PINMUX_EPHY1_ACT_LED ((uint64)1 << (EPHY1_ACT_LED << 1)) +#define PINMUX_EPHY2_ACT_LED ((uint64)1 << (EPHY2_ACT_LED << 1)) +#define PINMUX_EPHY3_ACT_LED ((uint64)1 << (EPHY3_ACT_LED << 1)) + + uint32 PinMuxSelOther; /* 24 */ +#define SEL_USB 12 +#define PINMUX_SEL_USB_MASK (3 << SEL_USB) +#define PINMUX_SEL_USB_HOST (1 << SEL_USB) +#define PINMUX_SEL_USB_DEV (2 << SEL_USB) + + uint32 TestControl; /* 28 */ + uint32 unused2; /* 2C */ + uint32 RoboSWLEDControl; /* 30 */ + uint32 RoboSWLEDLSR; /* 34 */ + uint32 unused3; /* 38 */ + uint32 RoboswEphyCtrl; /* 3C */ +#define EPHY_AUTO_PWR_DOWN_EN (1<<29) +#define EPHY_IDDQ_FROM_PHY (1<<28) +#define EPHY_PLL_LOCK (1<<27) +#define EPHY_ATEST_25MHZ_EN (1<<26) +#define EPHY_PWR_DOWN_DLL (1<<25) +#define EPHY_PWR_DOWN_BIAS (1<<24) +#define EPHY_PWR_DOWN_TX_4 (1<<23) +#define EPHY_PWR_DOWN_TX_3 (1<<22) +#define EPHY_PWR_DOWN_TX_2 (1<<21) +#define EPHY_PWR_DOWN_TX_1 (1<<20) +#define EPHY_PWR_DOWN_RX_4 (1<<19) +#define EPHY_PWR_DOWN_RX_3 (1<<18) +#define EPHY_PWR_DOWN_RX_2 (1<<17) +#define EPHY_PWR_DOWN_RX_1 (1<<16) +#define EPHY_PWR_DOWN_SD_4 (1<<15) +#define EPHY_PWR_DOWN_SD_3 (1<<14) +#define EPHY_PWR_DOWN_SD_2 (1<<13) +#define EPHY_PWR_DOWN_SD_1 (1<<12) +#define EPHY_PWR_DOWN_RD_4 (1<<11) +#define EPHY_PWR_DOWN_RD_3 (1<<10) +#define EPHY_PWR_DOWN_RD_2 (1<<9) +#define EPHY_PWR_DOWN_RD_1 (1<<8) +#define EPHY_PWR_DOWN_4 (1<<7) +#define EPHY_PWR_DOWN_3 (1<<6) +#define EPHY_PWR_DOWN_2 (1<<5) +#define EPHY_PWR_DOWN_1 (1<<4) +#define EPHY_RST_4 (1<<3) +#define EPHY_RST_3 (1<<2) +#define EPHY_RST_2 (1<<1) +#define EPHY_RST_1 (1<<0) + uint32 RoboswSwitchCtrl; /* 40 */ +#define RSW_SPI_MODE (1<<11) +#define RSW_BC_SUPP_EN (1<<10) +#define RSW_CLK_FREQ_MASK (3<<8) +#define RSW_ENF_DFX_FLOW (1<<7) +#define RSW_ENH_DFX_FLOW (1<<6) +#define RSW_GRX_0_SETUP (1<<5) +#define RSW_GTX_0_SETUP (1<<4) +#define RSW_HW_FWDG_EN (1<<3) +#define RSW_QOS_EN (1<<2) +#define RSW_WD_CLR_EN (1<<1) +#define RSW_MII_DUMB_FWDG_EN (1<<0) + + uint32 RegFileTmCtl; /* 44 */ + + uint32 RingOscCtrl0; /* 48 */ +#define RING_OSC_256_CYCLES 8 +#define RING_OSC_512_CYCLES 9 +#define RING_OSC_1024_CYCLES 10 + + uint32 RingOscCtrl1; /* 4C */ +#define RING_OSC_ENABLE_MASK (0x0f<<24) +#define RING_OSC_ENABLE_SHIFT 24 +#define RING_OSC_MAX 4 +#define RING_OSC_COUNT_RESET (0x1<<23) +#define RING_OSC_SELECT_MASK (0x7<<20) +#define RING_OSC_SELECT_SHIFT 20 +#define RING_OSC_IRQ (0x1<<18) +#define RING_OSC_COUNTER_OVERFLOW (0x1<<17) +#define RING_OSC_COUNTER_BUSY (0x1<<16) +#define RING_OSC_COUNT_MASK 0x0000ffff + + uint32 unused4[6]; /* 50 - 64 */ + uint32 DieRevID; /* 68 */ + uint32 unused5; /* 6c */ + uint32 DiagSelControl; /* 70 */ + uint32 DiagReadBack; /* 74 */ + uint32 DiagReadBackHi; /* 78 */ + uint32 DiagMiscControl; /* 7c */ +} GpioControl; +#pragma pack(pop) + +#define GPIO ((volatile GpioControl * const) GPIO_BASE) + +/* Number to mask conversion macro used for GPIODir and GPIOio */ +#define GPIO_NUM_MAX 32 +#define GPIO_NUM_TO_MASK(X) ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (1 << ((X) & BP_GPIO_NUM_MASK)) : (0) ) + +/* +** High-Speed SPI Controller +*/ + +#define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start) +typedef struct HsSpiControl { + + uint32 hs_spiGlobalCtrl; // 0x0000 +#define HS_SPI_MOSI_IDLE (1 << 18) +#define HS_SPI_CLK_POLARITY (1 << 17) +#define HS_SPI_CLK_GATE_SSOFF (1 << 16) +#define HS_SPI_PLL_CLK_CTRL (8) +#define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL) +#define HS_SPI_SS_POLARITY (0) +#define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY) + + uint32 hs_spiExtTrigCtrl; // 0x0004 +#define HS_SPI_TRIG_RAW_STATE (24) +#define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE) +#define HS_SPI_TRIG_LATCHED (16) +#define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED) +#define HS_SPI_TRIG_SENSE (8) +#define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE) +#define HS_SPI_TRIG_TYPE (0) +#define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE) +#define HS_SPI_TRIG_TYPE_EDGE (0) +#define HS_SPI_TRIG_TYPE_LEVEL (1) + + uint32 hs_spiIntStatus; // 0x0008 +#define HS_SPI_IRQ_PING1_USER (28) +#define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER) +#define HS_SPI_IRQ_PING0_USER (24) +#define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER) + +#define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQ_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQ_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntStatusMasked; // 0x000C +#define HS_SPI_IRQSM__PING1_USER (28) +#define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER) +#define HS_SPI_IRQSM__PING0_USER (24) +#define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER) + +#define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntMask; // 0x0010 +#define HS_SPI_IRQM_PING1_USER (28) +#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER) +#define HS_SPI_IRQM_PING0_USER (24) +#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER) + +#define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQM_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQM_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0) + +#define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F) + + uint32 hs_spiFlashCtrl; // 0x0014 +#define HS_SPI_FCTRL_MB_ENABLE (1 << 23) +#define HS_SPI_FCTRL_SS_NUM (20) +#define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM) +#define HS_SPI_FCTRL_PROFILE_NUM (16) +#define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM) +#define HS_SPI_FCTRL_DUMMY_BYTES (10) +#define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES (8) +#define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES_2 (0) +#define HS_SPI_FCTRL_ADDR_BYTES_3 (1) +#define HS_SPI_FCTRL_ADDR_BYTES_4 (2) +#define HS_SPI_FCTRL_READ_OPCODE (0) +#define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE) + + uint32 hs_spiFlashAddrBase; // 0x0018 + + char fill0[0x80 - 0x18]; + + uint32 hs_spiPP_0_Cmd; // 0x0080 +#define HS_SPI_PP_SS_NUM (12) +#define HS_SPI_PP_SS_NUM_MASK __mask(14, HS_SPI_PP_SS_NUM) +#define HS_SPI_PP_PROFILE_NUM (8) +#define HS_SPI_PP_PROFILE_NUM_MASK __mask(10, HS_SPI_PP_PROFILE_NUM) + +} HsSpiControl; + +typedef struct HsSpiPingPong { + + uint32 command; +#define HS_SPI_SS_NUM (12) +#define HS_SPI_PROFILE_NUM (8) +#define HS_SPI_TRIGGER_NUM (4) +#define HS_SPI_COMMAND_VALUE (0) + #define HS_SPI_COMMAND_NOOP (0) + #define HS_SPI_COMMAND_START_NOW (1) + #define HS_SPI_COMMAND_START_TRIGGER (2) + #define HS_SPI_COMMAND_HALT (3) + #define HS_SPI_COMMAND_FLUSH (4) + + uint32 status; +#define HS_SPI_ERROR_BYTE_OFFSET (16) +#define HS_SPI_WAIT_FOR_TRIGGER (2) +#define HS_SPI_SOURCE_BUSY (1) +#define HS_SPI_SOURCE_GNT (0) + + uint32 fifo_status; + uint32 control; + +} HsSpiPingPong; + +typedef struct HsSpiProfile { + + uint32 clk_ctrl; +#define HS_SPI_ACCUM_RST_ON_LOOP (15) +#define HS_SPI_SPI_CLK_2X_SEL (14) +#define HS_SPI_FREQ_CTRL_WORD (0) + + uint32 signal_ctrl; +#define HS_SPI_ASYNC_INPUT_PATH (1 << 16) +#define HS_SPI_LAUNCH_RISING (1 << 13) +#define HS_SPI_LATCH_RISING (1 << 12) + + uint32 mode_ctrl; +#define HS_SPI_PREPENDBYTE_CNT (24) +#define HS_SPI_MODE_ONE_WIRE (20) +#define HS_SPI_MULTIDATA_WR_SIZE (18) +#define HS_SPI_MULTIDATA_RD_SIZE (16) +#define HS_SPI_MULTIDATA_WR_STRT (12) +#define HS_SPI_MULTIDATA_RD_STRT (8) +#define HS_SPI_FILLBYTE (0) + + uint32 polling_config; + uint32 polling_and_mask; + uint32 polling_compare; + uint32 polling_timeout; + uint32 reserved; + +} HsSpiProfile; + +#define HS_SPI_OP_CODE 13 + #define HS_SPI_OP_SLEEP (0) + #define HS_SPI_OP_READ_WRITE (1) + #define HS_SPI_OP_WRITE (2) + #define HS_SPI_OP_READ (3) + #define HS_SPI_OP_SETIRQ (4) + +#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE) +#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80)) +#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0)) +#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100)) +#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200)) +#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400)) + + +/* +** Misc Register Set Definitions. +*/ + +typedef struct Misc { + uint32 miscSerdesCtrl; /* 0x0000 */ +#define SERDES_PCIE_ENABLE 0x00000001 +#define SERDES_PCIE_EXD_ENABLE (1<<15) + + uint32 miscSerdesSts; /* 0x0004 */ + uint32 miscIrqOutMask; /* 0x0008 */ +#define MISC_PCIE_EP_IRQ_MASK0 (1<<0) +#define MISC_PCIE_EP_IRQ_MASK1 (1<<1) + + uint32 miscMemcControl; /* 0x000c */ +#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE (1<<3) +#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE (1<<2) +#define MISC_MEMC_CONTROL_DDR_TEST_DONE (1<<1) +#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE (1<<0) + + uint32 unused0[2]; /* 0x0010 */ + + uint32 miscVregCtrl0; /* 0x0018 */ +#define VREG_VSEL1P2_SHIFT 0 +#define VREG_VSEL1P2_MASK 0x1f +#define VREG_VSEL1P2_MIDDLE 0x0f + + uint32 miscVregCtrl1; /* 0x001c */ + uint32 miscVregCtrl2; /* 0x0020 */ + uint32 miscLedXorReg; /* 0x0024 */ + uint32 miscExtra2ChipIrqMask; /* 0x0028 */ + uint32 miscExtra2ChipIrqStatus; /* 0x002c */ + uint32 miscExtra2ChipIrqMask1; /* 0x0030 */ + uint32 miscExtra2ChipIrqStatus1; /* 0x0034 */ + uint32 miscDdrPllTestCtrl; /* 0x0038 */ + uint32 miscPadCtrlLow; /* 0x003c */ + uint32 miscPadCtrlHigh; /* 0x0040 */ +#define MISC_MII_SEL_SHIFT 30 +#define MISC_MII_SEL_3P3V 0 +#define MISC_MII_SEL_2P5V 1 +#define MISC_MII_SEL_1P5V 2 + uint32 miscPeriphEcoReg; /* 0x0044 */ + + uint32 miscIddqCtrl; /* 0x0048 */ +#define MISC_IDDQ_CONTROL_USBH (1<<6) +#define MISC_IDDQ_CONTROL_USBD (1<<5) + + uint32 miscAdslClkSample; /* 0x004c */ + + uint32 unused3[(0x0100 - 0x0050) / 4]; /* 0x0050 */ + uint32 miscAdslCtrl; /* 0x0100 */ + uint32 unused4[(0x0180 - 0x0104) / 4]; /* 0x0104 */ + uint32 miscMipsTestCtrl; /* 0x0180 */ + uint32 miscMipsTestStatus; /* 0x0184 */ + uint32 unused5[(0x0200 - 0x0188) / 4]; /* 0x0188 */ + uint32 miscPllCtrlSysPll0; /* 0x0200 */ + uint32 miscPllCtrlSysPll1; /* 0x0204 */ + uint32 miscPllCtrlSysPll2; /* 0x0208 */ + uint32 miscPllCtrlSysPll3; /* 0x020c */ + uint32 miscPllCtrlDdrPll; /* 0x0210 */ + uint32 miscPllCtrlXtalEcoReg; /* 0x0214 */ + uint32 unused6[(0x0240 - 0x0218) / 4]; /* 0x0218 */ + uint32 miscStrapBus; /* 0x0240 */ +#define MISC_STRAP_BUS_BOOT_SEL_SHIFT 18 +#define MISC_STRAP_BUS_BOOT_SEL_MASK (0x1<<MISC_STRAP_BUS_BOOT_SEL_SHIFT) +#define MISC_STRAP_BUS_BOOT_SERIAL 0x01 +#define MISC_STRAP_BUS_BOOT_NAND 0x00 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 7 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK (0x1F<<MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT) + + uint32 miscStrapOverride; /* 0x0244 */ + uint32 unused7[(0x0280 - 0x0248) / 4]; /* 0x0248 */ + uint32 miscRtcSleepModeEn; /* 0x0280 */ + uint32 miscRtcSleepRtcEn; /* 0x0284 */ + uint32 miscRtcSleepRtcCountLow; /* 0x0288 */ + uint32 miscRtcSleepRtcCountHigh; /* 0x028c */ + uint32 miscRtcSleepRtcEvent; /* 0x0290 */ + uint32 miscRtcSleepWakeupMask; /* 0x0294 */ + uint32 miscRtcSleepWakeupStatus; /* 0x0298 */ + uint32 miscRtcSleepDebounceCtrl; /* 0x029c */ + uint32 miscRtcSleepCpuScratchPad; /* 0x02a0 */ +} Misc; + +#define MISC ((volatile Misc * const) MISC_BASE) + +/* +** LedControl Register Set Definitions. +*/ + +#pragma pack(push, 4) +typedef struct LedControl { + uint32 ledInit; +#define LED_LED_TEST (1 << 31) +#define LED_SHIFT_TEST (1 << 30) +#define LED_SERIAL_LED_SHIFT_DIR (1 << 16) +#define LED_SERIAL_LED_DATA_PPOL (1 << 15) +#define LEDSERIAL_LED_CLK_NPOL (1 << 14) +#define LED_SERIAL_LED_MUX_SEL (1 << 13) +#define LED_SERIAL_LED_EN (1 << 12) +#define LED_FAST_INTV_SHIFT 6 +#define LED_FAST_INTV_MASK (0x3F<<LED_FAST_INTV_SHIFT) +#define LED_SLOW_INTV_SHIFT 0 +#define LED_SLOW_INTV_MASK (0x3F<<LED_SLOW_INTV_SHIFT) +#define LED_INTERVAL_20MS 1 + + uint64 ledMode; +#define LED_MODE_MASK (uint64)0x3 +#define LED_MODE_OFF (uint64)0x0 +#define LED_MODE_FLASH (uint64)0x1 +#define LED_MODE_BLINK (uint64)0x2 +#define LED_MODE_ON (uint64)0x3 + + uint32 ledHWDis; + uint32 ledStrobe; + uint32 ledLinkActSelHigh; +#define LED_ENET0 4 +#define LED_ENET1 5 +#define LED_ENET2 6 +#define LED_ENET3 7 +#define LED_4_ACT_SHIFT 0 +#define LED_5_ACT_SHIFT 4 +#define LED_6_ACT_SHIFT 8 +#define LED_7_ACT_SHIFT 12 +#define LED_4_LINK_SHIFT 16 +#define LED_5_LINK_SHIFT 20 +#define LED_6_LINK_SHIFT 24 +#define LED_7_LINK_SHIFT 28 + uint32 ledLinkActSelLow; +#define LED_INET 0 +#define LED_0_ACT_SHIFT 0 +#define LED_1_ACT_SHIFT 4 +#define LED_2_ACT_SHIFT 8 +#define LED_3_ACT_SHIFT 12 +#define LED_0_LINK_SHIFT 16 +#define LED_1_LINK_SHIFT 20 +#define LED_2_LINK_SHIFT 24 +#define LED_3_LINK_SHIFT 28 + + uint32 ledReadback; + uint32 ledSerialMuxSelect; +} LedControl; +#pragma pack(pop) + +#define LED ((volatile LedControl * const) LED_BASE) + +#define GPIO_NUM_TO_LED_MODE_SHIFT(X) \ + ((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \ + ((((X) & BP_GPIO_NUM_MASK) - 8) << 1)) + +#define IUDMA_MAX_CHANNELS 32 + +/* +** DMA Channel Configuration (1 .. 32) +*/ +typedef struct DmaChannelCfg { + uint32 cfg; /* (00) assorted configuration */ +#define DMA_ENABLE 0x00000001 /* set to enable channel */ +#define DMA_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ +#define DMA_BURST_HALT 0x00000004 /* idle after finish current memory burst */ + uint32 intStat; /* (04) interrupts control and status */ + uint32 intMask; /* (08) interrupts mask */ +#define DMA_BUFF_DONE 0x00000001 /* buffer done */ +#define DMA_DONE 0x00000002 /* packet xfer complete */ +#define DMA_NO_DESC 0x00000004 /* no valid descriptors */ + uint32 maxBurst; /* (0C) max burst length permitted */ +#define DMA_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */ +} DmaChannelCfg; + +/* +** DMA State RAM (1 .. 16) +*/ +typedef struct DmaStateRam { + uint32 baseDescPtr; /* (00) descriptor ring start address */ + uint32 state_data; /* (04) state/bytes done/ring offset */ + uint32 desc_len_status; /* (08) buffer descriptor status and len */ + uint32 desc_base_bufptr; /* (0C) buffer descrpitor current processing */ +} DmaStateRam; + + +/* +** DMA Registers +*/ +typedef struct DmaRegs { + uint32 controller_cfg; /* (00) controller configuration */ +#define DMA_MASTER_EN 0x00000001 +#define DMA_FLOWC_CH1_EN 0x00000002 +#define DMA_FLOWC_CH3_EN 0x00000004 + + // Flow control Ch1 + uint32 flowctl_ch1_thresh_lo; /* 004 */ + uint32 flowctl_ch1_thresh_hi; /* 008 */ + uint32 flowctl_ch1_alloc; /* 00c */ +#define DMA_BUF_ALLOC_FORCE 0x80000000 + + // Flow control Ch3 + uint32 flowctl_ch3_thresh_lo; /* 010 */ + uint32 flowctl_ch3_thresh_hi; /* 014 */ + uint32 flowctl_ch3_alloc; /* 018 */ + + // Flow control Ch5 + uint32 flowctl_ch5_thresh_lo; /* 01C */ + uint32 flowctl_ch5_thresh_hi; /* 020 */ + uint32 flowctl_ch5_alloc; /* 024 */ + + // Flow control Ch7 + uint32 flowctl_ch7_thresh_lo; /* 028 */ + uint32 flowctl_ch7_thresh_hi; /* 02C */ + uint32 flowctl_ch7_alloc; /* 030 */ + + uint32 ctrl_channel_reset; /* 034 */ + uint32 ctrl_channel_debug; /* 038 */ + uint32 reserved1; /* 03C */ + uint32 ctrl_global_interrupt_status; /* 040 */ + uint32 ctrl_global_interrupt_mask; /* 044 */ + + // Unused words + uint8 reserved2[0x200-0x48]; + + // Per channel registers/state ram + DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */ + union { + DmaStateRam s[IUDMA_MAX_CHANNELS]; + uint32 u32[4 * IUDMA_MAX_CHANNELS]; + } stram; /* (400-5FF) state ram */ +} DmaRegs; + +#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE) + +/* +** DMA Buffer +*/ +typedef struct DmaDesc { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ +} DmaDesc; + +/* +** 16 Byte DMA Buffer +*/ +typedef struct { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ + uint32 control; +#define GEM_ID_MASK 0x001F + uint32 reserved; +} DmaDesc16; + + +typedef struct USBControl { + uint32 BrtControl1; + uint32 BrtControl2; + uint32 BrtStatus1; + uint32 BrtStatus2; + uint32 UTMIControl1; +#define USB_DEVICE_MODE_SEL (1<<0) + uint32 TestPortControl; + uint32 PllControl1; + uint32 SwapControl; +#define USB_DEVICE_SEL (1<<6) +#define EHCI_LOGICAL_ADDRESS_EN (1<<5) +#define EHCI_ENDIAN_SWAP (1<<4) +#define EHCI_DATA_SWAP (1<<3) +#define OHCI_LOGICAL_ADDRESS_EN (1<<2) +#define OHCI_ENDIAN_SWAP (1<<1) +#define OHCI_DATA_SWAP (1<<0) + uint32 GenericControl; +#define PLL_SUSPEND_EN (1<<1) + uint32 FrameAdjustValue; + uint32 Setup; +#define USBH_IOC (1<<4) + uint32 MDIO; + uint32 MDIO32; + uint32 USBSimControl; +} USBControl; + +#define USBH ((volatile USBControl * const) USBH_CFG_BASE) + +/* +** PCI-E +*/ +typedef struct PcieRegs{ + uint32 devVenID; + uint16 command; + uint16 status; + uint32 revIdClassCode; + uint32 headerTypeLatCacheLineSize; + uint32 bar1; + uint32 bar2; + uint32 priSecBusNo; +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK 0x00ff0000 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT 16 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK 0x0000ff00 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT 8 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK 0x000000ff + + uint32 ioBaseLimit; + uint32 secStatus; + uint32 rcMemBaseLimit; + uint32 rcPrefBaseLimit; + uint32 rcPrefBaseHi; + uint32 rcPrefLimitHi; + uint32 rcIoBaseLimit; + uint32 capPointer; + uint32 expRomBase; + uint32 brdigeCtrlIntPinIntLine; + uint32 bridgeCtrl; + uint32 unused1[27]; + + /* PcieExpressCtrlRegs */ + uint16 pciExpressCap; + uint16 pcieCapabilitiy; + uint32 deviceCapability; + uint16 deviceControl; + uint16 deviceStatus; + uint32 linkCapability; + uint16 linkControl; + uint16 linkStatus; + uint32 slotCapability; + uint16 slotControl; + uint16 slotStatus; + uint16 rootControl; + uint16 rootCap; + uint32 rootStatus; + uint32 deviceCapability2; + uint16 deviceControl2; + uint16 deviceStatus2; + uint32 linkCapability2; + uint16 linkControl2; + uint16 linkStatus2; + uint32 slotCapability2; + uint16 slotControl2; + uint16 slotStatus2; + uint32 unused2[6]; + + /* PcieErrorRegs */ + uint16 advErrCapId; + uint16 advErrCapOff; + uint32 ucErrStatus; + uint32 ucorrErrMask; + uint32 ucorrErrSevr; + uint32 corrErrStatus; + uint32 corrErrMask; + uint32 advErrCapControl; + uint32 headerLog1; + uint32 headerLog2; + uint32 headerLog3; + uint32 headerLog4; + uint32 rootErrorCommand; + uint32 rootErrorStatus; + uint32 rcCorrId; + uint32 rcFatalNonfatalId; + uint32 unused3[10]; + + /* PcieVcRegs */ + uint16 vcCapId; + uint16 vcCapOffset; + uint32 prtVcCapability; + uint32 portVcCapability2; + uint16 portVcControl; + uint16 portVcCtatus; + uint32 portArbStatus; + uint32 vcRsrcControl; + uint32 vcRsrcStatus; + uint32 unused4[1]; + + /* PcieVendor */ + uint32 vendorCapability; + uint32 vendorSpecificHdr; +} PcieRegs; + +typedef struct PcieBlk404Regs{ + uint32 unused; /* 0x404 */ + uint32 config2; /* 0x408 */ +#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK 0x0000000f +#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE 0 + uint32 config3; /* 0x40c */ + uint32 pmDataA; /* 0x410 */ + uint32 pmDataB; /* 0x414 */ +} PcieBlk404Regs; + +typedef struct PcieBlk428Regs{ + uint32 vpdIntf; /* 0x428 */ + uint16 unused_g; /* 0x42c */ + uint16 vpdAddrFlag; /* 0x42e */ + uint32 vpdData; /* 0x430 */ + uint32 idVal1; /* 0x434 */ + uint32 idVal2; /* 0x438 */ + uint32 idVal3; /* 0x43c */ +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK 0xff000000 +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT 24 +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK 0x00ffffff +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT 16 +#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT 8 + + uint32 idVal4; + uint32 idVal5; + uint32 unused_h; + uint32 idVal6; + uint32 msiData; + uint32 msiAddr_h; + uint32 msiAddr_l; + uint32 msiMask; + uint32 msiPend; + uint32 pmData_c; + uint32 msixControl; + uint32 msixTblOffBir; + uint32 msixPbaOffBit; + uint32 unused_k; + uint32 pcieCapability; + uint32 deviceCapability; + uint32 unused_l; + uint32 linkCapability; + uint32 bar2Config; + uint32 pcieDeviceCapability2; + uint32 pcieLinkCapability2; + uint32 pcieLinkControl; + uint32 pcieLinkCapabilityRc; + uint32 bar3Config; + uint32 rootCap; + uint32 devSerNumCapId; + uint32 lowerSerNum; + uint32 upperSerNum; + uint32 advErrCap; + uint32 pwrBdgtData0; + uint32 pwrBdgtData1; + uint32 pwrBdgtData2; + uint32 pwdBdgtData3; + uint32 pwrBdgtData4; + uint32 pwrBdgtData5; + uint32 pwrBdgtData6; + uint32 pwrBdgtData7; + uint32 pwrBdgtCapability; + uint32 vsecHdr; + uint32 rcUserMemLo1; + uint32 rcUserMemHi1; + uint32 rcUserMemLo2; + uint32 rcUserMemHi2; +}PcieBlk428Regs; + +typedef struct PcieBlk800Regs{ +#define NUM_PCIE_BLK_800_CTRL_REGS 6 + uint32 tlControl[NUM_PCIE_BLK_800_CTRL_REGS]; + uint32 tlCtlStat0; + uint32 pmStatus0; + uint32 pmStatus1; + +#define NUM_PCIE_BLK_800_TAGS 32 + uint32 tlStatus[NUM_PCIE_BLK_800_TAGS]; + uint32 tlHdrFcStatus; + uint32 tlDataFcStatus; + uint32 tlHdrFcconStatus; + uint32 tlDataFcconStatus; + uint32 tlTargetCreditStatus; + uint32 tlCreditAllocStatus; + uint32 tlSmlogicStatus; +} PcieBlk800Regs; + + +typedef struct PcieBlk1000Regs{ +#define NUM_PCIE_BLK_1000_PDL_CTRL_REGS 16 + uint32 pdlControl[NUM_PCIE_BLK_1000_PDL_CTRL_REGS]; + uint32 dlattnVec; + uint32 dlAttnMask; + uint32 dlStatus; /* 0x1048 */ +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK 0x00002000 +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT 13 + uint32 dlTxChecksum; + uint32 dlForcedUpdateGen1; + uint32 mdioAddr; + uint32 mdioWrData; + uint32 mdioRdData; + uint32 dlRxPFcCl; + uint32 dlRxCFcCl; + uint32 dlRxAckNack; + uint32 dlTxRxSeqnb; + uint32 dlTxPFcAl; + uint32 dlTxNpFcAl; + uint32 regDlSpare; + uint32 dlRegSpare; + uint32 dlTxRxSeq; + uint32 dlRxNpFcCl; +}PcieBlk1000Regs; + +typedef struct PcieBlk1800Regs{ +#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS 5 + uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS]; +#define REG_POWERDOWN_P1PLL_ENA (1<<12) + uint32 phyErrorAttnVec; + uint32 phyErrorAttnMask; + uint32 phyReceivedMcpErrors; + uint32 phyTransmittedMcpErrors; + uint32 phyGenDebug; + uint32 phyRecoveryHist; +#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS 3 + uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS]; +#define NUM_PCIE_BLK_1800_PHY_DBG_REGS 11 + uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS]; +} PcieBlk1800Regs; + +typedef struct PcieBridgeRegs{ + uint32 bar1Remap; /* 0x0818*/ +#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK 0xffff0000 +#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK_SHIFT 16 +#define PCIE_BRIDGE_BAR1_REMAP_remap_enable (1<<1) +#define PCIE_BRIDGE_BAR1_REMAP_swap_enable 1 + + uint32 bar2Remap; /* 0x081c*/ +#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK 0xffff0000 +#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK_SHIFT 16 +#define PCIE_BRIDGE_BAR2_REMAP_remap_enable (1<<1) +#define PCIE_BRIDGE_BAR2_REMAP_swap_enable 1 + + uint32 bridgeOptReg1; /* 0x0820*/ +#define PCIE_BRIDGE_OPT_REG1_en_l1_int_status_mask_polarity (1<<12) +#define PCIE_BRIDGE_OPT_REG1_en_pcie_bridge_hole_detection (1<<11) +#define PCIE_BRIDGE_OPT_REG1_en_rd_reply_be_fix (1<<9) +#define PCIE_BRIDGE_OPT_REG1_enable_rd_be_opt (1<<7) + + uint32 bridgeOptReg2; /* 0x0824*/ +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK 0xe0000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT 29 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK 0x1f000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT 24 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK 0x00ff0000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT 16 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK 0x00000080 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT 7 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK 0x00000040 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT 6 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK 0x00000020 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT 5 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK 0x00000010 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT 4 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK 0x00000004 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT 2 +#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK 0x0000ff0b + + uint32 Ubus2PcieBar0BaseMask; /* 0x0828 */ +#define PCIE_BRIDGE_BAR0_BASE_base_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR0_BASE_base_MASK_SHIFT 20 +#define PCIE_BRIDGE_BAR0_BASE_mask_MASK 0x0000fff0 +#define PCIE_BRIDGE_BAR0_BASE_mask_MASK_SHIFT 4 +#define PCIE_BRIDGE_BAR0_BASE_swap_enable (1<<1) +#define PCIE_BRIDGE_BAR0_BASE_remap_enable 1 + + uint32 Ubus2PcieBar0RemapAdd; /* 0x082c */ +#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_SHIFT 20 + + uint32 Ubus2PcieBar1BaseMask; /* 0x0830 */ +#define PCIE_BRIDGE_BAR1_BASE_base_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR1_BASE_base_MASK_SHIFT 20 +#define PCIE_BRIDGE_BAR1_BASE_mask_MASK 0x0000fff0 +#define PCIE_BRIDGE_BAR1_BASE_mask_MASK_SHIFT 4 +#define PCIE_BRIDGE_BAR1_BASE_swap_enable (1<<1) +#define PCIE_BRIDGE_BAR1_BASE_remap_enable 1 + + uint32 Ubus2PcieBar1RemapAdd; /* 0x0834 */ +#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_SHIFT 20 + + uint32 bridgeErrStatus; /* 0x0838 */ + uint32 bridgeErrMask; /* 0x083c */ + uint32 coreErrStatus2; /* 0x0840 */ + uint32 coreErrMask2; /* 0x0844 */ + uint32 coreErrStatus1; /* 0x0848 */ + uint32 coreErrMask1; /* 0x084c */ + uint32 rcInterruptStatus; /* 0x0850 */ + uint32 rcInterruptMask; /* 0x0854 */ +#define PCIE_BRIDGE_INTERRUPT_MASK_int_a_MASK (1<<0) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_b_MASK (1<<1) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_c_MASK (1<<2) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_d_MASK (1<<3) + +}PcieBridgeRegs; + +#define PCIEH_DEV_OFFSET 0x8000 +#define PCIEH ((volatile uint32 * const) PCIE_BASE) +#define PCIEH_REGS ((volatile PcieRegs * const) PCIE_BASE) + +#define PCIEH_BLK_404_REGS ((volatile PcieBlk404Regs * const) \ + (PCIE_BASE+0x404)) +#define PCIEH_BLK_428_REGS ((volatile PcieBlk428Regs * const) \ + (PCIE_BASE+0x428)) +#define PCIEH_BLK_800_REGS ((volatile PcieBlk800Regs * const) \ + (PCIE_BASE+0x800)) +#define PCIEH_BLK_1000_REGS ((volatile PcieBlk1000Regs * const) \ + (PCIE_BASE+0x1000)) +#define PCIEH_BLK_1800_REGS ((volatile PcieBlk1800Regs * const) \ + (PCIE_BASE+0x1800)) +#define PCIEH_BRIDGE_REGS ((volatile PcieBridgeRegs * const) \ + (PCIE_BASE+0x2818)) +/* +** NAND Controller Registers +*/ +typedef struct NandCtrlRegs { + uint32 NandRevision; /* NAND Revision */ + uint32 NandCmdStart; /* Nand Flash Command Start */ + uint32 NandCmdExtAddr; /* Nand Flash Command Extended Address */ + uint32 NandCmdAddr; /* Nand Flash Command Address */ + uint32 NandCmdEndAddr; /* Nand Flash Command End Address */ + uint32 NandNandBootConfig; /* Nand Flash Boot Config */ +#define NBC_AUTO_DEV_ID_CFG 0x40000000 + uint32 NandCsNandXor; /* Nand Flash EBI CS Address XOR with */ +} NandCtrlRegs; + +#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE) + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/shared/opensource/include/bcm963xx/6362_cpu.h b/shared/opensource/include/bcm963xx/6362_cpu.h new file mode 100755 index 0000000..f49a6ac --- /dev/null +++ b/shared/opensource/include/bcm963xx/6362_cpu.h @@ -0,0 +1,150 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM6362_CPU_H +#define __BCM6362_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* +#************************************************************************ +#* Coprocessor 0 Register Names +#************************************************************************ +*/ +#define C0_BCM_CONFIG $22 + +/* +# Select 1 +# Bit 31: unused +# Bits 30:25 MMU Size (Num TLB entries-1) +# Bits 24:22 ICache sets/way (2^n * 64) +# Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache +# Bits 18:16 ICache Associativity (n+1) way +# Bits 15:13 DCache sets/way (2^n * 64) +# Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache +# Bits 9:7 DCache Associativity (n+1) way +# Bits 6:4 unused +# Bit 3: 1=At least 1 watch register +# Bit 2: 1=MIPS16 code compression implemented +# Bit 1: 1=EJTAG implemented +# Bit 0: 1=FPU implemented +*/ +#define CP0_CFG_ISMSK (0x7 << 22) +#define CP0_CFG_ISSHF 22 +#define CP0_CFG_ILMSK (0x7 << 19) +#define CP0_CFG_ILSHF 19 +#define CP0_CFG_IAMSK (0x7 << 16) +#define CP0_CFG_IASHF 16 +#define CP0_CFG_DSMSK (0x7 << 13) +#define CP0_CFG_DSSHF 13 +#define CP0_CFG_DLMSK (0x7 << 10) +#define CP0_CFG_DLSHF 10 +#define CP0_CFG_DAMSK (0x7 << 7) +#define CP0_CFG_DASHF 7 + +/* +#************************************************************************ +#* Coprocessor 0 Broadcom Config Register Bits +#************************************************************************ +*/ +#define CP0_BCM_CFG_ICSHEN (0x1 << 31) +#define CP0_BCM_CFG_DCSHEN (0x1 << 30) +#define CP0_BCM_CFG_BTHD (0x1 << 21) +#define CP0_BCM_CFG_CLF (0x1 << 20) +#define CP0_BCM_CFG_NBK (0x1 << 17) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Interrupt Register +#************************************************************************ +*/ +#define CP0_CMT_XIR_4 (0x1 << 31) +#define CP0_CMT_XIR_3 (0x1 << 30) +#define CP0_CMT_XIR_2 (0x1 << 29) +#define CP0_CMT_XIR_1 (0x1 << 28) +#define CP0_CMT_XIR_0 (0x1 << 27) +#define CP0_CMT_SIR_1 (0x1 << 16) +#define CP0_CMT_SIR_0 (0x1 << 15) +#define CP0_CMT_NMIR_TP1 (0x1 << 1) +#define CP0_CMT_NMIR_TP0 (0x1 << 0) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Control Register +#************************************************************************ +*/ +#define CP0_CMT_DSU_TP1 (0x1 << 30) +#define CP0_CMT_TPS_SHFT 16 +#define CP0_CMT_TPS_MASK (0xF << CP0_CMT_TPS_SHFT) +#define CP0_CMT_PRIO_TP1 (0x1 << 5) +#define CP0_CMT_PRIO_TP0 (0x1 << 4) +#define CP0_CMT_RSTSE (0x1 << 0) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Local Register +#************************************************************************ +*/ +#define CP0_CMT_TPID (0x1 << 31) + +/* +#************************************************************************ +#* MIPS Registers +#************************************************************************ +*/ + +#define MIPS_BASE_BOOT 0xbfa00000 +#define MIPS_BASE 0xff400000 + +#define MIPS_RAC_CR0 0x00 // RAC Configuration Register +#define MIPS_RAC_CR1 0x08 // RAC Configuration Register 1 +#define RAC_FLH (1 << 8) +#define RAC_DPF (1 << 6) +#define RAC_NCH (1 << 5) +#define RAC_C_INV (1 << 4) +#define RAC_PF_D (1 << 3) +#define RAC_PF_I (1 << 2) +#define RAC_D (1 << 1) +#define RAC_I (1 << 0) + +#define MIPS_RAC_ARR 0x04 // RAC Address Range Register +#define RAC_UPB_SHFT 16 +#define RAC_LWB_SHFT 0 + +#define MIPS_LMB_CR 0x1C // LMB Control Register +#define LMB_EN (1 << 0) + +#define MIPS_SBR 0x20 // System Base Register + +#define MIPS_TP0_ALT_BV 0x30000 +#define MIPS_TP1_ALT_BV 0x38000 +#define ENABLE_ALT_BV (1 << 19) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/opensource/include/bcm963xx/6362_intr.h b/shared/opensource/include/bcm963xx/6362_intr.h new file mode 100755 index 0000000..b8e6a35 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6362_intr.h @@ -0,0 +1,123 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __6362_INTR_H +#define __6362_INTR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#define INTERRUPT_ID_SOFTWARE_0 0 +#define INTERRUPT_ID_SOFTWARE_1 1 + +/*=====================================================================*/ +/* BCM6362 Timer Interrupt Level Assignments */ +/*=====================================================================*/ +#define MIPS_TIMER_INT 7 + +/*=====================================================================*/ +/* Peripheral ISR Table Offset */ +/*=====================================================================*/ +#define INTERNAL_ISR_TABLE_OFFSET 8 +#define INTERNAL_HIGH_ISR_TABLE_OFFSET (INTERNAL_ISR_TABLE_OFFSET + 32) + +/*=====================================================================*/ +/* Logical Peripheral Interrupt IDs */ +/*=====================================================================*/ + +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0) +#define INTERRUPT_ID_RING_OSC (INTERNAL_ISR_TABLE_OFFSET + 1) +#define INTERRUPT_ID_LS_SPIM (INTERNAL_ISR_TABLE_OFFSET + 2) +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 3) +#define INTERRUPT_ID_UART1 (INTERNAL_ISR_TABLE_OFFSET + 4) +#define INTERRUPT_ID_HS_SPIM (INTERNAL_ISR_TABLE_OFFSET + 5) +#define INTERRUPT_ID_WLAN_GPIO (INTERNAL_ISR_TABLE_OFFSET + 6) +#define INTERRUPT_ID_WLAN (INTERNAL_ISR_TABLE_OFFSET + 7) +#define INTERRUPT_ID_IPSEC (INTERNAL_ISR_TABLE_OFFSET + 8) +#define INTERRUPT_ID_USBH (INTERNAL_ISR_TABLE_OFFSET + 9) +#define INTERRUPT_ID_USBH20 (INTERNAL_ISR_TABLE_OFFSET + 10) +#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 11) +#define INTERRUPT_ID_NAND_FLASH (INTERNAL_ISR_TABLE_OFFSET + 12) +#define INTERRUPT_ID_PCM (INTERNAL_ISR_TABLE_OFFSET + 13) +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 14) +#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 15) +#define INTERRUPT_ID_EPHY_ENERGY_0 (INTERNAL_ISR_TABLE_OFFSET + 16) +#define INTERRUPT_ID_EPHY_ENERGY_1 (INTERNAL_ISR_TABLE_OFFSET + 17) +#define INTERRUPT_ID_EPHY_ENERGY_2 (INTERNAL_ISR_TABLE_OFFSET + 18) +#define INTERRUPT_ID_EPHY_ENERGY_3 (INTERNAL_ISR_TABLE_OFFSET + 19) +#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 20) +#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 21) +#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 22) +#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 23) +#define INTERRUPT_ID_USB_ISO_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 24) +#define INTERRUPT_ID_USB_ISO_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 25) +#define INTERRUPT_ID_IPSEC_DMA_0 (INTERNAL_ISR_TABLE_OFFSET + 26) +#define INTERRUPT_ID_IPSEC_DMA_1 (INTERNAL_ISR_TABLE_OFFSET + 27) +#define INTERRUPT_ID_XDSL (INTERNAL_ISR_TABLE_OFFSET + 28) +#define INTERRUPT_ID_FAP (INTERNAL_ISR_TABLE_OFFSET + 29) +#define INTERRUPT_ID_PCIE_RC (INTERNAL_ISR_TABLE_OFFSET + 30) +#define INTERRUPT_ID_PCIE_EP (INTERNAL_ISR_TABLE_OFFSET + 31) +#define INTERRUPT_ID_ENETSW_RX_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 0) +#define INTERRUPT_ID_ENETSW_RX_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 1) +#define INTERRUPT_ID_ENETSW_RX_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 2) +#define INTERRUPT_ID_ENETSW_RX_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 3) +#define INTERRUPT_ID_PCM_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 4) +#define INTERRUPT_ID_PCM_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 5) +#define INTERRUPT_ID_DECT_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 6) +#define INTERRUPT_ID_DECT_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 7) +#define INTERRUPT_ID_EXTERNAL_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 8) +#define INTERRUPT_ID_EXTERNAL_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 9) +#define INTERRUPT_ID_EXTERNAL_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 10) +#define INTERRUPT_ID_EXTERNAL_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 11) +#define INTERRUPT_ID_ATM_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 12) +#define INTERRUPT_ID_ATM_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 13) +#define INTERRUPT_ID_ATM_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 14) +#define INTERRUPT_ID_ATM_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 15) +#define INTERRUPT_ID_ATM_DMA_4 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 16) +#define INTERRUPT_ID_ATM_DMA_5 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 17) +#define INTERRUPT_ID_ATM_DMA_6 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 18) +#define INTERRUPT_ID_ATM_DMA_7 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 19) +#define INTERRUPT_ID_ATM_DMA_8 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 20) +#define INTERRUPT_ID_ATM_DMA_9 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 21) +#define INTERRUPT_ID_ATM_DMA_10 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 22) +#define INTERRUPT_ID_ATM_DMA_11 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 23) +#define INTERRUPT_ID_ATM_DMA_12 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 24) +#define INTERRUPT_ID_ATM_DMA_13 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 25) +#define INTERRUPT_ID_ATM_DMA_14 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 26) +#define INTERRUPT_ID_ATM_DMA_15 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 27) +#define INTERRUPT_ID_ATM_DMA_16 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 28) +#define INTERRUPT_ID_ATM_DMA_17 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 29) +#define INTERRUPT_ID_ATM_DMA_18 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 30) +#define INTERRUPT_ID_ATM_DMA_19 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 31) + +#define INTERRUPT_ID_LAST INTERRUPT_ID_ATM_DMA_19 + +#ifdef __cplusplus + } +#endif + +#endif /* __BCM6362_H */ + + diff --git a/shared/opensource/include/bcm963xx/6362_map_part.h b/shared/opensource/include/bcm963xx/6362_map_part.h new file mode 100755 index 0000000..86d56e9 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6362_map_part.h @@ -0,0 +1,1478 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM6362_MAP_H +#define __BCM6362_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "bcmtypes.h" + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 /* NAND registers */ +#define NAND_CACHE_BASE 0xb0000600 +#define SPI_BASE 0xb0000800 /* SPI master controller registers */ +#define HSSPIM_BASE 0xb0001000 /* High-Speed SPI registers */ +#define MISC_BASE 0xb0001800 /* Miscellaneous Registers */ +#define LED_BASE 0xb0001900 /* LED control registers */ +#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10002500 /* USB host registers */ +#define USB_OHCI_BASE 0x10002600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0002700 +#define IPSEC_BASE 0xb0002800 +#define DDR_BASE 0xb0003000 /* Memory control registers */ +#define WLAN_CHIPC_BASE 0x10004000 /* WLAN ChipCommon registers, use 1xxx for ioremap */ +#define WLAN_MAC_BASE 0x10005000 /* WLAN d11mac registers */ +#define WLAN_SHIM_BASE 0xb0007000 /* shim interface to WLAN */ +#define SAR_DMA_BASE 0xb000b800 /* ATM SAR DMA control registers */ +#define PCIE_BASE 0xb0e40000 + +typedef struct DDRPhyControl { + uint32 REVISION; /* 0x00 */ + uint32 CLK_PM_CTRL; /* 0x04 */ + uint32 unused0[2]; /* 0x08-0x10 */ + uint32 PLL_STATUS; /* 0x10 */ + uint32 PLL_CONFIG; /* 0x14 */ + uint32 PLL_PRE_DIVIDER; /* 0x18 */ + uint32 PLL_DIVIDER; /* 0x1c */ + uint32 PLL_CONTROL1; /* 0x20 */ + uint32 PLL_CONTROL2; /* 0x24 */ + uint32 PLL_SS_EN; /* 0x28 */ + uint32 PLL_SS_CFG; /* 0x2c */ + uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ + uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ + uint32 IDLE_PAD_CONTROL; /* 0x38 */ + uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_REG_CONTROL; /* 0x44 */ + uint32 unused1[46]; +} DDRPhyControl; + +typedef struct DDRPhyByteLaneControl { + uint32 REVISION; /* 0x00 */ + uint32 VDL_CALIBRATE; /* 0x04 */ + uint32 VDL_STATUS; /* 0x08 */ + uint32 unused; /* 0x0c */ + uint32 VDL_OVERRIDE_0; /* 0x10 */ + uint32 VDL_OVERRIDE_1; /* 0x14 */ + uint32 VDL_OVERRIDE_2; /* 0x18 */ + uint32 VDL_OVERRIDE_3; /* 0x1c */ + uint32 VDL_OVERRIDE_4; /* 0x20 */ + uint32 VDL_OVERRIDE_5; /* 0x24 */ + uint32 VDL_OVERRIDE_6; /* 0x28 */ + uint32 VDL_OVERRIDE_7; /* 0x2c */ + uint32 READ_CONTROL; /* 0x30 */ + uint32 READ_FIFO_STATUS; /* 0x34 */ + uint32 READ_FIFO_CLEAR; /* 0x38 */ + uint32 IDLE_PAD_CONTROL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_PAD_DISABLE; /* 0x44 */ + uint32 WR_PREAMBLE_MODE; /* 0x48 */ + uint32 CLOCK_REG_CONTROL; /* 0x4C */ + uint32 unused0[44]; +} DDRPhyByteLaneControl; + +typedef struct DDRControl { + uint32 CNFG; /* 0x000 */ + uint32 CSST; /* 0x004 */ + uint32 CSEND; /* 0x008 */ + uint32 unused; /* 0x00c */ + uint32 ROW00_0; /* 0x010 */ + uint32 ROW00_1; /* 0x014 */ + uint32 ROW01_0; /* 0x018 */ + uint32 ROW01_1; /* 0x01c */ + uint32 unused0[4]; + uint32 ROW20_0; /* 0x030 */ + uint32 ROW20_1; /* 0x034 */ + uint32 ROW21_0; /* 0x038 */ + uint32 ROW21_1; /* 0x03c */ + uint32 unused1[4]; + uint32 COL00_0; /* 0x050 */ + uint32 COL00_1; /* 0x054 */ + uint32 COL01_0; /* 0x058 */ + uint32 COL01_1; /* 0x05c */ + uint32 unused2[4]; + uint32 COL20_0; /* 0x070 */ + uint32 COL20_1; /* 0x074 */ + uint32 COL21_0; /* 0x078 */ + uint32 COL21_1; /* 0x07c */ + uint32 unused3[4]; + uint32 BNK10; /* 0x090 */ + uint32 BNK32; /* 0x094 */ + uint32 unused4[26]; + uint32 DCMD; /* 0x100 */ +#define DCMD_CS1 (1 << 5) +#define DCMD_CS0 (1 << 4) +#define DCMD_SET_SREF 4 + uint32 DMODE_0; /* 0x104 */ + uint32 DMODE_1; /* 0x108 */ +#define DMODE_1_DRAMSLEEP (1 << 11) + uint32 CLKS; /* 0x10c */ + uint32 ODT; /* 0x110 */ + uint32 TIM1_0; /* 0x114 */ + uint32 TIM1_1; /* 0x118 */ + uint32 TIM2; /* 0x11c */ + uint32 CTL_CRC; /* 0x120 */ + uint32 DOUT_CRC; /* 0x124 */ + uint32 DIN_CRC; /* 0x128 */ + uint32 unused5[53]; + + DDRPhyControl PhyControl; /* 0x200 */ + DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ + DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ + DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ + DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ + uint32 unused6[64]; + + uint32 GCFG; /* 0x800 */ + uint32 LBIST_CFG; /* 0x804 */ + uint32 LBIST_SEED; /* 0x808 */ + uint32 ARB; /* 0x80c */ + uint32 PI_GCF; /* 0x810 */ + uint32 PI_UBUS_CTL; /* 0x814 */ + uint32 PI_MIPS_CTL; /* 0x818 */ + uint32 PI_DSL_MIPS_CTL; /* 0x81c */ + uint32 PI_DSL_PHY_CTL; /* 0x820 */ + uint32 PI_UBUS_ST; /* 0x824 */ + uint32 PI_MIPS_ST; /* 0x828 */ + uint32 PI_DSL_MIPS_ST; /* 0x82c */ + uint32 PI_DSL_PHY_ST; /* 0x830 */ + uint32 PI_UBUS_SMPL; /* 0x834 */ + uint32 TESTMODE; /* 0x838 */ + uint32 TEST_CFG1; /* 0x83c */ + uint32 TEST_PAT; /* 0x840 */ + uint32 TEST_COUNT; /* 0x844 */ + uint32 TEST_CURR_COUNT; /* 0x848 */ + uint32 TEST_ADDR_UPDT; /* 0x84c */ + uint32 TEST_ADDR; /* 0x850 */ + uint32 TEST_DATA0; /* 0x854 */ + uint32 TEST_DATA1; /* 0x858 */ + uint32 TEST_DATA2; /* 0x85c */ + uint32 TEST_DATA3; /* 0x860 */ +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define NAND_CLK_EN (1 << 20) +#define PHYMIPS_CLK_EN (1 << 19) +#define FAP_CLK_EN (1 << 18) +#define PCIE_CLK_EN (1 << 17) +#define HS_SPI_CLK_EN (1 << 16) +#define SPI_CLK_EN (1 << 15) +#define IPSEC_CLK_EN (1 << 14) +#define USBH_CLK_EN (1 << 13) +#define USBD_CLK_EN (1 << 12) +#define PCM_CLK_EN (1 << 11) +#define ROBOSW_CLK_EN (1 << 10) +#define SAR_CLK_EN (1 << 9) +#define SWPKT_SAR_CLK_EN (1 << 8) +#define SWPKT_USB_CLK_EN (1 << 7) +#define WLAN_OCP_CLK_EN (1 << 5) +#define MIPS_CLK_EN (1 << 4) +#define ADSL_CLK_EN (1 << 3) +#define ADSL_AFE_EN (1 << 2) +#define ADSL_QPROC_EN (1 << 1) +#define DISABLE_GLESS (1 << 0) + + uint32 pll_control; /* (08) word 2 */ +#define SOFT_RESET 0x00000001 // 0 + + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_WLAN_SHIM_UBUS (1 << 14) +#define SOFT_RST_FAP (1 << 13) +#define SOFT_RST_DDR_PHY (1 << 12) +#define SOFT_RST_WLAN_SHIM (1 << 11) +#define SOFT_RST_PCIE_EXT (1 << 10) +#define SOFT_RST_PCIE (1 << 9) +#define SOFT_RST_PCIE_CORE (1 << 8) +#define SOFT_RST_PCM (1 << 7) +#define SOFT_RST_USBH (1 << 6) +#define SOFT_RST_USBD (1 << 5) +#define SOFT_RST_SWITCH (1 << 4) +#define SOFT_RST_SAR (1 << 3) +#define SOFT_RST_EPHY (1 << 2) +#define SOFT_RST_IPSEC (1 << 1) +#define SOFT_RST_SPI (1 << 0) + + uint32 diagControl; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 unused1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo<thresh + */ + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1) + * if these bits are also enabled to GPIO_o + */ +#define DTREN 0x01 +#define RTSEN 0x02 + + byte unused1; + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to + * detect irq on rising AND falling + * edges for corresponding GPIO_i + * if enabled (edge insensitive) + */ + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense + * 0 for negedge sense if + * not configured for edge + * insensitive (see above) + * Lower 4 bits: Mask to enable change + * detection IRQ for corresponding + * GPIO_i + */ + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits + * have changed (may set IRQ). + * read automatically clears bit + * Lower 4 bits are actual status + */ + + uint16 intMask; /* Same Bit defs for Mask and status */ + uint16 intStatus; +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + + uint16 unused2; + uint16 Data; /* Write to TX, Read from RX */ + /* bits 11:8 are BRK,PAR,FRM errors */ + + uint32 unused3; + uint32 unused4; +} Uart; + +#define UART ((volatile Uart * const) UART_BASE) + +/* +** Gpio Controller +*/ + +typedef struct GpioControl { + uint64 GPIODir; /* 0 */ + uint64 GPIOio; /* 8 */ + uint32 LEDCtrl; /* 10 */ + uint32 SpiSlaveCfg; /* 14 */ + uint32 GPIOMode; /* 18 */ +#define GPIO_MODE_EXT_IRQ3 (1<<27) +#define GPIO_MODE_EXT_IRQ2 (1<<26) +#define GPIO_MODE_EXT_IRQ1 (1<<25) +#define GPIO_MODE_EXT_IRQ0 (1<<24) +#define GPIO_MODE_EPHY3_LED (1<<23) +#define GPIO_MODE_EPHY2_LED (1<<22) +#define GPIO_MODE_EPHY1_LED (1<<21) +#define GPIO_MODE_EPHY0_LED (1<<20) +#define GPIO_MODE_ADSL_SPI_SSB (1<<19) +#define GPIO_MODE_ADSL_SPI_CLK (1<<18) +#define GPIO_MODE_ADSL_SPI_MOSI (1<<17) +#define GPIO_MODE_ADSL_SPI_MISO (1<<16) +#define GPIO_MODE_UART2_SDOUT (1<<15) +#define GPIO_MODE_UART2_SDIN (1<<14) +#define GPIO_MODE_UART2_SRTS (1<<13) +#define GPIO_MODE_UART2_SCTS (1<<12) +#define GPIO_MODE_NTR_PULSE (1<<11) +#define GPIO_MODE_LS_SPIM_SSB3 (1<<10) +#define GPIO_MODE_LS_SPIM_SSB2 (1<<9) +#define GPIO_MODE_INET_LED (1<<8) +#define GPIO_MODE_ROBOSW_LED1 (1<<7) +#define GPIO_MODE_ROBOSW_LED0 (1<<6) +#define GPIO_MODE_ROBOSW_LED_CLK (1<<5) +#define GPIO_MODE_ROBOSW_LED_DATA (1<<4) +#define GPIO_MODE_SERIAL_LED_DATA (1<<3) +#define GPIO_MODE_SERIAL_LED_CLK (1<<2) +#define GPIO_MODE_SYS_IRQ (1<<1) +#define GPIO_MODE_USBD_LED (1<<0) + + uint32 GPIOCtrl; /* 1C */ + uint32 unused3[2]; /* 20 - 24*/ + uint32 TestControl; /* 28 */ + uint32 OscControl; /* 2C */ + uint32 RoboSWLEDControl; /* 30 */ + uint32 RoboSWLEDLSR; /* 34 */ + uint32 GPIOBaseMode; /* 38 */ +#define NAND_GPIO_OVERRIDE (1<<2) + uint32 RoboswEphyCtrl; /* 3C */ +#define EPHY_PLL_LOCK (1<<27) +#define EPHY_ATEST_25MHZ_EN (1<<26) +#define EPHY_PWR_DOWN_DLL (1<<25) +#define EPHY_PWR_DOWN_BIAS (1<<24) +#define EPHY_PWR_DOWN_TX_4 (1<<23) +#define EPHY_PWR_DOWN_TX_3 (1<<22) +#define EPHY_PWR_DOWN_TX_2 (1<<21) +#define EPHY_PWR_DOWN_TX_1 (1<<20) +#define EPHY_PWR_DOWN_RX_4 (1<<19) +#define EPHY_PWR_DOWN_RX_3 (1<<18) +#define EPHY_PWR_DOWN_RX_2 (1<<17) +#define EPHY_PWR_DOWN_RX_1 (1<<16) +#define EPHY_PWR_DOWN_SD_4 (1<<15) +#define EPHY_PWR_DOWN_SD_3 (1<<14) +#define EPHY_PWR_DOWN_SD_2 (1<<13) +#define EPHY_PWR_DOWN_SD_1 (1<<12) +#define EPHY_PWR_DOWN_RD_4 (1<<11) +#define EPHY_PWR_DOWN_RD_3 (1<<10) +#define EPHY_PWR_DOWN_RD_2 (1<<9) +#define EPHY_PWR_DOWN_RD_1 (1<<8) +#define EPHY_PWR_DOWN_4 (1<<7) +#define EPHY_PWR_DOWN_3 (1<<6) +#define EPHY_PWR_DOWN_2 (1<<5) +#define EPHY_PWR_DOWN_1 (1<<4) +#define EPHY_RST_4 (1<<3) +#define EPHY_RST_3 (1<<2) +#define EPHY_RST_2 (1<<1) +#define EPHY_RST_1 (1<<0) + uint32 RoboswSwitchCtrl; /* 40 */ +#define RSW_MII_2_IFC_EN (1<<23) +#define RSW_MII_2_AMP_EN (1<<22) +#define RSW_MII_2_SEL_SHIFT 20 +#define RSW_MII_SEL_3P3V 0 +#define RSW_MII_SEL_2P5V 1 +#define RSW_MII_SEL_1P5V 2 +#define RSW_MII_AMP_EN (1<<18) +#define RSW_MII_SEL_SHIFT 16 +#define RSW_SPI_MODE (1<<11) +#define RSW_BC_SUPP_EN (1<<10) +#define RSW_CLK_FREQ_MASK (3<<8) +#define RSW_ENF_DFX_FLOW (1<<7) +#define RSW_ENH_DFX_FLOW (1<<6) +#define RSW_GRX_0_SETUP (1<<5) +#define RSW_GTX_0_SETUP (1<<4) +#define RSW_HW_FWDG_EN (1<<3) +#define RSW_QOS_EN (1<<2) +#define RSW_WD_CLR_EN (1<<1) +#define RSW_MII_DUMB_FWDG_EN (1<<0) + + uint32 RegFileTmCtl; /* 44 */ + + uint32 RingOscCtrl0; /* 48 */ +#define RING_OSC_256_CYCLES 8 +#define RING_OSC_512_CYCLES 9 +#define RING_OSC_1024_CYCLES 10 + + uint32 RingOscCtrl1; /* 4C */ +#define RING_OSC_ENABLE_MASK (0x0f<<24) +#define RING_OSC_ENABLE_SHIFT 24 +#define RING_OSC_MAX 4 +#define RING_OSC_COUNT_RESET (0x1<<23) +#define RING_OSC_SELECT_MASK (0x7<<20) +#define RING_OSC_SELECT_SHIFT 20 +#define RING_OSC_IRQ (0x1<<18) +#define RING_OSC_COUNTER_OVERFLOW (0x1<<17) +#define RING_OSC_COUNTER_BUSY (0x1<<16) +#define RING_OSC_COUNT_MASK 0x0000ffff + + uint32 unused4[6]; /* 50 - 64 */ + uint32 DieRevID; /* 68 */ + uint32 unused5; /* 6c */ + uint32 DiagSelControl; /* 70 */ + uint32 DiagReadBack; /* 74 */ + uint32 DiagReadBackHi; /* 78 */ + uint32 DiagMiscControl; /* 7c */ +} GpioControl; + +#define GPIO ((volatile GpioControl * const) GPIO_BASE) + +/* Number to mask conversion macro used for GPIODir and GPIOio */ +#define GPIO_NUM_MAX 48 +#define GPIO_NUM_TO_MASK(X) ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) ) + +/* +** Spi Controller +*/ + +typedef struct SpiControl { + uint16 spiMsgCtl; /* (0x0) control byte */ +#define FULL_DUPLEX_RW 0 +#define HALF_DUPLEX_W 1 +#define HALF_DUPLEX_R 2 +#define SPI_MSG_TYPE_SHIFT 14 +#define SPI_BYTE_CNT_SHIFT 0 + byte spiMsgData[0x21e]; /* (0x02 - 0x21f) msg data */ + byte unused0[0x1e0]; + byte spiRxDataFifo[0x220]; /* (0x400 - 0x61f) rx data */ + byte unused1[0xe0]; + + uint16 spiCmd; /* (0x700): SPI command */ +#define SPI_CMD_NOOP 0 +#define SPI_CMD_SOFT_RESET 1 +#define SPI_CMD_HARD_RESET 2 +#define SPI_CMD_START_IMMEDIATE 3 + +#define SPI_CMD_COMMAND_SHIFT 0 +#define SPI_CMD_COMMAND_MASK 0x000f + +#define SPI_CMD_DEVICE_ID_SHIFT 4 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 +#define SPI_CMD_ONE_BYTE_SHIFT 11 +#define SPI_CMD_ONE_WIRE_SHIFT 12 +#define SPI_DEV_ID_0 0 +#define SPI_DEV_ID_1 1 +#define SPI_DEV_ID_2 2 +#define SPI_DEV_ID_3 3 + + byte spiIntStatus; /* (0x702): SPI interrupt status */ + byte spiMaskIntStatus; /* (0x703): SPI masked interrupt status */ + + byte spiIntMask; /* (0x704): SPI interrupt mask */ +#define SPI_INTR_CMD_DONE 0x01 +#define SPI_INTR_RX_OVERFLOW 0x02 +#define SPI_INTR_INTR_TX_UNDERFLOW 0x04 +#define SPI_INTR_TX_OVERFLOW 0x08 +#define SPI_INTR_RX_UNDERFLOW 0x10 +#define SPI_INTR_CLEAR_ALL 0x1f + + byte spiStatus; /* (0x705): SPI status */ +#define SPI_RX_EMPTY 0x02 +#define SPI_CMD_BUSY 0x04 +#define SPI_SERIAL_BUSY 0x08 + + byte spiClkCfg; /* (0x706): SPI clock configuration */ +#define SPI_CLK_0_391MHZ 1 +#define SPI_CLK_0_781MHZ 2 /* default */ +#define SPI_CLK_1_563MHZ 3 +#define SPI_CLK_3_125MHZ 4 +#define SPI_CLK_6_250MHZ 5 +#define SPI_CLK_12_50MHZ 6 +#define SPI_CLK_MASK 0x07 +#define SPI_SSOFFTIME_MASK 0x38 +#define SPI_SSOFFTIME_SHIFT 3 +#define SPI_BYTE_SWAP 0x80 + + byte spiFillByte; /* (0x707): SPI fill byte */ + byte unused2; + byte spiMsgTail; /* (0x709): msgtail */ + byte unused3; + byte spiRxTail; /* (0x70B): rxtail */ +} SpiControl; + +#define SPI ((volatile SpiControl * const) SPI_BASE) + + +/* +** High-Speed SPI Controller +*/ + +#define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start) +typedef struct HsSpiControl { + + uint32 hs_spiGlobalCtrl; // 0x0000 +#define HS_SPI_MOSI_IDLE (1 << 18) +#define HS_SPI_CLK_POLARITY (1 << 17) +#define HS_SPI_CLK_GATE_SSOFF (1 << 16) +#define HS_SPI_PLL_CLK_CTRL (8) +#define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL) +#define HS_SPI_SS_POLARITY (0) +#define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY) + + uint32 hs_spiExtTrigCtrl; // 0x0004 +#define HS_SPI_TRIG_RAW_STATE (24) +#define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE) +#define HS_SPI_TRIG_LATCHED (16) +#define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED) +#define HS_SPI_TRIG_SENSE (8) +#define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE) +#define HS_SPI_TRIG_TYPE (0) +#define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE) +#define HS_SPI_TRIG_TYPE_EDGE (0) +#define HS_SPI_TRIG_TYPE_LEVEL (1) + + uint32 hs_spiIntStatus; // 0x0008 +#define HS_SPI_IRQ_PING1_USER (28) +#define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER) +#define HS_SPI_IRQ_PING0_USER (24) +#define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER) + +#define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQ_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQ_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntStatusMasked; // 0x000C +#define HS_SPI_IRQSM__PING1_USER (28) +#define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER) +#define HS_SPI_IRQSM__PING0_USER (24) +#define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER) + +#define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntMask; // 0x0010 +#define HS_SPI_IRQM_PING1_USER (28) +#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER) +#define HS_SPI_IRQM_PING0_USER (24) +#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER) + +#define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQM_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQM_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0) + +#define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F) + + uint32 hs_spiFlashCtrl; // 0x0014 +#define HS_SPI_FCTRL_MB_ENABLE (1 << 23) +#define HS_SPI_FCTRL_SS_NUM (20) +#define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM) +#define HS_SPI_FCTRL_PROFILE_NUM (16) +#define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM) +#define HS_SPI_FCTRL_DUMMY_BYTES (10) +#define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES (8) +#define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES_2 (0) +#define HS_SPI_FCTRL_ADDR_BYTES_3 (1) +#define HS_SPI_FCTRL_ADDR_BYTES_4 (2) +#define HS_SPI_FCTRL_READ_OPCODE (0) +#define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE) + + uint32 hs_spiFlashAddrBase; // 0x0018 + + char fill0[0x80 - 0x18]; + + uint32 hs_spiPP_0_Cmd; // 0x0080 +#define HS_SPI_PP_SS_NUM (12) +#define HS_SPI_PP_SS_NUM_MASK __mask(14, HS_SPI_PP_SS_NUM) +#define HS_SPI_PP_PROFILE_NUM (8) +#define HS_SPI_PP_PROFILE_NUM_MASK __mask(10, HS_SPI_PP_PROFILE_NUM) + +} HsSpiControl; + +typedef struct HsSpiPingPong { + + uint32 command; +#define HS_SPI_SS_NUM (12) +#define HS_SPI_PROFILE_NUM (8) +#define HS_SPI_TRIGGER_NUM (4) +#define HS_SPI_COMMAND_VALUE (0) + #define HS_SPI_COMMAND_NOOP (0) + #define HS_SPI_COMMAND_START_NOW (1) + #define HS_SPI_COMMAND_START_TRIGGER (2) + #define HS_SPI_COMMAND_HALT (3) + #define HS_SPI_COMMAND_FLUSH (4) + + uint32 status; +#define HS_SPI_ERROR_BYTE_OFFSET (16) +#define HS_SPI_WAIT_FOR_TRIGGER (2) +#define HS_SPI_SOURCE_BUSY (1) +#define HS_SPI_SOURCE_GNT (0) + + uint32 fifo_status; + uint32 control; + +} HsSpiPingPong; + +typedef struct HsSpiProfile { + + uint32 clk_ctrl; +#define HS_SPI_ACCUM_RST_ON_LOOP (15) +#define HS_SPI_SPI_CLK_2X_SEL (14) +#define HS_SPI_FREQ_CTRL_WORD (0) + + uint32 signal_ctrl; +#define HS_SPI_ASYNC_INPUT_PATH (1 << 16) +#define HS_SPI_LAUNCH_RISING (1 << 13) +#define HS_SPI_LATCH_RISING (1 << 12) + + uint32 mode_ctrl; +#define HS_SPI_PREPENDBYTE_CNT (24) +#define HS_SPI_MODE_ONE_WIRE (20) +#define HS_SPI_MULTIDATA_WR_SIZE (18) +#define HS_SPI_MULTIDATA_RD_SIZE (16) +#define HS_SPI_MULTIDATA_WR_STRT (12) +#define HS_SPI_MULTIDATA_RD_STRT (8) +#define HS_SPI_FILLBYTE (0) + + uint32 polling_config; + uint32 polling_and_mask; + uint32 polling_compare; + uint32 polling_timeout; + uint32 reserved; + +} HsSpiProfile; + +#define HS_SPI_OP_CODE 13 + #define HS_SPI_OP_SLEEP (0) + #define HS_SPI_OP_READ_WRITE (1) + #define HS_SPI_OP_WRITE (2) + #define HS_SPI_OP_READ (3) + #define HS_SPI_OP_SETIRQ (4) + +#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE) +#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80)) +#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0)) +#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100)) +#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200)) +#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400)) + + +/* +** Misc Register Set Definitions. +*/ + +typedef struct Misc { + uint32 unused1; /* 0x00 */ + uint32 miscSerdesCtrl; /* 0x04 */ +#define SERDES_PCIE_ENABLE 0x00000001 +#define SERDES_PCIE_EXD_ENABLE (1<<15) + + uint32 miscSerdesSts; /* 0x08 */ + uint32 miscIrqOutMask; /* 0x0C */ +#define MISC_PCIE_EP_IRQ_MASK0 (1<<0) +#define MISC_PCIE_EP_IRQ_MASK1 (1<<1) + + uint32 miscMemcControl; /* 0x10 */ +#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE (1<<3) +#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE (1<<2) +#define MISC_MEMC_CONTROL_DDR_TEST_DONE (1<<1) +#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE (1<<0) + + uint32 miscStrapBus; /* 0x14 */ +#define MISC_STRAP_BUS_RESET_CFG_DELAY (1<<18) +#define MISC_STRAP_BUS_RESET_OUT_SHIFT 16 +#define MISC_STRAP_BUS_RESET_OUT_MASK (3<<MISC_STRAP_BUS_RESET_OUT_SHIFT) +#define MISC_STRAP_BUS_BOOT_SEL_SHIFT 15 +#define MISC_STRAP_BUS_BOOT_SEL_MASK (0x1<<MISC_STRAP_BUS_BOOT_SEL_SHIFT) +#define MISC_STRAP_BUS_BOOT_SERIAL 0x01 +#define MISC_STRAP_BUS_BOOT_NAND 0x00 +#define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR (1<<14) +#define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR (1<<14) +#define MISC_STRAP_BUS_HS_SPIM_CLK_SLOW_N_FAST (1<<13) +#define MISC_STRAP_BUS_LS_SPIM_CLK_FAST_N_SLOW (1<<12) +#define MISC_STRAP_BUS_LS_SPI_MASTER_N_SLAVE (1<<11) +#define MISC_STRAP_BUS_PLL_USE_LOCK (1<<10) +#define MISC_STRAP_BUS_PLL_MIPS_WAIT_FAST_N (1<<9) +#define MISC_STRAP_BUS_ROBOSW_P4_MODE_SHIFT 7 +#define MISC_STRAP_BUS_ROBOSW_P4_MODE_MASK (3<<MISC_STRAP_BUS_ROBOSW_P4_MODE_SHIFT) +#define MISC_STRAP_BUS_HARD_RESET_DELAY (1<<6) +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 1 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK (0x1F<<MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT) +#define MISC_STRAP_BUS_PCIE_ROOT_COMPLEX (1<<0) + + uint32 miscStrapOverride; /* 0x18 */ + uint32 miscVregCtrl0; /* 0x1C */ + + uint32 miscVregCtrl1; /* 0x20 */ +#define VREG_VSEL1P2_SHIFT 0 +#define VREG_VSEL1P2_MASK 0x1f +#define VREG_VSEL1P2_MIDDLE 0x0f + + uint32 miscVregCtrl2; /* 0x24 */ + uint32 miscExtra2ChipsIrqMask; /* 0x28 */ + uint32 miscExtra2ChipsIrqSts; /* 0x2C */ + uint32 miscExtra2ChipsIrqMask1; /* 0x30 */ + uint32 miscExtra2ChipsIrqSts1; /* 0x34 */ + uint32 miscFapIrqMask; /* 0x38 */ + uint32 miscExtraFapIrqMask; /* 0x3C */ + uint32 miscExtra2FapIrqMask; /* 0x40 */ + uint32 miscAdsl_clock_sample; /* 0x44 */ + + uint32 miscIddqCtrl; /* 0x48 */ +#define MISC_IDDQ_CONTROL_USBD (1<<5) +#define MISC_IDDQ_CONTROL_USBH (1<<4) + + uint32 miscSleep; /* 0x4C */ + uint32 miscRtc_enable; /* 0x50 */ + uint32 miscRtc_count_L; /* 0x54 */ + uint32 miscRtc_count_H; /* 0x58 */ + uint32 miscRtc_event; /* 0x5C */ + uint32 miscWakeup_mask; /* 0x60 */ + uint32 miscWakeup_status; /* 0x64 */ +} Misc; + +#define MISC ((volatile Misc * const) MISC_BASE) + +/* +** LedControl Register Set Definitions. +*/ + +#pragma pack(push, 4) +typedef struct LedControl { + uint32 ledInit; +#define LED_LED_TEST (1 << 31) +#define LED_SHIFT_TEST (1 << 30) +#define LED_SERIAL_LED_SHIFT_DIR (1 << 16) +#define LED_SERIAL_LED_DATA_PPOL (1 << 15) +#define LEDSERIAL_LED_CLK_NPOL (1 << 14) +#define LED_SERIAL_LED_MUX_SEL (1 << 13) +#define LED_SERIAL_LED_EN (1 << 12) +#define LED_FAST_INTV_SHIFT 6 +#define LED_FAST_INTV_MASK (0x3F<<LED_FAST_INTV_SHIFT) +#define LED_SLOW_INTV_SHIFT 0 +#define LED_SLOW_INTV_MASK (0x3F<<LED_SLOW_INTV_SHIFT) +#define LED_INTERVAL_20MS 1 + + uint64 ledMode; +#define LED_MODE_MASK (uint64)0x3 +#define LED_MODE_OFF (uint64)0x0 +#define LED_MODE_FLASH (uint64)0x1 +#define LED_MODE_BLINK (uint64)0x2 +#define LED_MODE_ON (uint64)0x3 + + uint32 ledHWDis; + uint32 ledStrobe; + uint32 ledLinkActSelHigh; +#define LED_ENET0 4 +#define LED_ENET1 5 +#define LED_ENET2 6 +#define LED_ENET3 7 +#define LED_4_ACT_SHIFT 0 +#define LED_5_ACT_SHIFT 4 +#define LED_6_ACT_SHIFT 8 +#define LED_7_ACT_SHIFT 12 +#define LED_4_LINK_SHIFT 16 +#define LED_5_LINK_SHIFT 20 +#define LED_6_LINK_SHIFT 24 +#define LED_7_LINK_SHIFT 28 + uint32 ledLinkActSelLow; +#define LED_USB 0 +#define LED_INET 1 +#define LED_0_ACT_SHIFT 0 +#define LED_1_ACT_SHIFT 4 +#define LED_2_ACT_SHIFT 8 +#define LED_3_ACT_SHIFT 12 +#define LED_0_LINK_SHIFT 16 +#define LED_1_LINK_SHIFT 20 +#define LED_2_LINK_SHIFT 24 +#define LED_3_LINK_SHIFT 28 + + uint32 ledReadback; + uint32 ledSerialMuxSelect; +} LedControl; +#pragma pack(pop) + +#define LED ((volatile LedControl * const) LED_BASE) + +#define GPIO_NUM_TO_LED_MODE_SHIFT(X) \ + ((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \ + (((X) & BP_GPIO_SERIAL) ? ((((X) & BP_GPIO_NUM_MASK) - 8) << 1) : \ + (((X) & BP_GPIO_NUM_MASK) < 16) ? (32 + ((((X) & BP_GPIO_NUM_MASK) - 8) << 1)) : \ + ((((X) & BP_GPIO_NUM_MASK) - 16) << 1))) + +#define IUDMA_MAX_CHANNELS 32 + +/* +** DMA Channel Configuration (1 .. 32) +*/ +typedef struct DmaChannelCfg { + uint32 cfg; /* (00) assorted configuration */ +#define DMA_ENABLE 0x00000001 /* set to enable channel */ +#define DMA_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ +#define DMA_BURST_HALT 0x00000004 /* idle after finish current memory burst */ + uint32 intStat; /* (04) interrupts control and status */ + uint32 intMask; /* (08) interrupts mask */ +#define DMA_BUFF_DONE 0x00000001 /* buffer done */ +#define DMA_DONE 0x00000002 /* packet xfer complete */ +#define DMA_NO_DESC 0x00000004 /* no valid descriptors */ + uint32 maxBurst; /* (0C) max burst length permitted */ +#define DMA_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */ +} DmaChannelCfg; + +/* +** DMA State RAM (1 .. 16) +*/ +typedef struct DmaStateRam { + uint32 baseDescPtr; /* (00) descriptor ring start address */ + uint32 state_data; /* (04) state/bytes done/ring offset */ + uint32 desc_len_status; /* (08) buffer descriptor status and len */ + uint32 desc_base_bufptr; /* (0C) buffer descrpitor current processing */ +} DmaStateRam; + + +/* +** DMA Registers +*/ +typedef struct DmaRegs { + uint32 controller_cfg; /* (00) controller configuration */ +#define DMA_MASTER_EN 0x00000001 +#define DMA_FLOWC_CH1_EN 0x00000002 +#define DMA_FLOWC_CH3_EN 0x00000004 + + // Flow control Ch1 + uint32 flowctl_ch1_thresh_lo; /* 004 */ + uint32 flowctl_ch1_thresh_hi; /* 008 */ + uint32 flowctl_ch1_alloc; /* 00c */ +#define DMA_BUF_ALLOC_FORCE 0x80000000 + + // Flow control Ch3 + uint32 flowctl_ch3_thresh_lo; /* 010 */ + uint32 flowctl_ch3_thresh_hi; /* 014 */ + uint32 flowctl_ch3_alloc; /* 018 */ + + // Flow control Ch5 + uint32 flowctl_ch5_thresh_lo; /* 01C */ + uint32 flowctl_ch5_thresh_hi; /* 020 */ + uint32 flowctl_ch5_alloc; /* 024 */ + + // Flow control Ch7 + uint32 flowctl_ch7_thresh_lo; /* 028 */ + uint32 flowctl_ch7_thresh_hi; /* 02C */ + uint32 flowctl_ch7_alloc; /* 030 */ + + uint32 ctrl_channel_reset; /* 034 */ + uint32 ctrl_channel_debug; /* 038 */ + uint32 reserved1; /* 03C */ + uint32 ctrl_global_interrupt_status; /* 040 */ + uint32 ctrl_global_interrupt_mask; /* 044 */ + + // Unused words + uint8 reserved2[0x200-0x48]; + + // Per channel registers/state ram + DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */ + union { + DmaStateRam s[IUDMA_MAX_CHANNELS]; + uint32 u32[4 * IUDMA_MAX_CHANNELS]; + } stram; /* (400-5FF) state ram */ +} DmaRegs; + +#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE) + +/* +** DMA Buffer +*/ +typedef struct DmaDesc { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ +} DmaDesc; + +/* +** 16 Byte DMA Buffer +*/ +typedef struct { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ + uint32 control; +#define GEM_ID_MASK 0x001F + uint32 reserved; +} DmaDesc16; + + +typedef struct USBControl { + uint32 BrtControl1; + uint32 BrtControl2; + uint32 BrtStatus1; + uint32 BrtStatus2; + uint32 UTMIControl1; + uint32 TestPortControl; + uint32 PllControl1; + uint32 SwapControl; +#define USB_DEVICE_SEL (1<<6) +#define EHCI_LOGICAL_ADDRESS_EN (1<<5) +#define EHCI_ENDIAN_SWAP (1<<4) +#define EHCI_DATA_SWAP (1<<3) +#define OHCI_LOGICAL_ADDRESS_EN (1<<2) +#define OHCI_ENDIAN_SWAP (1<<1) +#define OHCI_DATA_SWAP (1<<0) + uint32 unused1; + uint32 FrameAdjustValue; + uint32 Setup; +#define USBH_IOC (1<<4) + uint32 MDIO; + uint32 MDIO32; + uint32 USBSimControl; +} USBControl; + +#define USBH ((volatile USBControl * const) USBH_CFG_BASE) + +/* +** PCI-E +*/ +typedef struct PcieRegs{ + uint32 devVenID; + uint16 command; + uint16 status; + uint32 revIdClassCode; + uint32 headerTypeLatCacheLineSize; + uint32 bar1; + uint32 bar2; + uint32 priSecBusNo; +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK 0x00ff0000 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT 16 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK 0x0000ff00 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT 8 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK 0x000000ff + + uint32 ioBaseLimit; + uint32 secStatus; + uint32 rcMemBaseLimit; + uint32 rcPrefBaseLimit; + uint32 rcPrefBaseHi; + uint32 rcPrefLimitHi; + uint32 rcIoBaseLimit; + uint32 capPointer; + uint32 expRomBase; + uint32 brdigeCtrlIntPinIntLine; + uint32 bridgeCtrl; + uint32 unused1[27]; + + /* PcieExpressCtrlRegs */ + uint16 pciExpressCap; + uint16 pcieCapabilitiy; + uint32 deviceCapability; + uint16 deviceControl; + uint16 deviceStatus; + uint32 linkCapability; + uint16 linkControl; + uint16 linkStatus; + uint32 slotCapability; + uint16 slotControl; + uint16 slotStatus; + uint16 rootControl; + uint16 rootCap; + uint32 rootStatus; + uint32 deviceCapability2; + uint16 deviceControl2; + uint16 deviceStatus2; + uint32 linkCapability2; + uint16 linkControl2; + uint16 linkStatus2; + uint32 slotCapability2; + uint16 slotControl2; + uint16 slotStatus2; + uint32 unused2[6]; + + /* PcieErrorRegs */ + uint16 advErrCapId; + uint16 advErrCapOff; + uint32 ucErrStatus; + uint32 ucorrErrMask; + uint32 ucorrErrSevr; + uint32 corrErrStatus; + uint32 corrErrMask; + uint32 advErrCapControl; + uint32 headerLog1; + uint32 headerLog2; + uint32 headerLog3; + uint32 headerLog4; + uint32 rootErrorCommand; + uint32 rootErrorStatus; + uint32 rcCorrId; + uint32 rcFatalNonfatalId; + uint32 unused3[10]; + + /* PcieVcRegs */ + uint16 vcCapId; + uint16 vcCapOffset; + uint32 prtVcCapability; + uint32 portVcCapability2; + uint16 portVcControl; + uint16 portVcCtatus; + uint32 portArbStatus; + uint32 vcRsrcControl; + uint32 vcRsrcStatus; + uint32 unused4[1]; + + /* PcieVendor */ + uint32 vendorCapability; + uint32 vendorSpecificHdr; +} PcieRegs; + +typedef struct PcieBlk404Regs{ + uint32 unused; /* 0x404 */ + uint32 config2; /* 0x408 */ +#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK 0x0000000f +#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE 0 + uint32 config3; /* 0x40c */ + uint32 pmDataA; /* 0x410 */ + uint32 pmDataB; /* 0x414 */ +} PcieBlk404Regs; + +typedef struct PcieBlk428Regs{ + uint32 vpdIntf; /* 0x428 */ + uint16 unused_g; /* 0x42c */ + uint16 vpdAddrFlag; /* 0x42e */ + uint32 vpdData; /* 0x430 */ + uint32 idVal1; /* 0x434 */ + uint32 idVal2; /* 0x438 */ + uint32 idVal3; /* 0x43c */ +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK 0xff000000 +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT 24 +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK 0x00ffffff +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT 16 +#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT 8 + + uint32 idVal4; + uint32 idVal5; + uint32 unused_h; + uint32 idVal6; + uint32 msiData; + uint32 msiAddr_h; + uint32 msiAddr_l; + uint32 msiMask; + uint32 msiPend; + uint32 pmData_c; + uint32 msixControl; + uint32 msixTblOffBir; + uint32 msixPbaOffBit; + uint32 unused_k; + uint32 pcieCapability; + uint32 deviceCapability; + uint32 unused_l; + uint32 linkCapability; + uint32 bar2Config; + uint32 pcieDeviceCapability2; + uint32 pcieLinkCapability2; + uint32 pcieLinkControl; + uint32 pcieLinkCapabilityRc; + uint32 bar3Config; + uint32 rootCap; + uint32 devSerNumCapId; + uint32 lowerSerNum; + uint32 upperSerNum; + uint32 advErrCap; + uint32 pwrBdgtData0; + uint32 pwrBdgtData1; + uint32 pwrBdgtData2; + uint32 pwdBdgtData3; + uint32 pwrBdgtData4; + uint32 pwrBdgtData5; + uint32 pwrBdgtData6; + uint32 pwrBdgtData7; + uint32 pwrBdgtCapability; + uint32 vsecHdr; + uint32 rcUserMemLo1; + uint32 rcUserMemHi1; + uint32 rcUserMemLo2; + uint32 rcUserMemHi2; +}PcieBlk428Regs; + +typedef struct PcieBlk800Regs{ +#define NUM_PCIE_BLK_800_CTRL_REGS 6 + uint32 tlControl[NUM_PCIE_BLK_800_CTRL_REGS]; + uint32 tlCtlStat0; + uint32 pmStatus0; + uint32 pmStatus1; + +#define NUM_PCIE_BLK_800_TAGS 32 + uint32 tlStatus[NUM_PCIE_BLK_800_TAGS]; + uint32 tlHdrFcStatus; + uint32 tlDataFcStatus; + uint32 tlHdrFcconStatus; + uint32 tlDataFcconStatus; + uint32 tlTargetCreditStatus; + uint32 tlCreditAllocStatus; + uint32 tlSmlogicStatus; +} PcieBlk800Regs; + + +typedef struct PcieBlk1000Regs{ +#define NUM_PCIE_BLK_1000_PDL_CTRL_REGS 16 + uint32 pdlControl[NUM_PCIE_BLK_1000_PDL_CTRL_REGS]; + uint32 dlattnVec; + uint32 dlAttnMask; + uint32 dlStatus; /* 0x1048 */ +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK 0x00002000 +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT 13 + uint32 dlTxChecksum; + uint32 dlForcedUpdateGen1; + uint32 mdioAddr; + uint32 mdioWrData; + uint32 mdioRdData; + uint32 dlRxPFcCl; + uint32 dlRxCFcCl; + uint32 dlRxAckNack; + uint32 dlTxRxSeqnb; + uint32 dlTxPFcAl; + uint32 dlTxNpFcAl; + uint32 regDlSpare; + uint32 dlRegSpare; + uint32 dlTxRxSeq; + uint32 dlRxNpFcCl; +}PcieBlk1000Regs; + +typedef struct PcieBlk1800Regs{ +#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS 5 + uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS]; +#define REG_POWERDOWN_P1PLL_ENA (1<<12) + uint32 phyErrorAttnVec; + uint32 phyErrorAttnMask; + uint32 phyReceivedMcpErrors; + uint32 phyTransmittedMcpErrors; + uint32 phyGenDebug; + uint32 phyRecoveryHist; +#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS 3 + uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS]; +#define NUM_PCIE_BLK_1800_PHY_DBG_REGS 11 + uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS]; +} PcieBlk1800Regs; + +typedef struct PcieBridgeRegs{ + uint32 bar1Remap; /* 0x0818*/ +#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK 0xffff0000 +#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK_SHIFT 16 +#define PCIE_BRIDGE_BAR1_REMAP_remap_enable (1<<1) +#define PCIE_BRIDGE_BAR1_REMAP_swap_enable 1 + + uint32 bar2Remap; /* 0x081c*/ +#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK 0xffff0000 +#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK_SHIFT 16 +#define PCIE_BRIDGE_BAR2_REMAP_remap_enable (1<<1) +#define PCIE_BRIDGE_BAR2_REMAP_swap_enable 1 + + uint32 bridgeOptReg1; /* 0x0820*/ +#define PCIE_BRIDGE_OPT_REG1_en_l1_int_status_mask_polarity (1<<12) +#define PCIE_BRIDGE_OPT_REG1_en_pcie_bridge_hole_detection (1<<11) +#define PCIE_BRIDGE_OPT_REG1_en_rd_reply_be_fix (1<<9) +#define PCIE_BRIDGE_OPT_REG1_enable_rd_be_opt (1<<7) + + uint32 bridgeOptReg2; /* 0x0824*/ +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK 0xe0000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT 29 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK 0x1f000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT 24 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK 0x00ff0000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT 16 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK 0x00000080 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT 7 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK 0x00000040 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT 6 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK 0x00000020 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT 5 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK 0x00000010 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT 4 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK 0x00000004 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT 2 +#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK 0x0000ff0b + + uint32 Ubus2PcieBar0BaseMask; /* 0x0828 */ +#define PCIE_BRIDGE_BAR0_BASE_base_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR0_BASE_base_MASK_SHIFT 20 +#define PCIE_BRIDGE_BAR0_BASE_mask_MASK 0x0000fff0 +#define PCIE_BRIDGE_BAR0_BASE_mask_MASK_SHIFT 4 +#define PCIE_BRIDGE_BAR0_BASE_swap_enable (1<<1) +#define PCIE_BRIDGE_BAR0_BASE_remap_enable 1 + + uint32 Ubus2PcieBar0RemapAdd; /* 0x082c */ +#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_SHIFT 20 + + uint32 Ubus2PcieBar1BaseMask; /* 0x0830 */ +#define PCIE_BRIDGE_BAR1_BASE_base_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR1_BASE_base_MASK_SHIFT 20 +#define PCIE_BRIDGE_BAR1_BASE_mask_MASK 0x0000fff0 +#define PCIE_BRIDGE_BAR1_BASE_mask_MASK_SHIFT 4 +#define PCIE_BRIDGE_BAR1_BASE_swap_enable (1<<1) +#define PCIE_BRIDGE_BAR1_BASE_remap_enable 1 + + uint32 Ubus2PcieBar1RemapAdd; /* 0x0834 */ +#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_MASK 0xfff00000 +#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_SHIFT 20 + + uint32 bridgeErrStatus; /* 0x0838 */ + uint32 bridgeErrMask; /* 0x083c */ + uint32 coreErrStatus2; /* 0x0840 */ + uint32 coreErrMask2; /* 0x0844 */ + uint32 coreErrStatus1; /* 0x0848 */ + uint32 coreErrMask1; /* 0x084c */ + uint32 rcInterruptStatus; /* 0x0850 */ + uint32 rcInterruptMask; /* 0x0854 */ +#define PCIE_BRIDGE_INTERRUPT_MASK_int_a_MASK (1<<0) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_b_MASK (1<<1) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_c_MASK (1<<2) +#define PCIE_BRIDGE_INTERRUPT_MASK_int_d_MASK (1<<3) + +}PcieBridgeRegs; + +#define PCIEH_DEV_OFFSET 0x8000 +#define PCIEH ((volatile uint32 * const) PCIE_BASE) +#define PCIEH_REGS ((volatile PcieRegs * const) PCIE_BASE) + +#define PCIEH_BLK_404_REGS ((volatile PcieBlk404Regs * const) \ + (PCIE_BASE+0x404)) +#define PCIEH_BLK_428_REGS ((volatile PcieBlk428Regs * const) \ + (PCIE_BASE+0x428)) +#define PCIEH_BLK_800_REGS ((volatile PcieBlk800Regs * const) \ + (PCIE_BASE+0x800)) +#define PCIEH_BLK_1000_REGS ((volatile PcieBlk1000Regs * const) \ + (PCIE_BASE+0x1000)) +#define PCIEH_BLK_1800_REGS ((volatile PcieBlk1800Regs * const) \ + (PCIE_BASE+0x1800)) +#define PCIEH_BRIDGE_REGS ((volatile PcieBridgeRegs * const) \ + (PCIE_BASE+0x2818)) + +typedef struct WlanShimRegs_a0 { + uint32 CcIdA; /* CC desc A */ + uint32 CcIdB; /* CC desc B */ + uint32 CcAddr; /* CC base addr */ + uint32 MacIdA; /* MAC desc A */ + uint32 MacIdB; /* MAC desc B */ + uint32 MacAddr; /* MAC base addr */ + uint32 ShimIdA; /* SHIM desc A */ + uint32 ShimIdB; /* SHIM desc B */ + uint32 ShimAddr; /* SHIM addr */ + uint32 ShimEot; /* EOT */ + uint32 CcControl; /* CC control */ + uint32 CcStatus; /* CC status */ + uint32 MacControl; /* MAC control */ + uint32 MacStatus; /* MAC status */ + uint32 ShimMisc; /* SHIM control registers */ + uint32 ShimStatus; /* SHIM status */ +}WlanShimRegs_a0; + +typedef struct WlanShimRegs_b0 { + uint32 ShimMisc; /* SHIM control registers */ +#define WLAN_SHIM_FORCE_CLOCKS_ON (1 << 2) +#define WLAN_SHIM_MACRO_DISABLE (1 << 1) +#define WLAN_SHIM_MACRO_SOFT_RESET (1 << 0) + + uint32 ShimStatus; /* SHIM status */ + + uint32 CcControl; /* CC control */ +#define SICF_WOC_CORE_RESET 0x10000 +#define SICF_BIST_EN 0x8000 +#define SICF_PME_EN 0x4000 +#define SICF_CORE_BITS 0x3ffc +#define SICF_FGC 0x0002 +#define SICF_CLOCK_EN 0x0001 + + uint32 CcStatus; /* CC status */ +#define SISF_BIST_DONE 0x8000 +#define SISF_BIST_ERROR 0x4000 +#define SISF_GATED_CLK 0x2000 +#define SISF_DMA64 0x1000 +#define SISF_CORE_BITS 0x0fff + + uint32 MacControl; /* MAC control */ + uint32 MacStatus; /* MAC status */ + + uint32 CcIdA; /* CC desc A */ + uint32 CcIdB; /* CC desc B */ + uint32 CcAddr; /* CC base addr */ + uint32 MacIdA; /* MAC desc A */ + uint32 MacIdB; /* MAC desc B */ + uint32 MacAddr; /* MAC base addr */ + uint32 ShimIdA; /* SHIM desc A */ + uint32 ShimIdB; /* SHIM desc B */ + uint32 ShimAddr; /* SHIM addr */ + uint32 ShimEot; /* EOT */ +}WlanShimRegs_b0; + +typedef union WlanShimRegs { + WlanShimRegs_a0 a0; + WlanShimRegs_b0 b0; /* SHIM control registers */ +}WlanShimRegs; + +#define WLAN_SHIM ((volatile WlanShimRegs * const)WLAN_SHIM_BASE) + +/* +** NAND Controller Registers +*/ +typedef struct NandCtrlRegs { + uint32 NandRevision; /* NAND Revision */ + uint32 NandCmdStart; /* Nand Flash Command Start */ + uint32 NandCmdExtAddr; /* Nand Flash Command Extended Address */ + uint32 NandCmdAddr; /* Nand Flash Command Address */ + uint32 NandCmdEndAddr; /* Nand Flash Command End Address */ + uint32 NandNandBootConfig; /* Nand Flash Boot Config */ +#define NBC_AUTO_DEV_ID_CFG 0x40000000 + uint32 NandCsNandXor; /* Nand Flash EBI CS Address XOR with */ +} NandCtrlRegs; + +#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE) + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/shared/opensource/include/bcm963xx/6368_cpu.h b/shared/opensource/include/bcm963xx/6368_cpu.h new file mode 100755 index 0000000..75cdde2 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6368_cpu.h @@ -0,0 +1,150 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM6368_CPU_H +#define __BCM6368_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* +#************************************************************************ +#* Coprocessor 0 Register Names +#************************************************************************ +*/ +#define C0_BCM_CONFIG $22 + +/* +# Select 1 +# Bit 31: unused +# Bits 30:25 MMU Size (Num TLB entries-1) +# Bits 24:22 ICache sets/way (2^n * 64) +# Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache +# Bits 18:16 ICache Associativity (n+1) way +# Bits 15:13 DCache sets/way (2^n * 64) +# Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache +# Bits 9:7 DCache Associativity (n+1) way +# Bits 6:4 unused +# Bit 3: 1=At least 1 watch register +# Bit 2: 1=MIPS16 code compression implemented +# Bit 1: 1=EJTAG implemented +# Bit 0: 1=FPU implemented +*/ +#define CP0_CFG_ISMSK (0x7 << 22) +#define CP0_CFG_ISSHF 22 +#define CP0_CFG_ILMSK (0x7 << 19) +#define CP0_CFG_ILSHF 19 +#define CP0_CFG_IAMSK (0x7 << 16) +#define CP0_CFG_IASHF 16 +#define CP0_CFG_DSMSK (0x7 << 13) +#define CP0_CFG_DSSHF 13 +#define CP0_CFG_DLMSK (0x7 << 10) +#define CP0_CFG_DLSHF 10 +#define CP0_CFG_DAMSK (0x7 << 7) +#define CP0_CFG_DASHF 7 + +/* +#************************************************************************ +#* Coprocessor 0 Broadcom Config Register Bits +#************************************************************************ +*/ +#define CP0_BCM_CFG_ICSHEN (0x1 << 31) +#define CP0_BCM_CFG_DCSHEN (0x1 << 30) +#define CP0_BCM_CFG_BTHD (0x1 << 21) +#define CP0_BCM_CFG_CLF (0x1 << 20) +#define CP0_BCM_CFG_NBK (0x1 << 17) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Interrupt Register +#************************************************************************ +*/ +#define CP0_CMT_XIR_4 (0x1 << 31) +#define CP0_CMT_XIR_3 (0x1 << 30) +#define CP0_CMT_XIR_2 (0x1 << 29) +#define CP0_CMT_XIR_1 (0x1 << 28) +#define CP0_CMT_XIR_0 (0x1 << 27) +#define CP0_CMT_SIR_1 (0x1 << 16) +#define CP0_CMT_SIR_0 (0x1 << 15) +#define CP0_CMT_NMIR_TP1 (0x1 << 1) +#define CP0_CMT_NMIR_TP0 (0x1 << 0) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Control Register +#************************************************************************ +*/ +#define CP0_CMT_DSU_TP1 (0x1 << 30) +#define CP0_CMT_TPS_SHFT 16 +#define CP0_CMT_TPS_MASK (0xF << CP0_CMT_TPS_SHFT) +#define CP0_CMT_PRIO_TP1 (0x1 << 5) +#define CP0_CMT_PRIO_TP0 (0x1 << 4) +#define CP0_CMT_RSTSE (0x1 << 0) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Local Register +#************************************************************************ +*/ +#define CP0_CMT_TPID (0x1 << 31) + +/* +#************************************************************************ +#* MIPS Registers +#************************************************************************ +*/ + +#define MIPS_BASE_BOOT 0xbfa00000 +#define MIPS_BASE 0xff400000 + +#define MIPS_RAC_CR0 0x00 // RAC Configuration Register +#define MIPS_RAC_CR1 0x08 // RAC Configuration Register 1 +#define RAC_FLH (1 << 8) +#define RAC_DPF (1 << 6) +#define RAC_NCH (1 << 5) +#define RAC_C_INV (1 << 4) +#define RAC_PF_D (1 << 3) +#define RAC_PF_I (1 << 2) +#define RAC_D (1 << 1) +#define RAC_I (1 << 0) + +#define MIPS_RAC_ARR 0x04 // RAC Address Range Register +#define RAC_UPB_SHFT 16 +#define RAC_LWB_SHFT 0 + +#define MIPS_LMB_CR 0x1C // LMB Control Register +#define LMB_EN (1 << 0) + +#define MIPS_SBR 0x20 // System Base Register + +#define MIPS_TP0_ALT_BV 0x30000 +#define MIPS_TP1_ALT_BV 0x38000 +#define ENABLE_ALT_BV (1 << 19) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/opensource/include/bcm963xx/6368_intr.h b/shared/opensource/include/bcm963xx/6368_intr.h new file mode 100755 index 0000000..afbca5f --- /dev/null +++ b/shared/opensource/include/bcm963xx/6368_intr.h @@ -0,0 +1,123 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __6368_INTR_H +#define __6368_INTR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#define INTERRUPT_ID_SOFTWARE_0 0 +#define INTERRUPT_ID_SOFTWARE_1 1 + +/*=====================================================================*/ +/* BCM6368 Timer Interrupt Level Assignments */ +/*=====================================================================*/ +#define MIPS_TIMER_INT 7 + +/*=====================================================================*/ +/* Peripheral ISR Table Offset */ +/*=====================================================================*/ +#define INTERNAL_ISR_TABLE_OFFSET 8 +#define INTERNAL_HIGH_ISR_TABLE_OFFSET (INTERNAL_ISR_TABLE_OFFSET + 32) + +/*=====================================================================*/ +/* Logical Peripheral Interrupt IDs */ +/*=====================================================================*/ + +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0) +#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1) +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2) +#define INTERRUPT_ID_UART1 (INTERNAL_ISR_TABLE_OFFSET + 3) +#define INTERRUPT_ID_XDSL (INTERNAL_ISR_TABLE_OFFSET + 4) +#define INTERRUPT_ID_USBH (INTERNAL_ISR_TABLE_OFFSET + 5) +#define INTERRUPT_ID_IPSEC (INTERNAL_ISR_TABLE_OFFSET + 6) +#define INTERRUPT_ID_USBH20 (INTERNAL_ISR_TABLE_OFFSET + 7) +#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 8) +#define INTERRUPT_ID_RING_OSC (INTERNAL_ISR_TABLE_OFFSET + 9) +#define INTERRUPT_ID_NAND_FLASH (INTERNAL_ISR_TABLE_OFFSET + 10) +#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 11) +#define INTERRUPT_ID_PCM (INTERNAL_ISR_TABLE_OFFSET + 12) +#define INTERRUPT_ID_MPI (INTERNAL_ISR_TABLE_OFFSET + 13) +#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 14) +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 15) +#define INTERRUPT_ID_EPHY_ENERGY_0 (INTERNAL_ISR_TABLE_OFFSET + 16) +#define INTERRUPT_ID_EPHY_ENERGY_1 (INTERNAL_ISR_TABLE_OFFSET + 17) +#define INTERRUPT_ID_EPHY_ENERGY_2 (INTERNAL_ISR_TABLE_OFFSET + 18) +#define INTERRUPT_ID_EPHY_ENERGY_3 (INTERNAL_ISR_TABLE_OFFSET + 19) +#define INTERRUPT_ID_EXTERNAL_0 (INTERNAL_ISR_TABLE_OFFSET + 20) +#define INTERRUPT_ID_EXTERNAL_1 (INTERNAL_ISR_TABLE_OFFSET + 21) +#define INTERRUPT_ID_EXTERNAL_2 (INTERNAL_ISR_TABLE_OFFSET + 22) +#define INTERRUPT_ID_EXTERNAL_3 (INTERNAL_ISR_TABLE_OFFSET + 23) +#define INTERRUPT_ID_EXTERNAL_4 (INTERNAL_ISR_TABLE_OFFSET + 24) +#define INTERRUPT_ID_EXTERNAL_5 (INTERNAL_ISR_TABLE_OFFSET + 25) +#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 26) +#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 27) +#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 28) +#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 29) +#define INTERRUPT_ID_USB_ISO_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 30) +#define INTERRUPT_ID_USB_ISO_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 31) +#define INTERRUPT_ID_ENETSW_RX_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 0) +#define INTERRUPT_ID_ENETSW_RX_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 1) +#define INTERRUPT_ID_ENETSW_RX_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 2) +#define INTERRUPT_ID_ENETSW_RX_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 3) +#define INTERRUPT_ID_ENETSW_TX_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 4) +#define INTERRUPT_ID_ENETSW_TX_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 5) +#define INTERRUPT_ID_ENETSW_TX_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 6) +#define INTERRUPT_ID_ENETSW_TX_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 7) +#define INTERRUPT_ID_ATM_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 8) +#define INTERRUPT_ID_ATM_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 9) +#define INTERRUPT_ID_ATM_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 10) +#define INTERRUPT_ID_ATM_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 11) +#define INTERRUPT_ID_ATM_DMA_4 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 12) +#define INTERRUPT_ID_ATM_DMA_5 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 13) +#define INTERRUPT_ID_ATM_DMA_6 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 14) +#define INTERRUPT_ID_ATM_DMA_7 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 15) +#define INTERRUPT_ID_ATM_DMA_8 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 16) +#define INTERRUPT_ID_ATM_DMA_9 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 17) +#define INTERRUPT_ID_ATM_DMA_10 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 18) +#define INTERRUPT_ID_ATM_DMA_11 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 19) +#define INTERRUPT_ID_ATM_DMA_12 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 20) +#define INTERRUPT_ID_ATM_DMA_13 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 21) +#define INTERRUPT_ID_ATM_DMA_14 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 22) +#define INTERRUPT_ID_ATM_DMA_15 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 23) +#define INTERRUPT_ID_ATM_DMA_16 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 24) +#define INTERRUPT_ID_ATM_DMA_17 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 25) +#define INTERRUPT_ID_ATM_DMA_18 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 26) +#define INTERRUPT_ID_ATM_DMA_19 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 27) +#define INTERRUPT_ID_IPSEC_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 28) +#define INTERRUPT_ID_IPSEC_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 29) +#define INTERRUPT_ID_PCM_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 30) +#define INTERRUPT_ID_PCM_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 31) + +#define INTERRUPT_ID_LAST INTERRUPT_ID_PCM_DMA_1 + +#ifdef __cplusplus + } +#endif + +#endif /* __BCM6368_H */ + + diff --git a/shared/opensource/include/bcm963xx/6368_map_part.h b/shared/opensource/include/bcm963xx/6368_map_part.h new file mode 100755 index 0000000..165adc2 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6368_map_part.h @@ -0,0 +1,1035 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM6368_MAP_H +#define __BCM6368_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 /* NAND registers */ +#define NAND_CACHE_BASE 0xb0000600 +#define SPI_BASE 0xb0000800 /* SPI master controller registers */ +#define MPI_BASE 0xb0001000 /* MPI control registers */ +#define MEMC_BASE 0xb0001200 /* Memory control registers */ +#define DDR_BASE 0xb0001280 /* DDR IO Buf Control registers */ +#define USB_EHCI_BASE 0x10001500 /* USB host registers */ +#define USB_OHCI_BASE 0x10001600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0001700 +#define SAR_DMA_BASE 0xb0005000 /* ATM SAR DMA control registers */ + + +typedef struct MemoryControl +{ + uint32 Control; /* (00) */ +#define MEMC_SELF_REFRESH (1<<6) // enable self refresh mode +#define MEMC_MRS (1<<4) // generate a mode register select cycle +#define MEMC_PRECHARGE (1<<3) // generate a precharge cycle +#define MEMC_REFRESH (1<<2) // generate an auto refresh cycle +#define MEMC_SEQUENCE_ENABLE (1<<1) // enable memory controller sequencer +#define MEMC_MASTER_ENABLE (1<<0) // enable accesses to external sdram + + uint32 Config; /* (04) */ +#define MEMC_EARLY_HDR_CNT_SHFT 25 +#define MEMC_EARLY_HDR_CNT_MASK (0x7<<MEMC_EARLYHDRCNT_SHFT) +#define MEMC_USE_HDR_CNT (1<<24) +#define MEMC_EN_FAST_REPLY (1<<23) +#define MEMC_RR_ARB (1<<22) +#define MEMC_SFX_NO_MRS2 (1<<21) +#define MEMC_SFX_NO_DLL_RST (1<<20) +#define MEMC_LLMB_ONE_REQ (1<<19) +#define MEMC_SYS_PORT_CMD_MODE (1<<18) +#define MEMC_PAD_OP_MODE (1<<17) +#define MEMC_DQS_GATE_EN (1<<16) +#define MEMC_PRED_RD_STROBE_EN (1<<15) +#define MEMC_PRED_RD_LATENCY_SEL (1<<14) +#define MEMC_UBUS_CLF_EN (1<<8) + +#define MEMC_ROW_SHFT 6 +#define MEMC_ROW_MASK (0x3<<MEMC_ROW_SHFT) +#define MEMC_11BIT_ROW 0 +#define MEMC_12BIT_ROW 1 +#define MEMC_13BIT_ROW 2 +#define MEMC_14BIT_ROW 3 + +#define MEMC_COL_SHFT 3 +#define MEMC_COL_MASK (0x7<<MEMC_COL_SHFT) +#define MEMC_8BIT_COL 0 +#define MEMC_9BIT_COL 1 +#define MEMC_10BIT_COL 2 +#define MEMC_11BIT_COL 3 + +#define MEMC_SEL_PRIORITY (1<<2) + +#define MEMC_WIDTH_SHFT 1 +#define MEMC_WIDTH_MASK (0x1<<MEMC_WIDTH_SHFT) +#define MEMC_32BIT_BUS 0 +#define MEMC_16BIT_BUS 1 + +#define MEMC_MEMTYPE_SDR (0<<0) +#define MEMC_MEMTYPE_DDR (1<<0) + + uint32 RefreshPdControl; /* (08) */ +#define MEMC_REFRESH_ENABLE (1<<15) + + uint32 BistStatus; /* (0C) */ + uint32 ExtendedModeBuffer; /* (10) */ + uint32 BankClosingTimer; /* (14) */ + uint32 PriorityInversionTimer; /* (18) */ + + uint32 DramTiming; /* (1c) */ +#define MEMC_WR_NOP_RD (1<<23) +#define MEMC_WR_NOP_WR (1<<22) +#define MEMC_RD_NOP_WR (1<<21) +#define MEMC_RD_NOP_RD (1<<20) +#define MEMC_CAS_LATENCY_2 (0) +#define MEMC_CAS_LATENCY_2_5 (1) +#define MEMC_CAS_LATENCY_3 (2) + + uint32 IntStatus; /* (20) */ + uint32 IntMask; /* (24) */ +#define MEMC_INT3 (1<<3) +#define MEMC_INT2 (2<<3) +#define MEMC_INT1 (1<<3) +#define MEMC_INT0 (0<<3) + + uint32 IntInfo; /* (28) */ + uint8 unused5[0x50-0x2c]; /* (2c) */ + uint32 Barrier; /* (50) */ + uint32 CoreId; /* (54) */ +} MemoryControl; + +#define MEMC ((volatile MemoryControl * const) MEMC_BASE) + +typedef struct DDRControl { + uint32 RevID; /* 00 */ + uint32 PadSSTLMode; /* 04 */ + uint32 CmdPadCntl; /* 08 */ + uint32 DQPadCntl; /* 0c */ + uint32 DQSPadCntl; /* 10 */ + uint32 ClkPadCntl0; /* 14 */ + uint32 MIPSDDRPLLCntl0; /* 18 */ + uint32 MIPSDDRPLLCntl1; /* 1c */ + uint32 MIPSDDRPLLConfig; /* 20 */ +#define MIPSDDR_NDIV_SHFT 16 +#define MIPSDDR_NDIV_MASK (0x1ff<<MIPSDDR_NDIV_SHFT) +#define REF_MDIV_SHFT 8 +#define REF_MDIV_MASK (0xff<<REF_MDIV_SHFT) +#define MIPSDDR_P2_SHFT 4 +#define MIPSDDR_P2_MASK (0xf<<MIPSDDR_P2_SHFT) +#define MIPSDDR_P1_SHFT 0 +#define MIPSDDR_P1_MASK (0xf<<MIPSDDR_P1_SHFT) + uint32 MIPSDDRPLLMDiv; /* 24 */ +#define DDR_MDIV_SHFT 8 +#define DDR_MDIV_MASK (0xff<<DDR_MDIV_SHFT) +#define MIPS_MDIV_SHFT 0 +#define MIPS_MDIV_MASK (0xff<<MIPS_MDIV_SHFT) + uint32 DSLCorePhaseCntl; /* 28 */ + uint32 DSLCpuPhaseCntr; /* 2c */ +#define DSL_PHY_AFE_PI_CNTR_CYCLES_SHIFT 28 +#define DSL_PHY_AFE_PI_CNTR_CYCLES_MASK (0xF << DSL_PHY_AFE_PI_CNTR_CYCLES_SHIFT) +#define DSL_PHY_PI_CNTR_CYCLES_SHIFT 24 +#define DSL_PHY_PI_CNTR_CYCLES_MASK (0xF << DSL_PHY_PI_CNTR_CYCLES_SHIFT) +#define DSL_PHY_AFE_PI_CNTR_EN (1 << 22) +#define DSL_PHY_PI_CNTR_EN (1 << 21) +#define DSL_CPU_PI_CNTR_EN (1 << 20) +#define DSL_CPU_PI_CNTR_CYCLES_SHIFT 16 +#define DSL_CPU_PI_CNTR_CYCLES_MASK (0xF << DSL_CPU_PI_CNTR_CYCLES_SHIFT) + uint32 MIPSPhaseCntl; /* 30 */ +#define PH_CNTR_EN (1 << 20) + uint32 DDR1_2PhaseCntl0; /* 34 */ + uint32 DDR3_4PhaseCntl0; /* 38 */ + uint32 VCDLPhaseCntl0; /* 3c */ + uint32 VCDLPhaseCntl1; /* 40 */ + uint32 WSliceCntl; /* 44 */ + uint32 DeskewDLLCntl; /* 48 */ + uint32 DeskewDLLReset; /* 4c */ + uint32 DeskewDLLPhase; /* 50 */ + uint32 AnalogTestCntl; /* 54 */ + uint32 RdDQSGateCntl; /* 58 */ + uint32 PLLTestReg; /* 5c */ + uint32 Spare0; /* 60 */ + uint32 Spare1; /* 64 */ + uint32 Spare2; /* 68 */ + uint32 CLBist; /* 6c */ + uint32 LBistCRC; /* 70 */ + uint32 UBUSPhaseCntl; /* 74 */ + uint32 UBUSPIDeskewLLMB0; /* 78 */ + uint32 UBUSPIDeskewLLMB1; /* 7C */ + +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define USBH_IDDQ_EN (1 << 19) +#define IPSEC_CLK_EN (1 << 18) +#define NAND_CLK_EN (1 << 17) +#define DISABLE_GLESS (1 << 16) +#define USBH_CLK_EN (1 << 15) +#define PCM_CLK_EN (1 << 14) +#define UTOPIA_CLK_EN (1 << 13) +#define ROBOSW_CLK_EN (1 << 12) +#define SAR_CLK_EN (1 << 11) +#define USBD_CLK_EN (1 << 10) +#define SPI_CLK_EN (1 << 9) +#define SWPKT_SAR_CLK_EN (1 << 8) +#define SWPKT_USB_CLK_EN (1 << 7) +#define PHYMIPS_CLK_EN (1 << 6) +#define VDSL_CLK_EN (1 << 5) +#define VDSL_BONDING_EN (1 << 4) +#define VDSL_AFE_EN (1 << 3) +#define VDSL_QPROC_EN (1 << 2) + + uint32 pll_control; /* (08) word 2 */ +#define SOFT_RESET 0x00000001 // 0 + + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_PCM (1 << 13) +#define SOFT_RST_USBH (1 << 12) +#define SOFT_RST_USBD (1 << 11) +#define SOFT_RST_SWITCH (1 << 10) +#define SOFT_RST_SAR (1 << 7) +#define SOFT_RST_EPHY (1 << 6) +#define SOFT_RST_IPSEC (1 << 4) +#define SOFT_RST_MPI (1 << 3) +#define SOFT_RST_SPI (1 << 0) + + uint32 unused1; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 ExtIrqCfg1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo<thresh + */ + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1) + * if these bits are also enabled to GPIO_o + */ +#define DTREN 0x01 +#define RTSEN 0x02 + + byte unused1; + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to + * detect irq on rising AND falling + * edges for corresponding GPIO_i + * if enabled (edge insensitive) + */ + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense + * 0 for negedge sense if + * not configured for edge + * insensitive (see above) + * Lower 4 bits: Mask to enable change + * detection IRQ for corresponding + * GPIO_i + */ + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits + * have changed (may set IRQ). + * read automatically clears bit + * Lower 4 bits are actual status + */ + + uint16 intMask; /* Same Bit defs for Mask and status */ + uint16 intStatus; +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + + uint16 unused2; + uint16 Data; /* Write to TX, Read from RX */ + /* bits 11:8 are BRK,PAR,FRM errors */ + + uint32 unused3; + uint32 unused4; +} Uart; + +#define UART ((volatile Uart * const) UART_BASE) + +/* +** Gpio Controller +*/ + +typedef struct GpioControl { + uint64 GPIODir; /* 0 */ + uint64 GPIOio; /* 8 */ + uint32 LEDCtrl; +#define LED_ALL_STROBE 0x0f000000 +#define LED3_STROBE 0x08000000 +#define LED2_STROBE 0x04000000 +#define LED1_STROBE 0x02000000 +#define LED0_STROBE 0x01000000 +#define LED_TEST 0x00010000 +#define DISABLE_LINK_ACT_ALL 0x0000f000 +#define DISABLE_LINK_ACT_3 0x00008000 +#define DISABLE_LINK_ACT_2 0x00004000 +#define DISABLE_LINK_ACT_1 0x00002000 +#define DISABLE_LINK_ACT_0 0x00001000 +#define LED_INTERVAL_SET_MASK 0x00000f00 +#define LED_INTERVAL_SET_1280MS 0x00000700 +#define LED_INTERVAL_SET_640MS 0x00000600 +#define LED_INTERVAL_SET_320MS 0x00000500 +#define LED_INTERVAL_SET_160MS 0x00000400 +#define LED_INTERVAL_SET_80MS 0x00000300 +#define LED_INTERVAL_SET_40MS 0x00000200 +#define LED_INTERVAL_SET_20MS 0x00000100 +#define LED_ON_ALL 0x000000f0 +#define LED_ON_3 0x00000080 +#define LED_ON_2 0x00000040 +#define LED_ON_1 0x00000020 +#define LED_ON_0 0x00000010 +#define LED_ENABLE_ALL 0x0000000f +#define LED_ENABLE_3 0x00000008 +#define LED_ENABLE_2 0x00000004 +#define LED_ENABLE_1 0x00000002 +#define LED_ENABLE_0 0x00000001 + uint32 SpiSlaveCfg; /* 14 */ + uint32 GPIOMode; /* 18 */ +#define GPIO_MODE_SPI_SSN5 (1<<31) +#define GPIO_MODE_SPI_SSN4 (1<<30) +#define GPIO_MODE_SPI_SSN3 (1<<29) +#define GPIO_MODE_SPI_SSN2 (1<<28) +#define GPIO_MODE_EBI_CS3 (1<<27) +#define GPIO_MODE_EBI_CS2 (1<<26) +#define GPIO_MODE_PCMCIA_VS2 (1<<25) +#define GPIO_MODE_PCMCIA_VS1 (1<<24) +#define GPIO_MODE_PCMCIA_CD2 (1<<23) +#define GPIO_MODE_PCMCIA_CD1 (1<<22) +#define GPIO_MODE_PCI_GNT0 (1<<20) +#define GPIO_MODE_PCI_REQ0 (1<<19) +#define GPIO_MODE_PCI_INTB (1<<18) +#define GPIO_MODE_PCI_GNT1 (1<<17) +#define GPIO_MODE_PCI_REQ1 (1<<16) +#define GPIO_MODE_USBD_LED (1<<14) +#define GPIO_MODE_ROBOSW_LED1 (1<<13) +#define GPIO_MODE_ROBOSW_LED0 (1<<12) +#define GPIO_MODE_ROBOSW_LED_CLK (1<<11) +#define GPIO_MODE_ROBOSW_LED_DATA (1<<10) +#define GPIO_MODE_EPHY3_LED (1<<9) +#define GPIO_MODE_EPHY2_LED (1<<8) +#define GPIO_MODE_EPHY1_LED (1<<7) +#define GPIO_MODE_EPHY0_LED (1<<6) +#define GPIO_MODE_INET_LED (1<<5) +#define GPIO_MODE_SERIAL_LED_CLK (1<<4) +#define GPIO_MODE_SERIAL_LED_DATA (1<<3) +#define GPIO_MODE_SYS_IRQ (1<<2) +#define GPIO_MODE_ANALOG_AFE_1 (1<<1) +#define GPIO_MODE_ANALOG_AFE_0 (1<<0) + + uint32 VregConfig; /* 1C */ +#define VREG_VSEL1P2_SHIFT 8 +#define VREG_VSEL1P2_MASK (0x0f<<8) +#define VREG_VSEL1P2_MIDDLE 9 + + uint32 AuxLedInterval; /* 20 */ +#define AUX_LED_IN_7 0x80000000 +#define AUX_LED_IN_6 0x40000000 +#define AUX_LED_IN_5 0x20000000 +#define AUX_LED_IN_4 0x10000000 +#define AUX_LED_IN_MASK 0xf0000000 +#define LED_IN_3 0x08000000 +#define LED_IN_2 0x04000000 +#define LED_IN_1 0x02000000 +#define LED_IN_0 0x01000000 +#define AUX_LED_TEST 0x00400000 +#define USE_NEW_INTV 0x00200000 +#define LED7_LNK_ORAND 0x00100000 +#define LED7_LNK_MASK 0x000f0000 +#define LED7_LNK_MASK_SHFT 16 +#define LED7_ACT_MASK 0x0000f000 +#define LED7_ACT_MASK_SHFT 12 +#define AUX_FLASH_INTV 0x00000fc0 +#define AUX_FLASH_INTV_SHFT 6 +#define AUX_BLINK_INTV 0x0000003f + uint32 AuxLedCtrl; /* 24 */ +#define AUX_HW_DISAB_7 0x80000000 +#define AUX_STROBE_7 0x40000000 +#define AUX_MODE_7 0x30000000 +#define AUX_MODE_SHFT_7 28 +#define AUX_HW_DISAB_6 0x08000000 +#define AUX_STROBE_6 0x04000000 +#define AUX_MODE_6 0x03000000 +#define AUX_MODE_SHFT_6 24 +#define AUX_HW_DISAB_5 0x00800000 +#define AUX_STROBE_5 0x00400000 +#define AUX_MODE_5 0x00300000 +#define AUX_MODE_SHFT_5 20 +#define AUX_HW_DISAB_4 0x00080000 +#define AUX_STROBE_4 0x00040000 +#define AUX_MODE_4 0x00030000 +#define AUX_MODE_SHFT_4 16 +#define AUX_HW_DISAB_3 0x00008000 +#define AUX_STROBE_3 0x00004000 +#define AUX_MODE_3 0x00003000 +#define AUX_MODE_SHFT_3 12 +#define AUX_HW_DISAB_2 0x00000800 +#define AUX_STROBE_2 0x00000400 +#define AUX_MODE_2 0x00000300 +#define AUX_MODE_SHFT_2 8 +#define AUX_HW_DISAB_1 0x00000080 +#define AUX_STROBE_1 0x00000040 +#define AUX_MODE_1 0x00000030 +#define AUX_MODE_SHFT_1 4 +#define AUX_HW_DISAB_0 0x00000008 +#define AUX_STROBE_0 0x00000004 +#define AUX_MODE_0 0x00000003 +#define AUX_MODE_SHFT_0 0 + +#define LED_STEADY_OFF 0x0 +#define LED_FLASH 0x1 +#define LED_BLINK 0x2 +#define LED_STEADY_ON 0x3 + + uint32 TestControl; /* 28 */ + + uint32 VDSLControl; /* 2C */ +#define VDSL_CORE_RESET (1<<2) +#define VDSL_MIPS_RESET (1<<1) +#define VDSL_MIPS_POR_RESET (1<<0) +#define VDSL_CLK_RATIO_SHIFT 8 +#define VDSL_CLK_RATIO_MSK (0x1F << VDSL_CLK_RATIO_SHIFT) + uint32 RoboSWLEDControl; /* 30 */ + uint32 RoboSWLEDLSR; /* 34 */ + uint32 GPIOBaseMode; /* 38 */ +#define EN_PCI_CLK_66 (1<<20) +#define EN_UTO_CLK_FAST (1<<19) +#define EN_UTO (1<<18) +#define EN_GMII2 (1<<17) +#define EN_GMII1 (1<<16) + uint32 RoboswEphyCtrl; /* 3C */ +#define RSW_HW_FWDG_EN (1<<19) +#define RSW_MII_DUMB_FWDG_EN (1<<16) +#define EPHY_RST_4 (1<<9) +#define EPHY_RST_3 (1<<8) +#define EPHY_RST_2 (1<<7) +#define EPHY_RST_1 (1<<6) +#define EPHY_PWR_DOWN_4 (1<<5) +#define EPHY_PWR_DOWN_3 (1<<4) +#define EPHY_PWR_DOWN_2 (1<<3) +#define EPHY_PWR_DOWN_1 (1<<2) +#define EPHY_PWR_DOWN_DLL (1<<1) +#define EPHY_PWR_DOWN_BIAS (1<<0) + uint32 StrapBus; /* 40 */ +#define UTOPIA_MASTER_ON (1<<14) +#define MISC_STRAP_BUS_BOOT_SEL_MASK 0x3 +#define MISC_STRAP_BUS_BOOT_SEL_SHIFT 0 +#define MISC_STRAP_BUS_BOOT_PARALLEL 0x03 +#define MISC_STRAP_BUS_BOOT_SERIAL 0x01 +#define MISC_STRAP_BUS_BOOT_NAND 0x00 + uint32 StrapOverride; /* 44 */ + + uint32 RingOscCtrl0; /* 48 */ +#define RING_OSC_256_CYCLES 8 +#define RING_OSC_512_CYCLES 9 +#define RING_OSC_1024_CYCLES 10 + + uint32 RingOscCtrl1; /* 4C */ +#define RING_OSC_ENABLE_MASK (0x7f<<24) +#define RING_OSC_ENABLE_SHIFT 24 +#define RING_OSC_MAX 7 +#define RING_OSC_COUNT_RESET (0x1<<23) +#define RING_OSC_SELECT_MASK (0x7<<20) +#define RING_OSC_SELECT_SHIFT 20 +#define RING_OSC_IRQ (0x1<<18) +#define RING_OSC_COUNTER_OVERFLOW (0x1<<17) +#define RING_OSC_COUNTER_BUSY (0x1<<16) +#define RING_OSC_COUNT_MASK 0x0000ffff + + uint32 SerialLed; /* 50 */ + uint32 SerialLedCtrl; /* 54 */ +#define SER_LED_BUSY (1<<3) +#define SER_LED_POLARITY (1<<2) +#define SER_LED_DIV_1 0 +#define SER_LED_DIV_2 1 +#define SER_LED_DIV_4 2 +#define SER_LED_DIV_8 3 +#define SER_LED_DIV_MASK 0x3 +#define SER_LED_DIV_SHIFT 0 + uint32 unused2[4]; /* 58 */ + uint32 DieRevID; /* 68 */ + uint32 DiagMemStatus; /* 6c */ + uint32 DiagSelControl; /* 70 */ + uint32 DiagReadBack; /* 74 */ + uint32 DiagReadBackHi; /* 78 */ + uint32 DiagMiscControl; /* 7c */ +#define EPHY_SA_RESET_N 0x00000300 +#define EPHY_SA_TESTEN 0x00000500 +#define EPHY_SA_CLOCK_RESET 0x0000d900 +} GpioControl; + +#define GPIO ((volatile GpioControl * const) GPIO_BASE) + +/* Number to mask conversion macro used for GPIODir and GPIOio */ +#define GPIO_NUM_MAX 40 +#define GPIO_NUM_TO_MASK(X) ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) ) + +/* +** Spi Controller +*/ + +typedef struct SpiControl { + uint16 spiMsgCtl; /* (0x0) control byte */ +#define FULL_DUPLEX_RW 0 +#define HALF_DUPLEX_W 1 +#define HALF_DUPLEX_R 2 +#define SPI_MSG_TYPE_SHIFT 14 +#define SPI_BYTE_CNT_SHIFT 0 + byte spiMsgData[0x21e]; /* (0x02 - 0x21f) msg data */ + byte unused0[0x1e0]; + byte spiRxDataFifo[0x220]; /* (0x400 - 0x61f) rx data */ + byte unused1[0xe0]; + + uint16 spiCmd; /* (0x700): SPI command */ +#define SPI_CMD_NOOP 0 +#define SPI_CMD_SOFT_RESET 1 +#define SPI_CMD_HARD_RESET 2 +#define SPI_CMD_START_IMMEDIATE 3 + +#define SPI_CMD_COMMAND_SHIFT 0 +#define SPI_CMD_COMMAND_MASK 0x000f + +#define SPI_CMD_DEVICE_ID_SHIFT 4 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 +#define SPI_CMD_ONE_BYTE_SHIFT 11 +#define SPI_CMD_ONE_WIRE_SHIFT 12 +#define SPI_DEV_ID_0 0 +#define SPI_DEV_ID_1 1 +#define SPI_DEV_ID_2 2 +#define SPI_DEV_ID_3 3 + + byte spiIntStatus; /* (0x702): SPI interrupt status */ + byte spiMaskIntStatus; /* (0x703): SPI masked interrupt status */ + + byte spiIntMask; /* (0x704): SPI interrupt mask */ +#define SPI_INTR_CMD_DONE 0x01 +#define SPI_INTR_RX_OVERFLOW 0x02 +#define SPI_INTR_INTR_TX_UNDERFLOW 0x04 +#define SPI_INTR_TX_OVERFLOW 0x08 +#define SPI_INTR_RX_UNDERFLOW 0x10 +#define SPI_INTR_CLEAR_ALL 0x1f + + byte spiStatus; /* (0x705): SPI status */ +#define SPI_RX_EMPTY 0x02 +#define SPI_CMD_BUSY 0x04 +#define SPI_SERIAL_BUSY 0x08 + + byte spiClkCfg; /* (0x706): SPI clock configuration */ +#define SPI_CLK_0_391MHZ 1 +#define SPI_CLK_0_781MHZ 2 /* default */ +#define SPI_CLK_1_563MHZ 3 +#define SPI_CLK_3_125MHZ 4 +#define SPI_CLK_6_250MHZ 5 +#define SPI_CLK_12_50MHZ 6 +#define SPI_CLK_MASK 0x07 +#define SPI_SSOFFTIME_MASK 0x38 +#define SPI_SSOFFTIME_SHIFT 3 +#define SPI_BYTE_SWAP 0x80 + + byte spiFillByte; /* (0x707): SPI fill byte */ + byte unused2; + byte spiMsgTail; /* (0x709): msgtail */ + byte unused3; + byte spiRxTail; /* (0x70B): rxtail */ +} SpiControl; + +#define SPI ((volatile SpiControl * const) SPI_BASE) + +#define IUDMA_MAX_CHANNELS 32 + +/* +** DMA Channel Configuration (1 .. 32) +*/ +typedef struct DmaChannelCfg { + uint32 cfg; /* (00) assorted configuration */ +#define DMA_ENABLE 0x00000001 /* set to enable channel */ +#define DMA_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ +#define DMA_BURST_HALT 0x00000004 /* idle after finish current memory burst */ + uint32 intStat; /* (04) interrupts control and status */ + uint32 intMask; /* (08) interrupts mask */ +#define DMA_BUFF_DONE 0x00000001 /* buffer done */ +#define DMA_DONE 0x00000002 /* packet xfer complete */ +#define DMA_NO_DESC 0x00000004 /* no valid descriptors */ + uint32 maxBurst; /* (0C) max burst length permitted */ +} DmaChannelCfg; + +/* +** DMA State RAM (1 .. 16) +*/ +typedef struct DmaStateRam { + uint32 baseDescPtr; /* (00) descriptor ring start address */ + uint32 state_data; /* (04) state/bytes done/ring offset */ + uint32 desc_len_status; /* (08) buffer descriptor status and len */ + uint32 desc_base_bufptr; /* (0C) buffer descrpitor current processing */ +} DmaStateRam; + + +/* +** DMA Registers +*/ +typedef struct DmaRegs { + uint32 controller_cfg; /* (00) controller configuration */ +#define DMA_MASTER_EN 0x00000001 +#define DMA_FLOWC_CH1_EN 0x00000002 +#define DMA_FLOWC_CH3_EN 0x00000004 + + // Flow control Ch1 + uint32 flowctl_ch1_thresh_lo; /* 004 */ + uint32 flowctl_ch1_thresh_hi; /* 008 */ + uint32 flowctl_ch1_alloc; /* 00c */ +#define DMA_BUF_ALLOC_FORCE 0x80000000 + + // Flow control Ch3 + uint32 flowctl_ch3_thresh_lo; /* 010 */ + uint32 flowctl_ch3_thresh_hi; /* 014 */ + uint32 flowctl_ch3_alloc; /* 018 */ + + // Flow control Ch5 + uint32 flowctl_ch5_thresh_lo; /* 01C */ + uint32 flowctl_ch5_thresh_hi; /* 020 */ + uint32 flowctl_ch5_alloc; /* 024 */ + + // Flow control Ch7 + uint32 flowctl_ch7_thresh_lo; /* 028 */ + uint32 flowctl_ch7_thresh_hi; /* 02C */ + uint32 flowctl_ch7_alloc; /* 030 */ + + uint32 ctrl_channel_reset; /* 034 */ + uint32 ctrl_channel_debug; /* 038 */ + uint32 reserved1; /* 03C */ + uint32 ctrl_global_interrupt_status; /* 040 */ + uint32 ctrl_global_interrupt_mask; /* 044 */ + + // Unused words + uint8 reserved2[0x200-0x48]; + + // Per channel registers/state ram + DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */ + union { + DmaStateRam s[IUDMA_MAX_CHANNELS]; + uint32 u32[4 * IUDMA_MAX_CHANNELS]; + } stram; /* (400-5FF) state ram */ +} DmaRegs; + +/* +** DMA Buffer +*/ +typedef struct DmaDesc { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ +} DmaDesc; + +/* +** External Bus Interface +*/ +typedef struct EbiChipSelect { + uint32 base; /* base address in upper 24 bits */ +#define EBI_SIZE_8K 0 +#define EBI_SIZE_16K 1 +#define EBI_SIZE_32K 2 +#define EBI_SIZE_64K 3 +#define EBI_SIZE_128K 4 +#define EBI_SIZE_256K 5 +#define EBI_SIZE_512K 6 +#define EBI_SIZE_1M 7 +#define EBI_SIZE_2M 8 +#define EBI_SIZE_4M 9 +#define EBI_SIZE_8M 10 +#define EBI_SIZE_16M 11 +#define EBI_SIZE_32M 12 +#define EBI_SIZE_64M 13 +#define EBI_SIZE_128M 14 +#define EBI_SIZE_256M 15 + uint32 config; +#define EBI_ENABLE 0x00000001 /* .. enable this range */ +#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */ +#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */ +#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */ +#define EBI_WREN 0x00000020 /* enable posted writes */ +#define EBI_POLARITY 0x00000040 /* .. set to invert something, + ** don't know what yet */ +#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */ +#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */ +#define EBI_FIFO 0x00000200 /* .. use fifo */ +#define EBI_RE 0x00000400 /* .. Reverse Endian */ +#define EBI_SETUP_SHIFT 16 +#define EBI_HOLD_SHIFT 20 +#define EBI_SETUP_STATES 0x0f0000 +#define EBI_HOLD_STATES 0xf00000 +} EbiChipSelect; + +typedef struct MpiRegisters { + EbiChipSelect cs[7]; /* size chip select configuration */ +#define EBI_CS0_BASE 0 +#define EBI_CS1_BASE 1 +#define EBI_CS2_BASE 2 +#define EBI_CS3_BASE 3 +#define PCMCIA_COMMON_BASE 4 +#define PCMCIA_ATTRIBUTE_BASE 5 +#define PCMCIA_IO_BASE 6 + uint32 unused0[2]; /* reserved */ + uint32 ebi_control; /* ebi control */ + uint32 unused1[4]; /* reserved */ +#define EBI_ACCESS_TIMEOUT 0x000007FF + uint32 pcmcia_cntl1; /* pcmcia control 1 */ +#define PCCARD_CARD_RESET 0x00040000 +#define CARDBUS_ENABLE 0x00008000 +#define PCMCIA_ENABLE 0x00004000 +#define PCMCIA_GPIO_ENABLE 0x00002000 +#define CARDBUS_IDSEL 0x00001F00 +#define VS2_OEN 0x00000080 +#define VS1_OEN 0x00000040 +#define VS2_OUT 0x00000020 +#define VS1_OUT 0x00000010 +#define VS2_IN 0x00000008 +#define VS1_IN 0x00000004 +#define CD2_IN 0x00000002 +#define CD1_IN 0x00000001 +#define VS_MASK 0x0000000C +#define CD_MASK 0x00000003 + uint32 unused2; /* reserved */ + uint32 pcmcia_cntl2; /* pcmcia control 2 */ +#define PCMCIA_BYTESWAP_DIS 0x00000002 +#define PCMCIA_HALFWORD_EN 0x00000001 +#define RW_ACTIVE_CNT_BIT 2 +#define INACTIVE_CNT_BIT 8 +#define CE_SETUP_CNT_BIT 16 +#define CE_HOLD_CNT_BIT 24 + uint32 unused3[40]; /* reserved */ + + uint32 sp0range; /* PCI to internal system bus address space */ +#define ADDR_SPACE_MASK 0xFFFF0000 + uint32 sp0remap; + uint32 sp0cfg; + uint32 sp1range; + uint32 sp1remap; + uint32 sp1cfg; + + uint32 EndianCfg; + + uint32 l2pcfgctl; /* internal system bus to PCI IO/Cfg control */ +#define DIR_CFG_SEL 0x80000000 /* change from PCI I/O access to PCI config access */ +#define DIR_CFG_USEREG 0x40000000 /* use this register info for PCI configuration access */ +#define DEVICE_NUMBER 0x00007C00 /* device number for the PCI configuration access */ +#define FUNC_NUMBER 0x00000300 /* function number for the PCI configuration access */ +#define REG_NUMBER 0x000000FC /* register number for the PCI configuration access */ +#define CONFIG_TYPE 0x00000003 /* configuration type for the PCI configuration access */ + + uint32 l2pmrange1; /* internal system bus to PCI memory space */ +#define PCI_SIZE_64K 0xFFFF0000 +#define PCI_SIZE_128K 0xFFFE0000 +#define PCI_SIZE_256K 0xFFFC0000 +#define PCI_SIZE_512K 0xFFF80000 +#define PCI_SIZE_1M 0xFFF00000 +#define PCI_SIZE_2M 0xFFE00000 +#define PCI_SIZE_4M 0xFFC00000 +#define PCI_SIZE_8M 0xFF800000 +#define PCI_SIZE_16M 0xFF000000 +#define PCI_SIZE_32M 0xFE000000 + uint32 l2pmbase1; /* kseg0 or kseg1 address & 0x1FFFFFFF */ + uint32 l2pmremap1; +#define CARDBUS_MEM 0x00000004 +#define MEM_WINDOW_EN 0x00000001 + uint32 l2pmrange2; + uint32 l2pmbase2; + uint32 l2pmremap2; + uint32 l2piorange; /* internal system bus to PCI I/O space */ + uint32 l2piobase; + uint32 l2pioremap; + + uint32 pcimodesel; +#define PCI_INT_BUS_RD_PREFETCH 0x000001F0 +#define PCI_BAR2_NOSWAP 0x00000002 /* BAR at offset 0x20 */ +#define PCI_BAR1_NOSWAP 0x00000001 /* BAR at affset 0x1c */ + + uint32 pciintstat; /* PCI interrupt mask/status */ +#define MAILBOX1_SENT 0x08 +#define MAILBOX0_SENT 0x04 +#define MAILBOX1_MSG_RCV 0x02 +#define MAILBOX0_MSG_RCV 0x01 + uint32 locbuscntrl; /* internal system bus control */ +#define DIR_U2P_NOSWAP 0x00000002 +#define EN_PCI_GPIO 0x00000001 + uint32 locintstat; /* internal system bus interrupt mask/status */ +#define CSERR 0x0200 +#define SERR 0x0100 +#define EXT_PCI_INT 0x0080 +#define DIR_FAILED 0x0040 +#define DIR_COMPLETE 0x0020 +#define PCI_CFG 0x0010 + uint32 unused4[7]; + + uint32 mailbox0; + uint32 mailbox1; + + uint32 pcicfgcntrl; /* internal system bus PCI configuration control */ +#define PCI_CFG_REG_WRITE_EN 0x00000080 +#define PCI_CFG_ADDR 0x0000003C + uint32 pcicfgdata; /* internal system bus PCI configuration data */ + + uint32 locch2ctl; /* PCI to interrnal system bus DMA (downstream) local control */ +#define MPI_DMA_HALT 0x00000008 /* idle after finish current memory burst */ +#define MPI_DMA_PKT_HALT 0x00000004 /* idle after an EOP flag is detected */ +#define MPI_DMA_STALL 0x00000002 /* idle after an EOP flag is detected */ +#define MPI_DMA_ENABLE 0x00000001 /* set to enable channel */ + uint32 locch2intStat; +#define MPI_DMA_NO_DESC 0x00000004 /* no valid descriptors */ +#define MPI_DMA_DONE 0x00000002 /* packet xfer complete */ +#define MPI_DMA_BUFF_DONE 0x00000001 /* buffer done */ + uint32 locch2intMask; + uint32 unused5; + uint32 locch2descaddr; + uint32 locch2status1; +#define LOCAL_DESC_STATE 0xE0000000 +#define PCI_DESC_STATE 0x1C000000 +#define BYTE_DONE 0x03FFC000 +#define RING_ADDR 0x00003FFF + uint32 locch2status2; +#define BUFPTR_OFFSET 0x1FFF0000 +#define PCI_MASTER_STATE 0x000000C0 +#define LOC_MASTER_STATE 0x00000038 +#define CONTROL_STATE 0x00000007 + uint32 unused6; + + uint32 locch1Ctl; /*internal system bus to PCI DMA (upstream) local control */ +#define DMA_U2P_LE 0x00000200 /* local bus is little endian */ +#define DMA_U2P_NOSWAP 0x00000100 /* lccal bus is little endian but no data swapped */ + uint32 locch1intstat; + uint32 locch1intmask; + uint32 unused7; + uint32 locch1descaddr; + uint32 locch1status1; + uint32 locch1status2; + uint32 unused8; + + uint32 pcich1ctl; /* internal system bus to PCI DMA PCI control */ + uint32 pcich1intstat; + uint32 pcich1intmask; + uint32 pcich1descaddr; + uint32 pcich1status1; + uint32 pcich1status2; + + uint32 pcich2Ctl; /* PCI to internal system bus DMA PCI control */ + uint32 pcich2intstat; + uint32 pcich2intmask; + uint32 pcich2descaddr; + uint32 pcich2status1; + uint32 pcich2status2; + + uint32 perm_id; /* permanent device and vendor id */ + uint32 perm_rev; /* permanent revision id */ +} MpiRegisters; + +#define MPI ((volatile MpiRegisters * const) MPI_BASE) + +/* PCI configuration address space start offset 0x40 */ +#define BRCM_PCI_CONFIG_TIMER 0x40 +#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK 0x0000FF00 +#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK 0x000000FF + +typedef struct USBControl { + uint32 BrtControl1; + uint32 BrtControl2; + uint32 BrtStatus1; + uint32 BrtStatus2; + uint32 UTMIControl1; + uint32 TestPortControl; + uint32 PllControl1; + uint32 SwapControl; +#define USB_DEVICE_SEL (1<<6) +#define EHCI_LOGICAL_ADDRESS_EN (1<<5) +#define EHCI_ENDIAN_SWAP (1<<4) +#define EHCI_DATA_SWAP (1<<3) +#define OHCI_LOGICAL_ADDRESS_EN (1<<2) +#define OHCI_ENDIAN_SWAP (1<<1) +#define OHCI_DATA_SWAP (1<<0) + uint32 unused1; + uint32 FrameAdjustValue; + uint32 Setup; +#define USBH_IOC (1<<4) + uint32 MDIO; + uint32 MDIO32; + uint32 USBSimControl; +} USBControl; + +#define USBH ((volatile USBControl * const) USBH_CFG_BASE) + +/* +** NAND Controller Registers +*/ +typedef struct NandCtrlRegs { + uint32 NandRevision; /* NAND Revision */ + uint32 NandCmdStart; /* Nand Flash Command Start */ + uint32 NandCmdExtAddr; /* Nand Flash Command Extended Address */ + uint32 NandCmdAddr; /* Nand Flash Command Address */ + uint32 NandCmdEndAddr; /* Nand Flash Command End Address */ + uint32 NandNandBootConfig; /* Nand Flash Boot Config */ +#define NBC_AUTO_DEV_ID_CFG 0x40000000 + uint32 NandCsNandXor; /* Nand Flash EBI CS Address XOR with */ +} NandCtrlRegs; + +#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE) +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/shared/opensource/include/bcm963xx/6816_cpu.h b/shared/opensource/include/bcm963xx/6816_cpu.h new file mode 100755 index 0000000..56afce7 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6816_cpu.h @@ -0,0 +1,150 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM6816_CPU_H +#define __BCM6816_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* +#************************************************************************ +#* Coprocessor 0 Register Names +#************************************************************************ +*/ +#define C0_BCM_CONFIG $22 + +/* +# Select 1 +# Bit 31: unused +# Bits 30:25 MMU Size (Num TLB entries-1) +# Bits 24:22 ICache sets/way (2^n * 64) +# Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache +# Bits 18:16 ICache Associativity (n+1) way +# Bits 15:13 DCache sets/way (2^n * 64) +# Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache +# Bits 9:7 DCache Associativity (n+1) way +# Bits 6:4 unused +# Bit 3: 1=At least 1 watch register +# Bit 2: 1=MIPS16 code compression implemented +# Bit 1: 1=EJTAG implemented +# Bit 0: 1=FPU implemented +*/ +#define CP0_CFG_ISMSK (0x7 << 22) +#define CP0_CFG_ISSHF 22 +#define CP0_CFG_ILMSK (0x7 << 19) +#define CP0_CFG_ILSHF 19 +#define CP0_CFG_IAMSK (0x7 << 16) +#define CP0_CFG_IASHF 16 +#define CP0_CFG_DSMSK (0x7 << 13) +#define CP0_CFG_DSSHF 13 +#define CP0_CFG_DLMSK (0x7 << 10) +#define CP0_CFG_DLSHF 10 +#define CP0_CFG_DAMSK (0x7 << 7) +#define CP0_CFG_DASHF 7 + +/* +#************************************************************************ +#* Coprocessor 0 Broadcom Config Register Bits +#************************************************************************ +*/ +#define CP0_BCM_CFG_ICSHEN (0x1 << 31) +#define CP0_BCM_CFG_DCSHEN (0x1 << 30) +#define CP0_BCM_CFG_BTHD (0x1 << 21) +#define CP0_BCM_CFG_CLF (0x1 << 20) +#define CP0_BCM_CFG_NBK (0x1 << 17) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Interrupt Register +#************************************************************************ +*/ +#define CP0_CMT_XIR_4 (0x1 << 31) +#define CP0_CMT_XIR_3 (0x1 << 30) +#define CP0_CMT_XIR_2 (0x1 << 29) +#define CP0_CMT_XIR_1 (0x1 << 28) +#define CP0_CMT_XIR_0 (0x1 << 27) +#define CP0_CMT_SIR_1 (0x1 << 16) +#define CP0_CMT_SIR_0 (0x1 << 15) +#define CP0_CMT_NMIR_TP1 (0x1 << 1) +#define CP0_CMT_NMIR_TP0 (0x1 << 0) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Control Register +#************************************************************************ +*/ +#define CP0_CMT_DSU_TP1 (0x1 << 30) +#define CP0_CMT_TPS_SHFT 16 +#define CP0_CMT_TPS_MASK (0xF << CP0_CMT_TPS_SHFT) +#define CP0_CMT_PRIO_TP1 (0x1 << 5) +#define CP0_CMT_PRIO_TP0 (0x1 << 4) +#define CP0_CMT_RSTSE (0x1 << 0) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Local Register +#************************************************************************ +*/ +#define CP0_CMT_TPID (0x1 << 31) + +/* +#************************************************************************ +#* MIPS Registers +#************************************************************************ +*/ + +#define MIPS_BASE_BOOT 0xbfa00000 +#define MIPS_BASE 0xff400000 + +#define MIPS_RAC_CR0 0x00 // RAC Configuration Register +#define MIPS_RAC_CR1 0x08 // RAC Configuration Register 1 +#define RAC_FLH (1 << 8) +#define RAC_DPF (1 << 6) +#define RAC_NCH (1 << 5) +#define RAC_C_INV (1 << 4) +#define RAC_PF_D (1 << 3) +#define RAC_PF_I (1 << 2) +#define RAC_D (1 << 1) +#define RAC_I (1 << 0) + +#define MIPS_RAC_ARR 0x04 // RAC Address Range Register +#define RAC_UPB_SHFT 16 +#define RAC_LWB_SHFT 0 + +#define MIPS_LMB_CR 0x1C // LMB Control Register +#define LMB_EN (1 << 0) + +#define MIPS_SBR 0x20 // System Base Register + +#define MIPS_TP0_ALT_BV 0x30000 +#define MIPS_TP1_ALT_BV 0x38000 +#define ENABLE_ALT_BV (1 << 19) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/opensource/include/bcm963xx/6816_intr.h b/shared/opensource/include/bcm963xx/6816_intr.h new file mode 100755 index 0000000..6a8d9e8 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6816_intr.h @@ -0,0 +1,116 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __6816_INTR_H +#define __6816_INTR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#define INTERRUPT_ID_SOFTWARE_0 0 +#define INTERRUPT_ID_SOFTWARE_1 1 + +/*=====================================================================*/ +/* BCM6816 Timer Interrupt Level Assignments */ +/*=====================================================================*/ +#define MIPS_TIMER_INT 7 + +/*=====================================================================*/ +/* Peripheral ISR Table Offset */ +/*=====================================================================*/ +#define INTERNAL_ISR_TABLE_OFFSET 8 +#define INTERNAL_HIGH_ISR_TABLE_OFFSET (INTERNAL_ISR_TABLE_OFFSET + 32) + +/*=====================================================================*/ +/* Logical Peripheral Interrupt IDs */ +/*=====================================================================*/ + +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0) +#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1) +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2) +#define INTERRUPT_ID_UART1 (INTERNAL_ISR_TABLE_OFFSET + 3) +#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 4) +#define INTERRUPT_ID_USBH (INTERNAL_ISR_TABLE_OFFSET + 5) +#define INTERRUPT_ID_IPSEC (INTERNAL_ISR_TABLE_OFFSET + 6) +#define INTERRUPT_ID_USBH20 (INTERNAL_ISR_TABLE_OFFSET + 7) +#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 8) +#define INTERRUPT_ID_RING_OSC (INTERNAL_ISR_TABLE_OFFSET + 9) +#define INTERRUPT_ID_NAND_FLASH (INTERNAL_ISR_TABLE_OFFSET + 10) +#define INTERRUPT_ID_GPON (INTERNAL_ISR_TABLE_OFFSET + 11) +#define INTERRUPT_ID_APM (INTERNAL_ISR_TABLE_OFFSET + 12) +#define INTERRUPT_ID_MPI (INTERNAL_ISR_TABLE_OFFSET + 13) +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 14) +#define INTERRUPT_ID_PCIE_NMI (INTERNAL_ISR_TABLE_OFFSET + 15) +#define INTERRUPT_ID_PCIE_A (INTERNAL_ISR_TABLE_OFFSET + 16) +#define INTERRUPT_ID_PCIE_B (INTERNAL_ISR_TABLE_OFFSET + 17) +#define INTERRUPT_ID_PCIE_C (INTERNAL_ISR_TABLE_OFFSET + 18) +#define INTERRUPT_ID_PCIE_D (INTERNAL_ISR_TABLE_OFFSET + 19) +#define INTERRUPT_ID_EXTERNAL_0 (INTERNAL_ISR_TABLE_OFFSET + 20) +#define INTERRUPT_ID_EXTERNAL_1 (INTERNAL_ISR_TABLE_OFFSET + 21) +#define INTERRUPT_ID_EXTERNAL_2 (INTERNAL_ISR_TABLE_OFFSET + 22) +#define INTERRUPT_ID_EXTERNAL_3 (INTERNAL_ISR_TABLE_OFFSET + 23) +#define INTERRUPT_ID_EXTERNAL_4 (INTERNAL_ISR_TABLE_OFFSET + 24) +#define INTERRUPT_ID_EXTERNAL_5 (INTERNAL_ISR_TABLE_OFFSET + 25) +#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 26) +#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 27) +#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 28) +#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 29) +#define INTERRUPT_ID_USB_ISO_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 30) +#define INTERRUPT_ID_USB_ISO_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 31) +#define INTERRUPT_ID_ENETSW_RX_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 0) +#define INTERRUPT_ID_ENETSW_RX_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 1) +#define INTERRUPT_ID_ENETSW_RX_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 2) +#define INTERRUPT_ID_ENETSW_RX_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 3) +#define INTERRUPT_ID_ENETSW_TX_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 4) +#define INTERRUPT_ID_ENETSW_TX_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 5) +#define INTERRUPT_ID_ENETSW_TX_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 6) +#define INTERRUPT_ID_ENETSW_TX_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 7) +#define INTERRUPT_ID_MOCA_STOP (INTERNAL_HIGH_ISR_TABLE_OFFSET + 8) +#define INTERRUPT_ID_MOCA_START (INTERNAL_HIGH_ISR_TABLE_OFFSET + 9) +#define INTERRUPT_ID_MOCA_GEN (INTERNAL_HIGH_ISR_TABLE_OFFSET + 10) +#define INTERRUPT_ID_MOCA_WDG (INTERNAL_HIGH_ISR_TABLE_OFFSET + 11) +#define INTERRUPT_ID_EPHY_ENERGY_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 12) +#define INTERRUPT_ID_EPHY_ENERGY_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 13) +#define INTERRUPT_ID_GPON_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 14) +#define INTERRUPT_ID_GPON_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 15) +#define INTERRUPT_ID_APM_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 16) +#define INTERRUPT_ID_APM_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 17) +#define INTERRUPT_ID_APM_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 18) +#define INTERRUPT_ID_APM_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 19) +#define INTERRUPT_ID_APM_DMA_4 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 20) +#define INTERRUPT_ID_APM_DMA_5 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 21) +#define INTERRUPT_ID_IPSEC_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 28) +#define INTERRUPT_ID_IPSEC_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 29) +#define INTERRUPT_ID_I2C (INTERNAL_HIGH_ISR_TABLE_OFFSET + 31) + +#define INTERRUPT_ID_LAST INTERRUPT_ID_I2C + +#ifdef __cplusplus + } +#endif + +#endif /* __BCM6816_H */ + + diff --git a/shared/opensource/include/bcm963xx/6816_map_part.h b/shared/opensource/include/bcm963xx/6816_map_part.h new file mode 100755 index 0000000..f7aa541 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6816_map_part.h @@ -0,0 +1,1487 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM6816_MAP_H +#define __BCM6816_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define SPI_BASE 0xb0000800 /* SPI master controller registers */ +#define HSSPIM_BASE 0xb0001000 /* High-Speed SPI registers */ +#define MISC_BASE 0xb0001800 /* Miscellaneous Registers */ +#define NAND_REG_BASE 0xb0002000 /* NAND registers */ +#define MPI_BASE 0xb00020A0 /* MPI control registers */ +#define NAND_CACHE_BASE 0xb0002200 +#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10002500 /* USB host registers */ +#define USB_OHCI_BASE 0x10002600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0002700 +#define DDR_BASE 0xb0003000 /* Memory control registers */ +#define GPON_SERDES_BASE 0xb0004800 /* GPON SERDES Interface Registers */ +#define APM_HVG_BASE 0xb0008300 /* High-Voltage Generation */ +#define APM_HVG_BASE_REG_15 0xb0008408 /* High-Voltage Generation Register 15 */ +#define APM_HVG_BASE_REG_19 0xb0008488 /* High-Voltage Generation Register 19 */ +#define PCIE_BASE 0xb0e40000 /* PCIE registers */ + +typedef struct DDRPhyControl { + uint32 REVISION; /* 0x00 */ + uint32 CLK_PM_CTRL; /* 0x04 */ + uint32 unused0[2]; /* 0x08-0x10 */ + uint32 PLL_STATUS; /* 0x10 */ + uint32 PLL_CONFIG; /* 0x14 */ + uint32 PLL_PRE_DIVIDER; /* 0x18 */ + uint32 PLL_DIVIDER; /* 0x1c */ + uint32 PLL_CONTROL1; /* 0x20 */ + uint32 PLL_CONTROL2; /* 0x24 */ + uint32 PLL_SS_EN; /* 0x28 */ + uint32 PLL_SS_CFG; /* 0x2c */ + uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ + uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ + uint32 IDLE_PAD_CONTROL; /* 0x38 */ + uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_REG_CONTROL; /* 0x44 */ + uint32 unused1[46]; +} DDRPhyControl; + +typedef struct DDRPhyByteLaneControl { + uint32 REVISION; /* 0x00 */ + uint32 VDL_CALIBRATE; /* 0x04 */ + uint32 VDL_STATUS; /* 0x08 */ + uint32 unused; /* 0x0c */ + uint32 VDL_OVERRIDE_0; /* 0x10 */ + uint32 VDL_OVERRIDE_1; /* 0x14 */ + uint32 VDL_OVERRIDE_2; /* 0x18 */ + uint32 VDL_OVERRIDE_3; /* 0x1c */ + uint32 VDL_OVERRIDE_4; /* 0x20 */ + uint32 VDL_OVERRIDE_5; /* 0x24 */ + uint32 VDL_OVERRIDE_6; /* 0x28 */ + uint32 VDL_OVERRIDE_7; /* 0x2c */ + uint32 READ_CONTROL; /* 0x30 */ + uint32 READ_FIFO_STATUS; /* 0x34 */ + uint32 READ_FIFO_CLEAR; /* 0x38 */ + uint32 IDLE_PAD_CONTROL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_PAD_DISABLE; /* 0x44 */ + uint32 WR_PREAMBLE_MODE; /* 0x48 */ + uint32 CLOCK_REG_CONTROL; /* 0x4C */ + uint32 unused0[44]; +} DDRPhyByteLaneControl; + +typedef struct DDRControl { + uint32 CNFG; /* 0x000 */ + uint32 CSST; /* 0x004 */ + uint32 CSEND; /* 0x008 */ + uint32 unused; /* 0x00c */ + uint32 ROW00_0; /* 0x010 */ + uint32 ROW00_1; /* 0x014 */ + uint32 ROW01_0; /* 0x018 */ + uint32 ROW01_1; /* 0x01c */ + uint32 unused0[4]; + uint32 ROW20_0; /* 0x030 */ + uint32 ROW20_1; /* 0x034 */ + uint32 ROW21_0; /* 0x038 */ + uint32 ROW21_1; /* 0x03c */ + uint32 unused1[4]; + uint32 COL00_0; /* 0x050 */ + uint32 COL00_1; /* 0x054 */ + uint32 COL01_0; /* 0x058 */ + uint32 COL01_1; /* 0x05c */ + uint32 unused2[4]; + uint32 COL20_0; /* 0x070 */ + uint32 COL20_1; /* 0x074 */ + uint32 COL21_0; /* 0x078 */ + uint32 COL21_1; /* 0x07c */ + uint32 unused3[4]; + uint32 BNK10; /* 0x090 */ + uint32 BNK32; /* 0x094 */ + uint32 unused4[26]; + uint32 DCMD; /* 0x100 */ +#define DCMD_CS1 (1 << 5) +#define DCMD_CS0 (1 << 4) +#define DCMD_SET_SREF 4 + uint32 DMODE_0; /* 0x104 */ + uint32 DMODE_1; /* 0x108 */ +#define DMODE_1_DRAMSLEEP (1 << 11) + uint32 CLKS; /* 0x10c */ + uint32 ODT; /* 0x110 */ + uint32 TIM1_0; /* 0x114 */ + uint32 TIM1_1; /* 0x118 */ + uint32 TIM2; /* 0x11c */ + uint32 CTL_CRC; /* 0x120 */ + uint32 DOUT_CRC; /* 0x124 */ + uint32 DIN_CRC; /* 0x128 */ + uint32 unused5[53]; + + DDRPhyControl PhyControl; /* 0x200 */ + DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ + DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ + DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ + DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ + uint32 unused6[64]; + + uint32 GCFG; /* 0x800 */ + uint32 LBIST_CFG; /* 0x804 */ + uint32 LBIST_SEED; /* 0x808 */ + uint32 ARB; /* 0x80c */ + uint32 PI_GCF; /* 0x810 */ + uint32 PI_UBUS_CTL; /* 0x814 */ + uint32 PI_MIPS_CTL; /* 0x818 */ + uint32 PI_DSL_MIPS_CTL; /* 0x81c */ + uint32 PI_DSL_PHY_CTL; /* 0x820 */ + uint32 PI_UBUS_ST; /* 0x824 */ + uint32 PI_MIPS_ST; /* 0x828 */ + uint32 PI_DSL_MIPS_ST; /* 0x82c */ + uint32 PI_DSL_PHY_ST; /* 0x830 */ + uint32 PI_UBUS_SMPL; /* 0x834 */ + uint32 TESTMODE; /* 0x838 */ + uint32 TEST_CFG1; /* 0x83c */ + uint32 TEST_PAT; /* 0x840 */ + uint32 TEST_COUNT; /* 0x844 */ + uint32 TEST_CURR_COUNT; /* 0x848 */ + uint32 TEST_ADDR_UPDT; /* 0x84c */ + uint32 TEST_ADDR; /* 0x850 */ + uint32 TEST_DATA0; /* 0x854 */ + uint32 TEST_DATA1; /* 0x858 */ + uint32 TEST_DATA2; /* 0x85c */ + uint32 TEST_DATA3; /* 0x860 */ +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define ACP_A_CLK_EN (1 << 25) +#define ACP_B_CLK_EN (1 << 24) +#define NTP_CLK_EN (1 << 23) +#define PCM_CLK_EN (1 << 22) +#define BMU_CLK_EN (1 << 21) +#define PCIE_CLK_EN (1 << 20) +#define GPON_SER_CLK_EN (1 << 19) +#define IPSEC_CLK_EN (1 << 18) +#define NAND_CLK_EN (1 << 17) +#define DISABLE_GLESS (1 << 16) +#define USBH_CLK_EN (1 << 15) +#define APM_CLK_EN (1 << 14) +#define ROBOSW_CLK_EN (1 << 12) +#define USBD_CLK_EN (1 << 10) +#define SPI_CLK_EN (1 << 9) +#define SWPKT_GPON_CLK_EN (1 << 8) +#define SWPKT_USB_CLK_EN (1 << 7) +#define GPON_CLK_EN (1 << 6) + + uint32 pll_control; /* (08) word 2 */ +#define SOFT_RESET 0x00000001 // 0 + + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_SERDES_DIG (1 << 23) +#define SOFT_RST_SERDES (1 << 22) +#define SOFT_RST_SERDES_MDIO (1 << 21) +#define SOFT_RST_SERDES_PLL (1 << 20) +#define SOFT_RST_SERDES_HW (1 << 19) +#define SOFT_RST_GPON (1 << 18) +#define SOFT_RST_BMU (1 << 17) +#define SOFT_RST_HVG (1 << 16) +#define SOFT_RST_APM (1 << 15) +#define SOFT_RST_ACP (1 << 14) +#define SOFT_RST_PCM (1 << 13) +#define SOFT_RST_USBH (1 << 12) +#define SOFT_RST_USBD (1 << 11) +#define SOFT_RST_SWITCH (1 << 10) +#define SOFT_RST_MOCA_CPU (1 << 9) +#define SOFT_RST_MOCA_SYS (1 << 8) +#define SOFT_RST_MOCA (1 << 7) +#define SOFT_RST_EPHY (1 << 6) +#define SOFT_RST_PCIE (1 << 5) +#define SOFT_RST_IPSEC (1 << 4) +#define SOFT_RST_MPI (1 << 3) +#define SOFT_RST_PCIE_EXT (1 << 2) +#define SOFT_RST_PCIE_CORE (1 << 1) +#define SOFT_RST_SPI (1 << 0) + + uint32 diagControl; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 ExtIrqCfg1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo<thresh + */ + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1) + * if these bits are also enabled to GPIO_o + */ +#define DTREN 0x01 +#define RTSEN 0x02 + + byte unused1; + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to + * detect irq on rising AND falling + * edges for corresponding GPIO_i + * if enabled (edge insensitive) + */ + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense + * 0 for negedge sense if + * not configured for edge + * insensitive (see above) + * Lower 4 bits: Mask to enable change + * detection IRQ for corresponding + * GPIO_i + */ + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits + * have changed (may set IRQ). + * read automatically clears bit + * Lower 4 bits are actual status + */ + + uint16 intMask; /* Same Bit defs for Mask and status */ + uint16 intStatus; +#define DELTAIP 0x0001 +#define TXUNDERR 0x0002 +#define TXOVFERR 0x0004 +#define TXFIFOTHOLD 0x0008 +#define TXREADLATCH 0x0010 +#define TXFIFOEMT 0x0020 +#define RXUNDERR 0x0040 +#define RXOVFERR 0x0080 +#define RXTIMEOUT 0x0100 +#define RXFIFOFULL 0x0200 +#define RXFIFOTHOLD 0x0400 +#define RXFIFONE 0x0800 +#define RXFRAMERR 0x1000 +#define RXPARERR 0x2000 +#define RXBRK 0x4000 + + uint16 unused2; + uint16 Data; /* Write to TX, Read from RX */ + /* bits 11:8 are BRK,PAR,FRM errors */ + + uint32 unused3; + uint32 unused4; +} Uart; + +#define UART ((volatile Uart * const) UART_BASE) + +/* +** Gpio Controller +*/ + +typedef struct GpioControl { + uint64 GPIODir; /* 0 */ + uint64 GPIOio; /* 8 */ +#define GPIO_MoCA_OVERLAY_UART_WRITE 39 +#define GPIO_MoCA_OVERLAY_UART_READ 38 + uint32 LEDCtrl; +#define LED_ALL_STROBE 0x0f000000 +#define LED3_STROBE 0x08000000 +#define LED2_STROBE 0x04000000 +#define LED1_STROBE 0x02000000 +#define LED0_STROBE 0x01000000 +#define LED_TEST 0x00010000 +#define DISABLE_LINK_ACT_ALL 0x0000f000 +#define DISABLE_LINK_ACT_3 0x00008000 +#define DISABLE_LINK_ACT_2 0x00004000 +#define DISABLE_LINK_ACT_1 0x00002000 +#define DISABLE_LINK_ACT_0 0x00001000 +#define LED_INTERVAL_SET_MASK 0x00000f00 +#define LED_INTERVAL_SET_1280MS 0x00000700 +#define LED_INTERVAL_SET_640MS 0x00000600 +#define LED_INTERVAL_SET_320MS 0x00000500 +#define LED_INTERVAL_SET_160MS 0x00000400 +#define LED_INTERVAL_SET_80MS 0x00000300 +#define LED_INTERVAL_SET_40MS 0x00000200 +#define LED_INTERVAL_SET_20MS 0x00000100 +#define LED_ON_ALL 0x000000f0 +#define LED_ON_3 0x00000080 +#define LED_ON_2 0x00000040 +#define LED_ON_1 0x00000020 +#define LED_ON_0 0x00000010 +#define LED_ENABLE_ALL 0x0000000f +#define LED_ENABLE_3 0x00000008 +#define LED_ENABLE_2 0x00000004 +#define LED_ENABLE_1 0x00000002 +#define LED_ENABLE_0 0x00000001 + uint32 SpiSlaveCfg; /* 14 */ + uint32 GPIOMode; /* 18 */ +#define GPIO_MODE_SPI_SSN5 (1<<31) +#define GPIO_MODE_SPI_SSN4 (1<<30) +#define GPIO_MODE_SPI_SSN3 (1<<29) +#define GPIO_MODE_SPI_SSN2 (1<<28) +#define GPIO_MODE_EBI_CS3 (1<<27) +#define GPIO_MODE_EBI_CS2 (1<<26) +#define GPIO_MODE_APM_CLK (1<<25) +#define GPIO_MODE_APM_SDIN (1<<24) +#define GPIO_MODE_APM_SDOUT (1<<23) +#define GPIO_MODE_APM_FRAME_SYNC (1<<22) +#define GPIO_MODE_PCI_GNT0 (1<<20) +#define GPIO_MODE_PCI_REQ0 (1<<19) +#define GPIO_MODE_PCI_INTB (1<<18) +#define GPIO_MODE_PCI_GNT1 (1<<17) +#define GPIO_MODE_PCI_REQ1 (1<<16) +#define GPIO_MODE_NTR_PULSE (1<<15) +#define GPIO_MODE_USBD_LED (1<<14) +#define GPIO_MODE_ROBOSW_LED1 (1<<13) +#define GPIO_MODE_ROBOSW_LED0 (1<<12) +#define GPIO_MODE_ROBOSW_LED_CLK (1<<11) +#define GPIO_MODE_ROBOSW_LED_DATA (1<<10) +#define GPIO_MODE_GPON_LED (1<<8) +#define GPIO_MODE_GPHY1_LED (1<<7) +#define GPIO_MODE_GPHY0_LED (1<<6) +#define GPIO_MODE_MOCA_LED (1<<5) +#define GPIO_MODE_SERIAL_LED_CLK (1<<4) +#define GPIO_MODE_SERIAL_LED_DATA (1<<3) +#define GPIO_MODE_SYS_IRQ (1<<2) +#define GPIO_MODE_GPON_TX_APC_FAIL (1<<1) /*Anticipating B0*/ +#define GPIO_MODE_GPON_TX_EN_L (1<<0) + + uint32 VregConfig; /* 1C */ +#define VREG_VSEL1P2_SHIFT 8 +#define VREG_VSEL1P2_MASK (0x0f<<8) +#define VREG_VSEL1P2_MIDDLE 9 + + uint32 AuxLedInterval; /* 20 */ +#define AUX_LED_IN_7 0x80000000 +#define AUX_LED_IN_6 0x40000000 +#define AUX_LED_IN_5 0x20000000 +#define AUX_LED_IN_4 0x10000000 +#define AUX_LED_IN_MASK 0xf0000000 +#define LED_IN_3 0x08000000 +#define LED_IN_2 0x04000000 +#define LED_IN_1 0x02000000 +#define LED_IN_0 0x01000000 +#define AUX_LED_TEST 0x00400000 +#define USE_NEW_INTV 0x00200000 +#define LED7_LNK_ORAND 0x00100000 +#define LED7_LNK_MASK 0x000f0000 +#define LED7_LNK_MASK_SHFT 16 +#define LED7_ACT_MASK 0x0000f000 +#define LED7_ACT_MASK_SHFT 12 +#define AUX_FLASH_INTV 0x00000fc0 +#define AUX_FLASH_INTV_100MS 0x00000140 +#define AUX_FLASH_INTV_SHFT 6 +#define AUX_BLINK_INTV 0x0000003f +#define AUX_BLINK_INTV_60MS 0x00000003 + uint32 AuxLedCtrl; /* 24 */ +#define AUX_HW_DISAB_7 0x80000000 +#define AUX_STROBE_7 0x40000000 +#define AUX_MODE_7 0x30000000 +#define AUX_MODE_SHFT_7 28 +#define AUX_HW_DISAB_6 0x08000000 +#define AUX_STROBE_6 0x04000000 +#define AUX_MODE_6 0x03000000 +#define AUX_MODE_SHFT_6 24 +#define AUX_HW_DISAB_5 0x00800000 +#define AUX_STROBE_5 0x00400000 +#define AUX_MODE_5 0x00300000 +#define AUX_MODE_SHFT_5 20 +#define AUX_HW_DISAB_4 0x00080000 +#define AUX_STROBE_4 0x00040000 +#define AUX_MODE_4 0x00030000 +#define AUX_MODE_SHFT_4 16 +#define AUX_HW_DISAB_3 0x00008000 +#define AUX_STROBE_3 0x00004000 +#define AUX_MODE_3 0x00003000 +#define AUX_MODE_SHFT_3 12 +#define AUX_HW_DISAB_2 0x00000800 +#define AUX_STROBE_2 0x00000400 +#define AUX_MODE_2 0x00000300 +#define AUX_MODE_SHFT_2 8 +#define AUX_HW_DISAB_1 0x00000080 +#define AUX_STROBE_1 0x00000040 +#define AUX_MODE_1 0x00000030 +#define AUX_MODE_SHFT_1 4 +#define AUX_HW_DISAB_0 0x00000008 +#define AUX_STROBE_0 0x00000004 +#define AUX_MODE_0 0x00000003 +#define AUX_MODE_SHFT_0 0 + +#define LED_STEADY_OFF 0x0 +#define LED_FLASH 0x1 +#define LED_BLINK 0x2 +#define LED_STEADY_ON 0x3 + + uint32 TestControl; /* 28 */ + + uint32 OscControl; /* 2C */ + uint32 RoboSWLEDControl; /* 30 */ + uint32 RoboSWLEDLSR; /* 34 */ + uint32 GPIOBaseMode; /* 38 */ +#define EN_GMII2 (1<<17) +#define EN_GMII1 (1<<16) + uint32 RoboswEphyCtrl; /* 3C */ +#define RSW_HW_FWDG_EN (1<<19) +#define RSW_MII_DUMB_FWDG_EN (1<<16) +#define EPHY_RST_4 (1<<9) +#define EPHY_RST_3 (1<<8) +#define EPHY_RST_2 (1<<7) +#define EPHY_RST_1 (1<<6) +#define EPHY_PWR_DOWN_4 (1<<5) +#define EPHY_PWR_DOWN_3 (1<<4) +#define EPHY_PWR_DOWN_2 (1<<3) +#define EPHY_PWR_DOWN_1 (1<<2) + uint32 unused1[2]; /* 40 */ + + uint32 RingOscCtrl0; /* 48 */ +#define RING_OSC_256_CYCLES 8 +#define RING_OSC_512_CYCLES 9 +#define RING_OSC_1024_CYCLES 10 + + uint32 RingOscCtrl1; /* 4C */ +#define RING_OSC_ENABLE_MASK (0x57<<24) +#define RING_OSC_ENABLE_SHIFT 24 +#define RING_OSC_MAX 7 +#define RING_OSC_COUNT_RESET (0x1<<23) +#define RING_OSC_SELECT_MASK (0x7<<20) +#define RING_OSC_SELECT_SHIFT 20 +#define RING_OSC_IRQ (0x1<<18) +#define RING_OSC_COUNTER_OVERFLOW (0x1<<17) +#define RING_OSC_COUNTER_BUSY (0x1<<16) +#define RING_OSC_COUNT_MASK 0x0000ffff + + uint32 SerialLed; /* 50 */ + uint32 SerialLedCtrl; /* 54 */ +#define SER_LED_BUSY (1<<3) +#define SER_LED_POLARITY (1<<2) +#define SER_LED_DIV_1 0 +#define SER_LED_DIV_2 1 +#define SER_LED_DIV_4 2 +#define SER_LED_DIV_8 3 +#define SER_LED_DIV_MASK 0x3 +#define SER_LED_DIV_SHIFT 0 + uint32 SerialLedBlink; /* 58 */ + uint32 SerdesCtl; /* 5c */ +#define SERDES_PCIE_ENABLE 0x00000001 +#define SERDES_PCIE_EXD_ENABLE (1<<15) + uint32 SerdesStatus; /* 60 */ + uint32 unused2; /* 64 */ + uint32 DieRevID; /* 68 */ + uint32 DiagMemStatus; /* 6c */ + uint32 DiagSelControl; /* 70 */ + uint32 DiagReadBack; /* 74 */ + uint32 DiagReadBackHi; /* 78 */ + uint32 DiagMiscControl; /* 7c */ +#define EPHY_SA_RESET_N 0x00000300 +#define EPHY_SA_TESTEN 0x00000500 +#define EPHY_SA_CLOCK_RESET 0x0000d900 +} GpioControl; + +#define GPIO ((volatile GpioControl * const) GPIO_BASE) + +/* Number to mask conversion macro used for GPIODir and GPIOio */ +#define GPIO_NUM_MAX 40 +#define GPIO_NUM_TO_MASK(X) ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) ) + +/* +** Spi Controller +*/ + +typedef struct SpiControl { + uint16 spiMsgCtl; /* (0x0) control byte */ +#define FULL_DUPLEX_RW 0 +#define HALF_DUPLEX_W 1 +#define HALF_DUPLEX_R 2 +#define SPI_MSG_TYPE_SHIFT 14 +#define SPI_BYTE_CNT_SHIFT 0 + byte spiMsgData[0x21e]; /* (0x02 - 0x21f) msg data */ + byte unused0[0x1e0]; + byte spiRxDataFifo[0x220]; /* (0x400 - 0x61f) rx data */ + byte unused1[0xe0]; + + uint16 spiCmd; /* (0x700): SPI command */ +#define SPI_CMD_NOOP 0 +#define SPI_CMD_SOFT_RESET 1 +#define SPI_CMD_HARD_RESET 2 +#define SPI_CMD_START_IMMEDIATE 3 + +#define SPI_CMD_COMMAND_SHIFT 0 +#define SPI_CMD_COMMAND_MASK 0x000f + +#define SPI_CMD_DEVICE_ID_SHIFT 4 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 +#define SPI_CMD_ONE_BYTE_SHIFT 11 +#define SPI_CMD_ONE_WIRE_SHIFT 12 +#define SPI_DEV_ID_0 0 +#define SPI_DEV_ID_1 1 +#define SPI_DEV_ID_2 2 +#define SPI_DEV_ID_3 3 + + byte spiIntStatus; /* (0x702): SPI interrupt status */ + byte spiMaskIntStatus; /* (0x703): SPI masked interrupt status */ + + byte spiIntMask; /* (0x704): SPI interrupt mask */ +#define SPI_INTR_CMD_DONE 0x01 +#define SPI_INTR_RX_OVERFLOW 0x02 +#define SPI_INTR_INTR_TX_UNDERFLOW 0x04 +#define SPI_INTR_TX_OVERFLOW 0x08 +#define SPI_INTR_RX_UNDERFLOW 0x10 +#define SPI_INTR_CLEAR_ALL 0x1f + + byte spiStatus; /* (0x705): SPI status */ +#define SPI_RX_EMPTY 0x02 +#define SPI_CMD_BUSY 0x04 +#define SPI_SERIAL_BUSY 0x08 + + byte spiClkCfg; /* (0x706): SPI clock configuration */ +#define SPI_CLK_0_391MHZ 1 +#define SPI_CLK_0_781MHZ 2 /* default */ +#define SPI_CLK_1_563MHZ 3 +#define SPI_CLK_3_125MHZ 4 +#define SPI_CLK_6_250MHZ 5 +#define SPI_CLK_12_50MHZ 6 +#define SPI_CLK_MASK 0x07 +#define SPI_SSOFFTIME_MASK 0x38 +#define SPI_SSOFFTIME_SHIFT 3 +#define SPI_BYTE_SWAP 0x80 + + byte spiFillByte; /* (0x707): SPI fill byte */ + byte unused2; + byte spiMsgTail; /* (0x709): msgtail */ + byte unused3; + byte spiRxTail; /* (0x70B): rxtail */ +} SpiControl; + + +#define SPI ((volatile SpiControl * const) SPI_BASE) + + +/* +** High-Speed SPI Controller +*/ + +#define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start) +typedef struct HsSpiControl { + + uint32 hs_spiGlobalCtrl; // 0x0000 +#define HS_SPI_MOSI_IDLE (1 << 18) +#define HS_SPI_CLK_STATE_GATED (1 << 17) +#define HS_SPI_CLK_GATE_SSOFF (1 << 16) +#define HS_SPI_PLL_CLK_CTRL (8) +#define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL) +#define HS_SPI_SS_POLARITY (0) +#define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY) + + uint32 hs_spiExtTrigCtrl; // 0x0004 +#define HS_SPI_TRIG_RAW_STATE (24) +#define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE) +#define HS_SPI_TRIG_LATCHED (16) +#define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED) +#define HS_SPI_TRIG_SENSE (8) +#define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE) +#define HS_SPI_TRIG_TYPE (0) +#define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE) +#define HS_SPI_TRIG_TYPE_EDGE (0) +#define HS_SPI_TRIG_TYPE_LEVEL (1) + + uint32 hs_spiIntStatus; // 0x0008 +#define HS_SPI_IRQ_PING1_USER (28) +#define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER) +#define HS_SPI_IRQ_PING0_USER (24) +#define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER) + +#define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQ_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQ_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntStatusMasked; // 0x000C +#define HS_SPI_IRQSM__PING1_USER (28) +#define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER) +#define HS_SPI_IRQSM__PING0_USER (24) +#define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER) + +#define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0) + + uint32 hs_spiIntMask; // 0x0010 +#define HS_SPI_IRQM_PING1_USER (28) +#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER) +#define HS_SPI_IRQM_PING0_USER (24) +#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER) + +#define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12) +#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11) +#define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10) +#define HS_SPI_IRQM_PING1_RX_OVER (1 << 9) +#define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8) + +#define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4) +#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3) +#define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2) +#define HS_SPI_IRQM_PING0_RX_OVER (1 << 1) +#define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0) + +#define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F) + + uint32 hs_spiFlashCtrl; // 0x0014 +#define HS_SPI_FCTRL_MB_ENABLE (1 << 23) +#define HS_SPI_FCTRL_SS_NUM (20) +#define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM) +#define HS_SPI_FCTRL_PROFILE_NUM (16) +#define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM) +#define HS_SPI_FCTRL_DUMMY_BYTES (10) +#define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES (8) +#define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES) +#define HS_SPI_FCTRL_ADDR_BYTES_2 (0) +#define HS_SPI_FCTRL_ADDR_BYTES_3 (1) +#define HS_SPI_FCTRL_ADDR_BYTES_4 (2) +#define HS_SPI_FCTRL_READ_OPCODE (0) +#define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE) + + uint32 hs_spiFlashAddrBase; // 0x0018 + + char fill0[0x80 - 0x18]; + + uint32 hs_spiPP_0_Cmd; // 0x0080 +#define HS_SPI_PP_SS_NUM (12) +#define HS_SPI_PP_SS_NUM_MASK __mask(14, HS_SPI_PP_SS_NUM) +#define HS_SPI_PP_PROFILE_NUM (8) +#define HS_SPI_PP_PROFILE_NUM_MASK __mask(10, HS_SPI_PP_PROFILE_NUM) + +} HsSpiControl; + +typedef struct HsSpiPingPong { + + uint32 command; +#define HS_SPI_SS_NUM (12) +#define HS_SPI_PROFILE_NUM (8) +#define HS_SPI_TRIGGER_NUM (4) +#define HS_SPI_COMMAND_VALUE (0) + #define HS_SPI_COMMAND_NOOP (0) + #define HS_SPI_COMMAND_START_NOW (1) + #define HS_SPI_COMMAND_START_TRIGGER (2) + #define HS_SPI_COMMAND_HALT (3) + #define HS_SPI_COMMAND_FLUSH (4) + + uint32 status; +#define HS_SPI_ERROR_BYTE_OFFSET (16) +#define HS_SPI_WAIT_FOR_TRIGGER (2) +#define HS_SPI_SOURCE_BUSY (1) +#define HS_SPI_SOURCE_GNT (0) + + uint32 fifo_status; + uint32 control; + +} HsSpiPingPong; + +typedef struct HsSpiProfile { + + uint32 clk_ctrl; +#define HS_SPI_ACCUM_RST_ON_LOOP (15) +#define HS_SPI_SPI_CLK_2X_SEL (14) +#define HS_SPI_FREQ_CTRL_WORD (0) + + uint32 signal_ctrl; +#define HS_SPI_LAUNCH_RISING (1 << 13) +#define HS_SPI_LATCH_RISING (1 << 12) + + uint32 mode_ctrl; +#define HS_SPI_PREPENDBYTE_CNT (24) +#define HS_SPI_MODE_ONE_WIRE (20) +#define HS_SPI_MULTIDATA_WR_SIZE (18) +#define HS_SPI_MULTIDATA_RD_SIZE (16) +#define HS_SPI_MULTIDATA_WR_STRT (12) +#define HS_SPI_MULTIDATA_RD_STRT (8) +#define HS_SPI_FILLBYTE (0) + + uint32 polling_config; + uint32 polling_and_mask; + uint32 polling_compare; + uint32 polling_timeout; + uint32 reserved; + +} HsSpiProfile; + +#define HS_SPI_OP_CODE 13 + #define HS_SPI_OP_SLEEP (0) + #define HS_SPI_OP_READ_WRITE (1) + #define HS_SPI_OP_WRITE (2) + #define HS_SPI_OP_READ (3) + #define HS_SPI_OP_SETIRQ (4) + +#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE) +#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80)) +#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0)) +#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100)) +#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200)) +#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400)) + + +/* +** Periph - Misc Register Set Definitions. +*/ + +typedef struct Misc { + uint32 miscMoCADiv ; /* (0x0) MoCA Ref PLL Div */ +#define MISC_MOCA_DIV_REF_DIV_FB_MASK 0xFF000000 +#define MISC_MOCA_DIV_REF_DIV_FB_SHIFT 24 +#define MISC_MOCA_DIV_REF_OUTDIV_M1_MASK 0x00FF0000 +#define MISC_MOCA_DIV_REF_OUTDIV_M1_SHIFT 16 +#define MISC_MOCA_DIV_REF_OUTDIV_M4_MASK 0x0000FF00 +#define MISC_MOCA_DIV_REF_OUTDIV_M4_SHIFT 8 +#define MISC_MOCA_DIV_REF_OUTDIV_M5_MASK 0x000000FF +#define MISC_MOCA_DIV_REF_OUTDIV_M5_SHIFT 0 + uint32 miscMoCACtl ; /* (0x4) MoCA Ref PLL Ctl */ +#define MISC_MOCA_CTL_REF_OUTCML_LOWCUR_MASK 0x001FC000 +#define MISC_MOCA_CTL_REF_OUTCML_LOWCUR_SHIFT 14 +#define MISC_MOCA_CTL_REF_CLFCNT_MASK 0x00003000 +#define MISC_MOCA_CTL_REF_CLFCNT_SHIFT 12 +#define MISC_MOCA_CTL_REF_QP_ICTRL_MASK 0x00000E00 +#define MISC_MOCA_CTL_REF_QP_ICTRL_SHIFT 9 +#define MISC_MOCA_CTL_REF_VCOBUF_LATCH_ON 0x00000100 +#define MISC_MOCA_CTL_REF_LF_RCNTL_MASK 0x000000E0 +#define MISC_MOCA_CTL_REF_LF_RCNTL_SHIFT 5 +#define MISC_MOCA_CTL_REF_MUX_FBOFF 0x00000010 +#define MISC_MOCA_CTL_REF_MUX_SEL_MASK 0x0000000C +#define MISC_MOCA_CTL_REF_MUX_SEL_SHIFT 2 +#define MISC_MOCA_CTL_REF_REF_CMLBIAS_MASK 0x00000003 +#define MISC_MOCA_CTL_REF_REF_CMLBIAS_SHIFT 0 + uint32 miscMoCAPwr ; /* (0x8) MoCA Ref PLL Pwr */ +#define MISC_MOCA_PWR_REF_DEEP_PWRDN 0x01000000 +#define MISC_MOCA_PWR_REF_OUTDIV_PWRDN_M_MASK 0x00FE0000 +#define MISC_MOCA_PWR_REF_OUTDIV_PWRDN_M_SHIFT 17 +#define MISC_MOCA_PWR_REF_OUTCML_PWRDN_M_MASK 0x0001FC00 +#define MISC_MOCA_PWR_REF_OUTCML_PWRDN_M_SHIFT 10 +#define MISC_MOCA_PWR_REF_OUTCMOS_PWRDN_M_MASK 0x000003F8 +#define MISC_MOCA_PWR_REF_OUTCMOS_PWRDN_M_SHIFT 3 +#define MISC_MOCA_PWR_REF_UGB_PWRDN 0x00000004 +#define MISC_MOCA_PWR_REF_MUX_PWRDN 0x00000002 +#define MISC_MOCA_PWR_REF_VCO_PWRDN 0x00000001 + uint32 miscMoCARst ; /* (0xC) MoCA Ref PLL Rst */ +#define MISC_MOCA_RST_REF_OUTDIV_RESET_M_MASK 0x00000FE0 +#define MISC_MOCA_RST_REF_OUTDIV_RESET_M_SHIFT 5 +#define MISC_MOCA_RST_REF_DIV2RST 0x00000010 +#define MISC_MOCA_RST_REF_MDIV2RST 0x00000008 +#define MISC_MOCA_RST_REF_FBDIVRST 0x00000004 +#define MISC_MOCA_RST_REF_LD_RESET_STRT 0x00000002 +#define MISC_MOCA_RST_REF_VCRST 0x00000001 + uint32 miscMemcControl ; /* (0x10) MEMC Control */ +#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE 0x00000008 +#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE 0x00000004 +#define MISC_MEMC_CONTROL_DDR_TEST_DONE 0x00000002 +#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE 0x00000001 + uint32 miscStrapBus ; /* (0x14) Strap Register */ +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK 0xF8000000 +#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 27 +#define MISC_STRAP_BUS_HRD_RST_DELAY 0x04000000 +#define MISC_STRAP_BUS_ALT_BFC_EN 0x02000000 +#define MISC_STRAP_BUS_MOCA_STANDALONE_B 0x01000000 +#define MISC_STRAP_BUS_MOCA_CONFIG_RATIO 0x00800000 +#define MISC_STRAP_BUS_IXTAL_ADJ_MASK 0x00600000 +#define MISC_STRAP_BUS_IXTAL_ADJ_SHIFT 21 +#define MISC_STRAP_BUS_BYPASS_XTAL 0x00100000 +#define MISC_STRAP_BUS_TS 0x00080000 +#define MISC_STRAP_BUS_APM_PICO_BOOT_ROM 0x00040000 +#define MISC_STRAP_BUS_TA 0x00020000 +#define MISC_STRAP_BUS_ROBOSW_2_MODE_MASK 0x00018000 +#define MISC_STRAP_BUS_ROBOSW_2_MODE_SHIFT 15 +#define MISC_STRAP_BUS_ROBOSW_1_MODE_MASK 0x00006000 +#define MISC_STRAP_BUS_ROBOSW_1_MODE_SHIFT 13 +#define MISC_STRAP_BUS_BIST_CLRMEM_N 0x00001000 +#define MISC_STRAP_BUS_PLL_MIPS_WAIT_FAST_N 0x00000200 +#define MISC_STRAP_BUS_PLL_USE_LOCK 0x00000100 +#define MISC_STRAP_BUS_PCIE_ROOT_COMPLEX 0x00000080 +#define MISC_STRAP_BUS_LS_SPIM_ENABLED 0x00000040 +#define MISC_STRAP_BUS_USE_SPI_MASTER 0x00000020 +#define MISC_STRAP_BUS_SPI_CLK_FAST 0x00000010 +#define MISC_STRAP_BUS_SPI_BOOT_DELAY 0x00000008 +#define MISC_STRAP_BUS_MIPS_BOOT16 0x00000004 +#define MISC_STRAP_BUS_BOOT_SEL_MASK 0x00000003 +#define MISC_STRAP_BUS_BOOT_SEL_SHIFT 0 +#define MISC_STRAP_BUS_BOOT_PARALLEL 0x03 +#define MISC_STRAP_BUS_BOOT_SERIAL 0x01 +#define MISC_STRAP_BUS_BOOT_NAND 0x02 + uint32 miscStrapOverride ; /* (0x18) Strap Override Reg */ +#define MISC_STRAP_OVERRIDE_INT_MPI_ARB 0x00000008 +#define MISC_STRAP_OVERRIDE_INT_MPI_CLK 0x00000004 +#define MISC_STRAP_OVERRIDE_INT_HOST 0x00000002 +#define MISC_STRAP_OVERRIDE_STRAP_OVERRIDE 0x00000001 + uint32 miscMoCAClkStrapBus ; /* (0x1C) MoCA Clock Strap Reg */ +#define MISC_MOCA_CLK_STRAP_BUS_MDIV_10_OVERRIDE_MASK 0x0000FF00 +#define MISC_MOCA_CLK_STRAP_BUS_MDIV_10_OVERRIDE_SHIFT 8 +#define MISC_MOCA_CLK_STRAP_BUS_MDIV_9_OVERRIDE_MASK 0x000000FF +#define MISC_MOCA_CLK_STRAP_BUS_MDIV_9_OVERRIDE_SHIFT 0 + uint32 miscMoCAClkStrapOverride ; /* (0x20) MoCA Clock Strap Overdide Reg */ +#define MISC_MOCA_CLK_STRAP_OVERRIDE_MOCA_CLK_STRAP_OVERRIDE_CTL 0x00000001 + uint32 miscMoCAGpioOverlayLo ; /* (0x24) MoCA GPIO Overlay bus lo Reg */ + uint32 miscMoCAGpioOverlayHi ; /* (0x28) MoCA GPIO Overlay bus hi Reg */ +#define MISC_MOCA_GPIO_UART 0x000000C0 + uint32 miscDdrPllOutEnCh ; /* (0x2C) DDR PLL Out En Ch Number */ +#define MISC_DDR_PLL_OUTEN_CH_DDR_PLL_OUTEN_CH_MASK 0x000001FF +#define MISC_DDR_PLL_OUTEN_CH_DDR_PLL_OUTEN_CH_SHIFT 0 +#define MISC_DDR_PLL_OUTEN_CH_MOCA_CPU_CLK 0x00000080 +#define MISC_DDR_PLL_OUTEN_CH_MOCA_PHY_CLK 0x00000100 + uint32 miscGpioDiagOverlay ; /* (0x30) GPIO Diag Overlay Control Reg */ +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_EN 0x00000020 +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_MASK 0x0000001F +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_39_32 0x00000010 +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_31_24 0x00000008 +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_23_16 0x00000004 +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_15_8 0x00000002 +#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_7_0 0x00000001 + uint32 miscGpioModeCtrlHi ; /* (0x34) GPIO Pin Mode Control Reg Hi */ +} Misc ; + +#define MISC ((volatile Misc * const) MISC_BASE) + +typedef struct HvgMiscRegisterChannelA { + uint32 mask; +#define K_PROP 0x0000000f +#define K_INTEG 0x000000f0 +#define SER_TST_OUTPUT_SEL 0x00000700 +#define CONT_OR_BLOCK 0x00000800 +#define HVG_MODE 0x00003000 +#define HVG_MODE_OFFHOOK_TRACKING 0x00001000 +#define HVG_MODE_ONHOOK_FIXED 0x00002000 +#define HVG_SOFT_INIT_0 0x00004000 +#define HVG_RR_SINGLE 0x00008000 +} HvgMiscRegisterChannelA; + +#define HVG_MISC_REG_CHANNEL_A ((volatile HvgMiscRegisterChannelA * const) APM_HVG_BASE_REG_15) + +typedef struct HvgMiscRegisterChannelB { + uint32 mask; +} HvgMiscRegisterChannelB; + +#define HVG_MISC_REG_CHANNEL_B ((volatile HvgMiscRegisterChannelB * const) APM_HVG_BASE_REG_19) + +#define IUDMA_MAX_CHANNELS 32 + +/* +** DMA Channel Configuration (1 .. 32) +*/ +typedef struct DmaChannelCfg { + uint32 cfg; /* (00) assorted configuration */ +#define DMA_ENABLE 0x00000001 /* set to enable channel */ +#define DMA_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ +#define DMA_BURST_HALT 0x00000004 /* idle after finish current memory burst */ + uint32 intStat; /* (04) interrupts control and status */ + uint32 intMask; /* (08) interrupts mask */ +#define DMA_BUFF_DONE 0x00000001 /* buffer done */ +#define DMA_DONE 0x00000002 /* packet xfer complete */ +#define DMA_NO_DESC 0x00000004 /* no valid descriptors */ + uint32 maxBurst; /* (0C) max burst length permitted */ +#define DMA_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */ +} DmaChannelCfg; + +/* +** DMA State RAM (1 .. 16) +*/ +typedef struct DmaStateRam { + uint32 baseDescPtr; /* (00) descriptor ring start address */ + uint32 state_data; /* (04) state/bytes done/ring offset */ + uint32 desc_len_status; /* (08) buffer descriptor status and len */ + uint32 desc_base_bufptr; /* (0C) buffer descrpitor current processing */ +} DmaStateRam; + + +/* +** DMA Registers +*/ +typedef struct DmaRegs { + uint32 controller_cfg; /* (00) controller configuration */ +#define DMA_MASTER_EN 0x00000001 +#define DMA_FLOWC_CH1_EN 0x00000002 +#define DMA_FLOWC_CH3_EN 0x00000004 + + // Flow control Ch1 + uint32 flowctl_ch1_thresh_lo; /* 004 */ + uint32 flowctl_ch1_thresh_hi; /* 008 */ + uint32 flowctl_ch1_alloc; /* 00c */ +#define DMA_BUF_ALLOC_FORCE 0x80000000 + + // Flow control Ch3 + uint32 flowctl_ch3_thresh_lo; /* 010 */ + uint32 flowctl_ch3_thresh_hi; /* 014 */ + uint32 flowctl_ch3_alloc; /* 018 */ + + // Flow control Ch5 + uint32 flowctl_ch5_thresh_lo; /* 01C */ + uint32 flowctl_ch5_thresh_hi; /* 020 */ + uint32 flowctl_ch5_alloc; /* 024 */ + + // Flow control Ch7 + uint32 flowctl_ch7_thresh_lo; /* 028 */ + uint32 flowctl_ch7_thresh_hi; /* 02C */ + uint32 flowctl_ch7_alloc; /* 030 */ + + uint32 ctrl_channel_reset; /* 034 */ + uint32 ctrl_channel_debug; /* 038 */ + uint32 reserved1; /* 03C */ + uint32 ctrl_global_interrupt_status; /* 040 */ + uint32 ctrl_global_interrupt_mask; /* 044 */ + + // Unused words + uint8 reserved2[0x200-0x48]; + + // Per channel registers/state ram + DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */ + union { + DmaStateRam s[IUDMA_MAX_CHANNELS]; + uint32 u32[4 * IUDMA_MAX_CHANNELS]; + } stram; /* (400-5FF) state ram */ +} DmaRegs; + +#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE) + +/* +** DMA Buffer +*/ +typedef struct DmaDesc { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ +} DmaDesc; + +/* +** 16 Byte DMA Buffer +*/ +typedef struct { + union { + struct { + uint16 length; /* in bytes of data in buffer */ +#define DMA_DESC_USEFPM 0x8000 +#define DMA_DESC_MULTICAST 0x4000 +#define DMA_DESC_BUFLENGTH 0x0fff + uint16 status; /* buffer status */ +#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ +#define DMA_EOP 0x4000 /* last buffer in packet */ +#define DMA_SOP 0x2000 /* first buffer in packet */ +#define DMA_WRAP 0x1000 /* */ +#define DMA_PRIO 0x0C00 /* Prio for Tx */ +#define DMA_APPEND_BRCM_TAG 0x0200 +#define DMA_APPEND_CRC 0x0100 +#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet + }; + uint32 word0; + }; + + uint32 address; /* address of data */ + uint32 control; +#define GEM_ID_MASK 0x001F + uint32 reserved; +} DmaDesc16; + +/* +** External Bus Interface +*/ +typedef struct EbiChipSelect { + uint32 base; /* base address in upper 24 bits */ +#define EBI_SIZE_8K 0 +#define EBI_SIZE_16K 1 +#define EBI_SIZE_32K 2 +#define EBI_SIZE_64K 3 +#define EBI_SIZE_128K 4 +#define EBI_SIZE_256K 5 +#define EBI_SIZE_512K 6 +#define EBI_SIZE_1M 7 +#define EBI_SIZE_2M 8 +#define EBI_SIZE_4M 9 +#define EBI_SIZE_8M 10 +#define EBI_SIZE_16M 11 +#define EBI_SIZE_32M 12 +#define EBI_SIZE_64M 13 +#define EBI_SIZE_128M 14 +#define EBI_SIZE_256M 15 + uint32 config; +#define EBI_ENABLE 0x00000001 /* .. enable this range */ +#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */ +#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */ +#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */ +#define EBI_WREN 0x00000020 /* enable posted writes */ +#define EBI_POLARITY 0x00000040 /* .. set to invert something, + ** don't know what yet */ +#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */ +#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */ +#define EBI_FIFO 0x00000200 /* .. use fifo */ +#define EBI_RE 0x00000400 /* .. Reverse Endian */ +#define EBI_SETUP_SHIFT 16 +#define EBI_HOLD_SHIFT 20 +#define EBI_SETUP_STATES 0x0f0000 +#define EBI_HOLD_STATES 0xf00000 +} EbiChipSelect; + +typedef struct MpiRegisters { + EbiChipSelect cs[7]; /* size chip select configuration */ +#define EBI_CS0_BASE 0 +#define EBI_CS1_BASE 1 +#define EBI_CS2_BASE 2 +#define EBI_CS3_BASE 3 +#define EBI_CS4_BASE 4 +#define EBI_CS5_BASE 5 +#define EBI_CS6_BASE 6 + uint32 unused0[2]; /* reserved */ + uint32 ebi_control; /* ebi control */ +#define EBI_ACCESS_TIMEOUT 0x000007FF + uint32 unused1[7]; /* reserved */ + + uint32 sp0range; /* PCI to internal system bus address space */ +#define ADDR_SPACE_MASK 0xFFFF0000 + uint32 sp0remap; + uint32 sp0cfg; + uint32 sp1range; + uint32 sp1remap; + uint32 sp1cfg; + + uint32 EndianCfg; + + uint32 l2pcfgctl; /* internal system bus to PCI IO/Cfg control */ +#define DIR_CFG_SEL 0x80000000 /* change from PCI I/O access to PCI config access */ +#define DIR_CFG_USEREG 0x40000000 /* use this register info for PCI configuration access */ +#define DEVICE_NUMBER 0x00007C00 /* device number for the PCI configuration access */ +#define FUNC_NUMBER 0x00000300 /* function number for the PCI configuration access */ +#define REG_NUMBER 0x000000FC /* register number for the PCI configuration access */ +#define CONFIG_TYPE 0x00000003 /* configuration type for the PCI configuration access */ + + uint32 l2pmrange1; /* internal system bus to PCI memory space */ +#define PCI_SIZE_64K 0xFFFF0000 +#define PCI_SIZE_128K 0xFFFE0000 +#define PCI_SIZE_256K 0xFFFC0000 +#define PCI_SIZE_512K 0xFFF80000 +#define PCI_SIZE_1M 0xFFF00000 +#define PCI_SIZE_2M 0xFFE00000 +#define PCI_SIZE_4M 0xFFC00000 +#define PCI_SIZE_8M 0xFF800000 +#define PCI_SIZE_16M 0xFF000000 +#define PCI_SIZE_32M 0xFE000000 + uint32 l2pmbase1; /* kseg0 or kseg1 address & 0x1FFFFFFF */ + uint32 l2pmremap1; +#define CARDBUS_MEM 0x00000004 +#define MEM_WINDOW_EN 0x00000001 + uint32 l2pmrange2; + uint32 l2pmbase2; + uint32 l2pmremap2; + uint32 l2piorange; /* internal system bus to PCI I/O space */ + uint32 l2piobase; + uint32 l2pioremap; + + uint32 pcimodesel; +#define PCI_INT_BUS_RD_PREFETCH 0x000001F0 +#define PCI_BAR2_NOSWAP 0x00000002 /* BAR at offset 0x20 */ +#define PCI_BAR1_NOSWAP 0x00000001 /* BAR at affset 0x1c */ + + uint32 pciintstat; /* PCI interrupt mask/status */ +#define MAILBOX1_SENT 0x08 +#define MAILBOX0_SENT 0x04 +#define MAILBOX1_MSG_RCV 0x02 +#define MAILBOX0_MSG_RCV 0x01 + uint32 locbuscntrl; /* internal system bus control */ +#define DIR_U2P_NOSWAP 0x00000002 +#define EN_PCI_GPIO 0x00000001 + uint32 locintstat; /* internal system bus interrupt mask/status */ +#define CSERR 0x0200 +#define SERR 0x0100 +#define EXT_PCI_INT 0x0080 +#define DIR_FAILED 0x0040 +#define DIR_COMPLETE 0x0020 +#define PCI_CFG 0x0010 + uint32 unused4[7]; + + uint32 mailbox0; + uint32 mailbox1; + + uint32 pcicfgcntrl; /* internal system bus PCI configuration control */ +#define PCI_CFG_REG_WRITE_EN 0x00000080 +#define PCI_CFG_ADDR 0x0000003C + uint32 pcicfgdata; /* internal system bus PCI configuration data */ + + uint32 locch2ctl; /* PCI to interrnal system bus DMA (downstream) local control */ +#define MPI_DMA_HALT 0x00000008 /* idle after finish current memory burst */ +#define MPI_DMA_PKT_HALT 0x00000004 /* idle after an EOP flag is detected */ +#define MPI_DMA_STALL 0x00000002 /* idle after an EOP flag is detected */ +#define MPI_DMA_ENABLE 0x00000001 /* set to enable channel */ + uint32 locch2intStat; +#define MPI_DMA_NO_DESC 0x00000004 /* no valid descriptors */ +#define MPI_DMA_DONE 0x00000002 /* packet xfer complete */ +#define MPI_DMA_BUFF_DONE 0x00000001 /* buffer done */ + uint32 locch2intMask; + uint32 unused5; + uint32 locch2descaddr; + uint32 locch2status1; +#define LOCAL_DESC_STATE 0xE0000000 +#define PCI_DESC_STATE 0x1C000000 +#define BYTE_DONE 0x03FFC000 +#define RING_ADDR 0x00003FFF + uint32 locch2status2; +#define BUFPTR_OFFSET 0x1FFF0000 +#define PCI_MASTER_STATE 0x000000C0 +#define LOC_MASTER_STATE 0x00000038 +#define CONTROL_STATE 0x00000007 + uint32 unused6; + + uint32 locch1Ctl; /*internal system bus to PCI DMA (upstream) local control */ +#define DMA_U2P_LE 0x00000200 /* local bus is little endian */ +#define DMA_U2P_NOSWAP 0x00000100 /* lccal bus is little endian but no data swapped */ + uint32 locch1intstat; + uint32 locch1intmask; + uint32 unused7; + uint32 locch1descaddr; + uint32 locch1status1; + uint32 locch1status2; + uint32 unused8; + + uint32 pcich1ctl; /* internal system bus to PCI DMA PCI control */ + uint32 pcich1intstat; + uint32 pcich1intmask; + uint32 pcich1descaddr; + uint32 pcich1status1; + uint32 pcich1status2; + + uint32 pcich2Ctl; /* PCI to internal system bus DMA PCI control */ + uint32 pcich2intstat; + uint32 pcich2intmask; + uint32 pcich2descaddr; + uint32 pcich2status1; + uint32 pcich2status2; + + uint32 perm_id; /* permanent device and vendor id */ + uint32 perm_rev; /* permanent revision id */ +} MpiRegisters; + +#define MPI ((volatile MpiRegisters * const) MPI_BASE) + +/* PCI configuration address space start offset 0x40 */ +#define BRCM_PCI_CONFIG_TIMER 0x40 +#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK 0x0000FF00 +#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK 0x000000FF + +typedef struct USBControl { + uint32 BrtControl1; + uint32 BrtControl2; + uint32 BrtStatus1; + uint32 BrtStatus2; + uint32 UTMIControl1; + uint32 TestPortControl; + uint32 PllControl1; + uint32 SwapControl; +#define USB_DEVICE_SEL (1<<6) +#define EHCI_LOGICAL_ADDRESS_EN (1<<5) +#define EHCI_ENDIAN_SWAP (1<<4) +#define EHCI_DATA_SWAP (1<<3) +#define OHCI_LOGICAL_ADDRESS_EN (1<<2) +#define OHCI_ENDIAN_SWAP (1<<1) +#define OHCI_DATA_SWAP (1<<0) + uint32 unused1; + uint32 FrameAdjustValue; + uint32 Setup; +#define USBH_IOC (1<<4) + uint32 MDIO; + uint32 MDIO32; + uint32 USBSimControl; +} USBControl; + +#define USBH ((volatile USBControl * const) USBH_CFG_BASE) + +/* +** GPON SERDES Registers +*/ +typedef struct GponSerdesRegs { + uint32 topCfg; + uint32 swReset; + uint32 aeCfg; + uint32 aeStatus; + uint32 phyCfg; + uint32 phyStatus; + uint32 mdioWr; + uint32 mdioRd; + uint32 reserved[2]; + uint32 fifoCfg; + uint32 fifoStatus; + uint32 patternCfg[4]; + uint32 patternStatus[2]; + uint32 laserCfg; +#define GPON_SERDES_LASERMODE_MASK (3<<30) +#define GPON_SERDES_LASERMODE_NORMAL (0<<30) +#define GPON_SERDES_LASERMODE_FORCE_OFF (1<<30) +#define GPON_SERDES_LASERMODE_FORCE_ON (2<<30) + uint32 laserStatus; + uint32 miscCfg; + uint32 miscStatus; + uint32 phDet[5]; +} GponSerdesRegs; + +#define GPON_SERDES ((volatile GponSerdesRegs * const) GPON_SERDES_BASE) + + +/* +** PCI-E +*/ +typedef struct PcieRegs{ + uint32 devVenID; + uint16 command; + uint16 status; + uint32 revIdClassCode; + uint32 headerTypeLatCacheLineSize; + uint32 bar1; + uint32 bar2; + uint32 priSecBusNo; +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK 0x00ff0000 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT 16 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK 0x0000ff00 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT 8 +#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK 0x000000ff +} PcieRegs; + +typedef struct PcieBlk404Regs{ + uint32 unused; /* 0x404 */ + uint32 config2; /* 0x408 */ +#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK 0x0000000f +#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE 0 + uint32 config3; /* 0x40c */ + uint32 pmDataA; /* 0x410 */ + uint32 pmDataB; /* 0x414 */ +} PcieBlk404Regs; + +typedef struct PcieBlk428Regs{ + uint32 vpdIntf; /* 0x428 */ + uint16 unused_g; /* 0x42c */ + uint16 vpdAddrFlag; /* 0x42e */ + uint32 vpdData; /* 0x430 */ + uint32 idVal1; /* 0x434 */ + uint32 idVal2; /* 0x438 */ + uint32 idVal3; /* 0x43c */ +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK 0xff000000 +#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT 24 +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK 0x00ffffff +#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT 16 +#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT 8 +}PcieBlk428Regs; + +typedef struct PcieBridgeRegs{ + uint32 bar1Remap; /* 0x0818*/ + uint32 bar2Remap; /* 0x081c*/ + uint32 bridgeOptReg1; /* 0x0820*/ +#define PCIE_BRIDGE_OPT_REG1_EN_RD_BE (1 << 4) +#define PCIE_BRIDGE_OPT_REG1_EN_RD_BE_NOSWAP (1 << 5) + uint32 bridgeOptReg2; /* 0x0824*/ +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK 0xe0000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT 29 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK 0x1f000000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT 24 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK 0x00ff0000 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT 16 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK 0x00000080 +#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT 7 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK 0x00000040 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT 6 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK 0x00000020 +#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT 5 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK 0x00000010 +#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT 4 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK 0x00000004 +#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT 2 +#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK 0x0000ff0b +}PcieBridgeRegs; + +typedef struct PcieBlk1000Regs{ + uint32 undisclosed[18]; /*0x1000 - 0x1044*/ + uint32 dlStatus; /* 0x1048 */ +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK 0x00002000 +#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT 13 +}PcieBlk1000Regs; + +typedef struct PcieBlk1800Regs{ +#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS 4 + uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS]; +#define REG_POWERDOWN_P1PLL_ENA (1<<12) + uint32 phyErrorAttnVec; + uint32 phyErrorAttnMask; +#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS 3 + uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS]; +#define NUM_PCIE_BLK_1800_PHY_DBG_REGS 11 + uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS]; +} PcieBlk1800Regs; + +#define PCIEH_DEV_OFFSET 0x8000 +#define PCIEH ((volatile uint32 * const) PCIE_BASE) +#define PCIEH_REGS ((volatile PcieCfeType1Regs * const) PCIE_BASE) +#define PCIEH_BLK_404_REGS ((volatile PcieBlk404Regs * const)(PCIE_BASE+0x404)) +#define PCIEH_BLK_428_REGS ((volatile PcieBlk428Regs * const)(PCIE_BASE+0x428)) +#define PCIEH_BRIDGE_REGS ((volatile PcieBridgeRegs * const) (PCIE_BASE+0x818)) +#define PCIEH_BLK_1000_REGS ((volatile PcieBlk1000Regs * const) (PCIE_BASE+0x1000)) +#define PCIEH_BLK_1800_REGS ((volatile PcieBlk1800Regs * const) (PCIE_BASE+0x1800)) + +/* +** NAND Controller Registers +*/ +typedef struct NandCtrlRegs { + uint32 NandRevision; /* NAND Revision */ + uint32 NandCmdStart; /* Nand Flash Command Start */ + uint32 NandCmdExtAddr; /* Nand Flash Command Extended Address */ + uint32 NandCmdAddr; /* Nand Flash Command Address */ + uint32 NandCmdEndAddr; /* Nand Flash Command End Address */ + uint32 NandNandBootConfig; /* Nand Flash Boot Config */ +#define NBC_AUTO_DEV_ID_CFG 0x40000000 + uint32 NandCsNandXor; /* Nand Flash EBI CS Address XOR with */ +} NandCtrlRegs; + +#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE) + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/shared/opensource/include/bcm963xx/bcmSpi.h b/shared/opensource/include/bcm963xx/bcmSpi.h new file mode 100755 index 0000000..dfbfb4f --- /dev/null +++ b/shared/opensource/include/bcm963xx/bcmSpi.h @@ -0,0 +1,55 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM_SPI_H__ +#define __BCM_SPI_H__ + +#ifndef _CFE_ +#include <linux/autoconf.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spi/spi.h> + +struct bcmspi +{ + spinlock_t lock; + char * devName; + int irq; + unsigned bus_num; + unsigned num_chipselect; + u8 stopping; + struct list_head queue; + struct platform_device *pdev; + struct spi_transfer *curTrans; +}; +#endif + +#define BCM_SPI_READ 0 +#define BCM_SPI_WRITE 1 +#define BCM_SPI_FULL 2 + +#endif /* __BCM_SPI_H__ */ + diff --git a/shared/opensource/include/bcm963xx/bcmSpiRes.h b/shared/opensource/include/bcm963xx/bcmSpiRes.h new file mode 100755 index 0000000..cb39756 --- /dev/null +++ b/shared/opensource/include/bcm963xx/bcmSpiRes.h @@ -0,0 +1,101 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCMSPIRES_H__ +#define __BCMSPIRES_H__ + +#ifndef _CFE_ +#include <linux/spi/spi.h> +#endif + +#define SPI_STATUS_OK (0) +#define SPI_STATUS_INVALID_LEN (-1) +#define SPI_STATUS_ERR (-2) + +/* legacy and HS controllers can coexist - use bus num to differentiate */ +#define LEG_SPI_BUS_NUM 0 +#define HS_SPI_BUS_NUM 1 + +#define LEG_SPI_CLOCK_DEF 2 + +#if defined(_BCM96816_) || defined(CONFIG_BCM96816) || defined(_BCM96362_) || defined(CONFIG_BCM96362) +#define HS_SPI_PLL_FREQ 400000000 +#else +#define HS_SPI_PLL_FREQ 133333333 +#endif +#define HS_SPI_CLOCK_DEF 40000000 +#define HS_SPI_BUFFER_LEN 512 + +/* used to specify ctrlState for the interface BcmSpiReserveSlave2 + SPI_CONTROLLER_STATE_SET is used to differentiate a value of 0 which results in + the controller using default values and the case where CPHA_EXT, GATE_CLK_SSOFF, + CLK_POLARITY, and ASYNC_CLOCK all need to be 0 + + SPI MODE sets the values for CPOL and CPHA + SPI_CONTROLLER_STATE_CPHA_EXT will extend these modes +CPOL = 0 -> base value of clock is 0 +CPHA = 0, CPHA_EXT = 0 -> latch data on rising edge, launch data on falling edge +CPHA = 1, CPHA_EXT = 0 -> latch data on falling edge, launch data on rising edge +CPHA = 0, CPHA_EXT = 1 -> latch data on rising edge, launch data on rising edge +CPHA = 1, CPHA_EXT = 1 -> latch data on falling edge, launch data on falling edge + +CPOL = 1 -> base value of clock is 1 +CPHA = 0, CPHA_EXT = 0 -> latch data on falling edge, launch data on rising edge +CPHA = 1, CPHA_EXT = 0 -> latch data on rising edge, launch data on falling edge +CPHA = 0, CPHA_EXT = 1 -> latch data on falling edge, launch data on falling edge +CPHA = 1, CPHA_EXT = 1 -> latch data on rising edge, launch data on rising edge +*/ +#define SPI_CONTROLLER_STATE_SET (1 << 31) +#define SPI_CONTROLLER_STATE_CPHA_EXT (1 << 30) +#define SPI_CONTROLLER_STATE_GATE_CLK_SSOFF (1 << 29) +#define SPI_CONTROLLER_STATE_CLK_POLARITY (1 << 28) +#define SPI_CONTROLLER_STATE_ASYNC_CLOCK (1 << 27) + +/* set mode and controller state based on CHIP defaults + these values do not matter for the legacy controller */ +#if defined(CONFIG_BCM96816) +#define SPI_MODE_DEFAULT SPI_MODE_1 +#define SPI_CONTROLLER_STATE_DEFAULT (SPI_CONTROLLER_STATE_GATE_CLK_SSOFF | SPI_CONTROLLER_STATE_CPHA_EXT) +#elif (defined(CONFIG_BCM96362) || defined(CONFIG_BCM96328)) +#define SPI_MODE_DEFAULT SPI_MODE_0 +#define SPI_CONTROLLER_STATE_DEFAULT (SPI_CONTROLLER_STATE_GATE_CLK_SSOFF) +#else +#define SPI_MODE_DEFAULT SPI_MODE_3 +#define SPI_CONTROLLER_STATE_DEFAULT (0) +#endif + +#ifndef _CFE_ +int BcmSpiReserveSlave(int busNum, int slaveId, int maxFreq); +int BcmSpiReserveSlave2(int busNum, int slaveId, int maxFreq, int mode, int ctrlState); +int BcmSpiReleaseSlave(int busNum, int slaveId); +int BcmSpiSyncTrans(unsigned char *txBuf, unsigned char *rxBuf, int prependcnt, int nbytes, int busNum, int slaveId); +#endif + +int BcmSpi_SetFlashCtrl( int, int, int, int, int ); +int BcmSpi_GetMaxRWSize( int ); +int BcmSpi_Read(unsigned char *, int, int, int, int, int); +int BcmSpi_Write(unsigned char *, int, int, int, int); + +#endif /* __BCMSPIRES_H__ */ + diff --git a/shared/opensource/include/bcm963xx/bcmTag.h b/shared/opensource/include/bcm963xx/bcmTag.h new file mode 100755 index 0000000..8a1ca24 --- /dev/null +++ b/shared/opensource/include/bcm963xx/bcmTag.h @@ -0,0 +1,175 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +//************************************************************************************** +// File Name : bcmTag.h +// +// Description: add tag with validation system to the firmware image file to be uploaded +// via http +// +// Created : 02/28/2002 seanl +//************************************************************************************** + +#ifndef _BCMTAG_H_ +#define _BCMTAG_H_ + + +#define BCM_SIG_1 "Broadcom Corporation" +#define BCM_SIG_2 "ver. 2.0" // was "firmware version 2.0" now it is split 6 char out for chip id. + +#define BCM_TAG_VER "6" + +// file tag (head) structure all is in clear text except validationTokens (crc, md5, sha1, etc). Total: 128 unsigned chars +#define TAG_LEN 256 +#define TAG_VER_LEN 4 +#define SIG_LEN 20 +#define SIG_LEN_2 14 // Original second SIG = 20 is now devided into 14 for SIG_LEN_2 and 6 for CHIP_ID +#define CHIP_ID_LEN 6 +#define IMAGE_LEN 10 +#define ADDRESS_LEN 12 +#define FLAG_LEN 2 +#define TOKEN_LEN 20 +#define BOARD_ID_LEN 16 +#define RESERVED_LEN (TAG_LEN - TAG_VER_LEN - SIG_LEN - SIG_LEN_2 - CHIP_ID_LEN - BOARD_ID_LEN - \ + (4*IMAGE_LEN) - (3*ADDRESS_LEN) - (3*FLAG_LEN) - (2*TOKEN_LEN)) + + +// TAG for downloadable image (kernel plus file system) +typedef struct _FILE_TAG +{ + char tagVersion[TAG_VER_LEN]; // tag version. Will be 2 here. + char signiture_1[SIG_LEN]; // text line for company info + char signiture_2[SIG_LEN_2]; // additional info (can be version number) + char chipId[CHIP_ID_LEN]; // chip id + char boardId[BOARD_ID_LEN]; // board id + char bigEndian[FLAG_LEN]; // if = 1 - big, = 0 - little endia of the host + char totalImageLen[IMAGE_LEN]; // the sum of all the following length + char cfeAddress[ADDRESS_LEN]; // if non zero, cfe starting address + char cfeLen[IMAGE_LEN]; // if non zero, cfe size in clear ASCII text. + char rootfsAddress[ADDRESS_LEN]; // if non zero, filesystem starting address + char rootfsLen[IMAGE_LEN]; // if non zero, filesystem size in clear ASCII text. + char kernelAddress[ADDRESS_LEN]; // if non zero, kernel starting address + char kernelLen[IMAGE_LEN]; // if non zero, kernel size in clear ASCII text. + char imageSequence[FLAG_LEN * 2]; // incrments everytime an image is flashed + char reserved[RESERVED_LEN]; // reserved for later use + char imageValidationToken[TOKEN_LEN];// image validation token - can be crc, md5, sha; for + // now will be 4 unsigned char crc + char tagValidationToken[TOKEN_LEN]; // validation token for tag(from signiture_1 to end of // mageValidationToken) +} FILE_TAG, *PFILE_TAG; + +/* Whole flash image TAG definitions. */ +#define WFI_VERSION 0x00005731 +#define WFI_ANY_VERS_MASK 0x0000ff00 +#define WFI_ANY_VERS 0x00005700 +#define WFI_NOR_FLASH 1 +#define WFI_NAND16_FLASH 2 +#define WFI_NAND128_FLASH 3 + +/* TAG at end of whole flash ".w" image. Size must be TOKEN_LEN. */ +typedef struct _WFI_TAG +{ + unsigned long wfiCrc; + unsigned long wfiVersion; + unsigned long wfiChipId; + unsigned long wfiFlashType; + unsigned long wfiReserved; +} WFI_TAG, *PWFI_TAG; + +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */ +#define CRC_LEN 4 + +// only included if for bcmTag.exe program +#ifdef BCMTAG_EXE_USE + +static unsigned long Crc32_table[256] = { + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F, + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB, + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD, + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79, + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713, + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45, + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D +}; +#endif // BCMTAG_USE + + +#endif // _BCMTAG_H_ + diff --git a/shared/opensource/include/bcm963xx/bcm_hwdefs.h b/shared/opensource/include/bcm963xx/bcm_hwdefs.h new file mode 100755 index 0000000..07ecc29 --- /dev/null +++ b/shared/opensource/include/bcm963xx/bcm_hwdefs.h @@ -0,0 +1,193 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/***********************************************************************/ +/* */ +/* MODULE: bcm_hwdefs.h */ +/* PURPOSE: Define all base device addresses and HW specific macros. */ +/* */ +/***********************************************************************/ +#ifndef _BCM_HWDEFS_H +#define _BCM_HWDEFS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define DYING_GASP_API + +/*****************************************************************************/ +/* Physical Memory Map */ +/*****************************************************************************/ + +#define PHYS_DRAM_BASE 0x00000000 /* Dynamic RAM Base */ +#if defined(CONFIG_BRCM_IKOS) +#define PHYS_FLASH_BASE 0x18000000 /* Flash Memory */ +#else +#define PHYS_FLASH_BASE 0x1FC00000 /* Flash Memory */ +#endif + +/*****************************************************************************/ +/* Note that the addresses above are physical addresses and that programs */ +/* have to use converted addresses defined below: */ +/*****************************************************************************/ +#define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */ +#define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */ + +/* Binary images are always built for a standard MIPS boot address */ +#define IMAGE_BASE (0xA0000000 | PHYS_FLASH_BASE) + +/* Some chips don't support alternative boot vector */ +#if defined(CONFIG_BRCM_IKOS) +#define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */ +#define BOOT_OFFSET 0 +#else +#if defined(_BCM96328_) || defined(CONFIG_BCM96328) || defined(_BCM96362_) || defined(CONFIG_BCM96362) +#define FLASH_BASE 0xB8000000 +#else +#define FLASH_BASE (0xA0000000 | (MPI->cs[0].base & 0xFFFFFF00)) +#endif +#define BOOT_OFFSET (FLASH_BASE - IMAGE_BASE) +#endif + +/*****************************************************************************/ +/* Select the PLL value to get the desired CPU clock frequency. */ +/*****************************************************************************/ +#define FPERIPH 50000000 + +/*****************************************************************************/ +/* Board memory type offset */ +/*****************************************************************************/ +#define ONEK 1024 +#define FLASH_LENGTH_BOOT_ROM (64*ONEK) + +#define PROJECT_ID_LEN 7 /* Foxconn added by zacker, 02/29/2008, strlen("U12H094") */ +#ifdef _CFE_ +#define FLASH_SIZE 32 * 1024 * 1024 +#endif +#define BOARD_DATA_ADDR (FLASH_BASE + FLASH_SIZE - 0x20000) +#define BOARD_FOXNVRAM_ADDR (FLASH_BASE + FLASH_SIZE - 0x10000) +#define FOX_BOARD_ID_MAX_LEN 64 +#define BOARD_ID "U12L161" +/*****************************************************************************/ +/* NVRAM Offset and definition */ +/*****************************************************************************/ +#define NVRAM_SECTOR 0 +#define NVRAM_DATA_OFFSET 0x0580 +#define NVRAM_DATA_ID 0x0f1e2d3c // This is only for backwards compatability + +#define NVRAM_LENGTH ONEK // 1k nvram +#define NVRAM_VERSION_NUMBER 6 +#define NVRAM_FULL_LEN_VERSION_NUMBER 5 /* version in which the checksum was + placed at the end of the NVRAM + structure */ + +#define NVRAM_BOOTLINE_LEN 256 +#define NVRAM_BOARD_ID_STRING_LEN 16 +#define NVRAM_MAC_ADDRESS_LEN 6 + +#define NVRAM_GPON_SERIAL_NUMBER_LEN 13 +#define NVRAM_GPON_PASSWORD_LEN 11 + +#define NVRAM_WLAN_PARAMS_LEN 256 +#define NVRAM_WPS_DEVICE_PIN_LEN 8 + +#define THREAD_NUM_ADDRESS_OFFSET (NVRAM_DATA_OFFSET + 4 + NVRAM_BOOTLINE_LEN + NVRAM_BOARD_ID_STRING_LEN) +#define THREAD_NUM_ADDRESS (0x80000000 + THREAD_NUM_ADDRESS_OFFSET) + +#define DEFAULT_BOOTLINE "e=192.168.1.1:ffffff00 h=192.168.1.100 g= r=f f=vmlinux i=bcm963xx_fs_kernel d=1 p=0 " +#define DEFAULT_BOARD_IP "192.168.1.1" +#define DEFAULT_MAC_NUM 10 +#define DEFAULT_BOARD_MAC "00:10:18:00:00:00" +#define DEFAULT_TP_NUM 0 +#define DEFAULT_PSI_SIZE 24 +#define DEFAULT_GPON_SN "BRCM12345678" +#define DEFAULT_GPON_PW " " + +#define DEFAULT_WPS_DEVICE_PIN "12345670" + +#define DEFAULT_VOICE_BOARD_ID "NONE" + +#define NVRAM_MAC_COUNT_MAX 32 +#define NVRAM_MAX_PSI_SIZE 64 +#define NVRAM_MAX_SYSLOG_SIZE 256 + +#define NP_BOOT 0 +#define NP_ROOTFS_1 1 +#define NP_ROOTFS_2 2 +#define NP_DATA 3 +#define NP_BBT 4 +#define NP_TOTAL 5 + +#define NAND_DATA_SIZE_KB 1024 +#define NAND_BBT_THRESHOLD_KB (512 * 1024) +#define NAND_BBT_SMALL_SIZE_KB 1024 +#define NAND_BBT_BIG_SIZE_KB 4096 + +#define NAND_CFE_RAM_NAME "cferam.000" + +#ifndef _LANGUAGE_ASSEMBLY +typedef struct +{ + unsigned long ulVersion; + char szBootline[NVRAM_BOOTLINE_LEN]; + char szBoardId[NVRAM_BOARD_ID_STRING_LEN]; + unsigned long ulMainTpNum; + unsigned long ulPsiSize; + unsigned long ulNumMacAddrs; + unsigned char ucaBaseMacAddr[NVRAM_MAC_ADDRESS_LEN]; + char pad; + char backupPsi; /**< if 0x01, allocate space for a backup PSI */ + unsigned long ulCheckSumV4; + char gponSerialNumber[NVRAM_GPON_SERIAL_NUMBER_LEN]; + char gponPassword[NVRAM_GPON_PASSWORD_LEN]; + char wpsDevicePin[NVRAM_WPS_DEVICE_PIN_LEN]; + char wlanParams[NVRAM_WLAN_PARAMS_LEN]; + unsigned long ulSyslogSize; /**< number of KB to allocate for persistent syslog */ + unsigned long ulNandPartOfsKb[NP_TOTAL]; + unsigned long ulNandPartSizeKb[NP_TOTAL]; + char szVoiceBoardId[NVRAM_BOARD_ID_STRING_LEN]; + unsigned long afeId[2]; + char szFirmwareUpgradeBoardId[32]; /* foxconn added Bob, 07/12/2010, for TFTP firmware upgrade */ + char chUnused[332]; /* reduce array size from 364 to 332, total size of NVRAM_DATA is unchanged, Bob, 07/12/2010 */ + unsigned long ulCheckSum; +} NVRAM_DATA, *PNVRAM_DATA; +#endif + +#define BOOT_LATEST_IMAGE '0' +#define BOOT_PREVIOUS_IMAGE '1' + +/*****************************************************************************/ +/* Misc Offsets */ +/*****************************************************************************/ +#define CFE_VERSION_OFFSET 0x0570 +#define CFE_VERSION_MARK_SIZE 5 +#define CFE_VERSION_SIZE 5 + +#ifdef __cplusplus +} +#endif + +#endif /* _BCM_HWDEFS_H */ + diff --git a/shared/opensource/include/bcm963xx/bcmnetlink.h b/shared/opensource/include/bcm963xx/bcmnetlink.h new file mode 100755 index 0000000..e5fc77f --- /dev/null +++ b/shared/opensource/include/bcm963xx/bcmnetlink.h @@ -0,0 +1,47 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/************************************************************************** + * File Name : bcmnetlink.h + * + * Description: This file defines broadcom specific netlink message types + ***************************************************************************/ +#ifndef _BCMNETLINK_H +#define _BCMNETLINK_H + +#include<linux/netlink.h> + +#ifndef NETLINK_BRCM_MONITOR +#define NETLINK_BRCM_MONITOR 25 +#endif + +/* message types exchanged using NETLINK_BRCM_MONITOR */ +#define MSG_NETLINK_BRCM_WAKEUP_MONITOR_TASK 0X1000 + +#define MSG_NETLINK_BRCM_LINK_STATUS_CHANGED 0X2000 + + +extern void kerSysSendtoMonitorTask(int msgType, char *msgData, int msgDataLen); + +#endif /*_BCMNETLINK_H */ diff --git a/shared/opensource/include/bcm963xx/boardparms.h b/shared/opensource/include/bcm963xx/boardparms.h new file mode 100755 index 0000000..7fec91c --- /dev/null +++ b/shared/opensource/include/bcm963xx/boardparms.h @@ -0,0 +1,453 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/************************************************************************** + * File Name : boardparms.h + * + * Description: This file contains definitions and function prototypes for + * the BCM63xx board parameter access functions. + * + * Updates : 07/14/2003 Created. + ***************************************************************************/ + +#if !defined(_BOARDPARMS_H) +#define _BOARDPARMS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Return codes. */ +#define BP_SUCCESS 0 +#define BP_BOARD_ID_NOT_FOUND 1 +#define BP_VALUE_NOT_DEFINED 2 +#define BP_BOARD_ID_NOT_SET 3 + +/* Values for EthernetMacInfo PhyType. */ +#define BP_ENET_NO_PHY 0 +#define BP_ENET_INTERNAL_PHY 1 +#define BP_ENET_EXTERNAL_SWITCH 2 +#define BP_ENET_SWITCH_VIA_INTERNAL_PHY 3 /* it is for cpu internal phy connects to port 4 of 5325e */ + +/* Values for EthernetMacInfo Configuration type. */ +#define BP_ENET_CONFIG_MDIO 0 /* Internal PHY, External PHY, Switch+(no GPIO, no SPI, no MDIO Pseudo phy */ +#define BP_ENET_CONFIG_MDIO_PSEUDO_PHY 1 +#define BP_ENET_CONFIG_SPI_SSB_0 2 +#define BP_ENET_CONFIG_SPI_SSB_1 3 +#define BP_ENET_CONFIG_SPI_SSB_2 4 +#define BP_ENET_CONFIG_SPI_SSB_3 5 +#define BP_ENET_CONFIG_MMAP 6 +#define BP_ENET_CONFIG_GPIO_MDIO 7 /* use GPIO to simulate MDC/MDIO */ + +/* Values for VoIPDSPInfo DSPType. */ +#define BP_VOIP_NO_DSP 0 +#define BP_VOIP_DSP 1 +#define BP_VOIP_MIPS 2 + +/* Values for GPIO pin assignments (AH = Active High, AL = Active Low). */ +#define BP_GPIO_NUM_MASK 0x00FF +#define BP_ACTIVE_MASK 0x8000 +#define BP_ACTIVE_HIGH 0x0000 +#define BP_ACTIVE_LOW 0x8000 +#define BP_GPIO_SERIAL 0x4000 + +#define BP_GPIO_0_AH (0) +#define BP_GPIO_0_AL (0 | BP_ACTIVE_LOW) +#define BP_GPIO_1_AH (1) +#define BP_GPIO_1_AL (1 | BP_ACTIVE_LOW) +#define BP_GPIO_2_AH (2) +#define BP_GPIO_2_AL (2 | BP_ACTIVE_LOW) +#define BP_GPIO_3_AH (3) +#define BP_GPIO_3_AL (3 | BP_ACTIVE_LOW) +#define BP_GPIO_4_AH (4) +#define BP_GPIO_4_AL (4 | BP_ACTIVE_LOW) +#define BP_GPIO_5_AH (5) +#define BP_GPIO_5_AL (5 | BP_ACTIVE_LOW) +#define BP_GPIO_6_AH (6) +#define BP_GPIO_6_AL (6 | BP_ACTIVE_LOW) +#define BP_GPIO_7_AH (7) +#define BP_GPIO_7_AL (7 | BP_ACTIVE_LOW) +#define BP_GPIO_8_AH (8) +#define BP_GPIO_8_AL (8 | BP_ACTIVE_LOW) +#define BP_GPIO_9_AH (9) +#define BP_GPIO_9_AL (9 | BP_ACTIVE_LOW) +#define BP_GPIO_10_AH (10) +#define BP_GPIO_10_AL (10 | BP_ACTIVE_LOW) +#define BP_GPIO_11_AH (11) +#define BP_GPIO_11_AL (11 | BP_ACTIVE_LOW) +#define BP_GPIO_12_AH (12) +#define BP_GPIO_12_AL (12 | BP_ACTIVE_LOW) +#define BP_GPIO_13_AH (13) +#define BP_GPIO_13_AL (13 | BP_ACTIVE_LOW) +#define BP_GPIO_14_AH (14) +#define BP_GPIO_14_AL (14 | BP_ACTIVE_LOW) +#define BP_GPIO_15_AH (15) +#define BP_GPIO_15_AL (15 | BP_ACTIVE_LOW) +#define BP_GPIO_16_AH (16) +#define BP_GPIO_16_AL (16 | BP_ACTIVE_LOW) +#define BP_GPIO_17_AH (17) +#define BP_GPIO_17_AL (17 | BP_ACTIVE_LOW) +#define BP_GPIO_18_AH (18) +#define BP_GPIO_18_AL (18 | BP_ACTIVE_LOW) +#define BP_GPIO_19_AH (19) +#define BP_GPIO_19_AL (19 | BP_ACTIVE_LOW) +#define BP_GPIO_20_AH (20) +#define BP_GPIO_20_AL (20 | BP_ACTIVE_LOW) +#define BP_GPIO_21_AH (21) +#define BP_GPIO_21_AL (21 | BP_ACTIVE_LOW) +#define BP_GPIO_22_AH (22) +#define BP_GPIO_22_AL (22 | BP_ACTIVE_LOW) +#define BP_GPIO_23_AH (23) +#define BP_GPIO_23_AL (23 | BP_ACTIVE_LOW) +#define BP_GPIO_24_AH (24) +#define BP_GPIO_24_AL (24 | BP_ACTIVE_LOW) +#define BP_GPIO_25_AH (25) +#define BP_GPIO_25_AL (25 | BP_ACTIVE_LOW) +#define BP_GPIO_26_AH (26) +#define BP_GPIO_26_AL (26 | BP_ACTIVE_LOW) +#define BP_GPIO_27_AH (27) +#define BP_GPIO_27_AL (27 | BP_ACTIVE_LOW) +#define BP_GPIO_28_AH (28) +#define BP_GPIO_28_AL (28 | BP_ACTIVE_LOW) +#define BP_GPIO_29_AH (29) +#define BP_GPIO_29_AL (29 | BP_ACTIVE_LOW) +#define BP_GPIO_30_AH (30) +#define BP_GPIO_30_AL (30 | BP_ACTIVE_LOW) +#define BP_GPIO_31_AH (31) +#define BP_GPIO_31_AL (31 | BP_ACTIVE_LOW) +#define BP_GPIO_32_AH (32) +#define BP_GPIO_32_AL (32 | BP_ACTIVE_LOW) +#define BP_GPIO_33_AH (33) +#define BP_GPIO_33_AL (33 | BP_ACTIVE_LOW) +#define BP_GPIO_34_AH (34) +#define BP_GPIO_34_AL (34 | BP_ACTIVE_LOW) +#define BP_GPIO_35_AH (35) +#define BP_GPIO_35_AL (35 | BP_ACTIVE_LOW) +#define BP_GPIO_36_AH (36) +#define BP_GPIO_36_AL (36 | BP_ACTIVE_LOW) +#define BP_GPIO_37_AH (37) +#define BP_GPIO_37_AL (37 | BP_ACTIVE_LOW) +#define BP_GPIO_38_AH (38) +#define BP_GPIO_38_AL (38 | BP_ACTIVE_LOW) +#define BP_GPIO_39_AH (39) +#define BP_GPIO_39_AL (39 | BP_ACTIVE_LOW) +#define BP_GPIO_40_AH (40) +#define BP_GPIO_40_AL (40 | BP_ACTIVE_LOW) +#define BP_GPIO_41_AH (41) +#define BP_GPIO_41_AL (41 | BP_ACTIVE_LOW) +#define BP_GPIO_42_AH (42) +#define BP_GPIO_42_AL (42 | BP_ACTIVE_LOW) +#define BP_GPIO_43_AH (43) +#define BP_GPIO_43_AL (43 | BP_ACTIVE_LOW) +#define BP_GPIO_44_AH (44) +#define BP_GPIO_44_AL (44 | BP_ACTIVE_LOW) +#define BP_GPIO_45_AH (45) +#define BP_GPIO_45_AL (45 | BP_ACTIVE_LOW) +#define BP_GPIO_46_AH (46) +#define BP_GPIO_46_AL (46 | BP_ACTIVE_LOW) +#define BP_GPIO_47_AH (47) +#define BP_GPIO_47_AL (47 | BP_ACTIVE_LOW) + +#define BP_SERIAL_GPIO_0_AH (0 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_0_AL (0 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_1_AH (1 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_1_AL (1 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_2_AH (2 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_2_AL (2 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_3_AH (3 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_3_AL (3 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_4_AH (4 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_4_AL (4 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_5_AH (5 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_5_AL (5 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_6_AH (6 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_6_AL (6 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_7_AH (7 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_7_AL (7 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_8_AH (8 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_8_AL (8 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_9_AH (9 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_9_AL (9 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_10_AH (10 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_10_AL (10 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_11_AH (11 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_11_AL (11 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_12_AH (12 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_12_AL (12 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_13_AH (13 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_13_AL (13 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_14_AH (14 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_14_AL (14 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_15_AH (15 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_15_AL (15 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_16_AH (16 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_16_AL (16 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_17_AH (17 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_17_AL (17 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_18_AH (18 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_18_AL (18 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_19_AH (19 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_19_AL (19 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_20_AH (20 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_20_AL (20 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_21_AH (21 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_21_AL (21 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_22_AH (22 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_22_AL (22 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_23_AH (23 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_23_AL (23 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) + +/* Values for external interrupt assignments. */ +#define BP_EXT_INTR_0 0 +#define BP_EXT_INTR_1 1 +#define BP_EXT_INTR_2 2 +#define BP_EXT_INTR_3 3 +#define BP_EXT_INTR_4 4 +#define BP_EXT_INTR_5 5 + +/* Values for chip select assignments. */ +#define BP_CS_0 0 +#define BP_CS_1 1 +#define BP_CS_2 2 +#define BP_CS_3 3 + +#define BP_OVERLAY_GPON_TX_EN_L (1<<0) +#define BP_OVERLAY_PCI (1<<0) +#define BP_OVERLAY_CB (1<<1) +#define BP_OVERLAY_SPI_EXT_CS (1<<2) +#define BP_OVERLAY_UART1 (1<<3) +#define BP_OVERLAY_PHY (1<<4) +#define BP_OVERLAY_SERIAL_LEDS (1<<5) +#define BP_OVERLAY_EPHY_LED_0 (1<<6) +#define BP_OVERLAY_EPHY_LED_1 (1<<7) +#define BP_OVERLAY_GPHY_LED_0 (1<<6) +#define BP_OVERLAY_GPHY_LED_1 (1<<7) +#define BP_OVERLAY_EPHY_LED_2 (1<<8) +#define BP_OVERLAY_EPHY_LED_3 (1<<9) +#define BP_OVERLAY_INET_LED (1<<10) +#define BP_OVERLAY_MOCA_LED (1<<11) +#define BP_OVERLAY_USB_LED (1<<12) +#define BP_OVERLAY_USB_DEVICE (1<<13) + +/* Value for GPIO and external interrupt fields that are not used. */ +#define BP_NOT_DEFINED 0xffff + +/* Maximum size of the board id string. */ +#define BP_BOARD_ID_LEN 16 + +/* Maximum number of Ethernet MACs. */ +#define BP_MAX_ENET_MACS 2 +#define BP_MAX_SWITCH_PORTS 8 +/* Maximum number of VoIP DSPs. */ +#define BP_MAX_VOIP_DSP 2 + +/* Wireless Antenna Settings. */ +#define BP_WLAN_ANT_MAIN 0 +#define BP_WLAN_ANT_AUX 1 +#define BP_WLAN_ANT_BOTH 3 + +/* Wireless FLAGS */ +#define BP_WLAN_MAC_ADDR_OVERRIDE 0x0001 /* use kerSysGetMacAddress for mac address */ +#define BP_WLAN_EXCLUDE_ONBOARD 0x0002 /* exclude onboard wireless */ +#define BP_WLAN_EXCLUDE_ONBOARD_FORCE 0x0004 /* force exclude onboard wireless even without addon card*/ +#define BP_WLAN_USE_OTP 0x0008 /* don't use sw srom map, may fall to OTP or uninitialzed */ + +#define BP_WLAN_NVRAM_NAME_LEN 16 +#define BP_WLAN_MAX_PATCH_ENTRY 32 + +/* AFE IDs */ +#define BP_AFE_DEFAULT 0 + +#define BP_AFE_CHIP_INT (1 << 28) +#define BP_AFE_CHIP_6505 (2 << 28) +#define BP_AFE_CHIP_6306 (3 << 28) + +#define BP_AFE_LD_ISIL1556 (1 << 21) +#define BP_AFE_LD_6301 (2 << 21) +#define BP_AFE_LD_6302 (3 << 21) + +#define BP_AFE_FE_ANNEXA (1 << 15) +#define BP_AFE_FE_ANNEXB (2 << 15) +#define BP_AFE_FE_ANNEXJ (3 << 15) + +#define BP_AFE_FE_AVMODE_COMBO (0 << 13) +#define BP_AFE_FE_AVMODE_ADSL (1 << 13) +#define BP_AFE_FE_AVMODE_VDSL (2 << 13) + +/* VDSL only */ +#define BP_AFE_FE_REV_ISIL_REV1 (1 << 8) +/* Combo */ +#define BP_AFE_FE_REV_6302_REV1 (1 << 8) +#define BP_AFE_FE_REV_6302_REV_7_12 (1 << 8) +#define BP_AFE_FE_REV_6302_REV_7_4 (2 << 8) + +#define BP_AFE_FE_REV_6302_REV_7_2_1 (3 << 8) +#define BP_AFE_FE_REV_6302_REV_7_2 (4 << 8) +#define BP_AFE_FE_REV_6302_REV_7_2_UR2 (5 << 8) +#define BP_AFE_FE_REV_6302_REV_7_2_2 (6 << 8) +/* ADSL only*/ +#define BP_AFE_FE_REV_6302_REV_5_2_1 (1 << 8) +#define BP_AFE_FE_REV_6302_REV_5_2_2 (2 << 8) +#define BP_AFE_FE_REV_6301_REV_5_1_1 (1 << 8) + +#define BP_GET_EXT_AFE_DEFINED + +#if !defined(__ASSEMBLER__) + +/* Information about Ethernet switch */ +typedef struct { + int port_map; + int phy_id[BP_MAX_SWITCH_PORTS]; +} ETHERNET_SW_INFO; + +/* WAN port flag in the phy_id of ETHERNET_SW_INFO */ +#define BCM_WAN_PORT 0x40 +#define IsWanPort(id) (((id) & BCM_WAN_PORT) && ((id) != 0xFF)) + +#define c0(n) (((n) & 0x55555555) + (((n) >> 1) & 0x55555555)) +#define c1(n) (((n) & 0x33333333) + (((n) >> 2) & 0x33333333)) +#define c2(n) (((n) & 0x0f0f0f0f) + (((n) >> 4) & 0x0f0f0f0f)) +#define bitcount(r, n) {r = n; r = c0(r); r = c1(r); r = c2(r); r %= 255;} + +/* Information about an Ethernet MAC. If ucPhyType is BP_ENET_NO_PHY, + * then the other fields are not valid. + */ +typedef struct EthernetMacInfo +{ + unsigned char ucPhyType; /* BP_ENET_xxx */ + unsigned char ucPhyAddress; /* 0 to 31 */ + unsigned short usGpioLedPhyLinkSpeed; /* GPIO pin or not defined */ + unsigned short usConfigType; /* Configuration type */ + ETHERNET_SW_INFO sw; /* switch information */ + unsigned short usGpioMDC; /* GPIO pin to simulate MDC */ + unsigned short usGpioMDIO; /* GPIO pin to simulate MDIO */ +} ETHERNET_MAC_INFO, *PETHERNET_MAC_INFO; + +typedef struct WlanSromEntry { + char name[BP_WLAN_NVRAM_NAME_LEN]; + unsigned short wordOffset; + unsigned short value; +} WLAN_SROM_ENTRY; + +typedef struct WlanSromPatchInfo { + char szboardId[BP_BOARD_ID_LEN]; + unsigned short usWirelessChipId; + unsigned short usNeededSize; + WLAN_SROM_ENTRY entries[BP_WLAN_MAX_PATCH_ENTRY]; +} WLAN_SROM_PATCH_INFO, *PWLAN_SROM_PATCH_INFO; + +typedef struct WlanPciEntry { + char name[BP_WLAN_NVRAM_NAME_LEN]; + unsigned int dwordOffset; + unsigned int value; +} WLAN_PCI_ENTRY; + +typedef struct WlanPciPatchInfo { + char szboardId[BP_BOARD_ID_LEN]; + unsigned int usWirelessPciId; + int usNeededSize; + WLAN_PCI_ENTRY entries[BP_WLAN_MAX_PATCH_ENTRY]; +} WLAN_PCI_PATCH_INFO, *PWLAN_PCI_PATCH_INFO; + +/* Information about VoIP DSPs. If ucDspType is BP_VOIP_NO_DSP, + * then the other fields are not valid. + */ +typedef struct VoIPDspInfo +{ + unsigned char ucDspType; + unsigned char ucDspAddress; + unsigned short usGpioLedVoip; + unsigned short usGpioVoip1Led; + unsigned short usGpioVoip1LedFail; + unsigned short usGpioVoip2Led; + unsigned short usGpioVoip2LedFail; + unsigned short usGpioPotsLed; + unsigned short usGpioDectLed; + +} VOIP_DSP_INFO; + +int BpSetBoardId( char *pszBoardId ); +int BpGetBoardId( char *pszBoardId); +int BpGetBoardIds( char *pszBoardIds, int nBoardIdsSize ); + +int BpGetGPIOverlays( unsigned short *pusValue ); + +int BpGetRj11InnerOuterPairGpios( unsigned short *pusInner, unsigned short *pusOuter ); +int BpGetRtsCtsUartGpios( unsigned short *pusRts, unsigned short *pusCts ); + +int BpGetAdslLedGpio( unsigned short *pusValue ); +int BpGetAdslFailLedGpio( unsigned short *pusValue ); +int BpGetSecAdslLedGpio( unsigned short *pusValue ); +int BpGetSecAdslFailLedGpio( unsigned short *pusValue ); +int BpGetWirelessSesLedGpio( unsigned short *pusValue ); +int BpGetHpnaLedGpio( unsigned short *pusValue ); +int BpGetWanDataLedGpio( unsigned short *pusValue ); +int BpGetWanErrorLedGpio( unsigned short *pusValue ); +int BpGetBootloaderPowerOnLedGpio( unsigned short *pusValue ); +int BpGetBootloaderStopLedGpio( unsigned short *pusValue ); +int BpGetFpgaResetGpio( unsigned short *pusValue ); +int BpGetGponLedGpio( unsigned short *pusValue ); +int BpGetGponFailLedGpio( unsigned short *pusValue ); +int BpGetMoCALedGpio( unsigned short *pusValue ); +int BpGetMoCAFailLedGpio( unsigned short *pusValue ); + +int BpGetResetToDefaultExtIntr( unsigned short *pusValue ); +int BpGetWirelessSesExtIntr( unsigned short *pusValue ); +int BpGetHpnaExtIntr( unsigned long *pulValue ); + +int BpGetHpnaChipSelect( unsigned long *pulValue ); + +int BpGetWirelessAntInUse( unsigned short *pusValue ); +int BpGetWirelessFlags( unsigned short *pusValue ); +int BpGetWirelessPowerDownGpio( unsigned short *pusValue ); +int BpUpdateWirelessSromMap(unsigned short chipID, unsigned short* pBase, int sizeInWords); +int BpUpdateWirelessPciConfig (unsigned long pciID, unsigned long* pBase, int sizeInDWords); + +int BpGetEthernetMacInfo( PETHERNET_MAC_INFO pEnetInfos, int nNumEnetInfos ); +int BpGet6829PortInfo( unsigned char *portInfo6829 ); +int BpGetDslPhyAfeIds( unsigned long *pulValues ); +int BpGetExtAFEResetGpio( unsigned short *pulValues ); +int BpGetExtAFELDPwrGpio( unsigned short *pulValues ); +int BpGetExtAFELDModeGpio( unsigned short *pulValues ); + +VOIP_DSP_INFO *BpGetVoipDspConfig( unsigned char dspNum ); +int BpGetVoipLedGpio( unsigned short *pusValue ); +int BpGetVoip1LedGpio( unsigned short *pusValue ); +int BpGetVoip1FailLedGpio( unsigned short *pusValue ); +int BpGetVoip2LedGpio( unsigned short *pusValue ); +int BpGetVoip2FailLedGpio( unsigned short *pusValue ); +int BpGetPotsLedGpio( unsigned short *pusValue ); +int BpGetDectLedGpio( unsigned short *pusValue ); + +int bpstrcmp(const char *dest,const char *src); + + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BOARDPARMS_H */ + diff --git a/shared/opensource/include/bcm963xx/boardparms_voice.h b/shared/opensource/include/bcm963xx/boardparms_voice.h new file mode 100755 index 0000000..5d3c7e5 --- /dev/null +++ b/shared/opensource/include/bcm963xx/boardparms_voice.h @@ -0,0 +1,392 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/************************************************************************** + * File Name : boardparms_voice.h + * + * Description: This file contains definitions and function prototypes for + * the BCM63xx voice board parameter access functions. + * + ***************************************************************************/ + +#if !defined(_BOARDPARMS_VOICE_H) +#define _BOARDPARMS_VOICE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <boardparms.h> + +#define SI32261ENABLE /* Temporary #def until fully supported */ +#define SI32267ENABLE /* Temporary #def until fully supported */ + +/* Board string defines */ + +#define VOICECFG_NOSLIC_STR "NOSLIC" +#define VOICECFG_LE88276_STR "LE88276" +#define VOICECFG_LE88506_STR "LE88506" +#define VOICECFG_LE9530_STR "LE9530" +#define VOICECFG_VE890_STR "VE890" +#define VOICECFG_SI32178_STR "SI32178" +#define VOICECFG_SI3217X_STR "SI3217X" +#define VOICECFG_SI3226_STR "SI3226" +#define VOICECFG_6328AVNG_LE88276_NTR_STR "LE88276-NTR" +#define VOICECFG_6328AVNG_SI32267_STR "AVNG_SI32267" +#define VOICECFG_6328AVNG_VE890HV_PARTIAL_STR "AVNG_VE890HVP" +#define VOICECFG_6328AVNG_VE890HV_STR "AVNG_VE890HV" + +#define VOICECFG_6328AVNGR_SI32176_STR "AVNGR_SI32176" +#define VOICECFG_6328AVNGR_LE89116_STR "AVNGR_LE89116" +#define VOICECFG_6328AVNGR_SI3217X_STR "AVNGR_SI3217X" + +#define VOICECFG_6368MVWG_STR "MVWG" +#define VOICECFG_6368MBG_LE88276_STR "MBG_LE88276" +#define VOICECFG_6368MBG_LE88506_STR "MBG_LE88506" +#define VOICECFG_6368MBG_VE890_STR "MBG_VE890" +#define VOICECFG_6368MBG_LE89116_STR "MBG_LE89116" +#define VOICECFG_6368MBG_LE89316_STR "MBG_LE89316" +#define VOICECFG_6368MBG_SI3217X_STR "MBG_SI3217X" +#define VOICECFG_6368MBG_SI32176_STR "MBG_SI32176" +#define VOICECFG_6368MBG_SI32178_STR "MBG_SI32178" +#define VOICECFG_6368MBG_SI3226_STR "MBG_SI3226" + +#define VOICECFG_6362ADVNGP5_NOSLIC_STR "ADVNGP5_NOSLIC" +#define VOICECFG_6362ADVNGP5_SI3217X_STR "ADVNGP5_SI3217X" +#define VOICECFG_6362ADVNGP5_SI32176_STR "ADVNGP5_SI32176" +#define VOICECFG_6362ADVNGP5_SI32178_STR "ADVNGP5_SI32178" +#define VOICECFG_6362ADVNGP5_VE890_STR "ADVNGP5_VE890" +#define VOICECFG_6362ADVNGP5_LE89116_STR "ADVNGP5_LE89116" +#define VOICECFG_6362ADVNGP5_LE89316_STR "ADVNGP5_LE89316" +#define VOICECFG_6362ADVNGP5_LE88506_STR "ADVNGP5_LE88506" +#define VOICECFG_6362ADVNGP5_LE88276_STR "ADVNGP5_LE88276" +#define VOICECFG_6362ADVNGP5_SI3226_STR "ADVNGP5_SI3226" + +#define VOICECFG_6362ADVNGR_SI3217X_STR "ADVNGR_SI3217X" +#define VOICECFG_6362ADVNGR_SI32176_STR "ADVNGR_SI32176" +#define VOICECFG_6362ADVNGR_SI32178_STR "ADVNGR_SI32178" +#define VOICECFG_6362ADVNGR_SI3217X_NOFXO_STR "ADVNGR_SI3217XN" +#define VOICECFG_6362ADVNGR_VE890_STR "ADVNGR_VE890" +#define VOICECFG_6362ADVNGR_LE89116_STR "ADVNGR_LE89116" +#define VOICECFG_6362ADVNGR_LE89316_STR "ADVNGR_LE89316" +#define VOICECFG_6362ADVNGR_LE88506_STR "ADVNGR_LE88506" +#define VOICECFG_6362ADVNGR_LE88276_STR "ADVNGR_LE88276" +#define VOICECFG_6362ADVNGR_SI3226_STR "ADVNGR_SI3226" +#define VOICECFG_6362ADVNGR_SI32261_STR "ADVNGR_SI32261" +#define VOICECFG_6362ADVNGR_SI32267_STR "ADVNGR_SI32267" +#define VOICECFG_6362ADVNGR_VE890HV_PARTIAL_STR "ADVNGR_VE890HVP" +#define VOICECFG_6362ADVNGR_VE890HV_STR "ADVNGR_VE890HV" + +#define VOICECFG_6362ADVNGR2_SI3217X_STR "ADVNGR2_SI3217X" +#define VOICECFG_6362ADVNGR2_VE890_STR "ADVNGR2_VE890" +#define VOICECFG_6362ADVNGR2_LE88506_STR "ADVNGR2_LE88506" +#define VOICECFG_6362ADVNGR2_LE88276_STR "ADVNGR2_LE88276" +#define VOICECFG_6362ADVNGR2_SI3226_STR "ADVNGR2_SI3226" + +#define VOICECFG_6368MVNGR_SI3217X_STR "MVNGR_SI3217X" +#define VOICECFG_6368MVNGR_SI32176_STR "MVNGR_SI32176" +#define VOICECFG_6368MVNGR_SI32178_STR "MVNGR_SI32178" +#define VOICECFG_6368MVNGR_SI3217X_NOFXO_STR "MVNGR_SI3217XN" +#define VOICECFG_6368MVNGR_VE890_STR "MVNGR_VE890" +#define VOICECFG_6368MVNGR_LE89116_STR "MVNGR_LE89116" +#define VOICECFG_6368MVNGR_LE89316_STR "MVNGR_LE89316" +#define VOICECFG_6368MVNGR_LE88506_STR "MVNGR_LE88506" +#define VOICECFG_6368MVNGR_LE88276_STR "MVNGR_LE88276" +#define VOICECFG_6368MVNGR_SI3226_STR "MVNGR_SI3226" +#define VOICECFG_6368MVNGR_VE890HV_PARTIAL_STR "MVNGR_VE890HVP" +#define VOICECFG_6368MVNGR_VE890HV_STR "MVNGR_VE890HV" + + +/* Maximum number of devices in the system (on the board). +** Devices can refer to DECT, SLAC/SLIC, or SLAC/DAA combo. */ +#define BP_MAX_VOICE_DEVICES 5 + +/* Maximum numbers of channels per SLAC. */ +#define BP_MAX_CHANNELS_PER_DEVICE 2 + +/* Maximum number of voice channels in the system. +** This represents the sum of all channels available on the devices in the system */ +#define BP_MAX_VOICE_CHAN (BP_MAX_VOICE_DEVICES * BP_MAX_CHANNELS_PER_DEVICE) + +/* Max number of GPIO pins used for controling PSTN failover relays +** Note: the number of PSTN failover relays can be larger if multiple +** relays are controlled by single GPIO */ +#define BP_MAX_RELAY_PINS 2 + +#define BP_TIMESLOT_INVALID 0xFF + +/* General-purpose flag definitions (rename as appropriate) */ +#define BP_FLAG_DSP_APMHAL_ENABLE (1 << 0) +#define BP_FLAG_ISI_SUPPORT (1 << 1) +#define BP_FLAG_MODNAME_TESTNAME2 (1 << 2) +#define BP_FLAG_MODNAME_TESTNAME3 (1 << 3) +#define BP_FLAG_MODNAME_TESTNAME4 (1 << 4) +#define BP_FLAG_MODNAME_TESTNAME5 (1 << 5) +#define BP_FLAG_MODNAME_TESTNAME6 (1 << 6) +#define BP_FLAG_MODNAME_TESTNAME7 (1 << 7) +#define BP_FLAG_MODNAME_TESTNAME8 (1 << 8) + +/* +** Device-specific definitions +*/ +typedef enum +{ + BP_VD_NONE = -1, + BP_VD_IDECT1, /* Do not move this around, otherwise rebuild dect_driver.bin */ + BP_VD_EDECT1, + BP_VD_SILABS_3050, + BP_VD_SILABS_3215, + BP_VD_SILABS_3216, + BP_VD_SILABS_3217, + BP_VD_SILABS_32176, + BP_VD_SILABS_32178, + BP_VD_SILABS_3226, + BP_VD_SILABS_32261, + BP_VD_SILABS_32267, + BP_VD_ZARLINK_88010, + BP_VD_ZARLINK_88221, + BP_VD_ZARLINK_88276, + BP_VD_ZARLINK_88506, + BP_VD_ZARLINK_89010, + BP_VD_ZARLINK_89116, + BP_VD_ZARLINK_89316, + BP_VD_ZARLINK_9530, + BP_VD_ZARLINK_89136, + BP_VD_ZARLINK_89336, + BP_VD_MAX, +} BP_VOICE_DEVICE_TYPE; + + +/* +** Channel-specific definitions +*/ + +typedef enum +{ + BP_VOICE_CHANNEL_ACTIVE, + BP_VOICE_CHANNEL_INACTIVE, +} BP_VOICE_CHANNEL_STATUS; + +typedef enum +{ + BP_VCTYPE_NONE = -1, + BP_VCTYPE_SLIC, + BP_VCTYPE_DAA, + BP_VCTYPE_DECT +} BP_VOICE_CHANNEL_TYPE; + +typedef enum +{ + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_SAMPLE_SIZE_8BITS, +} BP_VOICE_CHANNEL_SAMPLE_SIZE; + +typedef enum +{ + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_WIDEBAND, +} BP_VOICE_CHANNEL_FREQRANGE; + + +typedef enum +{ + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_VOICE_CHANNEL_ENDIAN_LITTLE, +} BP_VOICE_CHANNEL_ENDIAN_MODE; + +typedef enum +{ + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ULAW, +} BP_VOICE_CHANNEL_PCMCOMP_MODE; + + +typedef struct +{ + unsigned int status; /* active/inactive */ + unsigned int type; /* SLIC/DAA/DECT */ + unsigned int pcmCompMode; /* u-law/a-law (applicable for 8-bit samples) */ + unsigned int freqRange; /* narrowband/wideband */ + unsigned int sampleSize; /* 8-bit / 16-bit */ + unsigned int endianMode; /* big/little */ + unsigned int rxTimeslot; /* Receive timeslot for the channel */ + unsigned int txTimeslot; /* Sending timeslot for the channel */ + +} BP_VOICE_CHANNEL; + +/* TODO: This structure could possibly be turned into union if needed */ +typedef struct +{ + int spiDevId; /* SPI device id */ + unsigned short spiGpio; /* SPI GPIO (if used for SPI control) */ +} BP_VOICE_SPI_CONTROL; + +typedef struct +{ + unsigned short relayGpio[BP_MAX_RELAY_PINS]; +} BP_PSTN_RELAY_CONTROL; + +typedef struct +{ + unsigned short dectUartGpioTx; + unsigned short dectUartGpioRx; +} BP_DECT_UART_CONTROL; + +typedef struct +{ + unsigned int voiceDeviceType; /* Specific type of device (Le88276, Si32176, etc.) */ + BP_VOICE_SPI_CONTROL spiCtrl; /* SPI control through dedicated SPI pin or GPIO */ + int requiresReset; /* Does the device requires reset (through GPIO) */ + unsigned short resetGpio; /* Reset GPIO */ + BP_VOICE_CHANNEL channel[BP_MAX_CHANNELS_PER_DEVICE]; /* Device channels */ + +} BP_VOICE_DEVICE; + + +/* +** Main structure for defining the board parameters and used by boardHal +** for proper initialization of the DSP and devices (SLACs, DECT, etc.) +*/ +typedef struct VOICE_BOARD_PARMS +{ + char szBoardId[BP_BOARD_ID_LEN]; /* board id string */ + unsigned int numFxsLines; /* Number of FXS lines in the system */ + unsigned int numFxoLines; /* Number of FXO lines in the system */ + unsigned int numDectLines; /* Number of DECT lines in the system */ + unsigned int numFailoverRelayPins; /* Number of GPIO pins controling PSTN failover relays */ + BP_VOICE_DEVICE voiceDevice[BP_MAX_VOICE_DEVICES]; /* Voice devices in the system */ + BP_PSTN_RELAY_CONTROL pstnRelayCtrl; /* Control for PSTN failover relays */ + BP_DECT_UART_CONTROL dectUartControl; /* Control for external DECT UART */ + unsigned int flags; /* General-purpose flags */ +} VOICE_BOARD_PARMS, *PVOICE_BOARD_PARMS; + +/* --- End of voice-specific structures and enums --- */ + +int BpGetVoiceParms( char* pszBoardId, VOICE_BOARD_PARMS* voiceParms ); +int BpSetVoiceBoardId( char *pszBoardId ); +int BpGetVoiceBoardId( char *pszBoardId ); +int BpGetVoiceBoardIds( char *pszBoardIds, int nBoardIdsSize ); + +/* Variable externs */ + +#if defined(_BCM96328_) || defined(CONFIG_BCM96328) + +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI3226; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI32267; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88276_NTR; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890HV_Partial; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890HV; + +extern VOICE_BOARD_PARMS voiceBoard_96328AVNGR_SI32176; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNGR_LE89116; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNGR_SI3217X; + +#endif + +#if defined(_BCM96362_) || defined(CONFIG_BCM96362) + +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_NOSLIC; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE89116; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE89316; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI32176; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI32178; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI3226; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE88506; + +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32176; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32178; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3217X_NOFXO; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE89116; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE89316; + +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3226; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32261; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32267; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890HVP; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890HV; + +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_SI3226; + +#endif + +#if defined(_BCM96368_) || defined(CONFIG_BCM96368) + +extern VOICE_BOARD_PARMS voiceBoard_96368MVWG; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE89116; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE89316; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI32176; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI32178; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI3226; + +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI32176; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI32178; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3217X_NOFXO; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE89116; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE89316; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3226; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890HV_Partial; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890HV; + +#endif + + +#if defined(_BCM96816_) || defined(CONFIG_BCM96816) + +extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_SI3226; +extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE9530; + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _BOARDPARMS_VOICE_H */ + diff --git a/shared/opensource/include/bcm963xx/fap_mod_size.h b/shared/opensource/include/bcm963xx/fap_mod_size.h new file mode 100644 index 0000000..03bb799 --- /dev/null +++ b/shared/opensource/include/bcm963xx/fap_mod_size.h @@ -0,0 +1,2 @@ +#define FAP_CORE_SIZE 0 +#define FAP_INIT_SIZE 0 diff --git a/shared/opensource/include/bcm963xx/flash_api.h b/shared/opensource/include/bcm963xx/flash_api.h new file mode 100755 index 0000000..7ac8022 --- /dev/null +++ b/shared/opensource/include/bcm963xx/flash_api.h @@ -0,0 +1,90 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/*************************************************************************** + * File Name : flash_api.h + * + * Description: This file contains definitions and prototypes for a public + * flash device interface and an internal flash device interface. + ***************************************************************************/ + +#if !defined(_FLASH_API_H) +#define _FLASH_API_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Flash definitions. */ +#define FLASH_API_OK 1 +#define FLASH_API_ERROR -1 + +#define FLASH_IFC_UNKNOWN 0 +#define FLASH_IFC_PARALLEL 1 +#define FLASH_IFC_SPI 2 +#define FLASH_IFC_HS_SPI 3 +#define FLASH_IFC_NAND 4 + +#define NAND_REINIT_FLASH 0xffff + +/* Public Interface Prototypes. */ +int flash_init(void); +int flash_sector_erase_int(unsigned short sector); +int flash_read_buf(unsigned short sector, int offset, unsigned char *buffer, + int numbytes); +int flash_write_buf(unsigned short sector, int offset, unsigned char *buffer, + int numbytes); +int flash_get_numsectors(void); +int flash_get_sector_size(unsigned short sector); +unsigned char *flash_get_memptr(unsigned short sector); +int flash_get_blk(int addr); +int flash_get_total_size(void); +int flash_get_flash_type(void); +void flash_change_flash_type(int type); + +/* Internal Flash Device Driver Information. */ +typedef struct flash_device_info_s +{ + unsigned short flash_device_id; + unsigned short flash_type; + char flash_device_name[30]; + + int (*fn_flash_sector_erase_int) (unsigned short sector); + int (*fn_flash_read_buf) (unsigned short sector, int offset, + unsigned char *buffer, int numbytes); + int (*fn_flash_write_buf) (unsigned short sector, int offset, + unsigned char *buffer, int numbytes); + int (*fn_flash_get_numsectors) (void); + int (*fn_flash_get_sector_size) (unsigned short sector); + unsigned char * (*fn_flash_get_memptr) (unsigned short sector); + int (*fn_flash_get_blk) (int addr); + int (*fn_flash_get_total_size) (void); +} flash_device_info_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _FLASH_API_H */ + diff --git a/shared/opensource/include/bcm963xx/flash_common.h b/shared/opensource/include/bcm963xx/flash_common.h new file mode 100755 index 0000000..4fcceca --- /dev/null +++ b/shared/opensource/include/bcm963xx/flash_common.h @@ -0,0 +1,103 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/*!\file flash_common.h + * \brief This file contains definitions and prototypes used by both + * CFE and kernel. + * + */ + +#if !defined(_FLASH_COMMON_H) +#define _FLASH_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** default scratch pad length */ +#define SP_MAX_LEN (8 * 1024) + + +/** Flash storage address information that is determined by the flash driver. + * + * This structure is used by CFE and kernel. + */ +typedef struct flashaddrinfo +{ + int flash_persistent_start_blk; /**< primary psi, for config file */ + int flash_persistent_number_blk; + int flash_persistent_length; /**< in bytes */ + unsigned long flash_persistent_blk_offset; + int flash_scratch_pad_start_blk; /**< start of scratch pad */ + int flash_scratch_pad_number_blk; + int flash_scratch_pad_length; /**< in bytes */ + unsigned long flash_scratch_pad_blk_offset; + unsigned long flash_rootfs_start_offset; /**< offset from start of flash to fs+kernel image */ + int flash_backup_psi_start_blk; /**< starting block of backup psi. Length is + the same as primary psi. + Start at begining of sector, so offset is always 0. + No sharing sectors with anybody else. */ + int flash_backup_psi_number_blk; /**< The number of sectors for primary and backup + * psi may be different due to the irregular + * sector sizes at the end of the flash. */ + int flash_syslog_start_blk; /**< starting block of persistent syslog. */ + int flash_syslog_number_blk; /**< number of blocks */ + int flash_syslog_length; /**< in bytes, set from CFE, note busybox syslogd uses 16KB buffer. + Like backup_psi, always start at beginning of sector, + so offset is 0, and no sharing of sectors. */ + int flash_meta_start_blk; /**< The first block which is used for meta info such + as the psi, scratch pad, syslog, backup psi. + The kernel can use everything above this sector. */ +} FLASH_ADDR_INFO, *PFLASH_ADDR_INFO; + + +/** Fill in the fInfo structure with primary PSI, scratch pad, syslog, secondary PSI info. + * + * @param nvRam (IN) nvram info. + * @param fInfo (OUT) flash addr info that will be filled out by this function. + */ +void flash_init_info(const NVRAM_DATA *nvRam, FLASH_ADDR_INFO *fInfo); + + +/** Get the total number of bytes at the bottom of the flash used for PSI, scratch pad, etc. + * + * Even though this function is returning the number of bytes, it it guaranteed to + * return the number of bytes of whole sectors at the end which are in use. + * If customer enables backup PSI and persistent syslog, the number of bytes + * may go above 64KB. This function replaces the old FLASH_RESERVED_AT_END define. + * + * @param fInfo (IN) Pointer to flash_addr_info struct. + * + * @return number of bytes reserved at the end. + */ +unsigned int flash_get_reserved_bytes_at_end(const FLASH_ADDR_INFO *fInfo); + + +#ifdef __cplusplus +} +#endif + +#endif /* _FLASH_COMMON_H */ + diff --git a/shared/opensource/include/bcm963xx/gpio_drv.h b/shared/opensource/include/bcm963xx/gpio_drv.h new file mode 100755 index 0000000..8131153 --- /dev/null +++ b/shared/opensource/include/bcm963xx/gpio_drv.h @@ -0,0 +1,40 @@ +/*************************************************************************** +*** +*** Copyright 2008 Hon Hai Precision Ind. Co. Ltd. +*** All Rights Reserved. +*** No portions of this material shall be reproduced in any form without the +*** written permission of Hon Hai Precision Ind. Co. Ltd. +*** +*** All information contained in this document is Hon Hai Precision Ind. +*** Co. Ltd. company private, proprietary, and trade secret property and +*** are protected by international intellectual property laws and treaties. +*** +****************************************************************************/ + +#ifndef __GPIO_DRV_H__ +#define __GPIO_DRV_H__ + +#define DEV_GPIO_DRV "gpio_drv" + +#define GPIO_IOCTL_NUM 'W' + +#define IOCTL_LAN_LED_STATE _IOWR(GPIO_IOCTL_NUM, 0, int *) +#define IOCTL_USB_LED_STATE _IOWR(GPIO_IOCTL_NUM, 1, int *) +#define IOCTL_WPS_LED_STATE _IOWR(GPIO_IOCTL_NUM, 2, int *) +#define IOCTL_VOIP_LED_OFF _IOWR(GPIO_IOCTL_NUM, 3, int *) +#define IOCTL_VOIP_LED_ON _IOWR(GPIO_IOCTL_NUM, 4, int *) +#define IOCTL_VOIP_LED_BS _IOWR(GPIO_IOCTL_NUM, 5, int *) +#define IOCTL_VOIP_LED_BF _IOWR(GPIO_IOCTL_NUM, 6, int *) +#define IOCTL_VOIP_LED_BN _IOWR(GPIO_IOCTL_NUM, 7, int *) +#define IOCTL_WAN_LED_STATE _IOWR(GPIO_IOCTL_NUM, 8, int *) +#define IOCTL_LAN_VLAN_ID _IOWR(GPIO_IOCTL_NUM, 9, int *) +#define IOCTL_WAN_VLAN_ID _IOWR(GPIO_IOCTL_NUM, 10, int *) +#define IOCTL_3G_LED_STATE _IOWR(GPIO_IOCTL_NUM, 11, int *) //Foxconn added, Neil Chen, 2009/11/2 +/* Foxconn added start Bob, 01/28/2010, for wan detection */ +#define IOCTL_PVC_DET_START _IOWR(GPIO_IOCTL_NUM, 12, int *) +#define IOCTL_PVC_DET_STOP _IOWR(GPIO_IOCTL_NUM, 13, int *) +#define IOCTL_PVC_DET_RESULT _IOWR(GPIO_IOCTL_NUM, 14, int *) +/* Foxconn added end Bob, 01/28/2010, for wan detection */ +#define IOCTL_LAN_UNTAGGED_VLAN_ID _IOWR(GPIO_IOCTL_NUM, 15, int *) /* Foxconn added Bob, 10/25/2010, for tag based vlan */ + +#endif /* __GPIO_DRV_H__ */ diff --git a/shared/opensource/include/bcm963xx/wan_det.h b/shared/opensource/include/bcm963xx/wan_det.h new file mode 100755 index 0000000..d8a5645 --- /dev/null +++ b/shared/opensource/include/bcm963xx/wan_det.h @@ -0,0 +1,245 @@ +/*************************************************************************** +*** +*** Copyright 2008 Hon Hai Precision Ind. Co. Ltd. +*** All Rights Reserved. +*** No portions of this material shall be reproduced in any form without the +*** written permission of Hon Hai Precision Ind. Co. Ltd. +*** +*** All information contained in this document is Hon Hai Precision Ind. +*** Co. Ltd. company private, proprietary, and trade secret property and +*** are protected by international intellectual property laws and treaties. +*** +****************************************************************************/ + +#ifndef __WAN_DET_H__ +#define __WAN_DET_H__ + +/* Foxconn added start Bob, 01/22/2010 */ + +#define MAX_SCAN_SERVICE 8 + +typedef struct _vpivcitable +{ + int portId; + int vpi; + int vci; +}_VpiVciTable; + + +typedef struct scanResult +{ + _VpiVciTable service[MAX_SCAN_SERVICE]; + _VpiVciTable oam; + _VpiVciTable BPDU; +}SCAN_RESULT; +/* Foxconn added end Bob, 01/22/2010 */ + +typedef unsigned short U16;
+typedef unsigned int U32;
+typedef unsigned char U8;
+
+#define PATTERN_ROUTED 0
+#define PATTERN_BRIDGED 1
+
+#define ETHER_TYPE_OFFSET 12
+#define ETHERTYPE_IP 0x0800
+#define ETHERTYPE_ARP 0x0806
+#define ETHERTYPE_PPPOE_DISCOVERY 0x8863
+#define ETHERHEADER_LEN 14
+
+typedef struct _PacketContent
+{
+ U32 length;
+ U8 *data;
+}PacketContent;
+
+typedef struct _Pattern
+{
+ const char *name;
+ const PacketContent *payload;
+ int protoType;
+ U16 ethertype;
+ const PacketContent *header;
+ const PacketContent *expected_payload;
+
+}Pattern;
+
+
+static U8 dhcp_request_bytes[] = {
+
+ // IP header
+ 0x45, 0x00, 0x01, 0x48, // version, IHL, TOS, Total Length
+ 0x00, 0x04, 0x00, 0x00, // ident, flags, frag off
+ 0x9b, 0x11, 0x1e, 0xa2, // TTL, proto, hdr checksum
+ 0x00, 0x00, 0x00, 0x00, // source addr
+ 0xff, 0xff, 0xff, 0xff, // destination addr
+
+ // UDP header
+ 0x00, 0x44, 0x00, 0x43, 0x01, 0x34, 0xe6, 0x9a, 0x01, 0x01, 0x06, 0x00,
+ 0xb3, 0x05, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x2b, 0x00, 0x74, 0xb1, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x82, 0x53, 0x63, 0x35, 0x01, 0x01, 0x33,
+ 0x04, 0x00, 0x00, 0x1c, 0x20, 0x37, 0x07, 0x01, 0x1c, 0x02, 0x03, 0x0f, 0x06, 0x0c, 0xff, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+};
+
+static PacketContent dhcp_request = { sizeof(dhcp_request_bytes), dhcp_request_bytes
+};
+
+static U8 pppoe_padi_bytes[] = {
+ 0x11, 0x09, 0x00, 0x00, 0x00, 0x04, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+static PacketContent pppoe_padi = { sizeof(pppoe_padi_bytes), pppoe_padi_bytes };
+
+/** Sequence of bytes for a PPP LCP Configure-Request (RFC1661). */
+static U8 ppp_lcp_confreq_bytes[] = {
+ 0xc0, 0x21, // LCP
+ 0x01, // Configure Request
+ 0x99, // randomish identifier
+ 0x00, 0x04, // length
+};
+static PacketContent ppp_lcp_confreq = { sizeof(ppp_lcp_confreq_bytes), ppp_lcp_confreq_bytes };
+
+/** Expected response from NULL (aka VcMux) encapsulated PPP/LCP */
+static U8 ppp_lcp_response_bytes[] = { 0xc0, 0x21 };
+static PacketContent ppp_lcp_response = { sizeof(ppp_lcp_response_bytes), ppp_lcp_response_bytes };
+
+/** SNAP/LLC routed */
+static U8 snap_llc_routed_bytes[] = { 0xaa, 0xaa, 3, 0, 0, 0, 8, 0 };
+static PacketContent snap_llc_routed = { sizeof(snap_llc_routed_bytes), snap_llc_routed_bytes };
+
+/** SNAP/LLC bridged, no fcs */
+static U8 snap_llc_bridged_bytes[] = {
+ 0xaa, 0xaa, 0x3, // LLC
+ 0x0, 0x80, 0xc2, // OUI
+ 0x00, 0x07, // PID
+ 0x00, 0x00 // PAD
+ };
+static PacketContent snap_llc_bridged = { sizeof(snap_llc_bridged_bytes), snap_llc_bridged_bytes };
+
+/* foxconn added start Bob, 12/07/2009, ignore BPDU frame */
+/** SNAP/LLC bridged BPDU */
+static U8 snap_llc_bridged_BPDU_bytes[] = {
+ 0xaa, 0xaa, 0x3, // LLC
+ 0x0, 0x80, 0xc2, // OUI
+ 0x00, 0x0e, // PID
+ };
+ /* foxconn added end Bob, 12/07/2009, ignore BPDU frame */
+
+/** LLC for PPPoA. See RFC2364 section 6. */
+static U8 llc_pppoa_bytes[] = { 0xfe, 0xfe, 0x03, 0xcf };
+static PacketContent llc_pppoa = {
+ sizeof(llc_pppoa_bytes), llc_pppoa_bytes
+};
+
+static U8 vcmux_bridged_bytes[] = { 0, 0 };
+static PacketContent vcmux_bridged = { sizeof(vcmux_bridged_bytes), vcmux_bridged_bytes };
+
+/**
+Patterns to be sent to CO side
+1. PPPoE LLC Bridged
+2. VcMux encapsulated PPPoA
+3. LLC encapsulated PPPoA
+4. RFC1483 SNAP/LLC Routed
+5. RFC1483 VcMux Bridged
+6. PPPoE VCMux Bridged
+7. RFC1483 SNAP/LLC Bridged
+8. RFC1483 VcMux Routed
+*/
+static Pattern patterns[] =
+{
+ {
+ "PPPoE LLC Bridged",
+ &pppoe_padi,
+ PATTERN_BRIDGED,
+ ETHERTYPE_PPPOE_DISCOVERY,
+ &snap_llc_bridged,
+ NULL
+ },
+ {
+ "VcMux encapsulated PPPoA",
+ &ppp_lcp_confreq,
+ PATTERN_ROUTED,
+ 0, // no need for etherheader!
+ NULL,
+ &ppp_lcp_response
+ },
+
+ {
+ "LLC encapsulated PPPoA",
+ &ppp_lcp_confreq,
+ PATTERN_ROUTED,
+ 0, // no need for etherheader!
+ &llc_pppoa, // encapsulated with PPPoA LLC header
+ NULL
+ },
+
+ /* RFC1483 SNAP/LLC routed */
+ {
+ "RFC1483 SNAP/LLC Routed",
+ &dhcp_request,
+ PATTERN_ROUTED,
+ 0,
+ &snap_llc_routed,
+ NULL
+ },
+
+ /* RFC1483 VC mux bridged */
+ {
+ "RFC1483 VcMux Bridged",
+ &dhcp_request,
+ PATTERN_BRIDGED,
+ ETHERTYPE_IP,
+ &vcmux_bridged,
+ NULL
+ },
+
+ /* PPPOE VCMux Bridged*/
+ {
+ "PPPoE VCMux Bridged",
+ &pppoe_padi,
+ PATTERN_BRIDGED,
+ ETHERTYPE_PPPOE_DISCOVERY,
+ &vcmux_bridged,
+ NULL
+ },
+
+ /* RFC1483 SNAP/LLC bridged */
+ {
+ "RFC1483 SNAP/LLC Bridged",
+ &dhcp_request,
+ PATTERN_BRIDGED,
+ ETHERTYPE_IP,
+ &snap_llc_bridged,
+ NULL
+ },
+
+ /* RFC1483 VC mux routed */
+ {
+ "RFC1483 VcMux Routed",
+ &dhcp_request,
+ PATTERN_ROUTED,
+ 0,
+ NULL,
+ NULL
+ },
+}; + +#endif /* __WAN_DET_H__ */ diff --git a/shared/opensource/include/bcm963xx/wps_led.h b/shared/opensource/include/bcm963xx/wps_led.h new file mode 100755 index 0000000..69f8682 --- /dev/null +++ b/shared/opensource/include/bcm963xx/wps_led.h @@ -0,0 +1,28 @@ +/*************************************************************************** +*** +*** Copyright 2007 Hon Hai Precision Ind. Co. Ltd. +*** All Rights Reserved. +*** No portions of this material shall be reproduced in any form without the +*** written permission of Hon Hai Precision Ind. Co. Ltd. +*** +*** All information contained in this document is Hon Hai Precision Ind. +*** Co. Ltd. company private, proprietary, and trade secret property and +*** are protected by international intellectual property laws and treaties. +*** +****************************************************************************/ + +#ifndef __WPS_LED_H__ +#define __WPS_LED_H__ + +#define DEV_GPIO_DRV "wps_led" + +#define WPS_LED_IOCTL_NUM 'W' + +#define WPS_LED_BLINK_NORMAL _IOWR(WPS_LED_IOCTL_NUM, 0, int *) +#define WPS_LED_BLINK_QUICK _IOWR(WPS_LED_IOCTL_NUM, 1, int *) +#define WPS_LED_BLINK_OFF _IOWR(WPS_LED_IOCTL_NUM, 2, int *) +#define WPS_LED_CHANGE_GREEN _IOWR(WPS_LED_IOCTL_NUM, 3, int *) +#define WPS_LED_CHANGE_AMBER _IOWR(WPS_LED_IOCTL_NUM, 4, int *) +#define WPS_LED_BLINK_QUICK2 _IOWR(WPS_LED_IOCTL_NUM, 5, int *) + +#endif diff --git a/shared/opensource/spi/Makefile b/shared/opensource/spi/Makefile new file mode 100755 index 0000000..b3eb2b1 --- /dev/null +++ b/shared/opensource/spi/Makefile @@ -0,0 +1,30 @@ + +ifeq ($(CONFIG_MIPS_BRCM),y) + +ifeq ($(strip $(BRCM_CHIP)),6362) +obj-y += \ + bcmHsSpi.o +else +ifeq ($(strip $(BRCM_CHIP)),6816) +obj-y += \ + bcmHsSpi.o +else +ifeq ($(strip $(BRCM_CHIP)),6328) +obj-y += \ + bcmHsSpi.o +endif +endif +endif + +ifneq ($(strip $(BRCM_CHIP)),6328) +obj-y += \ + bcmLegSpi.o +endif + +obj-y += \ + bcmSpiRes.o + +EXTRA_CFLAGS += -DCONFIG_BCM9$(BRCM_CHIP) -I$(INC_BRCMDRIVER_PUB_PATH)/$(BRCM_BOARD) -I$(INC_BRCMSHARED_PUB_PATH)/$(BRCM_BOARD) + +endif + diff --git a/shared/opensource/spi/bcmHsSpi.c b/shared/opensource/spi/bcmHsSpi.c new file mode 100755 index 0000000..b32e9fc --- /dev/null +++ b/shared/opensource/spi/bcmHsSpi.c @@ -0,0 +1,898 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifdef _CFE_ +#include "lib_types.h" +#include "lib_printf.h" +#include "lib_string.h" +#include "bcm_map.h" +#define printk printf +#else +#include <linux/autoconf.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/spi/spi.h> + +#include <bcm_map_part.h> +#include <bcm_intr.h> +#endif + +/* if HS_SPI is defined then the HS SPI controller is available, otherwise do not compile this code */ + +#ifdef HS_SPI + +#include "bcmSpiRes.h" +#include "bcmSpi.h" + +int BcmHsSpiRead(unsigned char * msg_buf, int prependcnt, int nbytes, int devId, int freqHz); +int BcmHsSpiWrite(unsigned char * msg_buf, int nbytes, int devId, int freqHz); + +#define HS_SPI_STATE_CLOCK_POLARITY (1 << 31) +#define HS_SPI_STATE_GATE_CLOCK_SSOFF (1 << 30) +#define HS_SPI_STATE_LAUNCH_RISING (1 << 29) +#define HS_SPI_STATE_LATCH_RISING (1 << 28) +#define HS_SPI_STATE_ASYNC_CLOCK (1 << 27) +#if defined(_BCM96816_) || defined(CONFIG_BCM96816) +#define HS_SPI_CONTROLLER_STATE_DEF (HS_SPI_STATE_GATE_CLOCK_SSOFF) +#endif +#if defined(_BCM96328_) || defined(CONFIG_BCM96328) +#define HS_SPI_CONTROLLER_STATE_DEF (HS_SPI_STATE_GATE_CLOCK_SSOFF | HS_SPI_STATE_LATCH_RISING) +#endif +#if defined(_BCM96362_) || defined(CONFIG_BCM96362) +#define HS_SPI_CONTROLLER_STATE_DEF (HS_SPI_STATE_GATE_CLOCK_SSOFF | HS_SPI_STATE_LATCH_RISING | HS_SPI_STATE_ASYNC_CLOCK) +#endif + + +#ifndef _CFE_ +//#define HS_SPI_USE_INTERRUPTS /* define this to use interrupts instead of polling */ +static struct bcmspi BcmHsSpi = { SPIN_LOCK_UNLOCKED, + "bcmHsSpiDev", + }; +#else +#define udelay(X) \ + do { { int i; for( i = 0; i < (X) * 500; i++ ) ; } } while(0) +#endif + +static int hsSpiRead( unsigned char *pRxBuf, int prependcnt, int nbytes, int devId ) +{ + uint16 msgCtrl; + + HS_SPI_PROFILES[devId].mode_ctrl = prependcnt<<HS_SPI_PREPENDBYTE_CNT | 0<<HS_SPI_MODE_ONE_WIRE | + 0<<HS_SPI_MULTIDATA_WR_SIZE | 0<<HS_SPI_MULTIDATA_RD_SIZE | 2<<HS_SPI_MULTIDATA_WR_STRT | + 2<<HS_SPI_MULTIDATA_RD_STRT | 0xff<<HS_SPI_FILLBYTE; + + msgCtrl = (HS_SPI_OP_READ<<HS_SPI_OP_CODE) | nbytes; + memcpy((char *)HS_SPI_FIFO0, (void *)(&msgCtrl), 2); + + if ( 0 != prependcnt ) + { + memcpy((char *)(HS_SPI_FIFO0+2), (char *)pRxBuf, prependcnt); + } + + HS_SPI_PINGPONG0->command = devId<<HS_SPI_SS_NUM | devId<<HS_SPI_PROFILE_NUM | 0<<HS_SPI_TRIGGER_NUM | + HS_SPI_COMMAND_START_NOW<<HS_SPI_COMMAND_VALUE; + + return SPI_STATUS_OK; + +} + +static int hsSpiWriteFull( unsigned char *pTxBuf, int nbytes, int devId, int opcode ) +{ + uint16 msgCtrl; + + HS_SPI_PROFILES[devId].mode_ctrl = 0<<HS_SPI_PREPENDBYTE_CNT | 0<<HS_SPI_MODE_ONE_WIRE | + 0<<HS_SPI_MULTIDATA_WR_SIZE | 0<<HS_SPI_MULTIDATA_RD_SIZE | 2<<HS_SPI_MULTIDATA_WR_STRT | + 2<<HS_SPI_MULTIDATA_RD_STRT | 0xff<<HS_SPI_FILLBYTE; + + if (BCM_SPI_FULL == opcode) + { + msgCtrl = (HS_SPI_OP_READ_WRITE<<HS_SPI_OP_CODE) | nbytes; + } + else + { + msgCtrl = (HS_SPI_OP_WRITE<<HS_SPI_OP_CODE) | nbytes; + } + memcpy((char *)HS_SPI_FIFO0, (void *)(&msgCtrl), 2); + memcpy((char *)(HS_SPI_FIFO0+2), (void *)pTxBuf, nbytes); + + HS_SPI_PINGPONG0->command = devId<<HS_SPI_SS_NUM | devId<<HS_SPI_PROFILE_NUM | 0<<HS_SPI_TRIGGER_NUM | + HS_SPI_COMMAND_START_NOW<<HS_SPI_COMMAND_VALUE; + + return SPI_STATUS_OK; + +} + +static int hsSpiTransEnd( unsigned char *rxBuf, int nbytes ) +{ + if ( NULL != rxBuf ) + { + memcpy((char *)rxBuf, (void *)HS_SPI_FIFO0, nbytes); + } + + return SPI_STATUS_OK; + +} + +static int hsSpiTransPoll(void) +{ + unsigned int wait; + + for (wait = (100*1000); wait>0; wait--) + { + if (!(HS_SPI_PINGPONG0->status & 1<<HS_SPI_SOURCE_BUSY )) + { + break; + } + udelay(1); + } + + if (wait == 0) + { + return SPI_STATUS_ERR; + } + + return SPI_STATUS_OK; +} + + +static void hsSpiClearIntStatus(void) +{ + HS_SPI->hs_spiIntStatus = HS_SPI_INTR_CLEAR_ALL; +} + +#ifdef HS_SPI_USE_INTERRUPTS +static void hsSpiEnableInt(bool bEnable) +{ + if ( bEnable ) + { + HS_SPI->hs_spiIntMask = HS_SPI_IRQ_PING0_CMD_DONE; + } + else + { + HS_SPI->hs_spiIntMask = 0; + } +} +#endif + +#ifndef _CFE_ +static int hsSpiSetClock( int clockHz, int profile ) +{ + int clock; + + clock = HS_SPI_PLL_FREQ/clockHz; + if (HS_SPI_PLL_FREQ%HS_SPI_CLOCK_DEF) + clock++; + + clock = 2048/clock; + if (2048%(clock)) + clock++; + + HS_SPI_PROFILES[profile].clk_ctrl = 1<<HS_SPI_ACCUM_RST_ON_LOOP | 0<<HS_SPI_SPI_CLK_2X_SEL | clock<<HS_SPI_FREQ_CTRL_WORD; + + return SPI_STATUS_OK; +} + +static void hsSpiSetControllerState(unsigned int ctrlState, unsigned char devId) +{ + unsigned int temp32; + + temp32 = HS_SPI->hs_spiGlobalCtrl; + if ( 0 == (ctrlState & HS_SPI_STATE_GATE_CLOCK_SSOFF) ) + { + temp32 &= ~HS_SPI_CLK_GATE_SSOFF; + } + else + { + temp32 |= HS_SPI_CLK_GATE_SSOFF; + } +#if defined(_BCM96328_) || defined(CONFIG_BCM96328) || defined(_BCM96362_) || defined(CONFIG_BCM96362) + if ( 0 == (ctrlState & HS_SPI_STATE_CLOCK_POLARITY) ) + { + temp32 &= ~HS_SPI_CLK_POLARITY; + } + else + { + temp32 |= HS_SPI_CLK_POLARITY; + } +#endif + /* write value if required */ + if ( temp32 != HS_SPI->hs_spiGlobalCtrl ) + { + HS_SPI->hs_spiGlobalCtrl = temp32; + } + + temp32 = HS_SPI_PROFILES[devId].signal_ctrl; + if ( 0 == (ctrlState & HS_SPI_STATE_LATCH_RISING) ) + { + temp32 &= ~HS_SPI_LATCH_RISING; + } + else + { + temp32 |= HS_SPI_LATCH_RISING; + } + if ( 0 == (ctrlState & HS_SPI_STATE_LAUNCH_RISING) ) + { + temp32 &= ~HS_SPI_LAUNCH_RISING; + } + else + { + temp32 |= HS_SPI_LAUNCH_RISING; + } + +#if defined(_BCM96328_) || defined(CONFIG_BCM96328) || defined(_BCM96362_) || defined(CONFIG_BCM96362) + if ( 0 == (ctrlState & HS_SPI_STATE_ASYNC_CLOCK) ) + { + temp32 &= ~HS_SPI_ASYNC_INPUT_PATH; + } + else + { + temp32 |= HS_SPI_ASYNC_INPUT_PATH; + } +#endif + + /* write value if required */ + if ( temp32 != HS_SPI_PROFILES[devId].signal_ctrl ) + { + HS_SPI_PROFILES[devId].signal_ctrl = temp32; + } + +} +#endif + +/* these interfaces are availble for the CFE and spi flash driver only + all modules must use the linux kernel framework + if this is called by a module and interrupts are being used there will + be a problem */ +int BcmHsSpiRead( unsigned char *msg_buf, int prependcnt, int nbytes, int devId, int freqHz ) +{ +#ifndef _CFE_ + struct bcmspi *pBcmSpi = &BcmHsSpi; + + if ( pBcmSpi->irq ) + { + printk("BcmHsSpiRead error - Interrupts are enabled\n"); + return( SPI_STATUS_ERR ); + } + + spin_lock(&pBcmSpi->lock); + hsSpiSetControllerState(HS_SPI_CONTROLLER_STATE_DEF, devId); + hsSpiSetClock(freqHz, devId); +#endif + hsSpiClearIntStatus(); + hsSpiRead(msg_buf, prependcnt, nbytes, devId); + hsSpiTransPoll(); + hsSpiTransEnd(msg_buf, nbytes); + hsSpiClearIntStatus(); +#ifndef _CFE_ + spin_unlock(&pBcmSpi->lock); +#endif + + return( SPI_STATUS_OK ); +} + +int BcmHsSpiWrite( unsigned char *msg_buf, int nbytes, int devId, int freqHz ) +{ +#ifndef _CFE_ + struct bcmspi *pBcmSpi = &BcmHsSpi; + + if ( pBcmSpi->irq ) + { + printk("BcmHsSpiWrite error - Interrupts are enabled\n"); + return( SPI_STATUS_ERR ); + } + + spin_lock(&pBcmSpi->lock); + hsSpiSetControllerState(HS_SPI_CONTROLLER_STATE_DEF, devId); + hsSpiSetClock(freqHz, devId); +#endif + hsSpiClearIntStatus(); + hsSpiWriteFull(msg_buf, nbytes, devId, BCM_SPI_WRITE); + hsSpiTransPoll(); + hsSpiTransEnd(msg_buf, nbytes); + hsSpiClearIntStatus(); +#ifndef _CFE_ + spin_unlock(&pBcmSpi->lock); +#endif + + return( SPI_STATUS_OK ); +} + + +#ifndef _CFE_ +static void hsSpiNextMessage(struct bcmspi *pBcmSpi); + +static void hsSpiMsgDone(struct bcmspi *pBcmSpi, struct spi_message *msg, int status) +{ + list_del(&msg->queue); + msg->status = status; + + spin_unlock(&pBcmSpi->lock); + msg->complete(msg->context); + spin_lock(&pBcmSpi->lock); + + pBcmSpi->curTrans = NULL; + + /* continue if needed */ + if (list_empty(&pBcmSpi->queue) || pBcmSpi->stopping) + { + // disable controler ... + } + else + { + hsSpiNextMessage(pBcmSpi); + } +} + +#ifdef HS_SPI_USE_INTERRUPTS +static void hsSpiIntXfer(struct bcmspi *pBcmSpi, struct spi_message *msg) +{ + struct spi_transfer *xfer; + struct spi_transfer *nextXfer; + int length; + int prependCnt; + char *pTxBuf; + char *pRxBuf; + int opCode; + + xfer = pBcmSpi->curTrans; + if ( NULL == xfer) + { + xfer = list_entry(msg->transfers.next, struct spi_transfer, transfer_list); + } + else + { + xfer = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list); + } + pBcmSpi->curTrans = xfer; + + length = xfer->len; + prependCnt = 0; + pRxBuf = xfer->rx_buf; + pTxBuf = (unsigned char *)xfer->tx_buf; + + if ( (NULL != pRxBuf) && (NULL != pTxBuf) ) + { + opCode = BCM_SPI_FULL; + } + else if ( NULL != pRxBuf ) + { + opCode = BCM_SPI_READ; + } + else + { + opCode = BCM_SPI_WRITE; + } + + if ( msg->state ) + { + /* this controller does not support keeping the chip select active for all transfers + non NULL state indicates that we need to combine the transfers */ + nextXfer = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list); + prependCnt = length; + length = nextXfer->len; + pRxBuf = nextXfer->rx_buf; + opCode = BCM_SPI_READ; + pBcmSpi->curTrans = nextXfer; + } + + hsSpiSetClock(xfer->speed_hz, msg->spi->chip_select); + + hsSpiClearIntStatus(); + hsSpiEnableInt(TRUE); + if ( BCM_SPI_READ == opCode ) + { + hsSpiRead(pTxBuf, prependCnt, length, msg->spi->chip_select); + } + else + { + hsSpiWriteFull(pTxBuf, length, msg->spi->chip_select, opCode); + } + + return; + +} +#endif + +static void hsSpiPollXfer(struct bcmspi *pBcmSpi, struct spi_message *msg) +{ + struct spi_transfer *xfer; + struct spi_transfer *nextXfer; + int length; + int prependCnt; + char *pTxBuf; + char *pRxBuf; + int opCode; + + list_for_each_entry(xfer, &msg->transfers, transfer_list) + { + pBcmSpi->curTrans = xfer; + length = xfer->len; + prependCnt = 0; + pRxBuf = xfer->rx_buf; + pTxBuf = (unsigned char *)xfer->tx_buf; + + if ( (NULL != pRxBuf) && (NULL != pTxBuf) ) + { + opCode = BCM_SPI_FULL; + } + else if ( NULL != pRxBuf ) + { + opCode = BCM_SPI_READ; + } + else + { + opCode = BCM_SPI_WRITE; + } + + if ( msg->state ) + { + /* this controller does not support keeping the chip select active for all transfers + non NULL state indicates that we need to combine the transfers */ + nextXfer = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list); + prependCnt = length; + length = nextXfer->len; + pRxBuf = nextXfer->rx_buf; + opCode = BCM_SPI_READ; + xfer = nextXfer; + } + + hsSpiSetClock(xfer->speed_hz, msg->spi->chip_select); + + hsSpiClearIntStatus(); + if ( BCM_SPI_READ == opCode ) + { + hsSpiRead(pTxBuf, prependCnt, length, msg->spi->chip_select); + } + else + { + hsSpiWriteFull(pTxBuf, length, msg->spi->chip_select, opCode); + } + + hsSpiTransPoll(); + hsSpiTransEnd(pRxBuf, length); + hsSpiClearIntStatus(); + + if (xfer->delay_usecs) + { + udelay(xfer->delay_usecs); + } + + msg->actual_length += length; + } + + hsSpiMsgDone(pBcmSpi, msg, SPI_STATUS_OK); + +} + + +static void hsSpiNextXfer(struct bcmspi *pBcmSpi, struct spi_message *msg) +{ +#ifdef HS_SPI_USE_INTERRUPTS + if (pBcmSpi->irq) + hsSpiIntXfer(pBcmSpi, msg); + else +#endif + hsSpiPollXfer(pBcmSpi, msg); +} + +static void hsSpiNextMessage(struct bcmspi *pBcmSpi) +{ + struct spi_message *msg; + unsigned int ctrlState; + + BUG_ON(pBcmSpi->curTrans); + + msg = list_entry(pBcmSpi->queue.next, struct spi_message, queue); + + /* set the controller state for this message */ + ctrlState = (unsigned int)spi_get_ctldata(msg->spi); + hsSpiSetControllerState(ctrlState, msg->spi->chip_select); + + /* there will always be one transfer in a given message */ + hsSpiNextXfer(pBcmSpi, msg); + +} + + +static int hsSpiSetup(struct spi_device *spi) +{ + struct bcmspi *pBcmSpi; + unsigned int spiCtrlData; + unsigned int spiCtrlState = 0; + + pBcmSpi = spi_master_get_devdata(spi->master); + + if (pBcmSpi->stopping) + return -ESHUTDOWN; + + spiCtrlData = (unsigned int)spi->controller_data; + if ( 0 == spiCtrlData ) + { + spiCtrlState = HS_SPI_CONTROLLER_STATE_DEF; + } + else + { + spiCtrlState = 0; + /* note that in HW, the meaning of latch and launch bits changes when CPOl = 1 */ + if ( (0 == (spi->mode & SPI_CPHA)) && + (0 == (spiCtrlData & SPI_CONTROLLER_STATE_CPHA_EXT)) ) + { + /* latch rising, launch falling */ + spiCtrlState = HS_SPI_STATE_LATCH_RISING; + } + else if ( (0 == (spi->mode & SPI_CPHA)) && + (0 != (spiCtrlData & SPI_CONTROLLER_STATE_CPHA_EXT)) ) + { + /* latch rising, launch rising */ + spiCtrlState = HS_SPI_STATE_LATCH_RISING | HS_SPI_STATE_LAUNCH_RISING; + } + else if ( (0 != (spi->mode & SPI_CPHA)) && + (0 == (spiCtrlData & SPI_CONTROLLER_STATE_CPHA_EXT)) ) + { + /* latch falling, launch rising */ + spiCtrlState = HS_SPI_STATE_LAUNCH_RISING; + } + // else - both set to 0, latch falling, launch falling + + if ( 0 != (spi->mode & SPI_CPOL) ) + { + spiCtrlState |= HS_SPI_STATE_CLOCK_POLARITY; + } + + if ( spiCtrlData & SPI_CONTROLLER_STATE_GATE_CLK_SSOFF ) + { + spiCtrlState |= HS_SPI_STATE_GATE_CLOCK_SSOFF; + } + + if ( spiCtrlData & SPI_CONTROLLER_STATE_ASYNC_CLOCK ) + { + spiCtrlState |= HS_SPI_STATE_ASYNC_CLOCK; + } + } + + spi_set_ctldata(spi, (void *)spiCtrlState); + + return 0; +} + + +static int hsSpiTransfer(struct spi_device *spi, struct spi_message *msg) +{ + struct bcmspi *pBcmSpi = &BcmHsSpi; + struct spi_transfer *xfer; + struct spi_transfer *nextXfer; + int xferCnt; + int bCsChange; + int xferLen; + + if (unlikely(list_empty(&msg->transfers))) + return -EINVAL; + + if (pBcmSpi->stopping) + return -ESHUTDOWN; + + /* make sure a completion callback is set */ + if ( NULL == msg->complete ) + { + return -EINVAL; + } + + xferCnt = 0; + bCsChange = 0; + xferLen = 0; + list_for_each_entry(xfer, &msg->transfers, transfer_list) + { + /* check transfer parameters */ + if (!(xfer->tx_buf || xfer->rx_buf)) + { + return -EINVAL; + } + + /* check the clock setting - if it is 0 then set to max clock of the device */ + if ( 0 == xfer->speed_hz ) + { + if ( 0 == spi->max_speed_hz ) + { + return -EINVAL; + } + xfer->speed_hz = spi->max_speed_hz; + } + + xferCnt++; + xferLen += xfer->len; + bCsChange |= xfer->cs_change; + + if ( xfer->len > HS_SPI_BUFFER_LEN ) + { + return -EINVAL; + } + } + + /* this controller does not support keeping the chip select active between + transfers. If a message is detected with a write transfer followed by a + read transfer and cs_change is set to 0 then the two transfers need to be + combined. The message state is used to indicate that the transfers + need to be combined */ + msg->state = NULL; + if ( (2 == xferCnt) && (0 == bCsChange) ) + { + xfer = list_entry(msg->transfers.next, struct spi_transfer, transfer_list); + if ( (NULL != xfer->tx_buf) && (NULL == xfer->rx_buf)) + { + nextXfer = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);; + if ( (NULL == nextXfer->tx_buf) && (NULL != nextXfer->rx_buf)) + { + msg->state = (void *)1; + } + } + } + + msg->status = -EINPROGRESS; + msg->actual_length = 0; + +#ifdef HS_SPI_USE_INTERRUPTS + /* disable interrupts for the SPI controller + using spin_lock_irqsave would disable all interrupts */ + if ( pBcmSpi->irq ) + hsSpiEnableInt(FALSE); +#endif + spin_lock(&pBcmSpi->lock); + + list_add_tail(&msg->queue, &pBcmSpi->queue); + if (NULL == pBcmSpi->curTrans) + { + hsSpiNextMessage(pBcmSpi); + } + + spin_unlock(&pBcmSpi->lock); +#ifdef HS_SPI_USE_INTERRUPTS + if ( pBcmSpi->irq ) + hsSpiEnableInt(TRUE); +#endif + + return 0; +} + + +#ifdef HS_SPI_USE_INTERRUPTS +static irqreturn_t hsSpiIntHandler(int irq, void *dev_id) +{ + struct bcmspi *pBcmSpi = dev_id; + struct spi_message *msg; + struct spi_transfer *xfer; + + if ( 0 == HS_SPI->hs_spiIntStatusMasked ) + { + return ( IRQ_NONE ); + } + + hsSpiClearIntStatus(); + hsSpiEnableInt(FALSE); + + spin_lock(&pBcmSpi->lock); + if ( NULL == pBcmSpi->curTrans ) + { + spin_unlock(&pBcmSpi->lock); + return IRQ_HANDLED; + } + + xfer = pBcmSpi->curTrans; + msg = list_entry(pBcmSpi->queue.next, struct spi_message, queue); + + hsSpiTransEnd(xfer->rx_buf, xfer->len); + + /* xfer can specify a delay before the next transfer is started + this delay would be processed here normally. However, delay in the + interrupt handler is bad so it is ignored. It is used for polling + mode */ + + /* check to see if this is the last transfer in the message */ + if (msg->transfers.prev == &xfer->transfer_list) + { + /* report completed message */ + hsSpiMsgDone(pBcmSpi, msg, SPI_STATUS_OK); + } + else + { + /* Submit the next transfer */ + hsSpiNextXfer(pBcmSpi, msg); + } + + spin_unlock(&pBcmSpi->lock); + + return IRQ_HANDLED; + +} + +int __init hsSpiIntrInit( void ) +{ + int ret = 0; + struct bcmspi *pBcmSpi = &BcmHsSpi; + + hsSpiEnableInt(FALSE); + ret = request_irq(INTERRUPT_ID_SPI, hsSpiIntHandler, (IRQF_DISABLED | IRQF_SAMPLE_RANDOM | IRQF_SHARED), pBcmSpi->devName, pBcmSpi); + + spin_lock(&pBcmSpi->lock); + pBcmSpi->irq = INTERRUPT_ID_SPI; + spin_unlock(&pBcmSpi->lock); + + BcmHalInterruptEnable(pBcmSpi->irq); + + return( 0 ); + +} +/* we cannot initialize interrupts early + The flash module is intialized before an interrupt handler can be installed + and before the Linux framework can be used. This means it needs direct access + to the controller initially. This conflicts with the interrupt handling so we + need to wait for all modules to intialize */ +late_initcall(hsSpiIntrInit); +#endif + +static void hsSpiCleanup(struct spi_device *spi) +{ + /* would free spi_controller memory here if any was allocated */ + +} + +static int __init hsSpiProbe(struct platform_device *pdev) +{ + int ret; + struct spi_master *master; + struct bcmspi *pBcmSpi; + + ret = -ENOMEM; + master = spi_alloc_master(&pdev->dev, 0); + if (!master) + goto out_free; + + master->bus_num = pdev->id; + master->num_chipselect = 8; + master->setup = hsSpiSetup; + master->transfer = hsSpiTransfer; + master->cleanup = hsSpiCleanup; + platform_set_drvdata(pdev, master); + + spi_master_set_devdata(master, (void *)&BcmHsSpi); + pBcmSpi = spi_master_get_devdata(master); + + INIT_LIST_HEAD(&pBcmSpi->queue); + + pBcmSpi->pdev = pdev; + pBcmSpi->bus_num = HS_SPI_BUS_NUM; + pBcmSpi->num_chipselect = 8; + pBcmSpi->curTrans = NULL; + + /* make sure irq is 0 here + since this is used to identify when interrupts are enabled + the IRQ is initialized in hsSpiIntrInit */ + pBcmSpi->irq = 0; + + /* Initialize the hardware */ + + /* register and we are done */ + ret = spi_register_master(master); + if (ret) + goto out_free; + + return 0; + +out_free: + spi_master_put(master); + + return ret; +} + + +static int __exit hsSpiRemove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct bcmspi *pBcmSpi = spi_master_get_devdata(master); + struct spi_message *msg; + + /* reset the hardware and block queue progress */ +#ifdef HS_SPI_USE_INTERRUPTS + hsSpiEnableInt(FALSE); +#endif + spin_lock(&pBcmSpi->lock); + pBcmSpi->stopping = 1; + + /* HW shutdown */ + + spin_unlock(&pBcmSpi->lock); + + /* Terminate remaining queued transfers */ + list_for_each_entry(msg, &pBcmSpi->queue, queue) + { + msg->status = -ESHUTDOWN; + msg->complete(msg->context); + } + +#ifdef HS_SPI_USE_INTERRUPTS + if ( pBcmSpi->irq ) + { + free_irq(pBcmSpi->irq, master); + } +#endif + spi_unregister_master(master); + + return 0; +} + +//#ifdef CONFIG_PM +#if 0 +static int hsSpiSuspend(struct platform_device *pdev, pm_message_t mesg) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct bcmspi *pBcmSpi = spi_master_get_devdata(master); + + return 0; +} + +static int hsSpiResume(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct bcmspi *pBcmSpi = spi_master_get_devdata(master); + + return 0; +} +#else +#define hsSpiSuspend NULL +#define hsSpiResume NULL +#endif + +static struct platform_device bcm_hsspi_device = { + .name = "bcmhs_spi", + .id = HS_SPI_BUS_NUM, +}; + +static struct platform_driver bcm_hsspi_driver = { + .driver = + { + .name = "bcmhs_spi", + .owner = THIS_MODULE, + }, + .suspend = hsSpiSuspend, + .resume = hsSpiResume, + .remove = __exit_p(hsSpiRemove), +}; + +int __init hsSpiModInit( void ) +{ + platform_device_register(&bcm_hsspi_device); + return platform_driver_probe(&bcm_hsspi_driver, hsSpiProbe); + +} +subsys_initcall(hsSpiModInit); +#endif + +#endif /* HS_SPI */ + diff --git a/shared/opensource/spi/bcmLegSpi.c b/shared/opensource/spi/bcmLegSpi.c new file mode 100755 index 0000000..6d1a391 --- /dev/null +++ b/shared/opensource/spi/bcmLegSpi.c @@ -0,0 +1,774 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifdef _CFE_ +#include "lib_types.h" +#include "lib_printf.h" +#include "lib_string.h" +#include "bcm_map.h" +#define printk printf +#else +#include <linux/autoconf.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/spi/spi.h> + +#include <bcm_map_part.h> +#include <bcm_intr.h> +#endif + +/* if SPI is defined then the legacy SPI controller is available, otherwise do not compile this code */ +#ifdef SPI + +#include "bcmSpiRes.h" +#include "bcmSpi.h" + +int BcmLegSpiRead(unsigned char * msg_buf, int prependcnt, int nbytes, int devId, int freqHz); +int BcmLegSpiWrite(unsigned char * msg_buf, int nbytes, int devId, int freqHz); + +#ifndef _CFE_ +//#define LEG_SPI_USE_INTERRUPTS /* define this to use interrupts instead of polling */ +static struct bcmspi BcmLegSpi = { SPIN_LOCK_UNLOCKED, + "bcmLegSpiDev", + }; +#endif + +/* following are the frequency tables for the SPI controllers + they are ordered by frequency in descending order with column + 2 represetning the register value */ +#define LEG_SPI_FREQ_TABLE_SIZE 7 +int legSpiClockFreq[LEG_SPI_FREQ_TABLE_SIZE][2] = { + { 20000000, 0}, + { 12500000, 6}, + { 6250000, 5}, + { 3125000, 4}, + { 1563000, 3}, + { 781000, 2}, + { 391000, 1} }; + +static int legSpiRead( unsigned char *pRxBuf, int prependcnt, int nbytes, int devId ) +{ + int i; + + SPI->spiMsgCtl = (HALF_DUPLEX_R << SPI_MSG_TYPE_SHIFT) | (nbytes << SPI_BYTE_CNT_SHIFT); + + for (i = 0; i < prependcnt; i++) + { + SPI->spiMsgData[i] = pRxBuf[i]; + } + + SPI->spiCmd = (SPI_CMD_START_IMMEDIATE << SPI_CMD_COMMAND_SHIFT | + devId << SPI_CMD_DEVICE_ID_SHIFT | + prependcnt << SPI_CMD_PREPEND_BYTE_CNT_SHIFT | + 0 << SPI_CMD_ONE_BYTE_SHIFT); + + return SPI_STATUS_OK; + +} + +static int legSpiWriteFull( unsigned char *pTxBuf, int nbytes, int devId, int opcode ) +{ + int i; + + if ( opcode == BCM_SPI_FULL ) + { + SPI->spiMsgCtl = (FULL_DUPLEX_RW << SPI_MSG_TYPE_SHIFT) | (nbytes << SPI_BYTE_CNT_SHIFT); + } + else + { + SPI->spiMsgCtl = (HALF_DUPLEX_W << SPI_MSG_TYPE_SHIFT) | (nbytes << SPI_BYTE_CNT_SHIFT); + } + + for (i = 0; i < nbytes; i++) + { + SPI->spiMsgData[i] = pTxBuf[i]; + } + + SPI->spiCmd = (SPI_CMD_START_IMMEDIATE << SPI_CMD_COMMAND_SHIFT | + devId << SPI_CMD_DEVICE_ID_SHIFT | + 0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT | + 0 << SPI_CMD_ONE_BYTE_SHIFT); + + return SPI_STATUS_OK; + +} + + +static int legSpiTransEnd( unsigned char *rxBuf, int nbytes ) +{ + int i; + if ( NULL != rxBuf ) + { + for (i = 0; i < nbytes; i++) + { + rxBuf[i] = SPI->spiRxDataFifo[i]; + } + } + + return SPI_STATUS_OK; + +} + +static int legSpiTransPoll(void) +{ + while ( 1 ) + { + if ( SPI->spiIntStatus & SPI_INTR_CMD_DONE ) + { + break; + } + } + + return SPI_STATUS_OK; +} + +static void legSpiClearIntStatus(void) +{ + SPI->spiIntStatus = SPI_INTR_CLEAR_ALL; +} + +#ifdef LEG_SPI_USE_INTERRUPTS +static void legSpiEnableInt(bool bEnable) +{ + if ( bEnable ) + { + SPI->spiIntMask = SPI_INTR_CMD_DONE; + } + else + { + SPI->spiIntMask = 0; + } +} +#endif + +#ifndef _CFE_ +static int legSpiSetClock( int clockHz ) +{ + int i; + int clock = -1; + + for( i = 0; i < LEG_SPI_FREQ_TABLE_SIZE; i++ ) + { + /* look for the closest frequency that is less than the frequency passed in */ + if ( legSpiClockFreq[i][0] <= clockHz ) + { + clock = legSpiClockFreq[i][1]; + break; + } + } + /* if no clock was found set to default */ + if ( -1 == clock ) + { + clock = LEG_SPI_CLOCK_DEF; + } + SPI->spiClkCfg = (SPI->spiClkCfg & ~SPI_CLK_MASK) | clock; + + return SPI_STATUS_OK; +} +#endif + +/* these interfaces are availble for the CFE and spi flash driver only + all modules must use the linux kernel framework + if this is called by a module and interrupts are being used there will + be a problem */ +int BcmLegSpiRead( unsigned char *msg_buf, int prependcnt, int nbytes, int devId, int freqHz ) +{ +#ifndef _CFE_ + struct bcmspi *pBcmSpi = &BcmLegSpi; + + if ( pBcmSpi->irq ) + { + printk("BcmLegSpiRead error - SPI Interrupts are enabled\n"); + return( SPI_STATUS_ERR ); + } + + spin_lock(&pBcmSpi->lock); + legSpiSetClock(freqHz); +#endif + legSpiClearIntStatus(); + legSpiRead(msg_buf, prependcnt, nbytes, devId); + legSpiTransPoll(); + legSpiTransEnd(msg_buf, nbytes); + legSpiClearIntStatus(); +#ifndef _CFE_ + spin_unlock(&pBcmSpi->lock); +#endif + + return( SPI_STATUS_OK ); +} + +int BcmLegSpiWrite( unsigned char *msg_buf, int nbytes, int devId, int freqHz ) +{ +#ifndef _CFE_ + struct bcmspi *pBcmSpi = &BcmLegSpi; + + if ( pBcmSpi->irq ) + { + printk("BcmLegSpiWrite error - SPI Interrupts are enabled\n"); + return( SPI_STATUS_ERR ); + } + + spin_lock(&pBcmSpi->lock); + legSpiSetClock(freqHz); +#endif + legSpiClearIntStatus(); + legSpiWriteFull(msg_buf, nbytes, devId, BCM_SPI_WRITE); + legSpiTransPoll(); + legSpiTransEnd(msg_buf, nbytes); + legSpiClearIntStatus(); +#ifndef _CFE_ + spin_unlock(&pBcmSpi->lock); +#endif + + return( SPI_STATUS_OK ); +} + + +#ifndef _CFE_ +static void legSpiNextMessage(struct bcmspi *pBcmSpi); + +static void legSpiMsgDone(struct bcmspi *pBcmSpi, struct spi_message *msg, int status) +{ + list_del(&msg->queue); + msg->status = status; + + spin_unlock(&pBcmSpi->lock); + msg->complete(msg->context); + spin_lock(&pBcmSpi->lock); + + pBcmSpi->curTrans = NULL; + + /* continue if needed */ + if (list_empty(&pBcmSpi->queue) || pBcmSpi->stopping) + { + // disable controler ... + } + else + { + legSpiNextMessage(pBcmSpi); + } +} + +#ifdef LEG_SPI_USE_INTERRUPTS +static void legSpiIntXfer(struct bcmspi *pBcmSpi, struct spi_message *msg) +{ + struct spi_transfer *xfer; + struct spi_transfer *nextXfer; + int length; + int prependCnt; + char *pTxBuf; + char *pRxBuf; + int opCode; + + xfer = pBcmSpi->curTrans; + if ( NULL == xfer) + { + xfer = list_entry(msg->transfers.next, struct spi_transfer, transfer_list); + } + else + { + xfer = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list); + } + pBcmSpi->curTrans = xfer; + + length = xfer->len; + prependCnt = 0; + pRxBuf = xfer->rx_buf; + pTxBuf = (unsigned char *)xfer->tx_buf; + + if ( (NULL != pRxBuf) && (NULL != pTxBuf) ) + { + opCode = BCM_SPI_FULL; + } + else if ( NULL != pRxBuf ) + { + opCode = BCM_SPI_READ; + } + else + { + opCode = BCM_SPI_WRITE; + } + + if ( msg->state ) + { + /* this controller does not support keeping the chip select active for all transfers + non NULL state indicates that we need to combine the transfers */ + nextXfer = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list); + prependCnt = length; + length = nextXfer->len; + pRxBuf = nextXfer->rx_buf; + opCode = BCM_SPI_READ; + pBcmSpi->curTrans = nextXfer; + } + + legSpiSetClock(xfer->speed_hz); + + legSpiClearIntStatus(); + legSpiEnableInt(TRUE); + if ( BCM_SPI_READ == opCode ) + { + legSpiRead(pTxBuf, prependCnt, length, msg->spi->chip_select); + } + else + { + legSpiWriteFull(pTxBuf, length, msg->spi->chip_select, opCode); + } + + return; + +} +#endif + +static void legSpiPollXfer(struct bcmspi *pBcmSpi, struct spi_message *msg) +{ + struct spi_transfer *xfer; + struct spi_transfer *nextXfer; + int length; + int prependCnt; + char *pTxBuf; + char *pRxBuf; + int opCode; + + list_for_each_entry(xfer, &msg->transfers, transfer_list) + { + pBcmSpi->curTrans = xfer; + length = xfer->len; + prependCnt = 0; + pRxBuf = xfer->rx_buf; + pTxBuf = (unsigned char *)xfer->tx_buf; + + if ( (NULL != pRxBuf) && (NULL != pTxBuf) ) + { + opCode = BCM_SPI_FULL; + } + else if ( NULL != pRxBuf ) + { + opCode = BCM_SPI_READ; + } + else + { + opCode = BCM_SPI_WRITE; + } + + if ( msg->state ) + { + /* this controller does not support keeping the chip select active for all transfers + non NULL state indicates that we need to combine the transfers */ + nextXfer = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list); + prependCnt = length; + length = nextXfer->len; + pRxBuf = nextXfer->rx_buf; + opCode = BCM_SPI_READ; + xfer = nextXfer; + } + + legSpiSetClock(xfer->speed_hz); + + legSpiClearIntStatus(); + if ( BCM_SPI_READ == opCode ) + { + legSpiRead(pTxBuf, prependCnt, length, msg->spi->chip_select); + } + else + { + legSpiWriteFull(pTxBuf, length, msg->spi->chip_select, opCode); + } + + legSpiTransPoll(); + legSpiTransEnd(pRxBuf, length); + legSpiClearIntStatus(); + + if (xfer->delay_usecs) + { + udelay(xfer->delay_usecs); + } + + msg->actual_length += length; + } + + legSpiMsgDone(pBcmSpi, msg, SPI_STATUS_OK); + +} + + +static void legSpiNextXfer(struct bcmspi *pBcmSpi, struct spi_message *msg) +{ +#ifdef LEG_SPI_USE_INTERRUPTS + if (pBcmSpi->irq) + legSpiIntXfer(pBcmSpi, msg); + else +#endif + legSpiPollXfer(pBcmSpi, msg); + +} + + +static void legSpiNextMessage(struct bcmspi *pBcmSpi) +{ + struct spi_message *msg; + + BUG_ON(pBcmSpi->curTrans); + + msg = list_entry(pBcmSpi->queue.next, struct spi_message, queue); + + /* there will always be one transfer in a given message */ + legSpiNextXfer(pBcmSpi, msg); + +} + + +static int legSpiSetup(struct spi_device *spi) +{ + struct bcmspi *pBcmSpi; + + pBcmSpi = spi_master_get_devdata(spi->master); + + if (pBcmSpi->stopping) + return -ESHUTDOWN; + + /* there is nothing to setup */ + + return 0; +} + + +int legSpiTransfer(struct spi_device *spi, struct spi_message *msg) +{ + struct bcmspi *pBcmSpi = &BcmLegSpi; + struct spi_transfer *xfer; + struct spi_transfer *nextXfer; + int xferCnt; + int bCsChange; + int xferLen; + + if (unlikely(list_empty(&msg->transfers))) + return -EINVAL; + + if (pBcmSpi->stopping) + return -ESHUTDOWN; + + /* make sure a completion callback is set */ + if ( NULL == msg->complete ) + { + return -EINVAL; + } + + xferCnt = 0; + bCsChange = 0; + xferLen = 0; + list_for_each_entry(xfer, &msg->transfers, transfer_list) + { + /* check transfer parameters */ + if (!(xfer->tx_buf || xfer->rx_buf)) + { + return -EINVAL; + } + + /* check the clock setting - if it is 0 then set to max clock of the device */ + if ( 0 == xfer->speed_hz ) + { + if ( 0 == spi->max_speed_hz ) + { + return -EINVAL; + } + xfer->speed_hz = spi->max_speed_hz; + } + + xferCnt++; + xferLen += xfer->len; + bCsChange |= xfer->cs_change; + + if ( xfer->len > (sizeof(SPI->spiMsgData) & ~0x3) ) + { + return -EINVAL; + } + } + + /* this controller does not support keeping the chip select active between + transfers. If a message is detected with a write transfer followed by a + read transfer and cs_change is set to 0 then the two transfers need to be + combined. The message state is used to indicate that the transfers + need to be combined */ + msg->state = NULL; + if ( (2 == xferCnt) && (0 == bCsChange) ) + { + xfer = list_entry(msg->transfers.next, struct spi_transfer, transfer_list); + if ( (NULL != xfer->tx_buf) && (NULL == xfer->rx_buf)) + { + nextXfer = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);; + if ( (NULL == nextXfer->tx_buf) && (NULL != nextXfer->rx_buf)) + { + msg->state = (void *)1; + } + } + } + + msg->status = -EINPROGRESS; + msg->actual_length = 0; + +#ifdef LEG_SPI_USE_INTERRUPTS + /* disable interrupts for the SPI controller + using spin_lock_irqsave would disable all interrupts */ + if ( pBcmSpi->irq ) + legSpiEnableInt(FALSE); +#endif + spin_lock(&pBcmSpi->lock); + + list_add_tail(&msg->queue, &pBcmSpi->queue); + if (NULL == pBcmSpi->curTrans) + { + legSpiNextMessage(pBcmSpi); + } + + spin_unlock(&pBcmSpi->lock); +#ifdef LEG_SPI_USE_INTERRUPTS + if ( pBcmSpi->irq ) + legSpiEnableInt(TRUE); +#endif + + return 0; +} + + +#ifdef LEG_SPI_USE_INTERRUPTS +static irqreturn_t legSpiIntHandler(int irq, void *dev_id) +{ + struct bcmspi *pBcmSpi = dev_id; + struct spi_message *msg; + struct spi_transfer *xfer; + + if ( 0 == SPI->spiMaskIntStatus ) + { + return ( IRQ_NONE ); + } + + legSpiClearIntStatus(); + legSpiEnableInt(FALSE); + + spin_lock(&pBcmSpi->lock); + if ( NULL == pBcmSpi->curTrans ) + { + spin_unlock(&pBcmSpi->lock); + return IRQ_HANDLED; + } + + xfer = pBcmSpi->curTrans; + msg = list_entry(pBcmSpi->queue.next, struct spi_message, queue); + + legSpiTransEnd(xfer->rx_buf, xfer->len); + + /* xfer can specify a delay before the next transfer is started + this is only used for polling mode */ + + /* check to see if this is the last transfer in the message */ + if (msg->transfers.prev == &xfer->transfer_list) + { + /* report completed message */ + legSpiMsgDone(pBcmSpi, msg, SPI_STATUS_OK); + } + else + { + /* Submit the next transfer */ + legSpiNextXfer(pBcmSpi, msg); + } + + spin_unlock(&pBcmSpi->lock); + + return IRQ_HANDLED; + +} + +int __init legSpiIntrInit( void ) +{ + int ret = 0; + struct bcmspi *pBcmSpi = &BcmLegSpi; + + legSpiEnableInt(FALSE); + ret = request_irq(INTERRUPT_ID_SPI, legSpiIntHandler, (IRQF_DISABLED | IRQF_SAMPLE_RANDOM | IRQF_SHARED), pBcmSpi->devName, pBcmSpi); + + spin_lock(&pBcmSpi->lock); + pBcmSpi->irq = INTERRUPT_ID_SPI; + spin_unlock(&pBcmSpi->lock); + + BcmHalInterruptEnable(pBcmSpi->irq); + + return( 0 ); + +} +/* we cannot initialize interrupts early + The flash module is intialized before an interrupt handler can be installed + and before the Linux framework can be used. This means it needs direct access + to the controller initially. This conflicts with the interrupt handling so we + need to wait for all modules to intialize */ +late_initcall(legSpiIntrInit); +#endif + +static void legSpiCleanup(struct spi_device *spi) +{ + /* would free spi_controller memory here if any was allocated */ + +} + +static int __init legSpiProbe(struct platform_device *pdev) +{ + int ret; + struct spi_master *master; + struct bcmspi *pBcmSpi; + + ret = -ENOMEM; + master = spi_alloc_master(&pdev->dev, 0); + if (!master) + goto out_free; + + master->bus_num = pdev->id; + master->num_chipselect = 8; + master->setup = legSpiSetup; + master->transfer = legSpiTransfer; + master->cleanup = legSpiCleanup; + platform_set_drvdata(pdev, master); + + spi_master_set_devdata(master, (void *)&BcmLegSpi); + pBcmSpi = spi_master_get_devdata(master); + + INIT_LIST_HEAD(&pBcmSpi->queue); + + pBcmSpi->pdev = pdev; + pBcmSpi->bus_num = LEG_SPI_BUS_NUM; + pBcmSpi->num_chipselect = 8; + pBcmSpi->curTrans = NULL; + + /* make sure irq is 0 here + since this is used to identify when interrupts are enabled + the IRQ is initialized in legSpiIntrInit */ + pBcmSpi->irq = 0; + + /* Initialize the hardware */ + + /* register and we are done */ + ret = spi_register_master(master); + if (ret) + goto out_free; + + return 0; + +out_free: + spi_master_put(master); + + return ret; +} + + +static int __exit legSpiRemove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct bcmspi *pBcmSpi = spi_master_get_devdata(master); + struct spi_message *msg; + + /* reset the hardware and block queue progress */ +#ifdef LEG_SPI_USE_INTERRUPTS + legSpiEnableInt(FALSE); +#endif + spin_lock(&pBcmSpi->lock); + pBcmSpi->stopping = 1; + + /* HW shutdown */ + + spin_unlock(&pBcmSpi->lock); + + /* Terminate remaining queued transfers */ + list_for_each_entry(msg, &pBcmSpi->queue, queue) + { + msg->status = -ESHUTDOWN; + msg->complete(msg->context); + } + +#ifdef LEG_SPI_USE_INTERRUPTS + if ( pBcmSpi->irq ) + { + free_irq(pBcmSpi->irq, master); + } +#endif + spi_unregister_master(master); + + return 0; +} + +//#ifdef CONFIG_PM +#if 0 +static int legSpiSuspend(struct platform_device *pdev, pm_message_t mesg) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct bcmspi *pBcmSpi = spi_master_get_devdata(master); + + return 0; +} + +static int legSpiResume(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct bcmspi *pBcmSpi = spi_master_get_devdata(master); + + return 0; +} +#else +#define legSpiSuspend NULL +#define legSpiResume NULL +#endif + + +static struct platform_device bcm_legacyspi_device = { + .name = "bcmleg_spi", + .id = LEG_SPI_BUS_NUM, +}; + +static struct platform_driver bcm_legspi_driver = { + .driver = + { + .name = "bcmleg_spi", + .owner = THIS_MODULE, + }, + .suspend = legSpiSuspend, + .resume = legSpiResume, + .remove = __exit_p(legSpiRemove), +}; + + +int __init legSpiModInit( void ) +{ + platform_device_register(&bcm_legacyspi_device); + return platform_driver_probe(&bcm_legspi_driver, legSpiProbe); + +} +subsys_initcall(legSpiModInit); +#endif + +#endif /* SPI */ + diff --git a/shared/opensource/spi/bcmSpiRes.c b/shared/opensource/spi/bcmSpiRes.c new file mode 100755 index 0000000..ed16575 --- /dev/null +++ b/shared/opensource/spi/bcmSpiRes.c @@ -0,0 +1,660 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifdef _CFE_ +#include "lib_types.h" +#include "lib_printf.h" +#include "lib_string.h" +#include "bcm_map.h" +#define printk printf +#else +#include <linux/version.h> +#include <linux/autoconf.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) +#include <linux/semaphore.h> +#endif +#include <linux/spi/spi.h> +#include <linux/autoconf.h> + +#include <bcm_map_part.h> +#endif +#include "bcmSpiRes.h" + +extern int BcmLegSpiRead(unsigned char * msg_buf, int prependcnt, int nbytes, int devId, int freqHz); +extern int BcmLegSpiWrite(unsigned char * msg_buf, int nbytes, int devId, int freqHz); +extern int BcmHsSpiRead(unsigned char * msg_buf, int prependcnt, int nbytes, int devId, int freqHz); +extern int BcmHsSpiWrite(unsigned char * msg_buf, int nbytes, int devId, int freqHz); + +#ifndef _CFE_ +#ifdef SPI +/* the BCM legacy controller supports up to 8 devices */ +static struct spi_board_info bcmLegSpiDevInfo[8] = +{ + { + .modalias = "bcm_LegSpiDev0", + .chip_select = 0, + .max_speed_hz = 781000, + .bus_num = LEG_SPI_BUS_NUM, + .mode = SPI_MODE_3, + }, + { + .modalias = "bcm_LegSpiDev1", + .chip_select = 1, + .max_speed_hz = 781000, + .bus_num = LEG_SPI_BUS_NUM, + .mode = SPI_MODE_3, + }, + { + .modalias = "bcm_LegSpiDev2", + .chip_select = 2, + .max_speed_hz = 781000, + .bus_num = LEG_SPI_BUS_NUM, + .mode = SPI_MODE_3, + }, + { + .modalias = "bcm_LegSpiDev3", + .chip_select = 3, + .max_speed_hz = 781000, + .bus_num = LEG_SPI_BUS_NUM, + .mode = SPI_MODE_3, + }, + { + .modalias = "bcm_LegSpiDev4", + .chip_select = 4, + .max_speed_hz = 781000, + .bus_num = LEG_SPI_BUS_NUM, + .mode = SPI_MODE_3, + }, + { + .modalias = "bcm_LegSpiDev5", + .chip_select = 5, + .max_speed_hz = 781000, + .bus_num = LEG_SPI_BUS_NUM, + .mode = SPI_MODE_3, + }, + { + .modalias = "bcm_LegSpiDev6", + .chip_select = 6, + .max_speed_hz = 781000, + .bus_num = LEG_SPI_BUS_NUM, + .mode = SPI_MODE_3, + }, + { + .modalias = "bcm_LegSpiDev7", + .chip_select = 7, + .max_speed_hz = 781000, + .bus_num = LEG_SPI_BUS_NUM, + .mode = SPI_MODE_3, + }, +}; + +static struct spi_driver bcmLegSpiDevDrv[8] = +{ + { + .driver = + { + .name = "bcm_LegSpiDev0", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_LegSpiDev1", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_LegSpiDev2", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_LegSpiDev3", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_LegSpiDev4", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_LegSpiDev5", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_LegSpiDev6", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_LegSpiDev7", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, +}; + +static struct spi_device * bcmLegSpiDevices[8]; +#endif + +#ifdef HS_SPI +/* the BCM HS controller supports up to 8 devices */ +static struct spi_board_info bcmHSSpiDevInfo[8] = +{ + { + .modalias = "bcm_HSSpiDev0", + .controller_data = (void *)SPI_CONTROLLER_STATE_DEFAULT, + .chip_select = 0, + .max_speed_hz = 781000, + .bus_num = HS_SPI_BUS_NUM, + .mode = SPI_MODE_DEFAULT, + }, + { + .modalias = "bcm_HSSpiDev1", + .controller_data = (void *)SPI_CONTROLLER_STATE_DEFAULT, + .chip_select = 1, + .max_speed_hz = 781000, + .bus_num = HS_SPI_BUS_NUM, + .mode = SPI_MODE_DEFAULT, + }, + { + .modalias = "bcm_HSSpiDev2", + .controller_data = (void *)SPI_CONTROLLER_STATE_DEFAULT, + .chip_select = 2, + .max_speed_hz = 781000, + .bus_num = HS_SPI_BUS_NUM, + .mode = SPI_MODE_DEFAULT, + }, + { + .modalias = "bcm_HSSpiDev3", + .controller_data = (void *)SPI_CONTROLLER_STATE_DEFAULT, + .chip_select = 3, + .max_speed_hz = 781000, + .bus_num = HS_SPI_BUS_NUM, + .mode = SPI_MODE_DEFAULT, + }, + { + .modalias = "bcm_HSSpiDev4", + .controller_data = (void *)SPI_CONTROLLER_STATE_DEFAULT, + .chip_select = 4, + .max_speed_hz = 781000, + .bus_num = HS_SPI_BUS_NUM, + .mode = SPI_MODE_DEFAULT, + }, + { + .modalias = "bcm_HSSpiDev5", + .controller_data = (void *)SPI_CONTROLLER_STATE_DEFAULT, + .chip_select = 5, + .max_speed_hz = 781000, + .bus_num = HS_SPI_BUS_NUM, + .mode = SPI_MODE_DEFAULT, + }, + { + .modalias = "bcm_HSSpiDev6", + .controller_data = (void *)SPI_CONTROLLER_STATE_DEFAULT, + .chip_select = 6, + .max_speed_hz = 781000, + .bus_num = HS_SPI_BUS_NUM, + .mode = SPI_MODE_DEFAULT, + }, + { + .modalias = "bcm_HSSpiDev7", + .controller_data = (void *)SPI_CONTROLLER_STATE_DEFAULT, + .chip_select = 7, + .max_speed_hz = 781000, + .bus_num = HS_SPI_BUS_NUM, + .mode = SPI_MODE_DEFAULT, + }, +}; + +static struct spi_driver bcmHSSpiDevDrv[8] = +{ + { + .driver = + { + .name = "bcm_HSSpiDev0", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_HSSpiDev1", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_HSSpiDev2", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_HSSpiDev3", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_HSSpiDev4", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_HSSpiDev5", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_HSSpiDev6", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, + { + .driver = + { + .name = "bcm_HSSpiDev7", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + }, +}; + +static struct spi_device * bcmHSSpiDevices[8]; +#endif + + +int BcmSpiReserveSlave2(int busNum, int slaveId, int maxFreq, int spiMode, int ctrlState) +{ + struct spi_master * pSpiMaster; + struct spi_driver * pSpiDriver; + + if ( slaveId > 7 ) + { + return SPI_STATUS_ERR; + } + + if ( LEG_SPI_BUS_NUM == busNum ) + { +#ifndef SPI + return( SPI_STATUS_ERR ); +#else + if ( NULL != bcmLegSpiDevices[slaveId] ) + { + printk(KERN_ERR "BcmSpiReserveSlave - slaveId %d, already registerd\n", slaveId); + return( SPI_STATUS_ERR ); + } + + bcmLegSpiDevInfo[slaveId].max_speed_hz = maxFreq; + bcmLegSpiDevInfo[slaveId].controller_data = (void *)ctrlState; + bcmLegSpiDevInfo[slaveId].mode = spiMode; + + pSpiMaster = spi_busnum_to_master( busNum ); + bcmLegSpiDevices[slaveId] = spi_new_device(pSpiMaster, &bcmLegSpiDevInfo[slaveId]); + pSpiDriver = &bcmLegSpiDevDrv[slaveId]; +#endif + } + else if ( HS_SPI_BUS_NUM == busNum ) + { +#ifndef HS_SPI + return( SPI_STATUS_ERR ); +#else + if ( NULL != bcmHSSpiDevices[slaveId] ) + { + printk(KERN_ERR "BcmSpiReserveSlave - slaveId %d, already registerd\n", slaveId); + return( SPI_STATUS_ERR ); + } + + bcmHSSpiDevInfo[slaveId].max_speed_hz = maxFreq; + bcmHSSpiDevInfo[slaveId].controller_data = (void *)ctrlState; + bcmHSSpiDevInfo[slaveId].mode = spiMode; + + pSpiMaster = spi_busnum_to_master( busNum ); + bcmHSSpiDevices[slaveId] = spi_new_device(pSpiMaster, &bcmHSSpiDevInfo[slaveId]); + pSpiDriver = &bcmHSSpiDevDrv[slaveId]; +#endif + } + else + return( SPI_STATUS_ERR ); + + /* register the SPI driver */ + spi_register_driver(pSpiDriver); + + return 0; + +} +EXPORT_SYMBOL(BcmSpiReserveSlave2); + +int BcmSpiReserveSlave(int busNum, int slaveId, int maxFreq) +{ + return( BcmSpiReserveSlave2(busNum, slaveId, maxFreq, SPI_MODE_DEFAULT, SPI_CONTROLLER_STATE_DEFAULT) ); +} +EXPORT_SYMBOL(BcmSpiReserveSlave); + +int BcmSpiReleaseSlave(int busNum, int slaveId) +{ + if ( slaveId > 7 ) + { + return SPI_STATUS_ERR; + } + + if ( LEG_SPI_BUS_NUM == busNum ) + { +#ifndef SPI + return( SPI_STATUS_ERR ); +#else + if ( NULL == bcmLegSpiDevices[slaveId] ) + { + printk(KERN_ERR "BcmSpiReleaseSlave - slaveId %d, already released\n", slaveId); + return( SPI_STATUS_ERR ); + } + + bcmLegSpiDevInfo[slaveId].max_speed_hz = 781000; + spi_unregister_driver(&bcmLegSpiDevDrv[slaveId]); + spi_unregister_device(bcmLegSpiDevices[slaveId]); + bcmLegSpiDevices[slaveId] = 0; +#endif + } + else if ( HS_SPI_BUS_NUM == busNum ) + { +#ifndef HS_SPI + return( SPI_STATUS_ERR ); +#else + if ( NULL == bcmHSSpiDevices[slaveId] ) + { + printk(KERN_ERR "BcmSpiReleaseSlave - slaveId %d, already released\n", slaveId); + return( SPI_STATUS_ERR ); + } + + bcmHSSpiDevInfo[slaveId].max_speed_hz = 781000; + spi_unregister_driver(&bcmHSSpiDevDrv[slaveId]); + spi_unregister_device(bcmHSSpiDevices[slaveId]); + bcmHSSpiDevices[slaveId] = 0; +#endif + } + else + return( SPI_STATUS_ERR ); + + return 0; + +} +EXPORT_SYMBOL(BcmSpiReleaseSlave); + + +int BcmSpiSyncTrans(unsigned char *txBuf, unsigned char *rxBuf, int prependcnt, int nbytes, int busNum, int slaveId) +{ + struct spi_message msg; + struct spi_transfer xfer[2]; + int status; + int maxLength; + struct spi_device *pSpiDevice; + + maxLength = BcmSpi_GetMaxRWSize(busNum); + if ( (nbytes > maxLength) || (prependcnt > maxLength) ) + { + printk(KERN_ERR "ERROR BcmSpiSyncTrans: invalid length len %d, pre %d, max %d\n", nbytes, prependcnt, maxLength); + return SPI_STATUS_ERR; + } + + if ( slaveId > 7 ) + { + printk(KERN_ERR "ERROR BcmSpiSyncTrans: invalid slave id %d\n", slaveId); + return SPI_STATUS_ERR; + } + + if ( LEG_SPI_BUS_NUM == busNum ) + { +#ifndef SPI + return( SPI_STATUS_ERR ); +#else + if ( NULL == bcmLegSpiDevices[slaveId] ) + { + printk(KERN_ERR "ERROR BcmSpiSyncTrans: device not registered\n"); + return SPI_STATUS_ERR; + } + pSpiDevice = bcmLegSpiDevices[slaveId]; +#endif + } + else if ( HS_SPI_BUS_NUM == busNum ) + { +#ifndef HS_SPI + return( SPI_STATUS_ERR ); +#else + if ( NULL == bcmHSSpiDevices[slaveId] ) + { + printk(KERN_ERR "ERROR BcmSpiSyncTrans: device not registered\n"); + return SPI_STATUS_ERR; + } + pSpiDevice = bcmHSSpiDevices[slaveId]; +#endif + } + else + return( SPI_STATUS_ERR ); + + spi_message_init(&msg); + memset(xfer, 0, (sizeof xfer)); + + if ( prependcnt ) + { + xfer[0].len = prependcnt; + xfer[0].speed_hz = pSpiDevice->max_speed_hz; + if ( txBuf ) + { + xfer[0].tx_buf = txBuf; + } + else + { + xfer[0].tx_buf = rxBuf; + } + spi_message_add_tail(&xfer[0], &msg); + } + + xfer[1].len = nbytes; + xfer[1].speed_hz = pSpiDevice->max_speed_hz; + xfer[1].rx_buf = rxBuf; + + /* for the controller to use the prepend count correctly the first operation must be a read and the second a write + make sure tx is NULL for second transaction */ + if ( 0 == prependcnt ) + { + xfer[1].tx_buf = txBuf; + } + spi_message_add_tail(&xfer[1], &msg); + + status = spi_sync(pSpiDevice, &msg); + if (status >= 0) + { + status = SPI_STATUS_OK; + } + else + { + status = SPI_STATUS_ERR; + } + + return( status ); + +} +EXPORT_SYMBOL(BcmSpiSyncTrans); +#endif + +int BcmSpi_SetFlashCtrl( int opCode, int addrBytes, int dummyBytes, int busNum, int devId ) +{ + if ( HS_SPI_BUS_NUM == busNum ) + { +#ifndef HS_SPI + return SPI_STATUS_ERR; +#else + int clock; + + clock = HS_SPI_PLL_FREQ/HS_SPI_CLOCK_DEF; + if (HS_SPI_PLL_FREQ%HS_SPI_CLOCK_DEF) + clock++; + + clock = 2048/clock; + if (2048%(clock)) + clock++; + + HS_SPI_PROFILES[0].clk_ctrl = 1<<HS_SPI_ACCUM_RST_ON_LOOP | 0<<HS_SPI_SPI_CLK_2X_SEL | clock<<HS_SPI_FREQ_CTRL_WORD; + HS_SPI->hs_spiFlashCtrl = devId<<HS_SPI_FCTRL_SS_NUM | 0<<HS_SPI_FCTRL_PROFILE_NUM | dummyBytes<<HS_SPI_FCTRL_DUMMY_BYTES | + addrBytes<<HS_SPI_FCTRL_ADDR_BYTES | opCode<<HS_SPI_FCTRL_READ_OPCODE; +#endif + } + else if ( LEG_SPI_BUS_NUM == busNum ) + { +#ifndef SPI + return SPI_STATUS_ERR; +#endif + } + else + return SPI_STATUS_ERR; + + return SPI_STATUS_OK; + +} + + +int BcmSpi_GetMaxRWSize( int busNum ) +{ + int maxRWSize = 0; + + if ( HS_SPI_BUS_NUM == busNum ) + { +#ifdef HS_SPI + maxRWSize = HS_SPI_BUFFER_LEN; +#endif + } + else if ( LEG_SPI_BUS_NUM == busNum ) + { +#ifdef SPI + maxRWSize = sizeof(SPI->spiMsgData); +#endif + } + + maxRWSize &= ~0x3; + + return(maxRWSize); + +} + + +/* The interface bcmSpi_Read and bcmSpi_Write provide direct access to the SPI controller. + these interfaces should only be called by CFE and early spi flash code */ +int BcmSpi_Read( unsigned char *msg_buf, int prependcnt, int nbytes, int busNum, int devId, int freqHz ) +{ + if ( LEG_SPI_BUS_NUM == busNum ) + { +#ifndef SPI + return SPI_STATUS_ERR; +#else + return BcmLegSpiRead( msg_buf, prependcnt, nbytes, devId, freqHz ); +#endif + } + else if ( HS_SPI_BUS_NUM == busNum ) + { +#ifndef HS_SPI + return SPI_STATUS_ERR; +#else + return BcmHsSpiRead( msg_buf, prependcnt, nbytes, devId, freqHz ); +#endif + } + else + { + return SPI_STATUS_ERR; + } + +} + +int BcmSpi_Write( unsigned char *msg_buf, int nbytes, int busNum, int devId, int freqHz ) +{ + if ( LEG_SPI_BUS_NUM == busNum ) + { +#ifndef SPI + return SPI_STATUS_ERR; +#else + return BcmLegSpiWrite( msg_buf, nbytes, devId, freqHz ); +#endif + } + else if ( HS_SPI_BUS_NUM == busNum ) + { +#ifndef HS_SPI + return SPI_STATUS_ERR; +#else + return BcmHsSpiWrite( msg_buf, nbytes, devId, freqHz ); +#endif + } + else + { + return SPI_STATUS_ERR; + } +} + +#ifndef _CFE_ +EXPORT_SYMBOL(BcmSpi_SetFlashCtrl); +EXPORT_SYMBOL(BcmSpi_GetMaxRWSize); +#endif + |