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| author | Jo-Philipp Wich <jo@mein.io> | 2016-11-23 16:21:50 +0100 |
|---|---|---|
| committer | Zoltan HERPAI <wigyori@uid0.hu> | 2016-11-23 16:21:50 +0100 |
| commit | 9e2f8fa1e5df297c172ce1472eb076c3c0b27cad (patch) | |
| tree | d87851afa0c09b71ff6685b56fc49837f6815517 /package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch | |
| parent | ce116bc6f997d8d6e6b976cacce5d4c60d705fc6 (diff) | |
| download | master-187ad058-9e2f8fa1e5df297c172ce1472eb076c3c0b27cad.tar.gz master-187ad058-9e2f8fa1e5df297c172ce1472eb076c3c0b27cad.tar.bz2 master-187ad058-9e2f8fa1e5df297c172ce1472eb076c3c0b27cad.zip | |
uboot-sunxi: fix default config for OLIMEX A13 SOM (FS#239)
The current uboot default config for the A13 SOM erroneously enables support
for the AXP209 power regulator IC which is not present on the board.
This superfluous support module sets an incorrect initial clock frequency and
confuses the kernel, ultimately leading to a boot failure later on.
Properly disable the PMIC support and enable the EHCI support by translating
the deprecated SYS_EXTRA_OPTIONS values into proper SUNXI_NO_PMIC and
USB_EHCI_HCD symbols respectively.
Also rename 002-add-olimex-a13-som.diff to 002-add-olimex-a13-som.patch and
refresh the remaining patches of the series while we're at it.
Reported-by: Mario Fischer <mario-fischer@web.de>
Signed-off-by: Jo-Philipp Wich <jo@mein.io>
Diffstat (limited to 'package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch')
| -rw-r--r-- | package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch index f782994c14..a402feb3cd 100644 --- a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch +++ b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch @@ -12,11 +12,9 @@ More specifically, the following settings are now used: * up to 1152MHz: mul=3, div=2 (unchanged) * above 1152MHz: mul=4, div=2 (was: mul=2, div=1) -diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c -index cfb32b4..2986539 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c -@@ -102,11 +102,12 @@ void clock_set_pll1(unsigned int clk) +@@ -122,11 +122,12 @@ void clock_set_pll1(unsigned int clk) struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int p = 0; @@ -32,6 +30,3 @@ index cfb32b4..2986539 100644 } else if (clk > 768000000) { k = 3; m = 2; --- -cgit v0.10.2 - |