diff options
Diffstat (limited to 'package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch')
| -rw-r--r-- | package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch index f782994c14..a402feb3cd 100644 --- a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch +++ b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch @@ -12,11 +12,9 @@ More specifically, the following settings are now used: * up to 1152MHz: mul=3, div=2 (unchanged) * above 1152MHz: mul=4, div=2 (was: mul=2, div=1) -diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c -index cfb32b4..2986539 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c -@@ -102,11 +102,12 @@ void clock_set_pll1(unsigned int clk) +@@ -122,11 +122,12 @@ void clock_set_pll1(unsigned int clk) struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int p = 0; @@ -32,6 +30,3 @@ index cfb32b4..2986539 100644 } else if (clk > 768000000) { k = 3; m = 2; --- -cgit v0.10.2 - |