blob: 7d2149e2cbaf7c758f78911721f781c1ad7a4886 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
PROJ=spdif
SRCS=$(wildcard *.vhd *.v *.qsf *.qpf )
S1=${SRCS:pll100.vhd=}
S2=${S1:pll200.vhd=}
TIDY_SRC=${S2}
SOF=output_files/${PROJ}.sof
POF=output_files/${PROJ}.pof
default: load_sof.stamp sim.stamp
sta.stamp:asm.stamp
tools/wrap quartus_sta ${PROJ} -c ${PROJ}
touch $@
asm.stamp:fit.stamp
tools/wrap quartus_asm --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ}
touch $@
${POF} ${SOF}:asm.stamp
fit.stamp: ans.stamp
tools/wrap quartus_fit --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ}
touch $@
ans.stamp: ${SRCS}
tools/wrap quartus_map --read_settings_files=on --write_settings_files=off ${PROJ} -c ${PROJ}
touch $@
sim.stamp: fit.stamp
tools/wrap quartus_eda ${PROJ} --simulation --tool=modelsim --format=verilog
load_sof.stamp: ${SOF}
tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"
flash: ${POF}
tools/wrap quartus_pgm -m AS -o "p;${POF}"
quartus:
tools/wrap quartus ${PROJ}.qpf
jtagd:
sudo killall jtagd || true
sudo tools/wrap jtagd
clean:
/bin/rm -rf ${BSP_DIR} db incremental_db src/obj simulation output_files
/bin/rm -f ${SOPC_FILE} src/Makefile elf.flash sof.flash *.stamp ${SOF} ${ELF} *.rpt *.html *.summary *.pin *.jdi *.qws *.pof *.smsg
/bin/rm -f src/${PROJ}.objdump src/${PROJ}.map
/bin/rm -f sopc_builder_log.txt src/*~ SDIF/*~
/bin/rm -f sim.stamp *.orig
tidy:
for i in ${TIDY_SRC}; do tools/vhdl-pretty < $$i > $$i.pp && mv -f $$i $$i.orig && mv $$i.pp $$i ; done
|
