PROJ=spdif

SRCS=$(wildcard *.vhd *.v *.qsf *.qpf )
S1=${SRCS:pll100.vhd=}
S2=${S1:pll200.vhd=}
TIDY_SRC=${S2}

SOF=output_files/${PROJ}.sof
POF=output_files/${PROJ}.pof

default: load_sof.stamp sim.stamp



sta.stamp:asm.stamp
	tools/wrap quartus_sta ${PROJ} -c ${PROJ}
	touch $@

asm.stamp:fit.stamp
	tools/wrap quartus_asm --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ}
	touch $@

${POF} ${SOF}:asm.stamp

fit.stamp: ans.stamp
	tools/wrap quartus_fit --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ}
	touch $@

ans.stamp: ${SRCS}
	tools/wrap quartus_map --read_settings_files=on --write_settings_files=off ${PROJ} -c ${PROJ}
	touch $@

sim.stamp: fit.stamp
	tools/wrap quartus_eda ${PROJ} --simulation --tool=modelsim --format=verilog


load_sof.stamp: ${SOF}
	tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"

flash: ${POF}
	tools/wrap quartus_pgm -m AS -o "p;${POF}"

quartus:
	tools/wrap quartus ${PROJ}.qpf

jtagd:
	sudo killall jtagd || true
	sudo tools/wrap jtagd

clean:
	/bin/rm -rf ${BSP_DIR} db incremental_db src/obj simulation output_files
	/bin/rm -f ${SOPC_FILE} src/Makefile elf.flash sof.flash *.stamp ${SOF} ${ELF} *.rpt *.html *.summary *.pin *.jdi *.qws *.pof *.smsg
	/bin/rm -f src/${PROJ}.objdump src/${PROJ}.map 
	/bin/rm -f sopc_builder_log.txt src/*~ SDIF/*~
	/bin/rm -f sim.stamp  *.orig
	
	

tidy:
	for i in ${TIDY_SRC}; do tools/vhdl-pretty < $$i > $$i.pp && mv -f $$i $$i.orig && mv $$i.pp $$i ; done