1 files changed, 58 insertions, 103 deletions

diff --git a/spdif.vhd b/spdif.vhd
index 5ee9a3c..cf78f55 100644
--- a/spdif.vhd
+++ b/spdif.vhd
@@ -12,29 +12,27 @@ entity spdif is
         n_leds     : out std_logic_vector(2 downto 0);
         n_mute_out : out std_logic;
         n_stby_out : out std_logic;
+        dbg : out std_logic_vector(7 downto 0)
 
-        dbg1 : out std_logic;
-        dbg2 : out std_logic;
-        dbg3 : out std_logic;
-        dbg4 : out std_logic;
-        dbg5 : out std_logic;
-        dbg6 : out std_logic;
-        dbg7 : out std_logic;
-        dbg8 : out std_logic
         );
 end spdif;
 
 
 architecture rtl of spdif is
-    component ccd is
-        port
-            (
-                n_reset : in  std_logic;
-                clk     : in  std_logic;
-                d       : in  std_logic;
-                q       : out std_logic
-                );
-    end component;
+
+component detector is
+    port (
+	clk_in	:	in std_logic;
+	spdif_in:	in std_logic;
+        n_reset   : in std_logic;
+	divisor : in integer;
+        silent_thresh : in integer;
+	valid_divisor: in integer;
+        valid_thresh : in integer;
+	mute : out std_logic;
+	dbg:out std_logic_vector(7 downto 0)
+        );
+end component;
 
     component pll100 is
         port (
@@ -53,63 +51,17 @@ architecture rtl of spdif is
             );
     end component;
 
-    component counter is
-        port
-            (
-                divisor : in  integer;
-                clk     : in  std_logic;
-                n_reset : in  std_logic;
-                clk_out : out std_logic
-                );
-    end component;
-
-    component spdif_decoder is
-        port
-            (
-                n_reset   : in  std_logic;
-                clk       : in  std_logic;
-                spdif     : in  std_logic;
-                bmc_ready : out std_logic;
-                bmc_e     : out std_logic;
-                bmc_l     : out std_logic;
-                bmc_d     : out std_logic;
-                sof       : out std_logic;
-                bna       : out std_logic;
-                d         : out std_logic_vector(26 downto 0);
-                ready     : out std_logic
-                );
-    end component;
-
-
-    component silence_detector is
-        port
-            (
-                max_ticks : in  integer;
-                clk       : in  std_logic;
-                d         : in  std_logic_vector(23 downto 0);
-                n_reset   : in  std_logic;
-                silent    : out std_logic
-                );
-    end component;
-
-
-
     signal n_reset :
         std_logic;
     signal clk_200mhz :
         std_logic;
 --    signal clk_100mhz :
 --        std_logic;
-    signal spdif_clkd1 :
-        std_logic;
-    signal clk1 :
-        std_logic;
-    signal d1     : std_logic_vector(26 downto 0);
-    signal bna1   : std_logic;
-    signal sof1   : std_logic;
-    signal ready1 : std_logic;
 
     signal mute1 : std_logic;
+    signal mute2 : std_logic;
+    signal mute3 : std_logic;
+    signal mute : std_logic;
 
 begin
     n_reset <= n_rst_in;
@@ -122,55 +74,58 @@ begin
             c0     => clk_200mhz
             );
 
-    div1 : counter port map (
-        n_reset => n_reset,
-        clk     => clk_200mhz,
-        divisor => 6,
-        clk_out => clk1
+    -- 96000Hz
+    det1 : detector port map (
+        n_reset   => n_reset,
+        clk_in       => clk_200mhz,
+        spdif_in     => spdif_in,
+
+	divisor		=> 2,   -- divisor to turn clk_in into 6x spdif base frequency
+	silent_thresh	=> 96000, -- number of samples of same sample before we declare silence
+	valid_divisor   => 100000000, --  (clk_in/(divisor*valid_divisor)) is period for validity checks
+	valid_thresh    => 90000, -- number of valid samples that must be received in validity period to declare it's all ok.
+
+	mute => mute1
         );
 
-    b1 :
-        ccd port map (
-            n_reset => n_reset,
-            clk     => clk1,
-            d       => spdif_in,
-            q       => spdif_clkd1
-            );
 
-    dec1 : spdif_decoder port map (
+    -- 44100Hz
+    det2 : detector port map (
         n_reset   => n_reset,
-        clk       => clk1,
-        spdif     => spdif_clkd1,
-        bmc_ready => dbg3,
-        bmc_e     => dbg4,
-        bmc_l     => dbg5,
-        bmc_d     => dbg6,
-        bna       => bna1,
-        d         => d1,
-        ready     => ready1
-        );
+        clk_in       => clk_200mhz,
+        spdif_in     => spdif_in,
 
+	divisor		=> 5,   -- divisor to turn clk_in into 6x spdif base frequency
+	silent_thresh	=> 44100, -- number of samples of same sample before we declare silence
+	valid_divisor   => 40000000, --  (clk_in/(divisor*valid_divisor)) is period for validity checks
+	valid_thresh    => 40000, -- number of valid samples that must be received in validity period to declare it's all ok.
 
-    dbg8 <= bna1;
+	mute => mute2,
+	dbg => dbg
+        );
 
-    sd1 : silence_detector port map(
+    -- 32000Hz
+    det3 : detector port map (
         n_reset   => n_reset,
-        clk       => clk1,
-        d         => d1(26 downto 3),
-        max_ticks => 33333333,          -- 1 second
-        silent    => mute1
+        clk_in       => clk_200mhz,
+        spdif_in     => spdif_in,
+
+	divisor		=> 8,   -- divisor to turn clk_in into 6x spdif base frequency
+	silent_thresh	=> 32000, -- number of samples of same sample before we declare silence
+	valid_divisor   => 25000000, --  (clk_in/(divisor*valid_divisor)) is period for validity checks
+	valid_thresh    => 30000, -- number of valid samples that must be received in validity period to declare it's all ok.
+
+	mute => mute3
         );
 
-    n_mute_out <= not mute1;
-    n_stby_out <= '0';
+mute <= mute1 or mute2 or mute3;
 
-    dbg1 <= spdif_clkd1;
-    dbg2 <= clk1;
-    dbg7 <= ready1;
+    n_mute_out <= not mute;
+    n_stby_out <= not mute;
 
-    n_leds(0) <= d1(26);
-    n_leds(1) <= d1(25);
-    n_leds(2) <= not mute1;
+    n_leds(0) <= mute1;
+    n_leds(1) <= mute2;
+    n_leds(2) <= mute3;