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| author | root <root@no.no.james.local> | 2018-05-17 18:12:57 +0100 |
|---|---|---|
| committer | root <root@no.no.james.local> | 2018-05-17 18:12:57 +0100 |
| commit | 85b8cf5877ed7082564a47d94917ca7151977625 (patch) | |
| tree | 31cec84d278a478105c3f12c9d04158315c40053 /spdif.sdc | |
| parent | 3769dd04597e39140755bd4b92023570e6fcde3c (diff) | |
| download | rob_spdif-85b8cf5877ed7082564a47d94917ca7151977625.tar.gz rob_spdif-85b8cf5877ed7082564a47d94917ca7151977625.tar.bz2 rob_spdif-85b8cf5877ed7082564a47d94917ca7151977625.zip | |
minor fixes, make clock simulator happy and fix AS programming
Diffstat (limited to 'spdif.sdc')
| -rw-r--r-- | spdif.sdc | 5 |
1 files changed, 4 insertions, 1 deletions
@@ -7,9 +7,12 @@ set_time_format -unit ns -decimal_places 3 ############################################################################## # Create Input reference clocks create_clock -name {xtal_50mhz} -period 20.000 -waveform { 0.000 10.000 } [get_ports { xtal_50mhz }] +create_clock -name {det1_clk} -period 10.000 -waveform { 0.000 5.000 } [get_nets { det1|divider:div1|q }] +create_clock -name {det2_clk} -period 25.000 -waveform { 0.000 12.500 } [get_nets { det2|divider:div1|q }] +create_clock -name {det3_clk} -period 40.000 -waveform { 0.000 20.000 } [get_nets { det3|divider:div1|q }] ############################################################################## # Now that we have created the custom clocks which will be base clocks, # derive_pll_clock is used to calculate all remaining clocks for PLLs derive_pll_clocks -create_base_clocks -derive_clock_uncertainty
\ No newline at end of file +derive_clock_uncertainty |