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| author | Rob Langley <rob.langley@bromium.com> | 2018-05-29 14:47:31 +0100 |
|---|---|---|
| committer | Rob Langley <rob.langley@bromium.com> | 2018-05-29 14:47:31 +0100 |
| commit | 7ab8f32168e55169c605c1a66446091f533ccdad (patch) | |
| tree | 5a9ddcb08fdacfeed04daa65148203d8c7889db1 /spdif.qsf | |
| parent | 741560238b27473cd9faa4e52abc55baa868ee27 (diff) | |
| download | rob_spdif-7ab8f32168e55169c605c1a66446091f533ccdad.tar.gz rob_spdif-7ab8f32168e55169c605c1a66446091f533ccdad.tar.bz2 rob_spdif-7ab8f32168e55169c605c1a66446091f533ccdad.zip | |
Just one freq supported
Diffstat (limited to 'spdif.qsf')
| -rw-r--r-- | spdif.qsf | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -52,8 +52,9 @@ set_global_assignment -name FAMILY "Cyclone II" set_location_assignment PIN_118 -to dbg[6] set_location_assignment PIN_119 -to dbg[7] set_global_assignment -name USE_CONFIGURATION_DEVICE on - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND" set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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