diff options
| author | root <root@no.no.james.local> | 2018-05-29 16:14:18 +0100 |
|---|---|---|
| committer | root <root@no.no.james.local> | 2018-05-29 16:14:18 +0100 |
| commit | 5749bc2572e4be1acea0d428e8d928a95b170701 (patch) | |
| tree | 9000196f333163c345135523d53c89468130a5d7 /spdif.qsf | |
| parent | 7ab8f32168e55169c605c1a66446091f533ccdad (diff) | |
| download | rob_spdif-master.tar.gz rob_spdif-master.tar.bz2 rob_spdif-master.zip | |
Diffstat (limited to 'spdif.qsf')
| -rw-r--r-- | spdif.qsf | 14 |
1 files changed, 10 insertions, 4 deletions
@@ -20,15 +20,20 @@ set_global_assignment -name FAMILY "Cyclone II" set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[0] set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[1] set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[2] + set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to led_r + set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to led_g set_location_assignment PIN_17 -to xtal_50mhz set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" - set_location_assignment PIN_143 -to spdif_in + set_location_assignment PIN_72 -to spdif_in set_location_assignment PIN_73 -to n_rst_in set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to spdif_in - set_location_assignment PIN_112 -to n_mute_out - set_location_assignment PIN_114 -to n_stby_out + set_location_assignment PIN_71 -to n_mute_out + + set_location_assignment PIN_57 -to led_r + set_location_assignment PIN_59 -to led_g + set_global_assignment -name VHDL_FILE ccd.vhd set_global_assignment -name VHDL_FILE counter.vhd set_global_assignment -name VHDL_FILE dflipflop.vhd @@ -48,6 +53,7 @@ set_global_assignment -name FAMILY "Cyclone II" set_location_assignment PIN_103 -to dbg[2] set_location_assignment PIN_104 -to dbg[3] set_location_assignment PIN_113 -to dbg[4] + set_location_assignment PIN_114 -to n_stby_out set_location_assignment PIN_115 -to dbg[5] set_location_assignment PIN_118 -to dbg[6] set_location_assignment PIN_119 -to dbg[7] @@ -57,4 +63,4 @@ set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |