tidy

1 files changed, 19 insertions, 19 deletions

diff --git a/divider.vhd b/divider.vhd
index 26280bf..1a8c2ca 100644
--- a/divider.vhd
+++ b/divider.vhd
@@ -18,37 +18,37 @@ end divider;
 
 architecture rtl of divider is
 
-component counter is
-    port
-        (
-            divisor : in  integer;
-            clk     : in  std_logic;
-            n_reset : in  std_logic;
-            pulse_out : out std_logic
-            );
-end component;
-
-
-    signal pulse: std_logic;
+    component counter is
+        port
+            (
+                divisor   : in  integer;
+                clk       : in  std_logic;
+                n_reset   : in  std_logic;
+                pulse_out : out std_logic
+                );
+    end component;
+
+
+    signal pulse : std_logic;
     signal q :
         std_logic;
 begin
 
     clk_out <= q;
 
-    c1:counter port map (
-	divisor => divisor,
-	clk => clk,
-	n_reset => n_reset,
-	pulse_out => pulse
-    );
+    c1 : counter port map (
+        divisor   => divisor,
+        clk       => clk,
+        n_reset   => n_reset,
+        pulse_out => pulse
+        );
 
 
     process (clk, pulse, n_reset)
     begin
         if n_reset = '0' then
             q <= '0';
-        elsif RISING_EDGE(clk) and pulse='1' then
+        elsif RISING_EDGE(clk) and pulse = '1' then
             q <= not q;
         end if;
     end process;