working 3 detectors with parity checks

1 files changed, 5 insertions, 4 deletions

diff --git a/counter.vhd b/counter.vhd
index 0be542f..9fad8b3 100644
--- a/counter.vhd
+++ b/counter.vhd
@@ -11,7 +11,7 @@ entity counter is
             divisor : in  integer;
             clk     : in  std_logic;
             n_reset : in  std_logic;
-            clk_out : out std_logic
+            pulse_out : out std_logic
             );
 end counter;
 
@@ -19,12 +19,12 @@ end counter;
 architecture rtl of counter is
 
     signal d :
-        std_logic_vector (15 downto 0);
+        std_logic_vector (31 downto 0);
     signal q :
         std_logic;
 begin
 
-    clk_out <= q;
+    pulse_out <= q;
     process (clk, d, q, divisor, n_reset)
     begin
         if n_reset = '0' then
@@ -34,9 +34,10 @@ begin
 
             if d < divisor then
                 d <= d + 1;
+		q<='0';
             else
                 d <= (others => '0');
-                q <= not q;
+                q <= '1';
             end if;
         end if;
     end process;