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| * | | Merge pull request #1511 from YosysHQ/dave/alwaysClifford Wolf2019-11-221-0/+63
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| | * | | sv: Add tests for SV always typesDavid Shah2019-11-211-0/+63
| * | | | gowin: Remove show command from tests.Marcin Kościelnicki2019-11-221-1/+0
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* | | | Missing endmoduleEddie Hung2019-11-221-0/+1
* | | | Merge branch 'eddie/xaig_dff_adff' into xaig_dffEddie Hung2019-11-213-3/+37
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| * | | Add a equiv test tooEddie Hung2019-11-192-0/+23
| * | | Add two testsEddie Hung2019-11-191-0/+12
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* | / Add testEddie Hung2019-11-211-1/+6
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* | Add multi clock testEddie Hung2019-11-201-0/+5
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* Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-1912-0/+248
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| * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-165-17/+34
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| * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-0/+11
| * | fix wide lutsPepijn de Vos2019-11-061-7/+10
| * | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
| * | add tristate buffer and testPepijn de Vos2019-10-281-0/+13
| * | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
| * | ALU sim tweaksPepijn de Vos2019-10-241-2/+2
| * | Add some testsPepijn de Vos2019-10-2110-0/+224
* | | Fix #1462, #1480.Marcin Kościelnicki2019-11-192-0/+29
* | | Fix #1496.Marcin Kościelnicki2019-11-181-0/+13
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* | Fixed testsMiodrag Milanovic2019-11-115-17/+34
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* fixed errorMiodrag Milanovic2019-10-181-1/+1
* Unify verilog styleMiodrag Milanovic2019-10-1811-191/+157
* Common memory test now sharedMiodrag Milanovic2019-10-1810-89/+5
* Remove not needed testsMiodrag Milanovic2019-10-184-52/+0
* Share common testsMiodrag Milanovic2019-10-18103-1316/+178
* fix yosys pathMiodrag Milanovic2019-10-181-2/+2
* Fix path to yosysMiodrag Milanovic2019-10-185-5/+5
* Moved all tests in arch sub directoryMiodrag Milanovic2019-10-18150-0/+0
* Add async2syncMiodrag Milanovic2019-10-182-8/+8
* Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-1893-59/+1832
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| * Merge branch 'master' into mmicko/anlogicMiodrag Milanović2019-10-1873-59/+1403
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| | * Merge branch 'master' into eddie/pr1352Miodrag Milanović2019-10-1843-59/+763
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| | | * hierarchy - proc reorderMiodrag Milanovic2019-10-1810-17/+21
| | | * Make equivalence work with latest masterMiodrag Milanovic2019-10-173-8/+8
| | | * remove not needed top moduleMiodrag Milanovic2019-10-172-20/+2
| | | * remove not needed top moduleMiodrag Milanovic2019-10-172-17/+2
| | | * split muxes synth per typeMiodrag Milanovic2019-10-172-39/+39
| | | * Test dffs separetelyMiodrag Milanovic2019-10-172-26/+19
| | | * Split latches into separete testsMiodrag Milanovic2019-10-172-42/+27
| | | * Fix formattingMiodrag Milanovic2019-10-171-1/+8
| | | * Clean verilog code from not used define blockMiodrag Milanovic2019-10-172-12/+0
| | | * Removed alu and div_mod test as agreed, ignore generated filesMiodrag Milanovic2019-10-175-70/+1
| | | * Test per flip-flop typeMiodrag Milanovic2019-10-172-47/+37
| | | * Add -assertEddie Hung2019-10-171-1/+1
| | | * Use built-in async2sync call as per #1417Eddie Hung2019-10-171-4/+0
| | | * Update mul test to DSP48E1Eddie Hung2019-10-171-9/+2
| | | * Update area for div_modEddie Hung2019-10-171-6/+6
| | | * Add comment for lack of tristate logic pointing to #1225Eddie Hung2019-10-171-1/+1
| | | * Move $x to end as 7f0eec8Eddie Hung2019-10-171-1/+1
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