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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 14:56:19 -0700 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:42 +0200 |
| commit | 8422ad3e3a5db583f59906f8a5d81587dd777f6d (patch) | |
| tree | 031e6d3c96c7b5f09399cb4e03258a89b6bb01a7 /tests | |
| parent | 5b7bc3ab85d31920883995636d26dc5b971ca24d (diff) | |
| download | yosys-8422ad3e3a5db583f59906f8a5d81587dd777f6d.tar.gz yosys-8422ad3e3a5db583f59906f8a5d81587dd777f6d.tar.bz2 yosys-8422ad3e3a5db583f59906f8a5d81587dd777f6d.zip | |
Use built-in async2sync call as per #1417
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/xilinx/latches.ys | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 1f643cb4e..795ac9074 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -4,11 +4,7 @@ design -save read proc async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -synth_xilinx equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -design -load read synth_xilinx flatten |