iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added test cases for sat command	Clifford Wolf	2014-02-04	6	-0/+126
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+39
*	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	Clifford Wolf	2014-02-03	1	-50/+10
*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30	1	-0/+24
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+17
*	Added autotest.sh -p option	Clifford Wolf	2014-01-02	1	-3/+8
*	Use "abc -dff" in "make test"	Clifford Wolf	2013-12-31	1	-3/+2
*	Fixed commented out techmap call in tests/tools/autotest.sh	Clifford Wolf	2013-12-31	1	-1/+1
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-0/+11
*	Added multiplier test case from eda playground	Clifford Wolf	2013-12-18	1	-0/+132
*	Added elsif preproc support	Clifford Wolf	2013-12-18	1	-1/+229
*	Added support for macro arguments	Clifford Wolf	2013-12-18	1	-0/+9
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	1	-0/+27
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-1/+1
*	Fix in sincos testbench gen	Clifford Wolf	2013-12-04	1	-1/+1
*	Added sincos test case	Clifford Wolf	2013-12-04	1	-0/+124
*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24	2	-2/+2
*	Removed now obsolete test cases	Clifford Wolf	2013-11-24	3	-72/+0
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-1/+7
*	Added modelsim support to autotest	Clifford Wolf	2013-11-24	2	-2/+31
*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20	1	-0/+48
*	Implemented indexed part selects	Clifford Wolf	2013-11-20	1	-0/+5
*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20	1	-0/+41
*	Added additional mem2reg testcase	Clifford Wolf	2013-11-18	1	-0/+28
*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18	1	-0/+22
*	Fixed handling of power operator	Clifford Wolf	2013-11-07	1	-0/+15
*	Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...	Clifford Wolf	2013-11-02	1	-6/+6
*	Various ast changes for early expression width detection (prep for constfold ...	Clifford Wolf	2013-11-02	1	-0/+7
*	Added support for complex set-reset flip-flops in proc_dff	Clifford Wolf	2013-10-24	1	-12/+26
*	Improved handling of dff with async resets	Clifford Wolf	2013-10-21	1	-0/+39
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	3	-5/+5
*	Added support for "2**n" shifter encoding	Clifford Wolf	2013-08-12	1	-24/+29
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09	2	-24/+43
*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12	1	-0/+8
*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12	1	-0/+8
*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11	1	-0/+7
*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09	1	-13/+15
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-07-09	2	-2/+20
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\| *	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	2	-2/+20
* \|	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09	1	-3/+43
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07	1	-0/+10
*	Removed tests/xsthammer	Clifford Wolf	2013-07-07	13	-1748/+0
*	Fixed vivado related xsthammer bugs	Clifford Wolf	2013-07-05	3	-2/+14
*	Various improvements in xsthammer report generator	Clifford Wolf	2013-07-05	1	-6/+23
*	Added work-around to isim bug in xsthammer report script	Clifford Wolf	2013-07-05	1	-4/+5
*	Added CARRY4 Xilinx cell to xsthammer cell lib	Clifford Wolf	2013-07-05	1	-0/+13
*	Added xsthammer report generator	Clifford Wolf	2013-07-05	4	-13/+170
*	Improved xsthammer quartus support	Clifford Wolf	2013-07-04	2	-1/+484
*	Added Altera Cyclon III cell library to xsthammer	Clifford Wolf	2013-07-04	3	-14/+115
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-0/+16