| Commit message (Expand) | Author | Age | Files | Lines |
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| * | test dlatchsr and adlatch | Miodrag Milanovic | 2022-02-16 | 4 | -4/+94 |
| * | Added test cases | Miodrag Milanovic | 2022-02-16 | 38 | -0/+896 |
| * | verilog: support for time scale delay values | Zachary Snow | 2022-02-14 | 1 | -0/+25 |
| * | Fix access to whole sub-structs (#3086) | Kamil Rakoczy | 2022-02-14 | 4 | -5/+51 |
| * | verilog: fix dynamic dynamic range asgn elab | Zachary Snow | 2022-02-11 | 2 | -0/+108 |
| * | verilog: fix const func eval with upto variables | Zachary Snow | 2022-02-11 | 2 | -0/+84 |
| * | gowin: Fix LUT RAM inference, add more models. | Marcelina Kościelnicka | 2022-02-09 | 1 | -3/+2 |
| * | Merge pull request #3185 from YosysHQ/micko/co_sim | Miodrag Milanović | 2022-02-07 | 7 | -0/+953 |
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| | * | bug fix and cleanups | Miodrag Milanovic | 2022-02-04 | 1 | -2/+2 |
| | * | Add test cases for co-simulation | Miodrag Milanovic | 2022-02-02 | 7 | -0/+953 |
| * | | opt_reduce: Add $bmux and $demux optimization patterns. | Marcelina Kościelnicka | 2022-01-30 | 2 | -0/+208 |
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| * | Merge pull request #3120 from Icenowy/anlogic-bram | Miodrag Milanović | 2022-01-19 | 2 | -1/+14 |
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| | * | anlogic: support BRAM mapping | Icenowy Zheng | 2021-12-17 | 2 | -1/+14 |
| * | | sv: auto add nosync to certain always_comb local vars | Zachary Snow | 2022-01-07 | 8 | -0/+135 |
| * | | sv: fix size cast internal expression extension | Zachary Snow | 2022-01-07 | 2 | -0/+145 |
| * | | logger: fix unmatched expected warnings and errors | Zachary Snow | 2022-01-04 | 1 | -0/+42 |
| * | | fix iverilog compatibility for new case expr tests | Zachary Snow | 2022-01-03 | 2 | -2/+2 |
| * | | fixup verilog doubleslash test | Zachary Snow | 2022-01-03 | 2 | -0/+3 |
| * | | sv: fix size cast clipping expression width | Zachary Snow | 2022-01-03 | 1 | -0/+7 |
| * | | memory_share: Fix SAT-based sharing for wide ports. | Marcelina Kościelnicka | 2021-12-20 | 1 | -0/+34 |
| * | | fix width detection of array querying function in case and case item expressions | Zachary Snow | 2021-12-17 | 2 | -0/+43 |
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| * | preprocessor: do not destroy double slash escaped identifiers | Thomas Sailer | 2021-12-15 | 1 | -0/+19 |
| * | Fix the tests we just broke | Claire Xenia Wolf | 2021-12-10 | 6 | -10/+10 |
| * | Add gitignore for gatemate | Miodrag Milanovic | 2021-12-03 | 1 | -0/+4 |
| * | sta: very crude static timing analysis pass | Lofty | 2021-11-25 | 1 | -0/+81 |
| * | Support parameters using struct as a wiretype (#3050) | Kamil Rakoczy | 2021-11-16 | 1 | -0/+51 |
| * | synth_gatemate: Update pass | Patrick Urban | 2021-11-13 | 1 | -4/+8 |
| * | synth_gatemate: Apply new test practice with assert-max | Patrick Urban | 2021-11-13 | 7 | -12/+12 |
| * | synth_gatemate: Fix fsm test | Patrick Urban | 2021-11-13 | 1 | -2/+2 |
| * | Allow initial blocks to be disabled during tests | Patrick Urban | 2021-11-13 | 6 | -4/+20 |
| * | synth_gatemate: Initial implementation | Patrick Urban | 2021-11-13 | 14 | -0/+337 |
| * | iopadmap: Add native support for negative-polarity output enable. | Marcelina Kościelnicka | 2021-11-09 | 2 | -3/+3 |
| * | dfflegalize: Add tests for aldff lowering. | Marcelina Kościelnicka | 2021-10-27 | 2 | -0/+240 |
| * | dfflegalize: Add tests targetting aldff. | Marcelina Kościelnicka | 2021-10-27 | 7 | -7/+320 |
| * | dfflegalize: Refactor, add aldff support. | Marcelina Kościelnicka | 2021-10-27 | 9 | -73/+46 |
| * | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 4 | -0/+79 |
| * | extract_reduce: Refactor and fix input signal construction. | Marcelina Kościelnicka | 2021-10-21 | 1 | -0/+12 |
| * | Fixes in vcdcd.pl for newer Perl versions | Claire Xenia Wolf | 2021-10-19 | 1 | -3/+3 |
| * | Fix a regression from #3035. | Marcelina Kościelnicka | 2021-10-08 | 1 | -0/+21 |
| * | FfData: some refactoring. | Marcelina Kościelnicka | 2021-10-07 | 2 | -5/+7 |
| * | Merge pull request #3014 from YosysHQ/claire/fix-vgtest | Claire Xen | 2021-09-24 | 40 | -79/+79 |
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| | * | Fix "make vgtest" so it runs to the end (but now it fails ;) | Claire Xenia Wolf | 2021-09-23 | 40 | -79/+79 |
| * | | sv: support wand and wor of data types | Zachary Snow | 2021-09-21 | 2 | -0/+39 |
| * | | verilog: fix multiple AST_PREFIX scope resolution issues | Zachary Snow | 2021-09-21 | 2 | -0/+100 |
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| * | abc9: make re-entrant (#2993) | Eddie Hung | 2021-09-09 | 1 | -0/+20 |
| * | abc9: holes module to instantiate cells with NEW_ID (#2992) | Eddie Hung | 2021-09-09 | 1 | -0/+14 |
| * | abc9: replace cell type/parameters if derived type already processed (#2991) | Eddie Hung | 2021-09-09 | 1 | -0/+7 |
| * | sv: support declaration in generate for initialization | Zachary Snow | 2021-08-31 | 8 | -0/+114 |
| * | sv: support declaration in procedural for initialization | Zachary Snow | 2021-08-30 | 4 | -0/+56 |
| * | opt_clean: Make the init attribute follow the FF's Q. | Marcelina Kościelnicka | 2021-08-22 | 1 | -2/+2 |
