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| author | Icenowy Zheng <icenowy@aosc.io> | 2021-12-17 20:25:32 +0800 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2021-12-17 20:28:22 +0800 |
| commit | c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5 (patch) | |
| tree | 70021f14e73c9b9db20047caf7f4995855edbc2b /tests | |
| parent | 60c3ea367c942459a95e610ed98f277ce46c0142 (diff) | |
| download | yosys-c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5.tar.gz yosys-c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5.tar.bz2 yosys-c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5.zip | |
anlogic: support BRAM mapping
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.
Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/anlogic/blockram.ys | 13 | ||||
| -rw-r--r-- | tests/arch/anlogic/lutram.ys | 2 |
2 files changed, 14 insertions, 1 deletions
diff --git a/tests/arch/anlogic/blockram.ys b/tests/arch/anlogic/blockram.ys new file mode 100644 index 000000000..da23409ba --- /dev/null +++ b/tests/arch/anlogic/blockram.ys @@ -0,0 +1,13 @@ +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sp +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +design -load postopt +cd sync_ram_sp + +select -assert-count 1 t:EG_PHY_BRAM +select -assert-none t:EG_PHY_BRAM %% t:* %D diff --git a/tests/arch/anlogic/lutram.ys b/tests/arch/anlogic/lutram.ys index 6dbdbdac3..fe6135c73 100644 --- a/tests/arch/anlogic/lutram.ys +++ b/tests/arch/anlogic/lutram.ys @@ -2,7 +2,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r proc memory -nomap -equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -nobram memory opt -full |