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* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-078-0/+135
| | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* sv: fix size cast internal expression extensionZachary Snow2022-01-072-0/+145
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* logger: fix unmatched expected warnings and errorsZachary Snow2022-01-041-0/+42
| | | | | | | | - Prevent unmatched expected error patterns from self-matching - Prevent infinite recursion on unmatched expected warnings - Always print the error message for unmatched error patterns - Add test coverage for all unmatched message types - Add test coverage for excess matched logs and warnings
* fix iverilog compatibility for new case expr testsZachary Snow2022-01-032-2/+2
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* fixup verilog doubleslash testZachary Snow2022-01-032-0/+3
| | | | | - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again
* sv: fix size cast clipping expression widthZachary Snow2022-01-031-0/+7
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* memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-201-0/+34
| | | | Fixes #3117.
* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-172-0/+43
| | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* preprocessor: do not destroy double slash escaped identifiersThomas Sailer2021-12-151-0/+19
| | | | | | | | | | | The preprocessor currently destroys double slash containing escaped identifiers (for example \a//b ). This is due to next_token trying to convert single line comments (//) into /* */ comments. This then leads to an unintuitive error message like this: ERROR: syntax error, unexpected '*' This patch fixes the error by recognizing escaped identifiers and returning them as single token. It also adds a testcase.
* Fix the tests we just brokeClaire Xenia Wolf2021-12-106-10/+10
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
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* sta: very crude static timing analysis passLofty2021-11-251-0/+81
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-0/+51
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* synth_gatemate: Update passPatrick Urban2021-11-131-4/+8
| | | | | | * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
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* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
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* Allow initial blocks to be disabled during testsPatrick Urban2021-11-136-4/+20
| | | | Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
* synth_gatemate: Initial implementationPatrick Urban2021-11-1314-0/+337
| | | | Signed-off-by: Patrick Urban <patrick.urban@web.de>
* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-092-3/+3
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* dfflegalize: Add tests for aldff lowering.Marcelina Kościelnicka2021-10-272-0/+240
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* dfflegalize: Add tests targetting aldff.Marcelina Kościelnicka2021-10-277-7/+320
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* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-279-73/+46
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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-254-0/+79
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-211-0/+12
| | | | Fixes #3047.
* Fixes in vcdcd.pl for newer Perl versionsClaire Xenia Wolf2021-10-191-3/+3
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fix a regression from #3035.Marcelina Kościelnicka2021-10-081-0/+21
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* FfData: some refactoring.Marcelina Kościelnicka2021-10-072-5/+7
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-2440-79/+79
|\ | | | | Fix "make vgtest"
| * Fix "make vgtest" so it runs to the end (but now it fails ;)Claire Xenia Wolf2021-09-2340-79/+79
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | sv: support wand and wor of data typesZachary Snow2021-09-212-0/+39
| | | | | | | | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec.
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-212-0/+100
|/ | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* abc9: make re-entrant (#2993)Eddie Hung2021-09-091-0/+20
| | | | | | | | | * Add testcase * Cleanup some state at end of abc9 * Re-assign abc9_box_id from scratch * Suppress delete unless prep_bypass did something
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-091-0/+14
| | | | | * Add testcase * holes module to instantiate cells with NEW_ID
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-0/+7
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* sv: support declaration in generate for initializationZachary Snow2021-08-318-0/+114
| | | | | | | | This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected.
* sv: support declaration in procedural for initializationZachary Snow2021-08-304-0/+56
| | | | | In line with other tools, this adds an extra wrapping block around such for loops to appropriately scope the variable.
* opt_clean: Make the init attribute follow the FF's Q.Marcelina Kościelnicka2021-08-221-2/+2
| | | | | | | | | | Previously, opt_clean would reconnect all ports (including FF Q ports) to a "canonical" SigBit chosen by complex rules, but would leave the init attribute on the old wire. This change applies the same canonicalization rules to the init attributes, ensuring that init moves to wherever the Q port moved. Part of another jab at #2920.
* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-201-1/+2
| | | | | | | | | * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests
* proc_prune: Make assign removal and promotion per-bit, remember promoted bits.Marcelina Kościelnicka2021-08-141-0/+22
| | | | Fixes #2962.
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-141-0/+36
| | | | If all of us are wide, then none of us are!
* memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-149-1/+228
| | | | This unlocks wide port recognition by default.
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-133-0/+904
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* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-131-0/+205
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* sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-122-0/+108
| | | | | | | | | | | | | | | | | - User-defined types must be data types. Using a net type (e.g. wire) is a syntax error. - User-defined types without a net type are always variables (i.e. logic). - Nets and variables can now be explicitly declared using user-defined types: typedef logic [1:0] W; wire W w; typedef logic [1:0] V; var V v; Fixes #2846
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
| | | | | | | | | | These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine.
* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-113-1/+55
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* proc_memwr: Use the v2 memwr cell.Marcelina Kościelnicka2021-08-112-5/+5
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* Add v2 memory cells.Marcelina Kościelnicka2021-08-118-32/+32
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* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-082-1/+43
| | | | Partial #2920 fix.
* proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-293-0/+323
| | | | | | | | If width of a case expression was large, explicit patterns could cause the existing logic to take an extremely long time, or exhaust the maximum size of the underlying set. For cases where all of the patterns are fully defined and there are no constants in the case expression, this change uses a simple set to track which patterns have been seen.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 13:08:34 +0000